A display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising a plurality of first signal lines, a plurality of power signal lines and a plurality of electrostatic discharge circuits; the plurality of electrostatic discharge circuits comprising a first electrostatic discharge circuit and a second electrostatic discharge circuit; the first electrostatic discharge circuit and the second electrostatic discharge circuit each comprising a first end and a second end; the first ends of the first electrostatic discharge circuit and the second electrostatic discharge circuit being electrically connected with different first signal lines respectively, and the second ends being electrically connected with different power signal lines respectively. By using the above device, the second ends of the first electrostatic discharge circuit and the second electrostatic discharge circuit are electrically connected with different power signal lines respectively, accurate on-off of the electrostatic discharge circuit is realized, the electrostatic discharge can be effectively performed, and the quality and performance of the display panel are improved.

Description

Technical Field

[0001] This invention relates to the technical field of display panels, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous advancement of display technology, display panels are gradually evolving towards thinner and lighter designs, higher screen-to-body ratios, and even borderless designs. In thin-film transistor (TFT) driven display panels, electrostatic discharge (ESD) problems often occur due to the inability to eliminate accumulated static electricity. ESD can damage components within the display panel, affecting product performance. Therefore, ESD protection circuits are needed on the display panel to release static charge on the signal lines.

[0003] Conventional display panels typically utilize a set of power lines—the high-level power signal line VGH and the low-level power signal line VGL—for electrostatic discharge (ESD) circuitry. However, this design can lead to leakage in the ESD circuit, causing it to interfere with the normal operation of the panel. Summary of the Invention

[0004] This invention provides a display panel and a display device to solve the leakage phenomenon of the electrostatic discharge circuit, realize the precise opening of the electrostatic discharge circuit, ensure that the electrostatic discharge circuit can work normally, and improve the display performance of the display panel.

[0005] In a first aspect, the present invention provides a display panel, including multiple first signal lines, multiple power signal lines, and multiple electrostatic discharge circuits;

[0006] Multiple electrostatic discharge circuits include a first electrostatic discharge circuit and a second electrostatic discharge circuit; both the first and second electrostatic discharge circuits include a first terminal and a second terminal; the first terminals of the first and second electrostatic discharge circuits are electrically connected to different first signal lines respectively; the second terminals of the first and second electrostatic discharge circuits are electrically connected to different power signal lines respectively.

[0007] Secondly, the present invention also provides a display device, including the display panel described above.

[0008] The technical solution of this invention, when releasing electrostatic voltage signals on multiple first signal lines, involves electrically connecting the first terminals of the first and second electrostatic release circuits to different first signal lines, and electrically connecting the second terminals of the first and second electrostatic release circuits to different power signal lines. This allows the electrostatic voltage signals of the first signal lines to be smoothly transmitted to the first terminals of the first and second electrostatic release circuits, enabling them to conduct. After the electrostatic release circuits are activated, the electrostatic voltage signals can be output to different power signal lines through their second terminals, and then electrostatically released through these different power signal lines. Using this device, by electrically connecting the second terminals of the first and second electrostatic release circuits to different power signal lines, accurate activation of the electrostatic release circuits is achieved, preventing leakage current and ensuring the quality and performance of the display panel. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0010] Figure 2 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram of the structure of a driving circuit in a display panel provided in an embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of the structure of a second type of display panel provided in an embodiment of the present invention;

[0013] Figure 5 A schematic diagram of the circuit routing of a second type of display panel provided in an embodiment of the present invention;

[0014] Figure 6 This is a schematic diagram of the structure of a third type of display panel provided in an embodiment of the present invention;

[0015] Figure 7 This is a schematic diagram of the structure of a fourth type of display panel provided in an embodiment of the present invention;

[0016] Figure 8 This is a schematic diagram of the structure of the fifth type of display panel provided in an embodiment of the present invention;

[0017] Figure 9 This is a schematic diagram of the structure of the sixth type of display panel provided in an embodiment of the present invention;

[0018] Figure 10A schematic diagram of the circuit routing structure of the sixth type of display panel provided in an embodiment of the present invention;

[0019] Figure 11 This is a schematic diagram of the structure of the seventh type of display panel provided in an embodiment of the present invention;

[0020] Figure 12 A schematic diagram illustrating the connection relationship between a shift register circuit, a power signal line, an electrostatic discharge circuit, and a pixel circuit, provided in an embodiment of the present invention.

[0021] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0022] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0023] The terminology used in the embodiments of this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. It should be noted that directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this invention are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this invention. Furthermore, in the context, it should be understood that when referring to an element being formed "on" or "below" another element, it can be formed not only directly on or below the other element, but also indirectly on or below it through intermediate elements. The terms "first," "second," etc., are used for descriptive purposes only and do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] The term "comprising" and its variations as used in this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment". It should be noted that the concepts of "first", "second", etc., mentioned in this invention are only used to distinguish corresponding content and are not intended to limit the order or interdependence. It should be noted that the modifications of "a" and "a plurality" mentioned in this invention are illustrative rather than restrictive, and those skilled in the art should understand that unless explicitly indicated in the context, they should be understood as "one or more".

[0025] Currently, with the increasing complexity of display panel circuit structures, different signal lines are connected to different circuits, resulting in significant differences in the voltage ranges of the signals transmitted on these lines. To ensure the stability of these different signal lines with significantly different voltage ranges, this application provides corresponding electrostatic discharge circuit designs for signal lines with different voltage amplitude ranges.

[0026] Specifically, embodiments of the present invention provide a display panel. The display panel includes multiple first signal lines, multiple power signal lines, and multiple electrostatic discharge circuits;

[0027] Multiple electrostatic discharge circuits include a first electrostatic discharge circuit and a second electrostatic discharge circuit; both the first and second electrostatic discharge circuits include a first terminal and a second terminal; the first terminals of the first and second electrostatic discharge circuits are electrically connected to different first signal lines respectively; the second terminals of the first and second electrostatic discharge circuits are electrically connected to different power signal lines respectively.

[0028] In the above technical solution, the first terminals of the first and second electrostatic discharge circuits are electrically connected to different first signal lines, and the second terminals are electrically connected to different power signal lines. Essentially, this means that electrostatic discharge circuits connected to first signal lines with different voltage domains perform electrostatic discharge through power signal lines with compatible voltage domains. Therefore, for the electrostatic discharge circuit, the first signal line receiving the electrostatic source and the power signal line performing the electrostatic discharge have compatible voltage domains. In the absence of electrostatic discharge, the electrostatic discharge circuit can be normally in a closed state. When electrostatic discharge occurs on the display panel, it can be normally turned on to release the electrostatic discharge from the first signal lines through the power signal lines, protecting the display panel. This invention solves the problem that existing methods of using the same power signal line for electrostatic discharge on different signal lines easily cause leakage in the electrostatic discharge circuit, affecting the normal operation of the display panel. It can achieve accurate switching of the electrostatic discharge circuit, ensuring effective electrostatic discharge when electrostatic discharge occurs, while avoiding design flaws in the electrostatic discharge circuit that could affect the normal operation of the display panel, thus helping to improve the quality and performance of the display panel.

[0029] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0030] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 1As shown, in this embodiment of the invention, the display panel may include a pixel driving area 1 and an electrostatic discharge area 2; the pixel driving area 1 includes multiple first signal lines 11, which extend through the electrostatic discharge area 2; the electrostatic discharge area 2 includes multiple power signal lines 21 and multiple electrostatic discharge circuits 22; the multiple electrostatic discharge circuits 22 include a first electrostatic discharge circuit 221 and a second electrostatic discharge circuit 222; both the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 include a first terminal 2201 and a second terminal 2202; the first terminal 2201 of the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 are electrically connected to different first signal lines 11 respectively; the second terminal 2202 of the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 are electrically connected to different power signal lines 21 respectively.

[0031] The pixel driving area 1 can be understood as the area where the pixel circuits driving the display are located in the display panel. The pixel driving area 1 may include multiple first signal lines 11, each extending through the electrostatic discharge area 2. Each first signal line 11 is independent of the others. When the display panel generates static electricity due to friction, etc., to prevent the first signal lines 11 from being damaged by static electricity and affecting the driving display function, the static electricity on the first signal lines 11 is discharged from the display panel. Specifically, the electrostatic discharge area 2 is provided with an electrostatic discharge circuit 22, whose two ends are respectively connected to the first signal lines 11 and the power signal line 21, responsible for discharging the static electricity on the first signal lines 11. When static electricity is generated on the first signal lines 11, the electrostatic discharge circuit 22 is automatically turned on under the control of the static electricity signal, and the static electricity is discharged to the outside through the conductive electrostatic discharge circuit via the power signal line 21. The material of the power signal line 21 can be a conductive metal material, such as, but not limited to, any one of copper, molybdenum, titanium, and aluminum.

[0032] It should be added that the pixel driving area 1 and the electrostatic discharge area 2 are divided according to the type of circuit structure therein. The display panel in this embodiment of the invention can be a borderless display, meaning that the light-emitting elements driven by the pixel circuit are arranged in various areas of the entire display panel, and the entire area of ​​the display panel is the display area. The light-emitting elements and the circuit structure are located in different film layers of the display panel. Therefore, as... Figure 1 The pixel driving area 1 and electrostatic discharge area 2 shown are essentially included in the display area. Of course, in other embodiments of the present invention, the display panel may also be divided into display area and non-display area according to the position of the light-emitting element, and the electrostatic discharge area 2 may be disposed in the non-display area.

[0033] In this embodiment, the electrostatic discharge area 2 includes multiple power signal lines 21 and multiple electrostatic discharge circuits 22. The multiple power signal lines 21 are used to release the electrostatic voltage signal generated by the first signal line 11 after passing through the electrostatic discharge circuits 22 and the power signal lines 21. The multiple electrostatic discharge circuits 22 include a first electrostatic discharge circuit 221 and a second electrostatic discharge circuit 222, and both the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 include a first terminal 2201 and a second terminal 2202. The first terminal 2201 of the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 are electrically connected to different first signal lines 11, so that the electrostatic voltage signal of each first signal line 11 can be transmitted to the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222. The second terminals 2202 of the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 are respectively electrically connected to different power signal lines 21, so that the electrostatic voltage signal can be transmitted to different power signal lines 21 after passing through the second terminals 2202 of the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222, and the electrostatic voltage signal can be electrostatically released through different power signal lines 21.

[0034] Optionally, the power signal line can be a signal line with a fixed potential or a signal line with a non-fixed potential.

[0035] Optionally, the display panel in this application includes at least two sub-circuits. These two sub-circuits can originate from different modules of the same circuit (e.g., the PWM and PAM modules described below), or they can originate from different circuits, such as a VSR circuit and a pixel circuit, respectively. Each of the two sub-circuits is electrically connected to a power signal line 21. The power signal lines 21 of the two sub-circuits can differ in function, the magnitude of the signals they transmit, or the amplitude of the signals. These two different power signal lines 21 are respectively connected to the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222.

[0036] Figure 2 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a driving circuit in a display panel provided in an embodiment of the present invention. The following refers to... Figure 2 and Figure 3 The principle of the electrostatic discharge circuit design in this embodiment of the invention will be introduced.

[0037] First, refer to Figure 2 and Figure 3As shown, exemplarily, the pixel circuit in the display panel of the present invention may include a pulse amplitude modulation (PAM) circuit and a pulse width modulation (PWM) circuit, and the PAM circuit and the PWM circuit require different scanning signals for drive control during normal operation. Exemplarily, it is possible to utilize... Figure 3 The driving circuit in the circuit provides a signal to the pulse width modulation (PWM) circuit or the pulse amplitude modulation (PAM) circuit, for example... Figure 3 The example driver circuit provides a Sweep[n] signal to the pulse width modulation (PWM) circuit. Furthermore, the driver circuits providing scan signals to the pulse amplitude modulation (PAM) circuit and the pulse width modulation (PWM) circuit, respectively, have different voltage domains. For example, in the driver circuit providing the scan signal to the PWM circuit, the power supply signals VGH and VGL have signal voltages of +8V and -7V, respectively; while in the driver circuit providing the scan signal to the PWM circuit, the power supply signals VGH and VGL have signal voltages of +3V and -12V, respectively.

[0038] It should be noted that, when performing electrostatic discharge on the drive signal in the pixel circuit, the inventors discovered that if the electrostatic discharge circuit uses a set of power signal lines for electrostatic discharge, for example, when... Figure 2 When the drive signals of the pixel circuits, namely the Pulse Amplitude Modulation (PAM) and Pulse Width Modulation (PWM) circuits, are subjected to electrostatic discharge (ESD), the +3V and -12V power signal lines VGH and VGL can be used for ESD discharge. However, for the drive signals in the Pulse Width Modulation (PWM) circuit, the voltage range is +8V to -7V. When these drive signal lines are connected to the ESD discharge circuit, the voltage range (+8V to -7V) is higher than the power signal lines (+3V to -12V) connected to the ESD discharge circuit. This can cause the ESD discharge circuit to be mistakenly activated, resulting in leakage current and affecting the normal driving of the pixel circuits and the performance of the display panel.

[0039] However, as Figure 1 As shown, in this embodiment of the invention, when... Figure 2When the signal lines of the intermediate pixel circuit, namely the pulse amplitude modulation circuit (PAM) and pulse width modulation circuit (PWM), are electrostatically discharged, the first terminals 2201 of the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 can be electrically connected to the first signal lines 11 with different voltage domains, according to the different voltage domains of the first signal lines 11. For example, the first terminal 2201 of the first electrostatic discharge circuit 221 is connected to the signal line of the pulse width modulation circuit (PWM) (voltage domain of +8 to -7V), and the first terminal 2201 of the second electrostatic discharge circuit 222 is connected to the signal line of the pulse amplitude modulation circuit (PAM) (voltage domain of +3 to -12V). At the same time, the second terminal 2202 is electrically connected to the power signal line 21 with different voltage domains. For example, the second terminal 2202 of the first electrostatic discharge circuit 221 is electrically connected to the power signal line 21 with a voltage domain of +8 to -7V, and the second terminal 2202 of the second electrostatic discharge circuit 222 is electrically connected to the power signal line 21 with a voltage domain of +3 to -12V. In this way, it can be ensured that the two ends of the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 are respectively connected to the first signal line 11 and the power signal line 21 with compatible voltage domains. This avoids the electrostatic discharge circuit being mistakenly turned on due to the voltage domain of the first signal line 11 (+8 to -7V) being higher than the voltage domain of the power signal line 21 (+3 to -12V) to which the electrostatic discharge circuit is connected, which could cause leakage problems and affect the normal driving of the pixel circuit and the performance of the display panel. This achieves accurate switching of the electrostatic discharge circuit, ensuring that the generated static electricity can be effectively discharged, avoiding design problems in the electrostatic discharge circuit from affecting the normal driving of the display panel, and improving the quality and performance of the display panel.

[0040] It should be noted that the second terminals 2202 of the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 are electrically connected to different power signal lines 21. In this embodiment, the number of the second terminals 2202 of the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222, i.e., the electrostatic output terminals, is at least two. The two electrostatic output terminals are respectively connected to different power signal lines 21 of the same group. That is, the high-level voltage VGH and the low-level voltage VGL are one group, and the two electrostatic output terminals are respectively connected to the high-level voltage VGH and the low-level voltage VGL of the same group. When the electrostatic voltage is high voltage, the high voltage can be transmitted to the electrostatic discharge circuit, enabling the electrostatic discharge circuit to work normally, and finally output through the second terminal 2202 of the electrostatic discharge circuit, transmitting to the power signal line 21 of the corresponding high-level voltage VGH, thereby releasing the high voltage electrostatic inside the panel by the high-level voltage VGH. When the electrostatic voltage is low, the low-voltage electrostatic charge can be transmitted to the electrostatic discharge circuit, enabling the electrostatic discharge circuit to work normally. Finally, it is output through the second terminal 2202 of the electrostatic discharge circuit and transmitted to the power signal line 21 of the corresponding low-level voltage VGL, thereby releasing the low-voltage electrostatic charge inside the panel by the low-level voltage VGL.

[0041] The technical solution of this invention connects the first terminals of the first and second electrostatic discharge circuits to different first signal lines, and their second terminals to different power signal lines. Essentially, it allows electrostatic discharge circuits connected to first signal lines with different voltage domains to perform electrostatic discharge through power signal lines with compatible voltage domains. Thus, for the electrostatic discharge circuit, the first signal line receiving the electrostatic source and the power signal line performing the electrostatic discharge have compatible voltage domains. In the absence of electrostatic discharge, the electrostatic discharge circuit can be normally in a closed state. When electrostatic discharge occurs on the display panel, it can be normally turned on to release the electrostatic discharge from the first signal lines through the power signal lines, protecting the display panel. This invention solves the problem that existing methods of using the same power signal line for electrostatic discharge on different signal lines easily cause leakage in the electrostatic discharge circuit, affecting the normal operation of the display panel. It enables accurate switching of the electrostatic discharge circuit, ensuring effective electrostatic discharge when electrostatic discharge occurs while avoiding design flaws in the electrostatic discharge circuit that could affect the normal operation of the display panel, thus contributing to improved display panel quality and performance.

[0042] Optional, Figure 4 This is a schematic diagram of the structure of a second type of display panel provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of the circuit routing of a second type of display panel provided in an embodiment of the present invention, with reference to... Figure 4 and Figure 5As shown, the signal range of the power signal line 21 electrically connected to the first electrostatic discharge circuit 221 is different from the signal range of the power signal line 21 electrically connected to the second electrostatic discharge circuit 222.

[0043] Specifically, the multiple power signal lines 21 include a first group of power signal lines 211 and a second group of power signal lines 212; the first group of power signal lines 211 and the second group of power signal lines 212 include a first power signal line 2111 and a second power signal line 2112; in the first group of power signal lines 211, the power signal voltage of the first power signal line 2111 is V11, and the power signal voltage of the second power signal line 2112 is V12; in the second group of power signal lines 212, the power signal voltage of the first power signal line 2111 is V21, and the second... The power signal voltage of power signal line 21112 is V22; where V11 > V12, V21 > V22, V11 ≠ V21, and V12 ≠ V22; the two second terminals 2202 of the first electrostatic discharge circuit 221 are electrically connected to the first power signal line 2111 and the second power signal line 2112 in the first group of power signal lines 211, respectively; the two second terminals 2202 of the second electrostatic discharge circuit 222 are electrically connected to the first power signal line 2111 and the second power signal line 2112 in the second group of power signal lines 212, respectively.

[0044] Specifically, the first group of power signal lines 211 can be the power signal lines for a pulse width modulation (PWM) circuit, and the second group of power signal lines 212 can be the power signal lines for a pulse amplitude modulation (PAM) circuit. Both the first group of power signal lines 211 and the second group of power signal lines 212 include one first power signal line 2111 and one second power signal line 2112. The first power signal line 2111 can be a high-level signal line VGH, and the second power signal line 2112 can be a low-level signal line VGL. In the first group of power signal lines 2111, the power signal voltage of the first power signal line 2111 is V11, and the power signal voltage of the second power signal line 2112 is V12. That is, in the power signal lines of the pulse width modulation circuit, the power signal voltage of the high-level signal line VGH is V11, and the power signal voltage of the low-level signal line VGL is V12. V11 can be +8V, and V12 can be -7V. In the second group of power signal lines 212, the power signal voltage of the first power signal line 2111 is V21, and the power signal voltage of the second power signal line 21112 is V22. That is, in the power signal lines of the pulse amplitude modulation circuit, the power signal voltage of the high-level signal line VGH is V21, and the power signal voltage of the low-level signal line VGL is V22. Here, V12 can be +3V, and V22 can be -12V. In addition, since the first power signal line 2111 is a high-level signal line VGH and the second power signal line 2112 is a low-level signal line VGL, the power signal voltage V11 (V21) of the first power signal line 2111 is greater than the power signal voltage V12 (V22) of the second power signal line 2112, that is, V11 > V12, V21 > V22. Furthermore, V11≠V21, V12≠V22. That is to say, the power signal voltage V11 of the first power signal line 2111 in the first group of power signal lines 211 is different from the power signal voltage V21 of the first power signal line 2111 in the second group of power signal lines 212. The power signal voltage V12 of the second power signal line 2112 in the first group of power signal lines 211 is different from the power signal voltage V22 of the second power signal line 2112 in the second group of power signal lines 212. The specific determination can be made according to the actual situation, and no specific restrictions are made here.

[0045] Furthermore, through this embodiment, because two different power signal lines 21 are provided with signal ranges, the electrostatic discharge circuits can each have more precise electrostatic discharge control capabilities, and the overall electrostatic discharge selectable range of the display panel can be increased, providing more options for circuit signal selection while further ensuring electrostatic discharge safety performance.

[0046] Of course, in some optional embodiments of this application, the signal range of the power signal line 21 electrically connected to the first electrostatic discharge circuit 221 may overlap with the signal range of the power signal line 21 electrically connected to the second electrostatic discharge circuit 222.

[0047] In some optional embodiments of this application, the signal range of the power signal line 21 electrically connected to the first electrostatic discharge circuit 221 and the signal range of the power signal line 21 electrically connected to the second electrostatic discharge circuit 222 may not overlap.

[0048] In some optional embodiments of this application, the signal range of the power signal line 21 electrically connected to the first electrostatic discharge circuit 221 and the signal range of the power signal line 21 electrically connected to the second electrostatic discharge circuit 222 may be one that includes the other.

[0049] Additionally, as mentioned earlier, the two second terminals 2202 of the first electrostatic discharge circuit 221 are electrically connected to the first power signal line 2111 and the second power signal line 2112 in the first group of power signal lines 211, respectively. Similarly, the two second terminals 2202 of the second electrostatic discharge circuit 222 are electrically connected to the first power signal line 2111 and the second power signal line 2112 in the second group of power signal lines 212. The first power signal line 2111 can be a high-level signal line VGH, and the second power signal line 2112 can be a low-level signal line VGL. This is to ensure that for any one of the first electrostatic discharge circuit 221 or the second electrostatic discharge circuit 222... In one case, when high-voltage static electricity exists on the first signal line 11, the electrostatic discharge circuit 22 can be activated by the high-voltage static electricity. The electrostatic discharge circuit 22 then transmits the high-voltage static electricity through one of its second terminals 2202 to the corresponding high-level voltage VGH first power signal line 2111, thereby releasing the high-voltage static electricity. Similarly, when low-voltage static electricity exists on the first signal line 11, the electrostatic discharge circuit 22 can be activated by the low-voltage static electricity. The electrostatic discharge circuit 22 then transmits the low-level voltage VGL second power signal line 2111 through its other second terminal 2202, thereby releasing the low-voltage static electricity. Thus, when different types (high-voltage or low-voltage) of static electricity exist in the panel, the electrostatic discharge circuit 22 in this application can effectively release static electricity from the first signal line 11 it is connected to, avoiding damage to the panel caused by static electricity and ensuring the normal display of the display panel.

[0050] Optionally, (V11-V21)×(V12-V22)>0.

[0051] Optionally, V11-V21 = V12-V22.

[0052] Optionally, V11-V12 = V21-V22.

[0053] Specifically, (V11-V21)×(V12-V22)>0 and V11-V21=V12-V22 are set, that is, the difference between the power signal voltage V11 of the first power signal line 2111 in the first group of power signal lines 211 and the power signal voltage V21 of the first power signal line 2111 in the second group of power signal lines 212 is equal to the difference between the power signal voltage V12 of the second power signal line 2112 in the first group of power signal lines 211 and the power signal voltage V22 of the second power signal line 2112 in the second group of power signal lines 212, and the product of the two differences is positive. In other words, when the difference between the power signal voltage V11 of the first power signal line 2111 in the first group of power signal lines 211 and the power signal voltage V21 of the first power signal line 2111 in the second group of power signal lines 212 is positive, the difference between the power signal voltage V12 of the second power signal line 2112 in the first group of power signal lines 211 and the power signal voltage V22 of the second power signal line 2112 in the second group of power signal lines 212 is also positive; when the difference between the power signal voltage V11 of the first power signal line 2111 and the power signal voltage V21 of the first power signal line 2111 in the first group of power signal lines 212 is negative, the difference between the power signal voltage V12 of the second power signal line 2112 in the first group of power signal lines 211 and the power signal voltage V22 of the second power signal line 2112 in the second group of power signal lines 212 is also negative. In this embodiment, V11 can be +8V, V12 can be -7V, V12 can be +3V, V22 can be -12V, the difference between V11 and V21 is +5V, the difference between V12 and V22 is +5V, the two differences are equal, and the product of the differences is +25V, which is a positive number.

[0054] In this embodiment, V11-V12 = V21-V22, meaning that the difference between the power signal voltage V11 of the first power signal line 2111 and the power signal voltage V12 of the second power signal line 2111 in the first group of power signal lines 211 is equal to the difference between the power signal voltage V21 of the first power signal line 2111 and the power signal voltage V22 of the second power signal line 2112 in the second group of power signal lines 212. In this embodiment, V11 can be +8V, V12 can be +3V, V12 can be -7V, and V22 can be -12V. The difference between V11 and V21 is 5V, and the difference between V12 and V22 is 5V, which are equal.

[0055] Optional, continue to refer to Figure 4As shown, the first electrostatic discharge circuit 221 includes a first transistor T1 and a second transistor T2; the control terminal and the first terminal of the first transistor T1 are both electrically connected to the first power signal line 2111 in the first group of power signal lines 211, and the second terminal of the first transistor T1 is electrically connected to the control terminal and the first terminal of the second transistor T2, and is electrically connected to the first signal line 11 as the first terminal 2201; the second terminal of the second transistor T2 is electrically connected to the second power signal line 2112 in the first group of power signal lines 211; the second electrostatic discharge circuit 222 includes a third transistor T3 and a fourth transistor T4; the control terminal and the first terminal of the third transistor T3 are both electrically connected to the first power signal line 2111 in the second group of power signal lines 212, and the second terminal of the third transistor T3 is electrically connected to the control terminal and the first terminal of the fourth transistor T4, and is electrically connected to the first signal line 11 as the first terminal 2201; the second terminal of the fourth transistor T4 is electrically connected to the second power signal line 2112 in the second group of power signal lines 212.

[0056] Among them, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be as follows: Figure 4The example uses an N-channel transistor, but a P-channel transistor can also be used; there is no restriction here. Taking the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 as N-channel transistors as an example, specifically, for the first electrostatic discharge circuit 221, when the first signal line 11 generates high-voltage electrostatic discharge, the high-voltage electrostatic discharge signal of the first signal line 11 is input to the first terminal 2201 of the first electrostatic discharge circuit 221. At this time, the first transistor T1 is turned on, and the high-voltage electrostatic discharge signal is released through the first transistor T1 to the first power signal line 2111 of the first group of power signal lines 211 with a high-level voltage VGH. When the first signal line 11 generates low-voltage electrostatic discharge, the low-voltage electrostatic discharge signal of the first signal line 11 is input to the first terminal 2201 of the first electrostatic discharge circuit 221. At this time, the second transistor T2 is turned on, and the low-voltage electrostatic discharge signal is released through the second transistor T2 to the second power signal line 2112 of the first group of power signal lines 211 with a low-level voltage VGL, thus realizing electrostatic discharge. Similarly, for the second electrostatic discharge circuit 222, when the first signal line 11 generates high-voltage static electricity, the high-voltage static electricity signal of the first signal line 11 is input to the first terminal 2201 of the second electrostatic discharge circuit 222. At this time, the third transistor T3 is turned on, and the high-voltage static electricity signal is released through the third transistor T3 to the first power signal line 2111 of the second group of power signal lines 212 with a high-level voltage VGH. When the first signal line 11 generates low-voltage static electricity, the low-voltage static electricity signal of the first signal line 11 is input to the first terminal 2201 of the second electrostatic discharge circuit 222. At this time, the fourth transistor T4 is turned on, and the low-voltage static electricity signal is released through the fourth transistor T4 to the second power signal line 2112 of the second group of power signal lines 212 with a low-level voltage VGL, thus realizing electrostatic discharge. In summary, the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 can effectively release the high-voltage and low-voltage static electricity generated in the display panel, which can avoid damage to the internal structure of the panel by static electricity, thereby ensuring the quality and performance of the display panel.

[0057] Optional, continue to refer to Figure 4 and Figure 5As shown, multiple electrostatic discharge circuits 22 are arranged along the first direction X, and the first power signal line 2111 and the second power signal line 2112 extend along the first direction X. Thus, when the two second terminals 2202 of the first electrostatic discharge circuit 221 are electrically connected to the first power signal line 2111 and the second power signal line 2112 of the first group of power signal lines 211, and when the two second terminals 2202 of the second electrostatic discharge circuit 222 are electrically connected to the first power signal line 2111 and the second power signal line 2112 of the second group of power signal lines 212, the first electrostatic discharge circuit 221 and the second electrostatic discharge circuit 222 can be arranged reasonably and compactly, effectively utilizing the area of ​​the display panel and improving the utilization rate of the display panel.

[0058] Optional, Figure 6 This is a schematic diagram of the structure of a third type of display panel provided in an embodiment of the present invention, with reference to... Figure 6 As shown, the pixel driving area 1 also includes multiple pixel circuits 12 and multiple light-emitting elements (not shown in the figure). The pixel circuits 12 are used to provide driving current to the light-emitting elements. The electrostatic discharge circuit 22 is located between the multiple pixel circuits 12 and the first edge 3 of the display panel. Specifically, the first edge 3 can be the edge of the display panel that is closest to the electrostatic discharge circuit 22.

[0059] Specifically, the pixel circuit 12 can be a pixel circuit used to provide driving current to the light-emitting element, so that the light-emitting element can emit light of different brightness according to the magnitude of the received driving current. The light-emitting element is a component used for emitting light; in this embodiment, the light-emitting element can be a micro light-emitting diode (Micro-LED). Additionally, the first edge 3 is the edge in the display panel closest to the electrostatic discharge circuit 22, as shown in the reference... Figure 6 The first edge 3 is the lower edge of the display panel. The electrostatic discharge circuit 22 is located between the multiple pixel circuits 12 and the first edge 3 of the display panel, so that the electrostatic discharge circuit 22 can release the electrostatic voltage signal normally.

[0060] Continue to refer to Figure 6 In an optional embodiment, a side trace 31 may be provided on the first edge 3. In this embodiment, the display panel is essentially a frameless display panel. A driving structure, such as a driving chip and a flexible circuit board connected to the driving motherboard, is provided on the back of the display panel. The driving structure is connected to the front of the display panel through the side trace 31 and is responsible for providing power signals, driving signals, timing signals, etc. to the display panel to control the display panel to realize the display function.

[0061] Optional, continue to refer to Figure 4 and Figure 6In the second direction Y, the first power signal line 2111 is located on the side of the electrostatic discharge circuit 22 that is close to or far from the first edge 3 of the display panel, and the second power signal line 2112 is located on the side of the electrostatic discharge circuit 22 that is close to or far from the first edge 3 of the display panel; the first edge 3 is the edge of the display panel that is closest to the electrostatic discharge circuit 22; wherein, the second direction Y is perpendicular to the first direction X.

[0062] Specifically, the first direction X and the second direction Y are perpendicular. In this embodiment, the first direction X can be a horizontal direction, and the second direction Y can be a vertical direction. In the second direction Y, the first power signal line 2111 is located on the side of the electrostatic discharge circuit 22 that is close to or far from the first edge 3 of the display panel, and the second power signal line 2112 is located on the side of the electrostatic discharge circuit 22 that is close to or far from the first edge 3 of the display panel. That is to say, the first power signal line 2111 and the second power signal line 2112 can be located on the same side or on different sides. When the first power signal line 2111 and the second power signal line 2112 are located on the same side, the first power signal line 2111 and the second power signal line 2112 can be located simultaneously on the side of the electrostatic discharge circuit 22 that is close to the first edge 3 of the display panel, or they can be located on the side of the electrostatic discharge circuit 22 that is far from the first edge 3 of the display panel. When the first power signal line 2111 and the second power signal line 2112 are located on different sides, the first power signal line 2111 can be located on the side of the electrostatic discharge circuit 22 closer to the first edge 3 of the display panel, and the second power signal line 2112 can be located on the side of the electrostatic discharge circuit 22 away from the first edge 3 of the display panel; or, the first power signal line 2111 can be located on the side of the electrostatic discharge circuit 22 away from the first edge 3 of the display panel, and the second power signal line 2112 can be located on the side of the electrostatic discharge circuit 22 closer to the first edge 3 of the display panel. The specific location can be determined according to the actual situation, and no specific restrictions are imposed here. When the first power signal line 2111 and / or the second power signal line 2112 are located on the side of the electrostatic discharge circuit 22 close to the first edge 3 of the display panel, it indicates that the first power signal line 2111 and / or the second power signal line 2112 are located between the electrostatic discharge circuit 22 and the first edge 3; when the first power signal line 2111 and / or the second power signal line 2112 are located on the side of the electrostatic discharge circuit 22 away from the first edge 3 of the display panel, it indicates that the first power signal line 2111 and / or the second power signal line 2112 are located above the electrostatic discharge circuit 22.

[0063] Understandable Figure 4 The diagram only shows an example where the first power signal line 2111 and the second power signal line 2112 are located on the same side and simultaneously on the side of the electrostatic discharge circuit 22 away from the first edge 3 of the display panel. Other cases can be determined according to... Figure 4Specific adjustments will be made.

[0064] Optional, continue to refer to Figure 4 and Figure 6 In the second direction Y, the first power signal line 2111 and the second power signal line 2112 are both located on the side of the electrostatic discharge circuit 22 away from the first edge 3 of the display panel.

[0065] Specifically, in the second direction Y, the first power signal line 2111 and the second power signal line 2112 are both located on the side of the electrostatic discharge circuit 22 away from the first edge 3 of the display panel. That is, the first power signal line 2111 and the second power signal line 2112 are located on the same side and are both located above the electrostatic discharge circuit 22 and the first edge 3.

[0066] As another specific embodiment, optionally, Figure 7 This is a schematic diagram of the structure of the fourth type of display panel provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of the fifth type of display panel provided in an embodiment of the present invention, with reference to... Figures 6 to 8 As shown, in the second direction Y, the first group of power signal lines 211 and the second group of power signal lines 212 are located on opposite sides of the electrostatic discharge circuit 22; or, in the second direction Y, the first power signal line 2111 of the first group of power signal lines 211 and the second group of power signal lines 212 is located on the first side of the electrostatic discharge circuit 22, and the second power signal line 2112 of the first group of power signal lines 211 and the second group of power signal lines 212 is located on the second side of the electrostatic discharge circuit 22.

[0067] For details, please refer to Figure 6 and Figure 7 In the second direction Y, i.e., the longitudinal direction, the first group of power signal lines 211 and the second group of power signal lines 212 are located on opposite sides of the electrostatic discharge circuit 22. That is, when both the first power signal line 2111 and the second power signal line 2112 in the first group of power signal lines 211 are located on the side of the electrostatic discharge circuit 22 away from the first edge 3, correspondingly, both the first power signal line 2111 and the second power signal line 2112 in the second group of power signal lines 212 are located on the side of the electrostatic discharge circuit 22 closer to the first edge 3; or, when both the first power signal line 2111 and the second power signal line 2112 in the first group of power signal lines 211 are located on the side of the electrostatic discharge circuit 22 closer to the first edge 3, correspondingly, both the first power signal line 2111 and the second power signal line 2112 in the second group of power signal lines 212 are located on the side of the electrostatic discharge circuit 22 away from the first edge 3. This does not affect the normal release of electrostatic voltage signals by the electrostatic discharge circuit 22, ensuring the performance of the display panel. It should be noted that... Figure 7This example only illustrates that when both the first power signal line 2111 and the second power signal line 2112 in the first group of power signal lines 211 are located on the side of the electrostatic discharge circuit 22 away from the first edge 3, and when both the first power signal line 2111 and the second power signal line 2112 in the second group of power signal lines 212 are located on the side of the electrostatic discharge circuit 22 closer to the first edge 3, the other case described above can be... Figure 7 Based on the above, appropriate adjustments have been made, but will not be shown in detail here.

[0068] Similarly, refer to Figure 6 and Figure 8 In the second direction Y, i.e., the longitudinal direction, the first power signal line 2111 of the first group of power signal lines 211 and the second group of power signal lines 212 is located on the first side of the electrostatic discharge circuit 22, and the second power signal line 2112 of the first group of power signal lines 211 and the second group of power signal lines 212 is located on the second side of the electrostatic discharge circuit 22. The first side can be the side of the electrostatic discharge circuit 22 away from the first edge 3, and the second side can be the side of the electrostatic discharge circuit 22 closer to the first edge 3; or, the first side can be the side of the electrostatic discharge circuit 22 closer to the first edge 3, and the second side can be the side of the electrostatic discharge circuit 22 away from the first edge 3. That is, when the first power signal line 2111 of the first group of power signal lines 211 and the second group of power signal lines 212 is located on the side of the electrostatic discharge circuit 22 away from the first edge 3, the second power signal line 2112 of the first group of power signal lines 211 and the second group of power signal lines 212 is located on the side of the electrostatic discharge circuit 22 closer to the first edge 3. When the first power signal line 2111 of the first group of power signal lines 211 and the second group of power signal lines 212 is located on the side of the electrostatic discharge circuit 22 closer to the first edge 3, the second power signal line 2112 of the first group of power signal lines 211 and the second group of power signal lines 212 is located on the side of the electrostatic discharge circuit 22 away from the first edge 3. This does not affect the normal release of electrostatic voltage signals by the electrostatic discharge circuit 22, ensuring the performance of the display panel. It should be noted that... Figure 8 This example only illustrates that when the first power signal line 2111 of the first group of power signal lines 211 and the second group of power signal lines 212 is located on the side of the electrostatic discharge circuit 22 away from the first edge 3, the second power signal line 2112 of the first group of power signal lines 211 and the second group of power signal lines 212 is located on the side of the electrostatic discharge circuit 22 closer to the first edge 3. For another situation described above, it is possible to... Figure 8 Based on the above, appropriate adjustments have been made, but will not be shown in detail here.

[0069] As another specific embodiment, optionally, Figure 9 This is a schematic diagram of the structure of the sixth type of display panel provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of the circuit routing structure of the sixth type of display panel provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of the structure of the seventh type of display panel provided in an embodiment of the present invention, with reference to... Figure 6 , Figures 9 to 11 As shown, in the first direction X, there are two adjacent first electrostatic discharge circuits 221, and the first signal lines 11 connected to the two adjacent first electrostatic discharge circuits 221 are respectively located on opposite sides of the two first electrostatic discharge circuits 221; in the first direction X, there are two adjacent second electrostatic discharge circuits 222, and the first signal lines 11 connected to the two adjacent second electrostatic discharge circuits 222 are respectively located on opposite sides of the two second electrostatic discharge circuits 222.

[0070] For details, please refer to Figure 9 and Figure 11 The first electrostatic discharge circuit 221 on the left half is shown, and Figure 9 The power signal line 21 is located on the side of the electrostatic discharge circuit 22 away from the first edge 3. Figure 11 The power signal line 21 is located on the side of the electrostatic discharge circuit 22 near the first edge 3. In the first direction X, i.e., the lateral direction, when the electrostatic voltage signal on the first signal line 11 is released from different power signal lines 21 by the electrostatic discharge circuit 22, the arrangement of the electrostatic discharge circuits 22 can also be such that two first electrostatic discharge circuits 221 are arranged adjacently, and the first signal lines 11 connected to the two adjacent first electrostatic discharge circuits 221 are respectively located on opposite sides of the two first electrostatic discharge circuits 221. That is, two adjacent first electrostatic discharge circuits 221 are arranged back-to-back between the corresponding two first signal lines 11. At this time, the first ends 2201 of the two first electrostatic discharge circuits 221 are electrically connected back-to-back to the corresponding first signal lines 11, and the two second ends 2202 are electrically connected to the first power signal line 2111 in the first group of power signal lines 211, and can share a first power signal line 2111. This can reduce the number of traces and reduce the space occupancy of the electrostatic discharge circuit 22.

[0071] Similarly, refer to Figure 9 and Figure 11 The second electrostatic discharge circuit 222 on the right half of the diagram is shown, and Figure 9 The power signal line 21 is located on the side of the electrostatic discharge circuit 22 away from the first edge 3. Figure 11The power signal line 21 is located on the side of the electrostatic discharge circuit 22 near the first edge 3. In the first direction X, i.e., the lateral direction, when the electrostatic voltage signal on the first signal line 11 is released from different power signal lines 21 by the electrostatic discharge circuit 22, the arrangement of the electrostatic discharge circuits 22 can also be such that two second electrostatic discharge circuits 222 are arranged adjacently, and the first signal lines 11 connected to the two adjacent second electrostatic discharge circuits 222 are respectively located on opposite sides of the two second electrostatic discharge circuits 222. That is, two adjacent second electrostatic discharge circuits 222 are arranged back-to-back between the corresponding two first signal lines 11. At this time, the first ends 2201 of the two second electrostatic discharge circuits 222 are electrically connected back-to-back to the corresponding first signal lines 11, and the two second ends 2202 are electrically connected to the first power signal line 2111 in the second group of power signal lines 212, and can share a first power signal line 2111. This can reduce the number of traces and reduce the space occupancy of the electrostatic discharge circuit 22.

[0072] In an optional embodiment of the present invention, the display panel may further include multiple pixel circuits 12 and multiple light-emitting elements (not shown in the figure); the same pixel circuit 12 includes a first module and a second module; multiple first signal lines 11 include first sub-signal lines 111 and second sub-signal lines 112, the first sub-signal lines 111 are electrically connected to the first electrostatic discharge circuit 221 and the first module respectively, and the second sub-signal lines 112 are electrically connected to the second electrostatic discharge circuit 222 and the second module respectively. Specifically, the light-emitting element may be a micro light-emitting diode, and the first module and the second module may be a circuit structure composed of transistors. Specifically, the first module may be a pulse width modulation circuit (PWM), and the second module may be a pulse amplitude modulation circuit (PAM).

[0073] Specifically, refer to Figure 1 , Figure 4 and Figure 6 As shown, the pixel driving area 1 also includes multiple pixel circuits 12 and multiple light-emitting elements. The pixel circuit 12 includes a pulse width modulation circuit (PWM) and a pulse amplitude modulation circuit (PAM). The pixel circuit 12 is used to provide driving current to the light-emitting elements. The multiple first signal lines 11 include a first sub-signal line 111 and a second sub-signal line 112. The first sub-signal line 111 is electrically connected to the first electrostatic discharge circuit 221 and the pulse width modulation circuit (PWM) respectively. The second sub-signal line 112 is electrically connected to the second electrostatic discharge circuit 222 and the pulse width modulation circuit (PWM) respectively.

[0074] The pixel circuit 12 can be a pixel circuit, and in this embodiment, the pixel circuit 12 includes a pulse width modulation (PWM) circuit and a pulse amplitude modulation (PAM) circuit. The pixel circuit 12 is used to provide a driving current to the light-emitting element under the control of the PWM circuit and the PAM circuit. The PWM circuit can be used to control the pulse width of the driving current, and the PAM circuit can be used to control the pulse amplitude of the driving current, so that the light-emitting element can emit light of different brightness according to the magnitude of the received driving current.

[0075] Specifically, since the pixel circuit 12 includes a pulse width modulation circuit (PWM) and a pulse amplitude modulation circuit (PAM), and the power supply signal voltages required by the PWM and PAM circuits are different, when electrostatic discharge is performed on the electrostatic voltage signals generated by the PWM and PAM circuits, the multiple first signal lines 11 can be divided into first sub-signal lines 111 and second sub-signal lines 112. The first sub-signal lines 111 are electrically connected to the first electrostatic discharge circuit 221 and the PWM circuit, respectively, and the second sub-signal lines 112 are electrically connected to the second electrostatic discharge circuit 222 and the PWM circuit, respectively. Thus, when electrostatic discharge is performed on the electrostatic voltage signal generated by the pulse width modulation circuit (PWM), the electrostatic voltage signal can be transmitted to the first electrostatic discharge circuit 221 through the first sub-signal line 111, turning on the first transistor T1 and the second transistor T2 in the first electrostatic discharge circuit 221. At this time, the electrostatic voltage signal can be transmitted through the first electrostatic discharge circuit 221 to the first power signal line 2111 and the second power signal line 2112 of the first group of power signal lines 211, and the electrostatic voltage signal is released through the first power signal line 2111 and the second power signal line 2112 of the first group of power signal lines 211, thereby realizing the rapid release of the electrostatic voltage signal generated by the pulse width modulation circuit (PWM).

[0076] Similarly, when electrostatic discharge is performed on the electrostatic voltage signal generated by the pulse amplitude modulation circuit (PAM), the electrostatic voltage signal can be transmitted to the second electrostatic discharge circuit (222) through the second sub-signal line 112, turning on the third transistor T3 and the fourth transistor T4 in the second electrostatic discharge circuit (222). At this time, the electrostatic voltage signal can be transmitted through the second electrostatic discharge circuit (222) to the first power signal line 2111 and the second power signal line 2112 of the second group of power signal lines (212), and the electrostatic voltage signal is released through the first power signal line 2111 and the second power signal line 2112 of the second group of power signal lines (212), thus realizing the rapid release of the electrostatic voltage signal generated by the pulse amplitude modulation circuit (PAM).

[0077] Optional, continue to refer to Figure 1 and Figure 4 The first sub-signal line 111 is electrically connected to the signal line that needs electrostatic discharge in the pulse width modulation circuit (PWM); the second sub-signal line 112 is electrically connected to the signal line that needs electrostatic discharge in the pulse amplitude modulation circuit (PAM).

[0078] Optional, continue to refer to Figure 1 and Figure 4 The same first sub-signal line 111 is electrically connected to one of the first scan signal line S1, the second scan signal line S2, the light emission control signal line EMIT, and the sweep frequency signal line SWEEP of the pulse width modulation circuit PWM; the same second sub-signal line 112 is electrically connected to one of the first scan signal line S1, the second scan signal line S2, the light emission control signal line EMIT, and the data signal line DATA of the pulse amplitude modulation circuit PAM.

[0079] Specifically, when performing electrostatic discharge on the electrostatic voltage signal generated by the pulse width modulation (PWM) circuit, the first sub-signal line 111 needs to be electrically connected to the signal line in the PWM circuit that requires electrostatic discharge, as shown in the reference. Figure 1 In the pulse width modulation (PWM) circuit, the signal lines requiring electrostatic discharge include the first scan signal line S1, the second scan signal line S2, the light emission control signal line EMIT, and the sweep frequency signal line SWEEP. These signals are independent of each other. Therefore, the first scan signal line S1, the second scan signal line S2, the light emission control signal line EMIT, and the sweep frequency signal line SWEEP need to be electrically connected via independent first sub-signal lines 111. For example, if there are four signal lines requiring electrostatic discharge in the PWM circuit, four first sub-signal lines 111 can be set up to be electrically connected to the first scan signal line S1, the second scan signal line S2, the light emission control signal line EMIT, and the sweep frequency signal line SWEEP, respectively. The electrostatic voltage signal generated by the PWM circuit is then transmitted to the first group of power signal lines 211 for electrostatic discharge via the first electrostatic discharge circuit 221.

[0080] Similarly, when performing electrostatic discharge on the electrostatic voltage signal generated by the pulse amplitude modulation circuit (PAM), the second sub-signal line 112 needs to be electrically connected to the signal line in the PAM circuit that needs electrostatic discharge, as shown in the reference. Figure 1The signal lines requiring electrostatic discharge in the pulse amplitude modulation circuit (PAM) include the first scan signal line S1, the second scan signal line S2, the light emission control signal line EMIT, and the data signal line DATA. These lines are independent of each other. Therefore, they need to be electrically connected via independent second sub-signal lines 112. For example, if there are four signal lines requiring electrostatic discharge in the PAM, four second sub-signal lines 112 can be connected to the first scan signal line S1, the second scan signal line S2, the light emission control signal line EMIT, and the data signal line DATA, respectively. The electrostatic voltage signal generated by the PAM is then transmitted to the second set of power signal lines 212 via the second electrostatic discharge circuit 222 for electrostatic discharge.

[0081] Optionally, the display panel of this application includes different circuits, wherein the lines in the first group of power signal lines 211 and the lines in the second group of power signal lines 212 come from different circuits; that is, the first power signal line 2111 and the second power signal line 2112 in the electrostatic discharge circuit 22 can reuse the signal lines in the driving circuit of the display panel; this can achieve the technical effects of the above embodiments and simplify the display panel.

[0082] For example, the driving circuit in the circuit includes a first driving circuit and a second driving circuit, and the first power supply terminal VGH and the second power supply terminal VGL in the first driving circuit and the second driving circuit are respectively multiplexed to different electrostatic discharge circuits 22.

[0083] Optional, Figure 12 This is a schematic diagram illustrating the connection relationship between a shift register circuit, a power signal line, an electrostatic discharge circuit, and a pixel circuit, provided in an embodiment of the present invention. (Refer to...) Figure 2 and 12 As shown, the pixel driving area 1 also includes multiple cascaded first shift register circuits 14 and multiple cascaded second shift register circuits 15; both the first shift register circuit 14 and the second shift register circuit 15 include a first power supply terminal VGH and a second power supply terminal VGL; in the first shift register circuit 14, the first power supply terminal VGH and the second power supply terminal VGL are electrically connected to the first power supply signal line 2111 and the second power supply signal line 2112 in the first group of power supply signal lines 211, respectively; in the second shift register circuit 15, the first power supply terminal VGH and the second power supply terminal VGL are electrically connected to the first power supply signal line 2111 and the second power supply signal line 2112 in the second group of power supply signal lines 212, respectively.

[0084] The first shift register circuit 14 and the second shift register circuit 15 are used to provide scanning signals to the correspondingly connected pixel circuit 12 to drive the pixel circuit 12 to operate. It can be understood that the shift register circuit in this embodiment is... Figure 2 The driving circuit shown in the figure.

[0085] Specifically, power supply voltages are provided to the first shift register circuit 14 and the second shift register circuit 15 through the first power supply terminal VGH and the second power supply terminal VGL. The power supply voltages at the first power supply terminals VGH and VGL in the first shift register circuit 14 are different from those at the second power supply terminals VGH and VGL in the second shift register circuit 15. After providing power supply voltages to the first shift register circuit 14 and the second shift register circuit 15, different pulse signals can be output under the control of the clock signal, for example... Figure 2 The output pulse signal is a scanning pulse signal. Furthermore, in the first shift register circuit 14, by electrically connecting the first power supply terminal VGH and the second power supply terminal VGL to the first power supply signal line 2111 and the second power supply signal line 2112 in the first group of power supply signal lines 211 respectively, the electrostatic voltage signal of the first sub-signal line 111 can be input to the first power supply signal line 2111 and the second power supply signal line 2112 in the first group of power supply signal lines 211 after passing through the first electrostatic discharge circuit 221, that is, input to the first power supply terminal VGH and the second power supply terminal VGL, and finally electrostatically discharged through the first power supply terminal VGH and the second power supply terminal VGL. Similarly, in the second shift register circuit 15, by electrically connecting the first power supply terminal VGH and the second power supply terminal VGL to the first power supply signal line 2111 and the second power supply signal line 2112 in the second group of power supply signal lines 212 respectively, the electrostatic voltage signal of the second sub-signal line 112 can be input to the first power supply signal line 2111 and the second power supply signal line 2112 in the second group of power supply signal lines 212 after passing through the second electrostatic discharge circuit 222, that is, input to the first power supply terminal VGH and the second power supply terminal VGL, and finally electrostatic discharge of the electrostatic voltage signal through the first power supply terminal VGH and the second power supply terminal VGL, ensuring that the electrostatic discharge circuit 22 can work normally and avoiding leakage during the non-electrostatic discharge stage.

[0086] It should be noted that, Figure 2 Only one shift register circuit is shown as an example, whose output pulse signal is a scan pulse signal, except... Figure 2 The shift register circuit shown can be further configured with other shift register circuits to achieve the output of other scan signals. The specific configuration can be tailored to the actual situation, and no specific limitations are imposed here. Additionally, Figure 12This diagram is only used to show the corresponding connection relationship between the shift register circuit (first shift register circuit 14 and second shift register circuit 15), the pixel circuit 12 (including pulse width modulation circuit PWM and pulse amplitude modulation circuit PAM), the power signal line 21, and the electrostatic discharge circuit 22 (first electrostatic discharge circuit 221 and second electrostatic discharge circuit 222). The specific location and number of the shift register circuit, pixel circuit 12, and electrostatic discharge circuit 22 are only examples. Those skilled in the art can select and design according to actual needs, and no restrictions are imposed here.

[0087] Optional, see reference Figure 1 , Figure 2 and Figure 6 The pixel driving area 1 also includes multiple pixel circuits 12 and multiple light-emitting elements. The pixel circuits 12 are used to provide driving current to the light-emitting elements. The pixel circuits 12 include a pulse width modulation circuit (PWM) and a pulse amplitude modulation circuit (PAM). The output terminal of the first shift register circuit 14 is electrically connected to the pulse width modulation circuit (PWM), and the output terminal of the second shift register circuit 15 is electrically connected to the pulse amplitude modulation circuit (PAM).

[0088] Specifically, when a pulse signal is input to the pulse width modulation circuit (PWM), the output terminal of the first shift register circuit 14 can be electrically connected to the PWM circuit, so that the pulse signals output by the first power supply terminal VGH and the second power supply terminal VGL through the first shift register circuit 14 can be input to the PWM circuit. If the PWM circuit requires multiple signal lines for electrostatic discharge, multiple first shift register circuits 14 need to be set up, and the pulse signals output by each first shift register circuit 14 are electrically connected to the corresponding signal lines of the PWM circuit that require electrostatic discharge, so as to realize the pulse signal input to the PWM circuit.

[0089] Similarly, when a pulse signal is input to the pulse amplitude modulation circuit (PAM), the output terminal of the second shift register circuit 15 can be electrically connected to the PAM, so that the pulse signals output by the first power supply terminal VGH and the second power supply terminal VGL through the second shift register circuit 15 can be input to the PAM. If the PAM requires multiple signal lines for electrostatic discharge, multiple second shift register circuits 15 need to be set up, and the pulse signals output by each second shift register circuit 15 are electrically connected to the corresponding signal lines of the PAM that require electrostatic discharge, so as to realize the pulse signal input to the PAM.

[0090] Through the above embodiments, since the first shift register circuit 14 receives the power signals of the first group of power signal lines 211, namely the high-level power signal PWM_VGH and the low-level power signal PWM_VGL, it provides a drive signal to the pulse width modulation circuit PWM. Its output terminal is electrically connected to the pulse width modulation circuit PWM. The first signal line 11 in the pulse width modulation circuit PWM is electrically connected to the first electrostatic discharge circuit 221 to realize electrostatic discharge. The first electrostatic discharge circuit 221 is also electrically connected to the first group of power signal lines 211 to perform electrostatic discharge. Thus, the first shift register circuit 14, the pulse width modulation circuit (PWM) in the pixel circuit, the first electrostatic discharge circuit 221, and the first group of power signal lines 211 are connected in a corresponding sequence. The first shift register circuit 14 and the first electrostatic discharge circuit 221 reuse the same group of power signal lines 21. At the same time, the voltage domains of the drive signal on the first signal line 11 and the power signal on the first group of power signal lines 211 connected to the two ends of the first electrostatic discharge circuit 221 are matched. Therefore, when there is no static electricity, the first electrostatic discharge circuit 221 can be normally in the off state. The switching state of the first electrostatic discharge circuit 221 will not be affected by the voltage domain mismatch. This ensures that the first electrostatic discharge circuit 221 does not interfere with the first signal line 11 in the non-static state, and can effectively release the static electricity on the first signal line 11 in the static state.

[0091] Similarly, the second shift register circuit 15 receives power signals from the second set of power signal lines 212, namely the high-level power signal PAM_VGH and the low-level power signal PAM_VGL, and provides drive signals to the pulse amplitude modulation circuit PAM. Its output terminal is electrically connected to the pulse amplitude modulation circuit PAM. The first signal line 11 in the pulse amplitude modulation circuit PAM is electrically connected to the second electrostatic discharge circuit 222 to realize electrostatic discharge. The second electrostatic discharge circuit 222 is also electrically connected to the second set of power signal lines 211 to perform electrostatic discharge. Thus, the second shift register circuit 15, the pulse amplitude modulation circuit PAM in the pixel circuit, the second electrostatic discharge circuit 222, and the second set of power signal lines 212 realize... Correspondingly, the second shift register circuit 15 and the second electrostatic discharge circuit 222 share the same set of power signal lines. At the same time, this ensures that the voltage domains of the drive signal on the first signal line 11 and the power signal on the first set of power signal lines 212 connected to the two ends of the second electrostatic discharge circuit 222 are compatible. Thus, in the absence of static electricity, the second electrostatic discharge circuit 222 can be normally in the off state, and the switching state of the first electrostatic discharge circuit 221 will not be affected by the voltage domain mismatch. This ensures that the first electrostatic discharge circuit 221 does not interfere with the first signal line 11 in the non-static state, and can effectively release the static electricity on the first signal line 11 in the static state.

[0092] In other words, the first module, the first driving circuit, and the first electrostatic discharge circuit 221 mentioned in the above embodiments are a set of combinations; the second module, the second driving circuit, and the second electrostatic discharge circuit 222 are a set of combinations. For example, VGH and VGL, which are electrically connected in the first driving circuit, affect or determine the magnitude of some signals in the first module, and also serve as the signal lines in the first module within the first electrostatic discharge circuit 221 for electrostatic protection. This achieves a correlation and match between the signal magnitude on the signal lines in the first module and the electrostatic protection range of the electrostatic discharge circuit 22. Thus, electrostatic protection can be achieved more accurately without adding new signals (VGH / VGL).

[0093] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, with reference to... Figure 13 The display device includes the display panel 1 provided in any embodiment of the present invention. Therefore, the display device provided in the embodiments of the present invention has the corresponding beneficial effects of the display panel provided in the embodiments of the present invention, which will not be elaborated here. For example, the display device may be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device, and the embodiments of the present invention do not limit it in this regard.

[0094] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises a plurality of first signal lines, a plurality of power signal lines and a plurality of electrostatic discharge circuits. The plurality of electrostatic discharge circuits comprises a first electrostatic discharge circuit and a second electrostatic discharge circuit; the first electrostatic discharge circuit and the second electrostatic discharge circuit each comprise a first end and a second end; the first ends of the first electrostatic discharge circuit and the second electrostatic discharge circuit are respectively electrically connected to different first signal lines; the second ends of the first electrostatic discharge circuit and the second electrostatic discharge circuit are respectively electrically connected to different power signal lines. The plurality of power signal lines comprises a first group of power signal lines and a second group of power signal lines; the first group of power signal lines and the second group of power signal lines comprise a first power signal line and a second power signal line. In the first group of power signal lines, the power signal voltage of the first power signal line is V11, and the power signal voltage of the second power signal line is V12; in the second group of power signal lines, the power signal voltage of the first power signal line is V21, and the power signal voltage of the second power signal line is V22; wherein V11>V12, V21>V22, V11≠V21, and V12≠V22. The two second ends of the first electrostatic discharge circuit are respectively electrically connected to the first power signal line and the second power signal line in the first group of power signal lines; the two second ends of the second electrostatic discharge circuit are respectively electrically connected to the first power signal line and the second power signal line in the second group of power signal lines.

2. The display panel of claim 1, wherein, In the first electrostatic discharge circuit and the second electrostatic discharge circuit, the first end is an electrostatic input end, and the second end is an electrostatic output end, and the number of the electrostatic output ends is at least two.

3. The display panel of claim 1, wherein, (V11-V21)×(V12-V22)>0.

4. The display panel of claim 1, wherein, V11-V21=V12-V22.

5. The display panel of claim 1, wherein, V11-V12=V21-V22.

6. The display panel of claim 1, wherein The first electrostatic discharge circuit comprises a first transistor and a second transistor. The control end and the first end of the first transistor are electrically connected to the first power signal line in the first group of power signal lines, the second end of the first transistor is electrically connected to the control end and the first end of the second transistor, and the second end of the first transistor is electrically connected to the first signal line as the first end; the second end of the second transistor is electrically connected to the second power signal line in the first group of power signal lines. The second electrostatic discharge circuit comprises a third transistor and a fourth transistor. The control end and the first end of the third transistor are electrically connected to the first power signal line in the second group of power signal lines, the second end of the third transistor is electrically connected to the control end and the first end of the fourth transistor, and the second end of the third transistor is electrically connected to the first signal line as the first end; the second end of the fourth transistor is electrically connected to the second power signal line in the second group of power signal lines.

7. The display panel of claim 1, wherein The plurality of electrostatic discharge circuits are arranged along a first direction, and the first power signal line and the second power signal line extend along the first direction.

8. The display panel of claim 7, wherein, in a second direction, the first power signal line is located on a side of the electrostatic discharge circuit close to or away from a first edge of the display panel, and the second power signal line is located on a side of the electrostatic discharge circuit close to or away from the first edge of the display panel; the first edge is an edge of the display panel closest to the electrostatic discharge circuit; wherein the second direction is perpendicular to the first direction.

9. The display panel of claim 8, wherein, in the second direction, the first power signal line and the second power signal line are both located on a side of the electrostatic discharge circuit away from the first edge of the display panel.

10. The display panel of claim 9, wherein, in the second direction, the first group of power signal lines and the second group of power signal lines are respectively located on two sides of the electrostatic discharge circuit away from each other; or, in the second direction, the first power signal line in the first group of power signal lines and the second group of power signal lines is located on a first side of the electrostatic discharge circuit, and the second power signal line in the first group of power signal lines and the second group of power signal lines is located on a second side of the electrostatic discharge circuit.

11. The display panel of claim 7, wherein, in the first direction, two of the first electrostatic discharge circuits are adjacent, and the first signal lines connected to the two adjacent first electrostatic discharge circuits are respectively located on two sides of the two first electrostatic discharge circuits away from each other; in the first direction, two of the second electrostatic discharge circuits are adjacent, and the first signal lines connected to the two adjacent second electrostatic discharge circuits are respectively located on two sides of the two second electrostatic discharge circuits away from each other.

12. The display panel of claim 1, wherein, The display panel further comprises a plurality of pixel circuits and a plurality of light emitting elements; The pixel circuit comprises a pulse width modulation circuit and a pulse amplitude modulation circuit; The plurality of first signal lines comprise a first sub-signal line and a second sub-signal line, the first sub-signal line is electrically connected to the first electrostatic discharge circuit and the pulse width modulation circuit, and the second sub-signal line is electrically connected to the second electrostatic discharge circuit and the pulse width modulation circuit.

13. The display panel of claim 12, wherein, The first sub-signal line is electrically connected to a signal line in the pulse width modulation circuit requiring electrostatic discharge; The second sub-signal line is electrically connected to a signal line in the pulse amplitude modulation circuit requiring electrostatic discharge.

14. The display panel of claim 13, wherein, The same first sub-signal line is electrically connected to one of a first scan signal line, a second scan signal line, a light emitting control signal line, or a frequency sweeping signal line of the pulse width modulation circuit; The same second sub-signal line is electrically connected to one of a first scan signal line, a second scan signal line, a light emitting control signal line, or a data signal line of the pulse amplitude modulation circuit.

15. The display panel of claim 1, wherein, The display panel further comprises a plurality of first shift register circuits and a plurality of second shift register circuits which are cascaded with each other. The first shift register circuit and the second shift register circuit each comprise a first power supply end and a second power supply end; in the first shift register circuit, the first power supply end and the second power supply end are electrically connected with the first power supply signal line and the second power supply signal line in the first group of power supply signal lines respectively; in the second shift register circuit, the first power supply end and the second power supply end are electrically connected with the first power supply signal line and the second power supply signal line in the second group of power supply signal lines respectively.

16. The display panel of claim 15, wherein, The display panel further comprises a plurality of pixel circuits and a plurality of light emitting elements; the pixel circuit comprises a pulse width modulation circuit and a pulse amplitude modulation circuit. The output end of the first shift register circuit is electrically connected with the pulse width modulation circuit, and the output end of the second shift register circuit is electrically connected with the pulse amplitude modulation circuit.

17. The display panel of claim 1, wherein, The display panel further comprises a plurality of pixel circuits and a plurality of light emitting elements. The electrostatic discharge circuit is located between the plurality of pixel circuits and the first edge of the display panel.

18. The display panel of claim 17, wherein, The first edge is provided with a side edge trace.

19. The display panel of claim 1, wherein, The signal range of the power supply signal line electrically connected with the first electrostatic discharge circuit is different from the signal range of the power supply signal line electrically connected with the second electrostatic discharge circuit.

20. The display panel of claim 1, wherein, The display panel further comprises a plurality of pixel circuits and a plurality of light emitting elements. The same pixel circuit comprises a first module and a second module. The plurality of first signal lines comprise a first sub-signal line and a second sub-signal line; the first sub-signal line is electrically connected with the first electrostatic discharge circuit and the first module respectively, and the second sub-signal line is electrically connected with the second electrostatic discharge circuit and the second module respectively.

21. The display panel of claim 1, wherein, The display panel further comprises a plurality of light emitting elements, and the light emitting element is a micro light emitting diode.

22. A display device comprising: The display panel comprises any one of claims 1-21. The display panel comprises any one of claims 1-21.

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