Quadrature Voltage Controlled Oscillator (QVCO) with Improved Phase Noise and Quadrature Imbalance Tradeoff

Abstract

Apparatus and method for generating multiple oscillation signals. An example circuit generally includes a first voltage controlled oscillator (VCO) circuit and a second VCO circuit having a differential bias input coupled to a differential output of the first VCO circuit. At least one of the first VCO circuit or the second VCO circuit generally includes: a pair of cross-coupled transistors, the pair of cross-coupled transistors including a first transistor and a second transistor; a first inductive element coupled between a first node and a drain of the first transistor; a second inductive element coupled between the first node and the drain of the second transistor; a third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node; and a fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Patent Application No. 17 / 650,834, filed on February 11, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits and, more particularly, to circuits for generating multiple oscillating signals, such as quadrature voltage controlled oscillators (QVCOs). Background Art

[0004] Wireless communication networks are widely deployed to provide various communication services, such as telephone, video, data, messaging, broadcast, etc. A wireless communication network may include multiple base stations that can support communications for multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. A downlink (or forward link) refers to a communication link from a base station to a mobile station, while an uplink (or reverse link) refers to a communication link from a mobile station to a base station. A base station may send data and control information to a mobile station on a downlink, and / or may receive data and control information from a mobile station on an uplink.

[0005] In order to send or receive data and / or control information, the radio frequency front end of the base station and / or mobile station may include one or more frequency synthesizers to generate oscillating signals for up-converting baseband signals and down-converting radio frequency (RF) signals. At least one of the frequency synthesizers may include a voltage controlled oscillator (VCO) for tuning the oscillating signal to different frequencies. In some cases, a quadrature local oscillator (LO) may be used to drive a mixer in an in-phase / quadrature (IQ) based radio. One way in which a quadrature oscillating signal may be generated is by using a quadrature VCO (QVCO). Summary of the invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single aspect of which is solely responsible for its desired characteristics. Without limiting the scope of the present disclosure as expressed in the appended claims, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description of the Invention," one will understand how the features of the present disclosure provide the advantages described herein.

[0007] Certain aspects of the present disclosure relate generally to techniques and apparatus for generating multiple oscillating signals.

[0008] Certain aspects provide a circuit for generating an oscillating signal. The circuit generally includes a first voltage controlled oscillator (VCO) circuit and a second VCO circuit, the second VCO circuit having a differential bias input coupled to a differential output of the first VCO circuit. At least one of the first VCO circuit or the second VCO circuit generally includes: a pair of cross-coupled transistors, the pair of cross-coupled transistors including a first transistor and a second transistor, wherein the first transistor has a gate coupled to a drain of the second transistor, and wherein the second transistor has a gate coupled to the drain of the first transistor; a first inductive element, the first inductive element coupled between a first node and the drain of the first transistor; a second inductive element, the second inductive element coupled between the first node and the drain of the second transistor; a third transistor, the third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node; and a fourth transistor, the fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node.

[0009] Certain aspects provide a method for generating multiple oscillation signals. The method generally includes: generating a first oscillation signal using a first VCO circuit; biasing a second VCO circuit using the first oscillation signal; and generating a second oscillation signal using the second VCO circuit. At least one of the first VCO circuit or the second VCO circuit generally includes: a pair of cross-coupled transistors, the pair of cross-coupled transistors including a first transistor and a second transistor, wherein the first transistor has a gate coupled to the drain of the second transistor, and wherein the second transistor has a gate coupled to the drain of the first transistor; a first inductive element, the first inductive element coupled between a first node and the drain of the first transistor; a second inductive element, the second inductive element coupled between the first node and the drain of the second transistor; a third transistor, the third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node; and a fourth transistor, the fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description briefly summarized above may be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the specification may admit to other equally effective aspects.

[0011] Figure 1 is an illustration of an example wireless communication network in which aspects of the present disclosure may be practiced.

[0012] Figure 2 is a block diagram of an example access point (AP) and example user terminals in which aspects of the present disclosure may be practiced.

[0013] Figure 3 is a block diagram of example transceiver circuitry in which aspects of the present disclosure may be practiced.

[0014] Figure 4 is a block diagram of an example quadrature voltage controlled oscillator (QVCO) in which aspects of the present disclosure may be practiced.

[0015] Fig. 5A is a schematic diagram of an example VCO circuit for a QVCO according to certain aspects of the present disclosure.

[0016] Figure 5B is a schematic diagram of an example VCO circuit for a QVCO with selectable impedance according to certain aspects of the present disclosure.

[0017] Figure 6 is a schematic diagram of an example QVCO according to certain aspects of the present disclosure.

[0018] Figure 7 is a flow chart illustrating example operations for generating a plurality of oscillation signals in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0019] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms, and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. Instead, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings herein, it should be appreciated by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functionality, or structure and functionality other than the various aspects of the disclosure set forth herein or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the present claim.

[0020] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0022] Example Wireless System

[0023] Figure 1 A wireless communication system 100 is illustrated with an access point 110 and a user terminal 120 in which aspects of the present disclosure may be practiced. Figure 1 Only one access point 110 is shown in FIG. An access point (AP) is typically a fixed station that communicates with a user terminal, and may also be referred to as a base station (BS), an evolved Node B (eNB), or some other term. A user terminal (UT) may be fixed or mobile, and may also be referred to as a mobile station (MS), an access terminal, a user equipment (UE), a station (STA), a client, a wireless device, or some other term. A user terminal may be a wireless device such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet computer, a personal computer, and the like.

[0024] Access point 110 can communicate with one or more user terminals 120 on downlink and uplink at any given moment. The downlink (i.e., forward link) is the communication link from the access point to the user terminal, and the uplink (i.e., reverse link) is the communication link from the user terminal to the access point. A user terminal can also communicate peer to peer with another user terminal. System controller 130 couples to the access point and provides coordination and control for the access point.

[0025] The system 100 uses multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. The access point 110 may be equipped with multiple (N ap A group of (N) antennas can be used to implement transmit diversity for downlink transmission and / or receive diversity for uplink transmission. u The selected user terminals 120 may receive downlink transmissions and send uplink transmissions. Each selected user terminal may send user-specific data to and / or receive user-specific data from the access point. Typically, each selected user terminal may be equipped with one or more antennas (i.e., N ut ≥1). N u The selected user terminals may have the same number of antennas, or different numbers of antennas.

[0026] The wireless system 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The system 100 may also transmit using a single carrier or multiple carriers. Each user terminal 120 may be equipped with a single antenna (e.g., to reduce costs) or multiple antennas (e.g., where additional costs can be supported). In certain aspects of the present disclosure, the access point 110 and / or the user terminal 120 may include a circuit for generating multiple oscillation signals (e.g., a quadrature voltage controlled oscillator (QVCO)), as described in more detail herein.

[0027] Figure 2 FIG. 1 is a block diagram showing an access point 110 and two user terminals 120m and 120x in a wireless system 100. The access point 110 is equipped with N ap The user terminal 120m is equipped with N antennas 224a to 224ap. ut,m antennas 252ma through 252mu, and user terminal 120x is equipped with N ut,x The access point 110 is a transmitting entity for the downlink and a receiving entity for the uplink. Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a "transmitting entity" is an independently operated device or equipment capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated device or equipment capable of receiving data via a frequency channel. In the following description, the subscript "dn" indicates a downlink, the subscript "up" indicates an uplink, and N up user terminals are selected to transmit simultaneously on the uplink, N dn user terminals are selected to transmit simultaneously on the downlink, N up May or may not be equal to N dn , and N up and N dn It may be a static value, or can change for each scheduling interval.Beam steering or some other spatial processing technique may be used at the access point and user terminal.

[0028] On the uplink, at each user terminal 120 selected for uplink transmission, a TX data processor 288 receives traffic data from a data source 286 and control data from a controller 280. TX data processor 288 processes the traffic data for that user terminal based on the coding and modulation scheme associated with the rate selected for that user terminal. up} is processed (eg, encoded, interleaved, and modulated), and is Nut,m One of the antennas provides a data symbol stream {s up The transceiver front end (TX / RX) 254 (also referred to as the radio frequency front end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and upconverts) the corresponding symbol streams to generate uplink signals. The transceiver front end 254 may also route the uplink signals to N channels for transmit diversity via, for example, a radio frequency (RF) switch. ut,m Controller 280 may control routing within transceiver front end 254. Memory 282 may store data and program codes for user terminal 120 and may interact with controller 280.

[0029] Multiple (N) up The access point may include multiple (404) user terminals 120 that transmit simultaneously on the uplink. Each of these user terminals transmits their set of processed symbol streams on the uplink to the access point.

[0030] At access point 110, N ap The antennas 224a to 224ap are connected to the entire N up The access point transceiver front end 222 also performs processing complementary to that performed by the transceiver front end 254 of the user terminal and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is a stream of data symbols transmitted by the user terminal. up}. RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the uplink data symbol stream in accordance with the rate for recovery to obtain decoded data. The decoded data for each user terminal may be provided to a data sink 244 for storage and / or to a controller 230 for further processing.

[0031] In certain aspects, the transceiver front end (TX / RX) 222 of the access point 110 and / or the transceiver front end 254 of the user terminal 120 may include one or more frequency synthesizers to generate oscillating signals for signal transmission and / or reception. At least one of the frequency synthesizers may include circuitry (e.g., a QVCO) for generating multiple oscillating signals, as described in more detail herein.

[0032] On the downlink, at access point 110, TX data processor 210 receives N data packets scheduled for downlink transmission from data source 208. dnThe TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on the rate selected for the user terminal. The TX data processor 210 may provide for N dn One or more of the user terminals are to be ap The transceiver front end 222 receives the symbol stream and processes the symbol stream (e.g., converts to analog, amplifies, filters, and up-converts) to generate a downlink signal. For example, the transceiver front end 222 can also route the downlink signal to the N antennas for transmit diversity via an RF switch. ap Controller 230 may control routing within transceiver front end 222. Memory 232 may store data and program codes for access point 110 and may interact with controller 230.

[0033] At each user terminal 120, N ut,m The antennas 252 receive downlink signals from the access point 110. For receive diversity at the user terminal 120, the transceiver front end 254 can select the signal received from one of the antennas 252 for processing. The signals received from the multiple antennas 252 can be combined to enhance receive diversity. The transceiver front end 254 of the user terminal also performs processing complementary to that performed by the transceiver front end 222 of the access point and provides a recovered downlink data symbol stream. The RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal.

[0034] Figure 3 is an example transceiver circuit 300 (such as Figure 2 2, 254 in FIG. 2 . The transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a "transmit chain") for transmitting signals via one or more antennas and at least one receive (RX) path 304 (also referred to as a "receive chain") for receiving signals via an antenna. When the TX path 302 and the RX path 304 share an antenna 303, these paths can be connected to the antenna via an interface 306, which can include any of a variety of suitable RF devices such as a duplexer, a switch, a diplexer, etc.

[0035] Receiving an in-phase (I) or quadrature (Q) baseband analog signal from a digital-to-analog converter (DAC) 308, the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The BBF 310, the mixer 312, and the DA 314 may be included in one or more radio frequency integrated circuits (RFICs). For some implementations, the PA 316 may be external to the RFIC.

[0036] The BBF 310 filters the baseband signal received from the DAC 308, and the mixer 312 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to RF). This frequency conversion process produces sum and difference frequencies of the LO frequency and the frequency of the signal of interest. The sum and difference frequencies are referred to as "beat frequencies." The beat frequencies may be in the RF range, so that the signal output by the mixer 312 may be an RF signal that may be amplified by the DA 314 and / or by the PA 316 before being transmitted by the antenna 303. Although one mixer 312 is illustrated, several mixers may be used to upconvert the filtered baseband signal to one or more intermediate frequencies and thereafter upconvert the intermediate frequency (IF) signal to a frequency for transmission.

[0037] RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. LNA 322, mixer 324, and BBF 326 may be included in one or more RFICs, which may or may not be the same RFIC as the RFIC that includes the TX path components. The RF signal received via antenna 303 may be amplified by LNA 322, and mixer 324 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., down-convert). The baseband signal output by mixer 324 may be filtered by BBF 326 before being converted into a digital I or Q signal by analog-to-digital converter (ADC) 328 for digital signal processing.

[0038] Some transceivers may employ a frequency synthesizer with a voltage controlled oscillator (VCO) to generate a stable, tunable LO with a particular tuning range. Thus, a transmit LO frequency may be generated by a TX frequency synthesizer 318, which may be buffered or amplified by an amplifier 320 before being mixed with a baseband signal in a mixer 312. Similarly, a receive LO frequency may be generated by an RX frequency synthesizer 330, which may be buffered or amplified by an amplifier 332 before being mixed with an RF signal in a mixer 324. In certain aspects, the TX frequency synthesizer 318 and / or the RX frequency synthesizer 330 may include circuitry (e.g., a QVCO) for generating multiple oscillating signals, as described in greater detail herein.

[0039] Although Figures 1 to 3 A wireless communication system is provided as an example application in which certain aspects of the present disclosure may be implemented to facilitate understanding, but certain aspects described herein may be used to generate an oscillating signal in any of a variety of other suitable systems.

[0040] Example VCO with improved phase noise and quadrature imbalance tradeoff

[0041] As mentioned above, quadrature local oscillations may be utilized to drive mixers in in-phase / quadrature (IQ) based radios. In such cases, the accuracy of the quadrature signals and the method of generating the quadrature signals may be a design issue.

[0042] One method of quadrature generation (e.g., a "frequency division method") includes operating a voltage controlled oscillator (VCO) at twice the selected frequency, and performing frequency division in the digital domain or the analog domain to obtain quadrature signals (e.g., I / Q local oscillator (LO) signals) at the selected frequencies. The frequency division method can reduce the push / pull effect on the VCO that can be caused by a strong signal from a power amplifier (PA) (e.g., PA 316) in a transmit chain (e.g., TX path 302) of a fully integrated transceiver. However, as a disadvantage, the higher VCO oscillation frequency and the frequency division circuit result in increased power consumption.

[0043] Orthogonal signals can also be obtained by feeding the differential output of the VCO to a polyphase filter, which can be implemented as a resistor-capacitor (RC) polyphase filter. However, this method may consume a lot of power and may suffer from poor phase noise (PN) performance. In addition, the situation where the VCO operates with a wide bandwidth may require a higher order polyphase filter and tunability. Hybrid couplers and ring oscillators have also been used to obtain orthogonality. However, hybrid couplers are usually large and difficult to integrate, and ring oscillators usually suffer from poor PN performance.

[0044] Quadrature signals can also be obtained by utilizing a quadrature VCO (QVCO). Figure 44 is a block diagram of an example QVCO 400 in which aspects of the present disclosure may be practiced. As shown, the QVCO 400 may include two VCO circuits (in Figure 4 400 (labeled "VCO_A" and "VCO_B"), where the differential output of one VCO circuit is used to bias the other VCO circuit. The two VCO circuits can be implemented as inductor-capacitor (LC) tank resonators. QVCO 400 can have direct connections (e.g., between the output of VCO_A and the input of VCO_B) and "crossed" or "anti-phase" connections (e.g., between the output of VCO_B and the input of VCO_A). The combination of direct and cross connections causes VCO_A and VCO_B to oscillate in quadrature.

[0045] There are currently two basic QVCO topologies: series-based and parallel-based. In a series-based QVCO (S-QVCO), the bias transistor is connected in series with the cross-coupled transistors, while in a parallel-based QVCO (P-QVCO), the bias transistor is connected in parallel with the cross-coupled transistors. The orthogonality error in an S-QVCO generally depends on the mismatch (e.g., of the transistors and / or capacitors) and is independent of the phase noise. Although the orthogonality accuracy in an S-QVCO can be improved by implementing the circuit over a larger area, area limitations can limit the orthogonality improvement. The S-QVCO also involves a relatively large voltage headroom. On the other hand, the P-QVCO has a tradeoff between orthogonality error and phase noise. The P-QVCO is able to pass four orthogonal signals (e.g., Figure 4 ), but may suffer from poor phase noise performance because the bias point of the bias transistor may not be programmable.

[0046] Each VCO circuit in a P-QVCO typically includes two bias transistors (also referred to as "coupling transistors") coupled in parallel with two cross-coupled transistors (also referred to as "switching transistors"). The bias transistors may be biased at the quiescent point of the cross-coupled transistors. Thus, the gate-to-source voltage (Vgs) of the bias transistors may oscillate across the bias point (e.g., 220 mV) of the cross-coupled transistors. In such cases, the bias transistors may be "on" for half a cycle (when the voltage Q+ swings high), and may be weakly on during the remaining half cycle. When turned on (even weakly on), the bias transistors may contribute phase noise. The phase noise contributed by each bias transistor increases as Vgs increases. Therefore, it may be desirable to bias the bias transistors near a lower voltage (e.g., 0 mV).

[0047] Certain aspects of the present disclosure provide a VCO topology having a p-type bias transistor coupled across an inductive element. Thus, the bias point of the bias transistor may be equal to (or at least close to) a direct current (DC) voltage drop across the inductive element of the resonant circuit, which may be equal to (or at least close to) 0 mV. Thus, by reducing the Vgs of the bias transistor, the phase noise contributed by the bias transistor is reduced.

[0048] Fig. 5A is a circuit diagram illustrating an example VCO circuit 500 for a QVCO according to certain aspects of the present disclosure. The VCO circuit 500 may include cross-coupled first and second transistors M1, a first inductive element L1, a second inductive element L2, a third transistor M3, and a fourth transistor M4.

[0049] The first transistor M1 may have a gate coupled to the drain of the second transistor M2, and the second transistor M2 may have a gate coupled to the drain of the first transistor M1. Thus, transistors M1 and M2 are cross-coupled transistors of the VCO circuit 500. According to certain aspects, the first transistor M1 and the second transistor M2 may be n-type transistors.

[0050] The first inductive element L1 may be coupled between node 502 and the drain of the first transistor M1, and the second inductive element L2 may be coupled between node 502 and the drain of the second transistor M2. In some cases, the first inductive element L1 and the second inductive element L2 may be part of a center-tapped inductive element. Node 502 may be a tap of the center-tapped inductive element. As shown, the source of the first transistor M1 and the source of the second transistor M2 may be coupled to a reference potential node (e.g., electrical ground).

[0051] For certain aspects, the third transistor M3 (bias transistor) can have a drain coupled to the drain of the first transistor M1 and a source coupled to the node 502. In some cases, the fourth transistor M4 (another bias transistor) can have a drain coupled to the drain of the second transistor M2 and a source coupled to the node 502. For certain aspects, as shown, the third transistor M3 and the fourth transistor M4 can be p-type transistors.

[0052] The VCO circuit 500 may have a differential bias input (e.g., across the gates of the third transistor M3 and the fourth transistor M4, where the input signals are labeled “Q+” and “Q-” for the positive quadrature component and the negative quadrature component, respectively) and a differential output (e.g., across the drains of the first transistor M1 and the second transistor M2, where the output signals are labeled “I+” and “I-” for the positive in-phase component and the negative in-phase component, respectively). As shown, the VCO circuit 500 may also include a current source I coupled between the power rail Vdd and the node 502.source .

[0053] The topology of the VCO circuit 500, in which the bias transistors M3 and M4 are arranged as shown, can provide improved phase noise performance compared to VCO circuits in the S-QVCO and P-QVCO topologies. However, in the case where the VCO circuit 500 operates at a low power level, the gate-to-source voltage (Vgs) of the bias transistors (e.g., the third transistor M3 and the fourth transistor M4) can be reduced. The reduced Vgs can cause the bias transistors to become more aligned with the bias transistors ( Fig. 5A Therefore, when the VCO circuit is operated at a low power level, it may be desirable to adjust the Vgs of the bias transistors to control the tradeoff between phase noise and quadrature performance.

[0054] Figure 5B is a circuit diagram illustrating an example VCO circuit 505 in accordance with certain aspects of the present disclosure. Figure 5B The VCO circuit 505 is similar to Fig. 5A 5. The VCO circuit 500 of FIG. 5 is shown, but also includes an impedance 510 coupled between a first node 512 and a second node 514. Impedance 510 may be implemented by a resistive element as shown or any other suitable component. Impedance 510 may be fixed or tunable (e.g., a tunable resistive element as shown). First node 512 may be coupled to inductive elements L1 and L2 (or taps of a center-tapped inductive element), and second node 514 may be coupled to a current source I source and the sources of bias transistors M3 and M4.

[0055] Impedance 510 may allow the Vgs of the third transistor M3 and the fourth transistor M4 to be set to a specific value and may be used to control the tradeoff between phase noise and quadrature performance. In other words, impedance 510 may allow the bias point of the coupling transistors to be programmed so that quadrature is not lost when the VCO circuit 505 is operating at a low power level.

[0056] In some cases, VCO circuits 500 and 505 may include one or more varactors and / or one or more capacitors coupled between the drain of first transistor M1 and the drain of second transistor M2 (eg, across inductive elements L1 and L2). Fig. 5A and Figure 5B The VCO circuits 500 and 505 in FIG. 5 have the varactor diode and capacitor removed. However, in Figure 6 An example VCO circuit having a network 602 of varactors and capacitors is shown in FIG.

[0057] Figure 66 is a circuit diagram illustrating an example QVCO circuit 600 including a first VCO circuit 610 and a second VCO circuit 620 according to certain aspects of the present disclosure. According to certain aspects, each of the VCO circuits 610 and 620 may be similar to Fig. 5A and Figure 5B The VCO circuits 500 or 505 are similar to those in the embodiment of the present invention, but each VCO circuit has a different differential bias signal and a different differential output signal than the other VCO circuit.

[0058] In certain aspects, the differential output signal of the second VCO circuit 620 (e.g., at the drains of the first transistor M1 and the second transistor M2 having output signals labeled “I+” and “I-”) can be cross-coupled to the differential bias input of the first VCO circuit 610 (e.g., at the gates of the third transistor M3 and the fourth transistor M4 having input signals labeled “I-” and “I+”). In addition, as shown, the differential output signal of the first VCO circuit 610 (e.g., at the drains of the first transistor M1 and the second transistor M2 having output signals labeled “Q+” and “Q-”) can be coupled to the differential bias input of the second VCO circuit 610 (e.g., at the gates of the third transistor M3 and the fourth transistor M4 having input signals labeled “Q+” and “Q-”).

[0059] Thus, the drain of the first transistor M1 and the drain of the second transistor M2 of the first VCO circuit 610 may be coupled to the differential output of the first VCO circuit 610 (having output signals labeled “Q+” and “Q-”). In some cases, the gate of the third transistor M3 of the first VCO circuit 610 may be coupled to the negative output of the differential output of the second VCO circuit 620 (e.g., having an output signal labeled “I-”), and the gate of the fourth transistor M4 of the first VCO circuit 610 may be coupled to the positive output of the differential output of the second VCO circuit 620 (e.g., having an output signal labeled “I+”). Similarly, the drain of the first transistor M1 and the drain of the second transistor M2 of the second VCO circuit 620 may be coupled to the differential output of the second VCO circuit 620 (having output signals labeled “I+” and “I-”). In some aspects, the gate of the third transistor M3 of the second VCO circuit 620 can be coupled to the positive output of the differential output of the first VCO circuit 610 (e.g., having an output signal labeled “Q+”), and the gate of the fourth transistor M4 of the second VCO circuit 620 can be coupled to the negative output of the differential output of the first VCO circuit 610 (e.g., having an output signal labeled “Q-”). The sources of the first transistor M1 and the second transistor M2 can be coupled to a reference potential node (e.g., electrical ground).

[0060] In some aspects, the differential bias inputs of the first VCO circuit 610 may be configured to receive in-phase differential signals (e.g., “I+” and “I-”), wherein the first VCO circuit 610 is configured to generate quadrature differential signals (e.g., “Q+” and “Q-”) at differential outputs of the first VCO circuit 610. In some cases, the second VCO circuit 620 may be configured to receive the quadrature differential signals at the differential bias inputs of the second VCO circuit 620 and generate complementary in-phase differential signals at differential outputs of the second VCO circuit 620.

[0061] At least one of the first VCO circuit 610 or the second VCO circuit 620 may include a plurality of varactors and / or a plurality of capacitors coupled between the drain of the first transistor M1 and the drain of the second transistor M2, as illustrated by a network 602 in both the first VCO circuit 610 and the second VCO circuit 620. The voltage applied to the plurality of varactors may be adjusted in order to adjust the frequency of the output oscillation signal of the VCO circuit.

[0062] Example operation for generating multiple oscillating signals

[0063] Figure 7 is a flow diagram illustrating example operations 700 for generating multiple oscillation signals in accordance with certain aspects of the present disclosure. Operations 700 may be performed by a circuit having multiple VCO circuits, such as QVCO circuit 600.

[0064] Operations 700 may begin at block 702, where a first VCO circuit (e.g., VCO circuit 610) generates a first oscillating signal (e.g., "Q+" and "Q-"). At block 704, the circuit may bias a second VCO circuit (e.g., VCO circuit 620) with the first oscillating signal. At block 706, the second VCO circuit may generate a second oscillating signal (e.g., "I-" and "I+").

[0065] At least one of the first VCO circuit or the second VCO circuit may include: a pair of cross-coupled transistors, the pair of cross-coupled transistors including a first transistor (e.g., transistor M1) and a second transistor (e.g., transistor M2), wherein the first transistor has a gate coupled to a drain of the second transistor, and wherein the second transistor has a gate coupled to the drain of the first transistor; a first inductive element (e.g., inductive element L1) coupled between a first node (e.g., node 502 or node 512) and the drain of the first transistor; a second inductive element (e.g., inductive element L2) coupled between the first node and the drain of the second transistor; a third transistor (e.g., transistor M3) having a drain coupled to the drain of the first transistor and having a source coupled to a second node (e.g., node 502 or node 514); and a fourth transistor (e.g., transistor M4) having a drain coupled to the drain of the second transistor and having a source coupled to the second node.

[0066] In certain aspects, operations 700 may optionally involve biasing the first VCO circuit with an inverted version of the second oscillating signal at block 708. The inverted version of the second oscillating signal may be an in-phase differential signal (e.g., “I+” and “I-”), wherein the first oscillating signal may be a quadrature differential signal (e.g., “Q+” and “Q-”), and wherein the second oscillating signal may be a complementary in-phase differential signal (e.g., “I-” and “I+”).

[0067] In some aspects, operation 700 may also include tuning a resistive element (e.g., impedance 510 having a tunable resistance) coupled between the first node and the second node. For other aspects, the first node and the second node of at least one of the first VCO circuit or the second VCO circuit may be shorted together (e.g., to form a resistor such as Fig. 5A , a single node 502 shown in FIG.

[0068] In some aspects, the first transistor and the second transistor may be n-type transistors. In this case, the third transistor and the fourth transistor may be p-type transistors.

[0069] In some aspects, operation 700 may include adjusting a voltage applied to a plurality of varactors (e.g., varactors in network 602 of varactors and / or capacitors) to adjust a frequency of at least one of the first oscillating signal or the second oscillating signal. The plurality of varactors may be coupled between a drain of a first transistor and a drain of a second transistor in at least one of the first VCO circuit or the second VCO circuit, respectively.

[0070] Example aspects

[0071] In addition to the above-mentioned various aspects, specific combinations of the various aspects are also within the scope of the present disclosure, and the details of some of the specific combinations are as follows:

[0072] Aspect 1: A circuit for generating an oscillation signal, the circuit comprising: a first voltage controlled oscillator (VCO) circuit; and a second VCO circuit, the second VCO circuit having a differential bias input coupled to a differential output of the first VCO circuit, at least one of the first VCO circuit or the second VCO circuit comprising: a pair of cross-coupled transistors, the pair of cross-coupled transistors comprising a first transistor and a second transistor, wherein the first transistor has a gate coupled to a drain of the second transistor, and wherein the second transistor has a gate coupled to the drain of the first transistor; a first inductive element, the first inductive element coupled between a first node and the drain of the first transistor; a second inductive element, the second inductive element coupled between the first node and the drain of the second transistor; a third transistor, the third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node; and a fourth transistor, the fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node.

[0073] Aspect 2: The circuit according to aspect 1, further comprising a resistance element coupled between the first node and the second node.

[0074] Aspect 3: The circuit according to aspect 2, wherein the resistance element is tunable.

[0075] Aspect 4: The circuit according to any one of the preceding aspects, wherein the third transistor and the fourth transistor are p-type transistors.

[0076] Aspect 5: The circuit according to aspect 4, wherein the first transistor and the second transistor are n-type transistors.

[0077] Aspect 6: The circuit of any of the preceding aspects, wherein the differential output of the second VCO circuit is cross-coupled to the differential bias input of the first VCO circuit.

[0078] Aspect 7: A circuit according to Aspect 6, wherein: the drain of the first transistor and the drain of the second transistor are coupled to the differential output of the first VCO circuit; the gate of the third transistor is coupled to the negative output of the differential output of the second VCO circuit; and the gate of the fourth transistor is coupled to the positive output of the differential output of the second VCO circuit.

[0079] Aspect 8: A circuit according to Aspect 6 or 7, wherein: the drain of the first transistor and the drain of the second transistor are coupled to the differential output of the second VCO circuit; the gate of the third transistor is coupled to the positive output of the differential output of the first VCO circuit; and the gate of the fourth transistor is coupled to the negative output of the differential output of the first VCO circuit.

[0080] Aspect 9: A circuit according to any one of Aspects 6 to 8, wherein the differential bias input of the first VCO circuit is configured to receive an in-phase differential signal, wherein the first VCO circuit is configured to generate an orthogonal differential signal at the differential output of the first VCO circuit, and wherein the second VCO circuit is configured to receive the orthogonal differential signal at the differential bias input of the second VCO circuit and generate a complementary in-phase differential signal at the differential output of the second VCO circuit.

[0081] Aspect 10: A circuit according to any one of the preceding aspects, the circuit further comprising: a current source coupled between a power rail and the second node; and a plurality of varactors coupled between the drain of the first transistor and the drain of the second transistor, wherein sources of the first transistor and the second transistor are coupled to a reference potential node.

[0082] Aspect 11: The circuit of any of the preceding aspects, wherein the first inductive element and the second inductive element are part of a center-tapped inductive element, and wherein the first node is a tap of the center-tapped inductive element.

[0083] Aspect 12: A method for generating multiple oscillation signals, the method comprising: generating a first oscillation signal using a first voltage controlled oscillator (VCO) circuit; biasing a second VCO circuit using the first oscillation signal; and generating a second oscillation signal using the second VCO circuit, at least one of the first VCO circuit or the second VCO circuit comprising: a pair of cross-coupled transistors, the pair of cross-coupled transistors comprising a first transistor and a second transistor, wherein the first transistor has a gate coupled to a drain of the second transistor, and wherein the second transistor has a gate coupled to the drain of the first transistor; a first inductive element, the first inductive element coupled between a first node and the drain of the first transistor; a second inductive element, the second inductive element coupled between the first node and the drain of the second transistor; a third transistor, the third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node; and a fourth transistor, the fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node.

[0084] Aspect 13: The method according to aspect 12, further comprising tuning a resistance element coupled between the first node and the second node.

[0085] Aspect 14: The method according to aspect 12 or 13, the method further comprising biasing the first VCO circuit with an inverted version of the second oscillating signal.

[0086] Aspect 15: The method of aspect 14, wherein the inverted version of the second oscillating signal is an in-phase differential signal, wherein the first oscillating signal is an orthogonal differential signal, and wherein the second oscillating signal is a complementary in-phase differential signal.

[0087] Aspect 16: The method according to any one of aspects 12 to 15, wherein the first transistor and the second transistor are n-type transistors, and wherein the third transistor and the fourth transistor are p-type transistors.

[0088] Aspect 17: According to the method described in any one of Aspects 12 to 16, the method also includes adjusting the voltage applied to a plurality of varactor diodes to adjust the frequency of at least one of the first oscillation signal or the second oscillation signal respectively, and the plurality of varactor diodes are coupled between the drain of the first transistor and the drain of the second transistor in the at least one of the first VCO circuit or the second VCO circuit.

[0089] Additional considerations

[0090] The various operations of the above method can be performed by any suitable component that can perform the corresponding function. These components may include various hardware components and / or modules, including but not limited to one or more circuits. Usually, in the case of the operations illustrated in the accompanying drawings, those operations can have corresponding corresponding components plus functional components with similar numbers.

[0091] As used herein, the term "determine" encompasses a wide variety of actions. For example, "determine" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, a database, or another data structure), ascertaining, etc. In addition, "determine" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. In addition, "determine" may include resolving, selecting, choosing, establishing, etc.

[0092] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). For example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple of the same elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc or any other ordering of a, b, and c).

[0093] The various illustrative logical blocks, modules, and circuits described in connection with the present disclosure may be implemented or performed using discrete hardware components designed to perform the functions described herein.

[0094] The methods disclosed herein include one or more steps or actions for implementing the described methods. The method steps and / or actions may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0095] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A circuit for generating an oscillation signal, the circuit comprising: a first voltage controlled oscillator (VCO) circuit; and a second VCO circuit having a differential bias input coupled to a differential output of the first VCO circuit, at least one of the first VCO circuit or the second VCO circuit comprising: a pair of cross-coupled transistors, the pair of cross-coupled transistors comprising a first transistor and a second transistor, wherein the first transistor has a gate coupled to a drain of the second transistor, and wherein the second transistor has a gate coupled to the drain of the first transistor; a first inductive element coupled between a first node and the drain of the first transistor; a second inductive element coupled between the first node and the drain of the second transistor; a third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node; and a fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node, wherein the third transistor and the fourth transistor are p-type transistors. 2 . The circuit of claim 1 , further comprising a resistive element coupled between the first node and the second node.

3. The circuit of claim 2, wherein the resistive element is tunable.

4. The circuit of claim 1, wherein the first transistor and the second transistor are n-type transistors.

5. The circuit of claim 1, wherein differential outputs of the second VCO circuit are cross-coupled to differential bias inputs of the first VCO circuit.

6. The circuit of claim 5, wherein: the drain of the first transistor and the drain of the second transistor coupled to the differential output of the first VCO circuit; The gate of the third transistor is coupled to a negative output of the differential output of the second VCO circuit; and The gate of the fourth transistor is coupled to a positive output of the differential output of the second VCO circuit.

7. The circuit of claim 5, wherein: the drain of the first transistor and the drain of the second transistor coupled to the differential output of the second VCO circuit; The gate of the third transistor is coupled to a positive output of the differential output of the first VCO circuit; and The gate of the fourth transistor is coupled to a negative output of the differential output of the first VCO circuit.

8. The circuit of claim 5 , wherein the differential bias input of the first VCO circuit is configured to receive an in-phase differential signal, wherein the first VCO circuit is configured to generate an orthogonal differential signal at the differential output of the first VCO circuit, and wherein the second VCO circuit is configured to receive the orthogonal differential signal at the differential bias input of the second VCO circuit and generate a complementary in-phase differential signal at the differential output of the second VCO circuit.

9. The circuit according to claim 1, further comprising: a current source coupled between a power rail and the second node; and A plurality of varactors are coupled between the drain of the first transistor and the drain of the second transistor, wherein sources of the first transistor and the second transistor are coupled to a reference potential node.

10. The circuit of claim 1, wherein the first inductive element and the second inductive element are part of a center-tapped inductive element, and wherein the first node is a tap of the center-tapped inductive element.

11. A method for generating a plurality of oscillation signals, the method comprising: generating a first oscillation signal using a first voltage controlled oscillator (VCO) circuit; biasing a second VCO circuit using the first oscillating signal; as well as The second oscillation signal is generated by the second VCO circuit, wherein at least one of the first VCO circuit or the second VCO circuit comprises: a pair of cross-coupled transistors, the pair of cross-coupled transistors comprising a first transistor and a second transistor, wherein the first transistor has a gate coupled to a drain of the second transistor, and wherein the second transistor has a gate coupled to the drain of the first transistor; a first inductive element coupled between a first node and the drain of the first transistor; a second inductive element coupled between the first node and the drain of the second transistor; a third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node; and a fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node, wherein the third transistor and the fourth transistor are p-type transistors. 12 . The method of claim 11 , further comprising tuning a resistive element coupled between the first node and the second node.

13. The method of claim 11, further comprising biasing the first VCO circuit with an inverted version of the second oscillating signal.

14. The method of claim 13, wherein the inverted version of the second oscillating signal is an in-phase differential signal, wherein the first oscillating signal is a quadrature differential signal, and wherein the second oscillating signal is a complementary in-phase differential signal.

15. The method of claim 11, wherein the first transistor and the second transistor are n-type transistors.

16. The method of claim 11, further comprising adjusting a voltage applied to a plurality of varactors coupled between the drain of the first transistor and the drain of the second transistor in the at least one of the first VCO circuit or the second VCO circuit to adjust a frequency of at least one of the first oscillation signal or the second oscillation signal, respectively.

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