A high-reliability parallel running method for a space SPARC multi-core processor

Abstract

The application provides a kind of high-reliability parallel running method of aerospace SPARC multi-core processor, and the multi-core processor chip includes at least two processor cores, and all processor cores of the multi-core processor chip are independently running and performing inter-core notification and synchronization;Multi-processor state register monitors the running state of processor core and activates multi-core running.The application independently deploys multiple software modules on multiple processor cores for parallel computing, breaking through the traditional aerospace single-core processor software design mode, so that the software can adapt to large-scale software, multi-module integration, high real-time and high reliability requirements.At the same time, the application expands the supporting technology related to aerospace multi-core processor, including multi-core loading, inter-core interrupt, peripheral management, data sharing area, inter-core dynamic monitoring, etc., which has great value for the development of comprehensive electronic, integrated control and health management aerospace software in the field of satellite payload software.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electric digital data processing, in particular to a high-reliability parallel running method of a space SPARC multi-core processor. BACKGROUND

[0002] A traditional space software architecture is designed in a multi-module multi-task mode on a single-core processor, and a communication interaction mechanism is formulated. With the increase of the scale of embedded software, the number of software modules increases, and the function tends to be more complex. Under the single-core architecture, the internal interface of the software is complex, the integrated debugging difficulty is significantly increased, the software processing speed is slowed down, the development and debugging efficiency is reduced, and the communication delay is increased.

[0003] At present, the running speed of the CPU single-core processor running the operating system software of the large-scale on-board satellite remote sensing image intelligent processing software, inter-satellite router software, control management software, data storage software and the like has been difficult to meet the demand, and a multi-core parallel computing method is urgently needed to improve the processing efficiency. Secondly, with the increase of module division, the integrated development and joint debugging difficulty of the multi-module multi-tasks in the single-core software is significantly increased, and the development efficiency is low. The communication mechanism of the multi-tasks is more complex, which leads to insufficient real-time performance, and it is necessary to reduce the communication delay between modules. The traditional single-core processor software architecture has been difficult to meet the processing speed and real-time performance requirements.

[0004] Therefore, a high-reliability and fast running method for space is needed. SUMMARY

[0005] The present application is to solve the problems of complex internal modules and interfaces of space single-core processor software, great integrated debugging difficulty, slow software processing speed and poor real-time performance, and provides a high-reliability parallel running method of a space SPARC multi-core processor. By adopting a multi-core processing software architecture, a plurality of space field software modules are independently deployed on a plurality of processor cores, a plurality of software is independently compiled and independently run, the software development amount of multi-module scheduling is reduced, the coupling between modules is reduced, the consumption of data stream mutual transmission is reduced, data sharing between multi-cores is carried out by using a shared data area, notification synchronization is realized by using inter-core interruption, the overall running capability of the multi-core processor software is improved, the software processing efficiency is finally improved, the communication delay is reduced, the quality of space products is improved, and the reliability of space products is improved.

[0006] The application provides a high-reliability parallel running method of a space SPARC multi-core processor, a hardware platform uses a multi-core processor chip of a SPARC architecture, the multi-core processor chip comprises at least two processor cores, CPU0 and CPU1, and further comprises a FLASH storage space, a multi-processor state register and a running program, the multi-processor state register monitors the running state of the processor cores and activates the processor cores except CPU0 in the multi-core processor chip, and the running program comprises at least a CPU0 application program and a CPU1 application program, and further comprises a BOOT booting program, the running program is burned in the FLASH storage space during ground assembly;

[0007] All the processor cores of the multi-core processor chip run independently and perform inter-core notification and synchronization;

[0008] After power-on, CPU0 of the multi-core processor chip is in a working state by default, the BOOT program is first started to perform CPU interrupt vector table initialization, multi-core running environment configuration, stack pointer initialization of each CPU core, transfer of the running program from the FLASH storage space to a DDR running space and pointing of a PC current program running pointer to a program entry address Main function of CPU0, and then the BOOT program configures the multi-processor state register to start the multi-core running state; once CPU1 is started, the PC pointer of CPU1 points to the Main function entry of CPU1, and the multi-cores start running simultaneously.

[0009] The high-reliability parallel running method of the space SPARC multi-core processor, as a preferred mode, can know whether the processor core is in a running state by reading bit[3:0] of the multi-processor state register; when the read bit number is 1, the corresponding processor core is suspended and in a power-down mode; when the read bit number is 0, the corresponding processor core has been activated and in a normal working mode.

[0010] Writing 1 to the corresponding position of bit[3:0] of the multi-processor state register can activate the corresponding processor core.

[0011] After system reset, the CPUs of the cores except CPU0 are in the power-down mode, and CPU0 can activate part or all of the processor cores in the other processor cores by operating bit[3:0] of the multi-processor state register.

[0012] The high-reliability parallel running method of the space SPARC multi-core processor, as a preferred mode, sets a shared memory space for inter-core data interaction.

[0013] The running space address of the BOOT boot program is 0x6000000-0x60100000, the address of the CPU0 running space+stack space is 0x61000000-0x67fffffc, the address of the CPU1 running space+stack space is 0x68000000-0x6efffffc, and the CPU1 and CPU0 shared memory space address for inter-core data interaction is 0x6f000000-0x6ffffffc.

[0014] The high-reliability parallel running method of the aerospace SPARC multi-core processor, as a preferred mode, each CPU core of the multi-core processor core independently uses a respective peripheral, and the peripheral includes a timer, a serial port and an external interrupt.

[0015] The high-reliability parallel running method of the aerospace SPARC multi-core processor, as a preferred mode, the inter-core notification and synchronization method is to read and write the specified data sharing area address of the DDR.

[0016] The inter-core notification and synchronization are protected by using a mutex mechanism, and the common peripheral operation is written between the locking LOCK and unlocking UNLOCK operations to protect the multi-core from being simultaneously used with the common peripheral, thereby avoiding conflicts.

[0017] The high-reliability parallel running method of the aerospace SPARC multi-core processor, as a preferred mode, the specific method of the mutex mechanism is that the CPU of the multi-core processor core provides two interface functions SMP_LOCK and SMP_UNLOCK for the application layer to use the mutex function; a fixed address is used as a lock flag, and the functions SMP_LOCK and SMP_UNLOCK are used to lock the protection code, and if the lock flag has been locked when SMP_LOCK, the software will be blocked and waited until unlocking.

[0018] The high-reliability parallel running method of the aerospace SPARC multi-core processor, as a preferred mode, the inter-core notification and synchronization are realized by the interrupt forced triggering provided by the multi-core processor chip.

[0019] Each CPU in the multi-core processor chip corresponds to a separate interrupt mask register and an interrupt forced register, the interrupt mask register sets whether the corresponding CPU enables a specified interrupt, and the interrupt forced register forcibly triggers the specified interrupt; one CPU in the multi-core processor chip can receive the interrupt forced triggering initiated by another CPU in real time, and the interrupt service program of the receiving interrupt forced triggering CPU correctly responds and executes the interrupt.

[0020] The high-reliability parallel operation method of the aerospace SPARC multi-core processor has the following advantages: the CPU0 application program performs bus control and data analysis functions, and the CPU1 application program performs high-speed floating-point data operation functions; meanwhile, the CPU1 application program compares the DDR program area with the FLASH storage data, and completes the abnormal monitoring and health management functions.

[0021] The high-reliability parallel operation method of the aerospace SPARC multi-core processor has the following advantages: the CPU0 application program performs bus control and data analysis functions, and the CPU1 application program performs high-speed floating-point data operation functions; meanwhile, the CPU1 application program compares the DDR program area with the FLASH storage data, and completes the abnormal monitoring and health management functions.

[0022] The CPU0 application program executes an embedded real-time operating system program and performs overall scheduling and bus control, and the CPU1 application program executes a bare machine program and simultaneously performs dynamic monitoring and health management on the CPU0 application program.

[0023] The CPU0 reads multi-core program data stored in a FLASH storage space; the CPU1 uses a CAN bus to receive CAN data sent by a PC end in response to a CAN interrupt; after interrupt and GPIO related registers are configured, the multi-core responds to respective external GPIO interrupts.

[0024] The high-reliability parallel operation method of the aerospace SPARC multi-core processor has the following advantages: the CPU0 application program performs bus control and data analysis functions, and the CPU1 application program performs high-speed floating-point data operation functions; meanwhile, the CPU1 application program compares the DDR program area with the FLASH storage data, and completes the abnormal monitoring and health management functions.

[0025] The multi-core processor chip further comprises a GPIO, a UART, a timer, an interrupt controller, a debugging support unit, a memory controller, a 1553B bus controller, a CAN bus controller, an Ethernet controller and a SpaceWire bus node controller.

[0026] The high-reliability parallel operation method of the aerospace SPARC multi-core processor has the following advantages:

[0027] The application independently deploys multiple software modules on multiple processor cores for parallel computing, breaks through the traditional aerospace single-core processor software design mode, and makes the software adapt to large-scale software, multi-module integration, high real-time performance and high reliability. Meanwhile, the application expands the supporting technologies related to the aerospace multi-core processor, including multi-core loading and starting, inter-core interrupts, peripheral management, data sharing area and inter-core dynamic monitoring, and has great value for the development of comprehensive electronic, comprehensive control and health management aerospace software in the field of satellite payload software.

[0028] (1) The application solves the problems of difficult decoupling, slow operation and difficult debugging of large high-integration software developed on a traditional space navigation single-core processor, and each core software can be debugged independently, and the development efficiency is significantly improved.

[0029] (2) The application uses a shared data area for data sharing between multiple cores, and uses inter-core interrupts to realize notification synchronization, which can reduce storage space and processing time consumption, and improve the overall running ability of the multi-core processor software.

[0030] (3) The application can realize dynamic monitoring between multiple cores without affecting the real-time performance of the business function of the software itself, and realizes the health management function, and the reliability of the software product is significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a dual-core software storage and running space allocation diagram of a space navigation SPARC multi-core processor high-reliability parallel running method.

[0032] Figure 2 It is a dual-core processor software startup flowchart of a space navigation SPARC multi-core processor high-reliability parallel running method.

[0033] Figure 3 It is an embodiment CPU chip structure block diagram of a space navigation SPARC multi-core processor high-reliability parallel running method.

[0034] Figure 4 It is an embodiment test hardware connection relationship diagram of a space navigation SPARC multi-core processor high-reliability parallel running method.

[0035] Figure 5 It is a dual-core CPU loading schematic diagram of a space navigation SPARC multi-core processor high-reliability parallel running method.

[0036] Figure 6 It is a mutual exclusion lock protection shared peripheral schematic diagram of a space navigation SPARC multi-core processor high-reliability parallel running method. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, not all embodiments.

[0038] Embodiment 1

[0039] A space navigation SPARC multi-core processor high-reliability parallel running method, Figure 1Is the dual-core software storage and running space allocation chart of the application, which describes the storage distribution of BOOT loader, CPU0 program, CPU1 program in the Flash, and the space allocation in the DDR running space of CPU.

[0040] Figure 2 Is the dual-core processor software startup flow chart of the application. The function of BOOT program is to move CPU0 and CPU1 programs from Flash to DDR running space, and configure multi-core registers to start dual-core running.

[0041] (1) First, the hardware platform and software test environment need to be built, and the multi-core deployment and startup method need to be verified. The chip uses S698PM processor chip with SPARC architecture, which is a multi-core parallel processor SOC chip with anti-radiation, high performance, high reliability, high integration and low power consumption. It uses LEON4 kernel and symmetric multiprocessing architecture (SMP), and complies with SPARC V8 standard. S698PM chip integrates 4 high-performance processors, each of which is composed of 32-bit RISC integer processing unit (IU), double-precision floating-point processing unit (FPU), high-speed level 1 cache (L1 Cache) and memory management unit (MMU), etc., as shown in Figure 3

[0042] (2) At the same time, the hardware platform integrates rich on-chip peripherals, including GPIO, UART, timer, interrupt controller, debugging support unit, memory controller, 1553B bus controller, CAN bus controller, Ethernet controller, SpaceWire bus node controller, etc., and deploys FLASH storage chip as startup storage medium.

[0043] The hardware connection relationship and physical diagram of the development verification platform are shown in Figure 4

[0044] ​​(3) S698PM chip can monitor the status of each processor core through the multiprocessor status register MSR. Reading bit[3:0] of the MSR register can know whether the processor core is in running state. If a bit is 1, it means that the corresponding processor core is suspended (halted) and in power-down mode. If a bit is 0, it means that the corresponding processor core has been activated and is in normal working mode. Writing 1 to a bit of bit[3:0] of the MSR register can activate the corresponding processor core. After system reset, except for CPU0, the other three CPUs are in power-down mode. CPU0 can activate part or all of CPU1-CPU3 by operating bit[3:0] of the multiprocessor status register MSR.

[0045] (4) After power-on, the chip defaults CPU0 to be in working state. In dual-core mode, software includes BOOT boot program, CPU0 application program and CPU1 application program, as shown in Figure 5 . The three programs are burned in the startup storage medium FLASH. The BOOT program is first started after product power-on. Its function is to initialize the CPU interrupt vector table, configure the multi-core running environment, initialize the stack pointer of each CPU core, move the program from the peripheral memory to the DDR running space, point the PC current program running pointer to the program entry address Main function of CPU0, and finally configure the "multiprocessor status register MSR" to start the multi-core running state. Once CPU1 is started, the PC pointer of CPU1 points to the Main function entry thereof, and the multi-cores start running simultaneously.

[0046] (5) Taking dual-core mode as an example, dual-core software independently runs in each core. CPU0 executes embedded real-time operating system program to perform overall scheduling and bus control. CPU1 executes bare machine program with simple control logic and high time efficiency requirement, and simultaneously performs dynamic monitoring and health management on the program area of CPU0 software. The dual-core running space allocation is shown in Table 1:

[0047] Table 1

[0048]

[0049] (6) Dual-core independently manages its own peripherals, such as CPU0 uses chip No. 1 timer, No. 1 serial port, No. 12 external interrupt, CPU1 uses chip No. 2 timer, No. 2 serial port, No. 13 external interrupt. Each peripheral function is independent, and there is no use conflict, which ensures the relative independence of dual-core software and reduces the interaction consumption. The practical results show that: CPU0 can correctly read the dual-core program data stored in FLASH; CPU1 can use CAN bus to receive CAN data sent by PC after responding to CAN interrupt, indicating that dual-core can independently use its own peripherals; after configuring the interrupt and GPIO related registers, dual-core can correctly respond to its own external GPIO interrupt; CPU0 can respond to general timer 1 interrupt, and CPU2 can respond to general timer 2 interrupt, and the two timers work independently and do not affect each other; the dual-core test conditions are shown in Table 2.

[0050] Table 2

[0051]

[0052]

[0053] (7) Dual-core software completes data interaction by reading and writing DDR specified data sharing area address. In order to avoid conflict, mutual exclusion mechanism can be used for protection. CPU provides mutual exclusion function and provides two interface functions SMP_LOCK and SMP_UNLOCK for application layer. A fixed address is used as a lock flag, and the functions SMP_LOCK and SMP_UNLOCK are used to lock the protection code. If the lock flag is locked when SMP_LOCK, the software will be blocked until it is unlocked. The software flow is shown in Figure 6 , and the common peripheral operation is written between the locking LOCK and unlocking UNLOCK operations, so that the common peripheral can be protected from being used by two cores at the same time to avoid conflict.

[0054] (8) High real-time notification and synchronization between dual-cores can also be achieved through the interrupt forced trigger provided by the multi-core processor. The inter-core No. 14 interrupt is triggered by setting the interrupt forced register between dual-cores, and the inter-core synchronization and notification is completed.

[0055] Each processor core of the CPU corresponds to a separate interrupt mask register (IMR) and an interrupt force register (IFR), the interrupt mask register is used to set whether the corresponding CPU enables a certain interrupt, and the interrupt force register is used to forcibly trigger a certain interrupt. The CPU0 program sets the position 1 corresponding to the 14th interrupt in the interrupt force register of the CPU1, and the CPU1 opens the 14th interrupt enable. The experimental results show that the CPU1 can receive the interrupt force trigger initiated by the CPU0 in real time, and the 14th interrupt service program of the CPU1 can correctly respond and execute. At the same time, the communication time is measured by using the timer query method, and the communication delay is less than 200us, which is less than 1ms. This proves the effectiveness of the inter-core high real-time interaction by using the forced interrupt method.

[0056] (9) The CPU0 program performs the bus control and data analysis functions, and the CPU1 program performs the floating point data high-speed operation function. At the same time, the CPU1 compares the DDR program area with the flash storage data to complete the abnormal monitoring and health management functions. The functions of the two cores cooperate with each other to complete the efficient and reliable operation of the large, multi-module and multi-core software.

[0057] The above merely describes the preferred embodiments of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can make equivalent replacements or changes to the technical solutions and the inventive concept of the present application within the technical range disclosed by the present application, and all of them should be covered within the protection scope of the present application.

Claims

1. A highly reliable parallel operation method for aerospace SPARC multi-core processors, characterized in that: The hardware platform uses a SPARC architecture multi-core processor chip, which includes at least two processor cores: CPU0 and CPU1, as well as FLASH storage space, a multi-processor status register, and a running program. The multi-processor status register monitors the running status of the processor cores and activates the processor cores other than CPU0 in the multi-core processor chip. The running program includes at least CPU0 application and CPU1 application, as well as a BOOT bootloader. The running program is burned into the FLASH storage space during ground assembly. All processor cores of the multi-core processor chip operate independently and perform inter-core notification and synchronization. After power-on, the multi-core processor chip defaults to CPU0 being in working state. First, the boot program initializes the CPU interrupt vector table, configures the multi-core running environment, initializes the stack pointers of each CPU core, moves the running program from the FLASH storage space to the DDR running space, and points the PC current program running pointer to the program entry address Main function of CPU0. Then, the boot program configures the multi-processor status register to enable multi-core running state. Once CPU1 is enabled, the PC pointer of CPU1 points to the entry point of the Main function of CPU1, and multiple cores start running simultaneously. Inter-core notification and synchronization are achieved through interrupt-driven forced triggering provided by the multi-core processor chip; Each CPU in the multi-core processor chip has a separate interrupt mask register and an interrupt force register. The interrupt mask register sets whether the corresponding CPU enables a specified interrupt, and the interrupt force register forcibly triggers the specified interrupt. In the multi-core processor chip, one CPU can receive an interrupt forced trigger initiated by another CPU in real time, and the interrupt service routine of the CPU receiving the interrupt forced trigger can correctly respond to and execute the interrupt.

2. The method for high-reliability parallel operation of aerospace SPARC multi-core processors according to claim 1, characterized in that: By reading bits [3:0] of the multiprocessor status register, it can be determined whether the processor core is in a running state; when the bit read is 1, the corresponding processor core is suspended and in power-down mode; when the bit read is 0, the corresponding processor core has been activated and is in normal working mode. Writing 1 to the corresponding bit[3:0] of the multiprocessor status register will activate the corresponding processor core; After the system is reset, all CPU cores except CPU0 are in power-down mode. CPU0 can activate some or all of the other processor cores by operating bits [3:0] of the multiprocessor status register.

3. The method for high-reliability parallel operation of aerospace SPARC multi-core processors according to claim 1, characterized in that: Inter-core data exchange sets up shared memory space; The BOOT bootloader runs in the address space of 0x6000000 ~ 0x60100000, the CPU0 running space + stack space runs in the address space of 0x61000000 ~ 0x67fffffc, the CPU1 running space + stack space runs in the address space of 0x68000000 ~ 0x6efffffc, and the shared memory space between CPU1 and CPU0 used for inter-core data exchange runs in the address space of 0x6f000000 ~ 0x6ffffffc.

4. The highly reliable parallel operation method for aerospace SPARC multi-core processors according to claim 1, characterized in that: Each CPU core of the multi-core processor chip independently uses its own peripherals, which include timers, serial ports, and external interrupts.

5. A highly reliable parallel operation method for aerospace SPARC multi-core processors according to claim 1, characterized in that: The method for inter-core notification and synchronization is: reading and writing the DDR specified data sharing area address; Inter-core notification and synchronization are protected using a mutex mechanism. Shared peripheral operations are written between the LOCK and UNLOCK operations to prevent multiple cores from using the shared peripheral at the same time, thus avoiding conflicts.

6. A highly reliable parallel operation method for aerospace SPARC multi-core processors according to claim 5, characterized in that: The specific method of the mutex lock mechanism is as follows: The CPU of the multi-core processor chip provides two interface functions, SMP_LOCK and SMP_UNLOCK, for the application layer to use for mutex lock functionality; a fixed address is used as the lock flag, and the protected code is locked using the functions SMP_LOCK and SMP_UNLOCK. If the lock flag is already locked when SMP_LOCK is called, the software will block and wait until it is unlocked.

7. A highly reliable parallel operation method for aerospace SPARC multi-core processors according to claim 1, characterized in that: The CPU0 application performs bus control and data parsing functions, while the CPU1 application performs high-speed floating-point data operations. At the same time, the CPU1 application compares the DDR program area with the FLASH stored data and performs anomaly monitoring and health management functions.

8. A highly reliable parallel operation method for aerospace SPARC multi-core processors according to claim 1, characterized in that: The application on CPU0 runs on CPU0, and the application on CPU1 runs on CPU1. The CPU0 application executes the embedded real-time operating system program and performs overall scheduling and bus control, while the CPU1 application executes the bare-metal program and simultaneously performs dynamic monitoring and health management of the CPU0 application. CPU0 reads the multi-core program data stored in the FLASH memory space; CPU1 can receive CAN data sent by the PC after responding to the CAN interrupt using the CAN bus; after configuring the interrupt and GPIO related registers, the multi-core responds to their respective external GPIO interrupts.

9. A highly reliable parallel operation method for aerospace SPARC multi-core processors according to claim 1, characterized in that: Each processor core in the multi-core processor chip includes a 32-bit RISC integer processing unit, a double-precision floating-point processing unit, a high-speed L1 cache, and a memory management unit. The multi-core processor chip also includes GPIO, UART, timers, interrupt controllers, debug support units, memory controllers, 1553B bus controllers, CAN bus controllers, Ethernet controllers, and SpaceWire bus node controllers.

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