An ONFI PHY training method applicable to multiple types of delay line structures

Abstract

The present invention discloses an ONFI PHY training method applicable to multiple types of delay line structures. This process first determines the range of sampleable values through coarse scanning, and uses a long delay line to obtain a coarse sampling window with a fixed step as a subsequent reference. Subsequently, the minimum value of the long delay line is found through training and dq is aligned. During the process, a short delay line is used to adjust the dq skew until dq is aligned or the adjustment ability of the short delay line is exhausted. Then, the average value of the center value of the coarse scan window and the minimum value is used as the initial point to train the maximum value of the long delay line. Finally, the average value of the minimum value and the maximum value is taken as the final configuration value to complete the entire training process. Through the present invention, the actions of finding the sampling window and aligning dq can be performed simultaneously, increasing the data window and improving the training effect and efficiency.

Description

Technical Field

[0001] The present invention relates to the field of memory data reading and writing, and more specifically, to an ONFI PHY training method applicable to multiple types of delay line structures. Background Art

[0002] For storage devices that follow the ONFI protocol, when a device accessing flash performs read and write operations, dq (data) and dqs (data strobe) need to meet the setup and hold timing of sampling. Inside the PHY, a delay adjustment circuit (delay line) is used to adjust the phase relationship between different dq bits and dqs in the read and write directions, so as to meet the data sampling timing requirements.

[0003] Affected by factors such as the operating frequency point, temperature, voltage, implementation process, IO quality, and delay line design, the time for phy_dq and phy_dqs to reach the data sampling circuit flash through the data path varies and changes under different conditions, and a preset value of the delay line that meets all scenarios cannot be provided. Therefore, in fact, it is necessary to adjust the delay line configuration and adjust the dq dqs phase through training (training) to ensure that the FLASH in the write direction and the PHY in the read direction can correctly sample data.

[0004] Due to factors such as the increase in working speed, IO quality, chip process, package design and manufacturing, and temperature and voltage changes during the operation of the chip, the impact on timing has become increasingly obvious. And the ONFI protocol DQ outputs data in parallel, and the skew between dq bits also affects the sampling window. These factors pose challenges to the normal operation of the system. In this case, there are a series of problems with the existing training solutions. First, there is a lack of flexibility. When the existing technology looks for the maximum and minimum values, the initial value needs to be set in advance through additional operations. If the actual configuration differs greatly from the theory, the initial value may not be able to sample correctly, resulting in training failure. Second, the sampling window is small, and the ability to cope with PVT changes is reduced. The ONFI protocol DQ signal is 8-bit parallel data. Due to reasons such as wiring, IO quality, and process, the dq paths cannot be completely flush, and there is skew between dqs. The single-segment delay line and the training solution do not consider the dq skew factor, which will lose part of the sampling window and reduce the ability to resist PVT changes. Third, when the temperature, voltage, and process change, the sampling of different dq bits will change. When the overlapping part of the dq sampling window decreases, it is easy to drift. When the window completely disappears, retraining is required, thus reducing usability. Summary of the Invention

[0005] The present invention overcomes the deficiencies of the prior art and proposes an ONFI PHY training method applicable to multi-type delay line structures.

[0006] In a first aspect of the present invention, there is provided an ONFI PHY training method applicable to multi-type delay line structures, including:

[0007] S1: Coarse scan to obtain sampleable values, use a fixed step scan on the long delay line to obtain a coarse sampling window, and take the configuration obtained from the coarse scan window as the configuration reference for the subsequent process;

[0008] S2: Train to obtain the minimum value in the long delay line configuration and align dq;

[0009] Step a1: All short delay lines are configured to 0, and the minimum value of the coarse scan window is used as the initial point for the long delay line;

[0010] Step a2: Execute a preset training instruction to compare data. If the data is correct, the long delay line is decreased by a preset unit and step 2 is repeated; if the data is incorrect and the long delay line configuration is not 0, then step a2 is exited and the next process is entered. At this time, it means that the delay line has reached the critical position; if the delay line configuration is 0, then step a2 is exited, indicating that the long delay line is already the minimum;

[0011] Step a3: Record the incorrect dq bit positions; if all dq bit positions are incorrect, it means that dq has been aligned, the skew has been reduced to the lowest level and step 3 is exited; if a group of short delay lines has reached the maximum value, it means that the adjustment ability of a certain dq corresponding to the short delay line has been used up and the short delay line is full, and the dq skew cannot be further reduced. At this time, step 3 is exited; otherwise, the short delay line corresponding to the incorrect dq is increased by a preset unit and step a2 is returned;

[0012] Step a4: Freeze the short delay line configuration at this time, indicating that dq has been aligned, and record the long delay line at this time as MIN, indicating the lower limit of the sampling window;

[0013] S3: Take the average of MIN obtained in process two and the center value of the coarse scan window as the initial point for process S4;

[0014] S4: Train to obtain the maximum value of the long delay line configuration;

[0015] Step b1: Execute a training instruction to compare data. If the data is correct, increase the long delay line configuration value by a preset unit and loop to execute the training instruction to compare data until the data is incorrect, and then enter step b2;

[0016] Step b2: Record the current long delay line as MAX, indicating the upper limit of the sampling window.

[0017] S5: Take the average of MIN obtained from process S2 and MAX obtained from process S4 as the final training result value, marked as the final configuration value.

[0018] The second aspect of the present invention also provides an ONFI PHY training system applicable to multi-type delay line structures, which includes: a memory and a processor. The memory includes an ONFI PHY training program applicable to multi-type delay line structures. When the ONFI PHY training program applicable to multi-type delay line structures is executed by the processor, the following steps are implemented:

[0019] S1: Coarse scan to obtain sampleable values, use a fixed step to scan on the long delay line to obtain a coarse sampling window, and take the configuration obtained from the coarse scan window as the configuration reference for the subsequent process.

[0020] S2: Train to obtain the minimum value in the long delay line configuration and align dq.

[0021] Step a1: All short delay lines are configured to 0, and the long delay line uses the minimum value of the coarse scan window as the initial point.

[0022] Step a2: Execute a preset training instruction to compare data. If the data is correct, the long delay line is decreased by a preset unit and step 2 is repeated; if the data is incorrect and the long delay line configuration is not 0, then step a2 is exited and the next process is entered. At this time, it means that the delay line has reached the critical position; if the delay line configuration is 0, then step a2 is exited, indicating that the long delay line is already the minimum.

[0023] Step a3: Record the dq bit positions where errors occur; if all dq bit positions have errors, it means that dq is already aligned, the skew has dropped to the lowest and step 3 is exited; if a group of short delay lines has reached the maximum value, it means that the adjustment ability of a certain dq corresponding to the short delay line has been used up and the short delay line is full, and the dq skew cannot be further reduced. At this time, step 3 is exited; otherwise, the short delay line corresponding to the incorrect dq is increased by a preset unit and return to step a2.

[0024] Step a4: Freeze the current short delay line configuration, indicating that dq is already aligned, and record the current long delay line as MIN, indicating the lower limit of the sampling window.

[0025] S3: Take the average of the MIN obtained in Process 2 and the center value of the coarse scan window as the initial point for Process S4;

[0026] S4: Train to obtain the maximum value of the long delayline configuration;

[0027] Step b1: Execute the training instruction to compare data. If the data is correct, increase the preset unit long delayline configuration value, and loop to execute the training instruction to compare data until the data is incorrect, then enter Step b2;

[0028] Step b2: Record the long delayline at this time as MAX, representing the upper limit of the sampling window;

[0029] S5: Take the average of the MIN obtained in Process S2 and the MAX obtained in Process S4 as the final training result value, marked as the final configuration value.

[0030] The third aspect of the present invention also provides a computer-readable storage medium, which includes an ONFI PHY training program applicable to multi-type delay line structures. When the ONFI PHY training program applicable to multi-type delay line structures is executed by a processor, it realizes the steps of the ONFI PHY training method applicable to multi-type delay line structures as described in any one of the above.

[0031] The present invention discloses an ONFI PHY training method applicable to multi-type delay line structures. This process first determines the range of sampleable values through coarse scanning, and uses the long delayline fixed step to obtain the coarse sampling window as a subsequent reference. Subsequently, the minimum value of the long delayline is found through training and dq is aligned. During the process, the short delayline is used to adjust dqskew until dq is aligned or the adjustment ability of the short delayline is exhausted. Then, the average of the center value of the coarse scan window and the minimum value is used as the initial point to train the maximum value of the long delayline. Finally, the average of the minimum value and the maximum value is used as the final configuration value to complete the entire training process. Through the present invention, the actions of finding the sampling window and aligning dq can be performed simultaneously, increasing the data window and improving the training effect and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Shows a flowchart of an ONFI PHY training method applicable to multi-type delay line structures of the present invention;

[0033] Figure 2 Shows a structural diagram of a segmented delay adjustment circuit of the present invention;

[0034] Figure 3 Shows a structural diagram of a multi-segment delay adjustment circuit of the present invention;

[0035] Figure 4 Shows the structural diagram of the single-stage delay adjustment circuit of the present invention;

[0036] Figure 5 Shows the block diagram of an ONFI PHY training system applicable to multiple types of delay line structures according to the present invention. Detailed implementation manners

[0037] In order to more clearly understand the above objects, features and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

[0038] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

[0039] Figure 1 Shows the flowchart of an ONFI PHY training method applicable to multiple types of delay line structures according to the present invention.

[0040] As Figure 1 shown, the first aspect of the present invention provides an ONFI PHY training method applicable to multiple types of delay line structures;

[0041] The training method flow provided by the present invention is simultaneously adapted to the existing single-stage delay adjustment circuit and the following two types of delay adjustment circuit structures: the segmented delay adjustment circuit and the multi-stage delay adjustment circuit.

[0042] Figure 2 Shows the structural diagram of the segmented delay adjustment circuit of the present invention;

[0043] Figure 3 Shows the structural diagram of the multi-stage delay adjustment circuit of the present invention;

[0044] Figure 4 Shows the structural diagram of the single-stage delay adjustment circuit of the present invention;

[0045] The segmented delay adjustment circuit has one long delay line and multiple short delay lines, as Figure 2 shown;

[0046] The multi-stage delay adjustment circuit has multiple delay lines, and the structure is as Figure 3 shown;

[0047] Taking the delay adjustment circuit design for adjusting DQS as an example, if a single-segment delay line controls the phase relationship between all DQs and the corresponding DQS, the structure is as follows Figure 4 as shown;

[0048] In the embodiments of the present invention, the "long delay line (delay line)" and "short delay line" mentioned are described based on the structural basis of the segmented delay adjustment circuit. For the multi-segment delay adjustment circuit structure, during the training process, when performing the long delay line operation, multiple delay lines are regarded as one delay line for configuration, and when performing the short delay line operation, they are regarded as different DQ pairs for delay line configuration. For the single-segment delay line structure, only the process S1 of the present invention needs to be completed.

[0049] The present invention provides an ONFI PHY training method based on a segmented design delay line, and it is also applicable to other delay line structures. As Figure 1 shown, it is mainly divided into five processes:

[0050] S1: Coarse scan to obtain sampleable values, use a fixed step to scan on the long delay line to obtain a coarse sampling window, and take the configuration obtained from the coarse scan window as the configuration reference for the subsequent processes;

[0051] S2: Train to obtain the minimum value in the long delay line configuration and align the DQs;

[0052] Step a1: All short delay lines are configured to 0, and the long delay line uses the minimum value of the coarse scan window as the initial point;

[0053] Step a2: Execute the preset training instruction to compare the data. If the data is correct, the long delay line decreases by a preset unit and repeats step 2; if the data is incorrect and the long delay line configuration is not 0, then exit step a2 and proceed to the next process. At this time, it means that the delay line has reached the critical position; if the delay line configuration is 0, then exit step a2, indicating that the long delay line is already the minimum;

[0054] Step a3: Record the error DQ bit positions; if all DQ bit positions are in error, it means that the DQs are already aligned, the skew has dropped to the lowest and exit step 3; if a group of short delay lines has reached the maximum value, it means that the adjustment ability of a certain DQ corresponding to the short delay line has been used up and the short delay line is full, and it is impossible to continue to reduce the DQ skew. At this time, exit step 3; otherwise, increase the preset unit of the short delay line corresponding to the error DQ and return to step a2;

[0055] Step a4: Freeze the short delay line configuration at this time, indicating that dq is aligned. Record the long delay line at this time as MIN, representing the lower limit of the sampling window.

[0056] S3: Take the average of MIN obtained in Process 2 and the center value of the coarse scan window as the initial point for Process S4.

[0057] S4: Train to obtain the maximum value of the long delay line configuration.

[0058] Step b1: Execute the training instruction to compare data. If the data is correct, increase the preset unit long delay line configuration value, and loop to execute the training instruction to compare data until the data is incorrect, then enter Step b2.

[0059] Step b2: Record the long delay line at this time as MAX, representing the upper limit of the sampling window.

[0060] S5: Take the average of MIN obtained in Process S2 and MAX obtained in Process S4 as the final training result value, marked as the final configuration value.

[0061] It should be noted that in Process S1, the sampleable points can be automatically obtained, and other preset methods or other preset steps can be used to scan the acquisition of the coarse sampling window. The preset unit is the preset step size. In S3, because during the dq alignment process, the short delay line provides partial delay, the window obtained in Process S1 or the original ideal point corresponds to a larger actual delay line. Therefore, this step is needed to select a more appropriate initial point. If it is necessary to reduce the coupling relationship, the assignment here can be made without relying on the result value of the coarse scan process.

[0062] Through the present invention, the following technical effects can be achieved:

[0063] Simultaneously execute the actions of finding the sampling window and aligning dq, increase the data window, and improve the training effect and efficiency.

[0064] Regard delay lines with different structures as similar structures, and use the same set of processes for training. The same set of processes can adapt to multiple types of delay line structures.

[0065] Add a coarse scan process to automatically obtain sample points; change the initial point setting for finding the upper and lower limits of the sampling window to avoid the situation of training failure caused by incorrect initial values; improve the robustness of the training process.

[0066] There is no large coupling relationship between different processes, and the specific implementation method can be freely implemented, improving the flexibility of the training process.

[0067] Figure 5 The block diagram of an ONFI PHY training system according to the present invention applicable to multi-type delay line structures is shown.

[0068] In a second aspect of the present invention, there is also provided an ONFI PHY training system 5 applicable to multi-type delay line structures, the system comprising: a memory 51, a processor 52, wherein the memory includes an ONFI PHY training program applicable to multi-type delay line structures, and when the ONFI PHY training program applicable to multi-type delay line structures is executed by the processor, the following steps are implemented:

[0069] S1: Coarse scan to obtain sampleable values, use a fixed step scan on the long delay line to obtain a coarse sampling window, and take the configuration obtained from the coarse scan window as the configuration reference for the subsequent process;

[0070] S2: Train to obtain the minimum value in the long delay line configuration and align dq;

[0071] Step a1: All short delay lines are configured to 0, and the minimum value of the coarse scan window is used as the initial point for the long delay line;

[0072] Step a2: Execute a preset training instruction to compare data. If the data is correct, the long delay line is decreased by a preset unit and step 2 is repeated; if the data is incorrect and the long delay line configuration is not 0, then step a2 is exited and the next process is entered. At this time, it means that the delay line has reached the critical position; if the delay line configuration is 0, then step a2 is exited, indicating that the long delay line is already the minimum;

[0073] Step a3: Record the dq bit positions where errors occur; if all dq bit positions have errors, it means that dq has been aligned, the skew has been reduced to the lowest and step 3 is exited; if a group of short delay lines has reached the maximum value, it means that the adjustment ability of a certain dq corresponding to the short delay line has been used up and the short delay line is full, and the dq skew cannot be further reduced. At this time, step 3 is exited; otherwise, the short delay line corresponding to the incorrect dq is increased by a preset unit and return to step a2;

[0074] Step a4: Freeze the short delay line configuration at this time, indicating that dq has been aligned, and record the long delay line at this time as MIN, indicating the lower limit of the sampling window;

[0075] S3: Take the average value of MIN obtained in process two and the center value of the coarse scan window as the initial point for process S4;

[0076] S4: Train to obtain the maximum value of the long delay line configuration;

[0077] Step b1: execute the training command to compare the data. If the data is correct, increase the preset unit length delayline configuration value, and execute the training command to compare the data repeatedly until the data is wrong, and then enter step b2;

[0078] Step b2: record the long delayline at this time as MAX, indicating the upper limit of the sampling window;

[0079] S5: Take the average of the MIN obtained in process S2 and the MAX obtained in process S4 as the final training result value, and mark it as the final configuration value.

[0080] It should be noted that the S1 process can automatically obtain sampleable points, and the coarse sampling window can be scanned in other preset ways or other preset steps. The preset unit is the preset step size. In S3, because the short delayline provides partial delay during the dq alignment process, the window or original ideal point obtained in the process S1 will be larger than the actual delayline, so a more suitable initial point needs to be selected in this step. If the coupling relationship needs to be reduced, the value can be assigned here without relying on the result value of the coarse scanning process.

[0081] The third aspect of the present invention also provides a computer-readable storage medium, which includes an ONFI PHY training program applicable to multiple types of delay line structures. When the ONFIPHY training program applicable to multiple types of delay line structures is executed by a processor, the steps of the ONFIPHY training method applicable to multiple types of delay line structures as described in any one of the above items are implemented.

[0082] The present invention discloses an ONFI PHY training method suitable for multi-type delay line structures. In this process, the range of sampleable values ​​is first determined by coarse scanning, and a coarse sampling window is obtained by fixed stepping of a long delayline as a subsequent reference. Subsequently, the minimum value of the long delayline is found through training and dq is aligned. During the process, a short delayline is used to adjust dqskew until dq is aligned or the adjustment capacity of the short delayline is exhausted. Then, the average value of the center value and the minimum value of the coarse scanning window is used as the initial point to train the maximum value of the long delayline. Finally, the average value of the minimum value and the maximum value is taken as the final configuration value to complete the entire training process. Through the present invention, the actions of finding the sampling window and aligning dq can be performed simultaneously, the data window can be enlarged, and the effect and efficiency of training can be improved.

[0083] In several embodiments provided by this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed with each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be electrical, mechanical, or other forms.

[0084] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units. They can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0085] In addition, each functional unit in the embodiments of the present invention can be all integrated in a processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in a unit. The above integrated units can be implemented in the form of hardware or in the form of hardware plus software functional units.

[0086] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments. The foregoing storage medium includes: removable storage devices, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs and other various media that can store program codes.

[0087] Alternatively, if the above integrated units of the present invention are implemented in the form of software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present invention essentially or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present invention. The foregoing storage medium includes: removable storage devices, ROM, RAM, magnetic disks, or optical discs and other various media that can store program codes.

[0088] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims described.

Claims

1. An ONFI PHY training method applicable to multiple types of delay line structures, characterized in that: include: S1: Coarse scanning obtains sampleable values. Fixed step scanning is used on a long delayline to obtain a coarse sampling window. The configuration obtained from the coarse scanning window is used as a configuration reference for subsequent processes. S2: Train to get the minimum value in the long delayline configuration and align dq; Step a1: All short delay lines are set to 0, and the long delay line uses the minimum value of the coarse scan window as the initial point; Step a2: Execute the preset training instruction to compare the data. If the data is correct, the long delayline is reduced by the preset unit and step a2 is repeated; if the data is wrong and the long delayline configuration is not 0, exit step a2 and proceed to the next process, which means that the long delayline has reached the critical position; if the long delayline configuration is 0, exit step a2, which means that the long delayline has been minimized; Step a3: record the erroneous dq bit; if all dq bits are erroneous, it means that the dq has been aligned, the skew has been reduced to the minimum and step a3 is exited; if a group of short delay lines has reached the maximum value, it means that the adjustment capacity of the short delay line corresponding to a certain dq has been exhausted and the short delay line is full, and the dq skew cannot be further reduced, and step a3 is exited at this time; otherwise, the short delay line corresponding to the erroneous dq increases by a preset unit and returns to step a2; Step a4: Freeze the short delayline configuration at this time, indicating that dq is aligned, and record the long delayline at this time as MIN, indicating the lower limit of the sampling window; S3: Take the average of the MIN and the center value of the rough scan window obtained in process S2 as the starting point of process S4; S4: Train to obtain the maximum value of the long delayline configuration; Step b1: execute the training command to compare the data. If the data is correct, increase the preset unit length delayline configuration value, and execute the training command to compare the data repeatedly until the data is wrong, and then enter step b2; Step b2: record the long delayline at this time as MAX, indicating the upper limit of the sampling window; S5: Take the average of the MIN obtained in process S2 and the MAX obtained in process S4 as the final training result value, and mark it as the final configuration value.

2. An ONFI PHY training system suitable for multiple types of delay line structures, characterized in that: The system includes: a memory and a processor, wherein the memory includes an ONFI PHY training program applicable to multiple types of delay line structures, and when the ONFI PHY training program applicable to multiple types of delay line structures is executed by the processor, the following steps are implemented: S1: Coarse scanning obtains sampleable values. Fixed step scanning is used on a long delayline to obtain a coarse sampling window. The configuration obtained from the coarse scanning window is used as a configuration reference for subsequent processes. S2: Train to get the minimum value in the long delayline configuration and align dq; Step a1: All short delay lines are set to 0, and the long delay line uses the minimum value of the coarse scan window as the initial point; Step a2: Execute the preset training instruction to compare the data. If the data is correct, the long delayline is reduced by the preset unit and step a2 is repeated; if the data is wrong and the long delayline configuration is not 0, exit step a2 and proceed to the next process, which means that the long delayline has reached the critical position; if the long delayline configuration is 0, exit step a2, which means that the long delayline has been minimized; Step a3: record the erroneous dq bit; if all dq bits are erroneous, it means that the dq has been aligned, the skew has been reduced to the minimum and step a3 is exited; if a group of short delay lines has reached the maximum value, it means that the adjustment capacity of the short delay line corresponding to a certain dq has been exhausted and the short delay line is full, and the dq skew cannot be further reduced, and step a3 is exited at this time; otherwise, the short delay line corresponding to the erroneous dq increases by a preset unit and returns to step a2; Step a4: Freeze the short delayline configuration at this time, indicating that dq is aligned, and record the long delayline at this time as MIN, indicating the lower limit of the sampling window; S3: Take the average of the MIN and the center value of the rough scan window obtained in process S2 as the starting point of process S4; S4: Train to obtain the maximum value of the long delayline configuration; Step b1: execute the training command to compare the data. If the data is correct, increase the preset unit length delayline configuration value, and execute the training command to compare the data repeatedly until the data is wrong, and then enter step b2; Step b2: record the long delayline at this time as MAX, indicating the upper limit of the sampling window; S5: Take the average of the MIN obtained in process S2 and the MAX obtained in process S4 as the final training result value, and mark it as the final configuration value.

3. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes an ONFI PHY training program applicable to multiple types of delay line structures. When the ONFI PHY training program applicable to multiple types of delay line structures is executed by a processor, the steps of the ONFI PHY training method applicable to multiple types of delay line structures as claimed in claim 1 are implemented.

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