A pipeline analog-to-digital conversion circuit and method

Abstract

The present invention discloses a pipeline analog-to-digital conversion circuit and method. The pipeline analog-to-digital conversion circuit includes a pipeline conversion module, a random sequence generation module and a digital calibration module; the pipeline conversion module includes a multi-stage analog-to-digital conversion unit; the random sequence generation module includes a plurality of random sequence generators; the random sequence generator is used to send the random number sequence to the first m-stage analog-to-digital conversion unit and the digital calibration module; the pipeline conversion module is used to perform multi-stage analog-to-digital conversion on the input signal based on the random number sequence, and output a plurality of digital codes; the digital calibration module is used to calibrate the digital codes output by the first m-stage analog-to-digital conversion unit according to the random number sequence and the calibration parameters based on the order of receiving the plurality of digital codes, calibrate the digital codes output by the remaining analog-to-digital conversion units according to the calibration parameters, and obtain the target digital value according to the calibration result. The technical solution of the present invention reduces the delay of data processing and improves the overall performance of the pipeline analog-to-digital conversion circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and in particular to a pipeline analog-to-digital conversion circuit and method. Background Art

[0002] The pipeline analog-to-digital converter is a high-speed, high-precision analog-to-digital converter that is widely used in various high-performance data acquisition systems. The pipeline analog-to-digital converter performs multi-stage analog-to-digital conversion and outputs multiple digital codes. In order to improve the accuracy of the analog-to-digital conversion, a digital calibration circuit is set to calibrate multiple digital codes.

[0003] Multiple delay circuits are arranged between the pipeline analog-to-digital converter and the digital-to-analog conversion circuit to delay the output of each stage of the analog-to-digital converter so that the digital calibration circuit can receive all digital codes at the same time. After receiving all the digital codes, multiple digital codes can be calibrated and the final digital value can be output. However, this method causes a large delay in data output, which makes the response time of the analog-to-digital conversion system longer. Summary of the invention

[0004] The present invention provides a pipeline analog-to-digital conversion circuit and method to solve the problem that there is a large delay in data output, resulting in a long response time of the analog-to-digital conversion system.

[0005] According to one aspect of the present invention, a pipeline analog-to-digital conversion circuit is provided, the pipeline analog-to-digital conversion circuit comprising: a pipeline conversion module, a random sequence generation module and a digital calibration module; the pipeline conversion module comprises multiple stages of interconnected analog-to-digital conversion units;

[0006] The random sequence generation module includes a plurality of random sequence generators, the number of which is less than the number of stages of the analog-to-digital conversion units; in the first m stages of the analog-to-digital conversion units, each of the analog-to-digital conversion units is connected to a random sequence generator; m is an integer greater than 1; the random sequence generation module is also connected to the digital calibration module; the random sequence generator is used to generate a random number sequence, and send the random number sequence to the first m stages of the analog-to-digital conversion units and the digital calibration module;

[0007] The pipeline conversion module receives an input signal and is connected to the digital calibration module; the pipeline conversion module is used to perform multi-stage analog-to-digital conversion on the input signal based on the random number sequence, and output a plurality of digital codes to the digital calibration module;

[0008] The digital calibration module is used to calibrate the digital codes output by the first m-stage analog-to-digital conversion units based on the order in which multiple digital codes are received, according to the random number sequence and the calibration parameters, calibrate the digital codes output by the remaining analog-to-digital conversion units after the m-th stage analog-to-digital conversion unit according to the calibration parameters, and obtain the target digital value according to the calibration result.

[0009] Optionally, the digital calibration module is specifically used to subtract the random number sequence corresponding to each analog-to-digital conversion unit from each digital code corresponding to the first m analog-to-digital conversion units to obtain m first digital values; and multiply the first digital values ​​corresponding to the analog-to-digital conversion units from the 2nd to the mth level by the corresponding calibration parameters to obtain m-1 second digital values; add the digital codes corresponding to the remaining analog-to-digital conversion units after the mth level analog-to-digital conversion unit to obtain a first sum value, and multiply the first sum value by the corresponding calibration parameters to obtain a third digital value; and add the first digital value corresponding to the first-level analog-to-digital conversion unit, m-1 second digital values, and the third digital value to obtain the target digital value.

[0010] Optionally, the calibration parameter corresponding to the second-level analog-to-digital conversion unit is the first calibration parameter, and the calibration parameter corresponding to the k-th-level analog-to-digital conversion unit is the product of the calibration parameters corresponding to all analog-to-digital conversion units from the second level to the k-th level; wherein k is an integer greater than or equal to 3 and less than or equal to m;

[0011] The calibration parameters corresponding to the remaining analog-to-digital conversion units after the m-th stage analog-to-digital conversion unit are the products of all the calibration parameters from the first calibration parameter to the m-th calibration parameter.

[0012] Optionally, the digital calibration module includes m subtractors and a first adder;

[0013] The first input end of the subtractor is connected to the random sequence generator, the second input end of the subtractor is connected to the corresponding analog-to-digital conversion unit, and the subtractor is used to subtract the random number sequence corresponding to each analog-to-digital conversion unit from each digital code corresponding to the first m stages of analog-to-digital conversion units to obtain m first digital values;

[0014] The input end of the first adder is connected to the remaining analog-to-digital conversion units after the mth stage analog-to-digital conversion unit, and the first adder is used to add the digital codes output by the remaining analog-to-digital conversion units after the mth stage analog-to-digital conversion unit to obtain a first sum value.

[0015] Optionally, the digital calibration module further includes m multipliers;

[0016] The input end of the i-th multiplier is connected to the output end of the subtractor corresponding to the i+1-th analog-to-digital conversion unit; wherein i is an integer greater than or equal to 1 and less than or equal to m-1; the first m-1 multipliers are used to multiply the first digital values ​​corresponding to the second to m-th analog-to-digital conversion units by the corresponding calibration parameters to obtain m-1 second digital values;

[0017] The input end of the m-th multiplier is connected to the output end of the first adder, and the m-th multiplier is used to multiply the first added value by the corresponding calibration parameter to obtain a third digital value.

[0018] Optionally, the digital calibration module further includes m second adders;

[0019] A first input terminal of the first second adder is connected to the output terminal of the first multiplier, and a second input terminal of the first second adder is connected to the output terminal of the first subtractor;

[0020] The first input terminal of the jth second adder is connected to the output terminal of the jth multiplier, and the second input terminal of the jth second adder is connected to the output terminal of the j-1th second adder; wherein j is an integer greater than or equal to 2 and less than or equal to m.

[0021] Optionally, the digital calibration module further includes m+1 registers;

[0022] The first register is connected between the output terminal of the first subtractor and the second input terminal of the first second adder;

[0023] The j-th register is connected between the output terminal of the j-1-th second adder and the second input terminal of the j-th second adder;

[0024] The input end of the m+1th register is connected to the output end of the mth second adder, and the output end of the m+1th register is the output end of the digital calibration module.

[0025] Optionally, the pipeline analog-to-digital conversion circuit further includes a calibration parameter calculation module;

[0026] The calibration parameter calculation module is connected to the digital calibration module, and is used to calculate the calibration parameters corresponding to the second-level analog-to-digital conversion unit to the m-th-level analog-to-digital conversion unit, and calculate the calibration parameters corresponding to the remaining analog-to-digital conversion units after the m-th-level analog-to-digital conversion unit.

[0027] According to another aspect of the present invention, a pipeline analog-to-digital conversion method is provided, and the pipeline analog-to-digital conversion method is implemented by the pipeline analog-to-digital conversion circuit described in any embodiment of the present invention;

[0028] The pipeline analog-to-digital conversion method comprises:

[0029] The random sequence generator generates a random number sequence and sends the random number sequence to the first m-stage analog-to-digital conversion unit and the digital calibration module;

[0030] The pipeline conversion module performs multi-stage analog-to-digital conversion on the input signal based on the random number sequence, and outputs a plurality of digital codes to the digital calibration module;

[0031] The digital calibration module calibrates the digital codes output by the first m-stage analog-to-digital conversion units based on the random number sequence and the calibration parameters, and obtains a target digital value according to the calibration result.

[0032] Optionally, the digital calibration module calibrates the digital code output by the first m-stage analog-to-digital conversion unit based on the random number sequence and the calibration parameter, and obtains a target digital value according to the calibration result, including:

[0033] The digital calibration module subtracts the random number sequence corresponding to each analog-to-digital conversion unit from each digital code corresponding to the first m analog-to-digital conversion units to obtain m first digital values;

[0034] The digital calibration module multiplies the first digital values ​​corresponding to the 2nd to mth analog-to-digital conversion units by corresponding calibration parameters to obtain m-1 second digital values;

[0035] The digital calibration module adds up the digital codes corresponding to the remaining analog-to-digital conversion units after the m-th analog-to-digital conversion unit to obtain a first sum value, and multiplies the first sum value by a corresponding calibration parameter to obtain a third digital value;

[0036] The digital calibration module adds the first digital value corresponding to the first-stage analog-to-digital conversion unit, m-1 second digital values, and the third digital value to obtain the target digital value.

[0037] The technical solution of the embodiment of the present invention is to transmit the random number sequence output by the random sequence generator to each analog-to-digital conversion unit of the first m analog-to-digital conversion units, so that the quantization errors of the first m analog-to-digital conversion units are randomized, and the output errors of the first m analog-to-digital conversion units are reduced. After reducing the output errors of the first m analog-to-digital conversion units, the errors of the analog-to-digital conversion units after the m-th analog-to-digital conversion unit will also be reduced, so that the analog-to-digital conversion units after the m-th analog-to-digital conversion unit do not need to be connected to the random sequence generator. In this way, the number of random sequence generators can be reduced on the basis of ensuring the reduction of errors, the circuit cost can be reduced, and the calculation time can be reduced. The digital calibration module can calibrate the digital codes output by the first m-stage analog-to-digital conversion units according to the random number sequence and the calibration parameters based on the order in which the multiple digital codes are received, and calibrate the digital codes output by the remaining analog-to-digital conversion units after the m-th stage analog-to-digital conversion unit according to the calibration parameters. The digital codes that arrive at the digital calibration module first can be calibrated first, so there is no need to set a delay circuit, reduce the delay time, and provide a faster data conversion speed, so that the response time of the entire pipeline analog-to-digital conversion circuit is shorter, and higher real-time performance can be achieved, which is conducive to the application of the pipeline analog-to-digital conversion circuit in an instant response system. And while the digital calibration module is calibrating, the subsequent analog-to-digital conversion unit can perform analog-to-digital conversion, which can reduce the duration of the analog-to-digital conversion, that is, reduce the operation time, increase the clock frequency, and reduce the total delay of data processing, thereby improving the overall performance of the pipeline analog-to-digital conversion circuit.

[0038] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 It is a structural schematic diagram of a pipeline analog-to-digital conversion circuit provided by an embodiment of the present invention;

[0041] Figure 2 It is a structural schematic diagram of another pipeline analog-to-digital conversion circuit provided by an embodiment of the present invention;

[0042] Figure 3 It is a structural schematic diagram of another pipeline analog-to-digital conversion circuit provided by an embodiment of the present invention;

[0043] Figure 4 It is a structural schematic diagram of a pipeline analog-to-digital conversion unit provided by an embodiment of the present invention;

[0044] Figure 5 is a flow chart of a pipeline analog-to-digital conversion method provided by an embodiment of the present invention;

[0045] Figure 6 This is a flow chart of another pipeline analog-to-digital conversion method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] The embodiment of the present invention provides a pipeline analog-to-digital conversion circuit. Figure 1 is a schematic diagram of a pipeline analog-to-digital conversion circuit provided by an embodiment of the present invention, with reference to Figure 1 The pipeline analog-to-digital conversion circuit includes: a pipeline conversion module 10, a random sequence generation module 20 and a digital calibration module 30; the pipeline conversion module 10 includes a plurality of interconnected analog-to-digital conversion units 110;

[0049] The random sequence generation module 20 includes a plurality of random sequence generators 210, the number of which is less than the number of stages of the analog-to-digital conversion unit 110; in the first m stages of the analog-to-digital conversion unit, each analog-to-digital conversion unit is connected to a random sequence generator 210; m is an integer greater than 1; the random sequence generation module 20 is also connected to the digital calibration module 30; the random sequence generator 210 is used to generate a random number sequence, and send the random number sequence to the first m stages of the analog-to-digital conversion unit and the digital calibration module 30;

[0050] The pipeline conversion module 10 is connected to the input signal VIN, and the pipeline conversion module 10 is connected to the digital calibration module 30; the pipeline conversion module 10 is used to perform multi-stage analog-to-digital conversion on the input signal VIN based on a random number sequence, and output multiple digital codes to the digital calibration module 30;

[0051] The digital calibration module 30 is used to calibrate the digital codes output by the first m-stage analog-to-digital conversion units 110 based on the order in which multiple digital codes are received, according to a random number sequence and calibration parameters, calibrate the digital codes output by the remaining analog-to-digital conversion units 110 after the m-th-stage analog-to-digital conversion unit 110 according to the calibration parameters, and obtain a target digital value based on the calibration result.

[0052] Among them, the input signal VIN is a collected analog signal. The pipeline conversion module 10 may include a multi-stage analog-to-digital conversion unit 110, and the pipeline conversion module 10 may perform analog-to-digital conversion on the input signal VIN and output multiple digital codes. The number of stages of the pipeline conversion module 10 is greater than m. For example, the first-stage analog-to-digital conversion unit 110 performs analog-to-digital conversion on the input signal VIN to obtain the first digital code, and outputs it to the digital calibration module 30; and performs digital-to-analog conversion on the first digital code, and the obtained analog value is subtracted from the input signal VIN of the first-stage analog-to-digital conversion unit 110, and the difference is amplified and output to the second-stage analog-to-digital conversion unit 110. The second-stage analog-to-digital conversion unit 110 performs analog-to-digital conversion on the amplified difference output by the first-stage analog-to-digital conversion unit 110 to obtain a second digital code, and outputs it to the digital calibration module 30; and performs digital-to-analog conversion on the second digital code to obtain an analog value different from the signal input by the second-stage analog-to-digital conversion unit 110 (the amplified difference output by the first-stage analog-to-digital conversion unit 110), and amplifies the difference and outputs it to the third-stage analog-to-digital conversion unit 110. This is repeated until the last-stage analog-to-digital conversion unit 110 outputs the last digital code to the digital calibration module 30. In this way, the analog input (input signal VIN) can be converted into a digital code output, and the digital calibration module 30 calibrates and sums all the digital codes to obtain an accurate analog-to-digital conversion result, that is, the digital value corresponding to the input signal VIN.

[0053] Among them, the random sequence generator 210 can generate a random number sequence, and the random number sequence can include multiple numbers, and the value of each number can be 1 or -1, for example, but it is not limited. The random number sequence output by the random sequence generator 210 can be transmitted to each analog-to-digital conversion unit 110 of the first m-level analog-to-digital conversion unit, so that the first m-level analog-to-digital conversion unit 110 performs multiple analog-to-digital conversions based on multiple random number sequences and outputs multiple digital codes. In this way, the quantization error can be randomized, thereby reducing the harmonic distortion caused by fixed step quantization, that is, reducing the digital code distortion problem caused by fixed errors between each level of analog-to-digital conversion unit 110. In addition, the random number sequence generated by the random sequence generation module 20 is not related to the input signal VIN, and can correct the offset and inter-stage gain error of the entire pipeline conversion module 10 channel, expand the effective dynamic range of the analog-to-digital conversion unit 110 in the pipeline conversion module 10, and improve the linearity of the signal in the pipeline conversion module 10.

[0054] Specifically, each analog-to-digital conversion unit 110 of the first m analog-to-digital conversion units corresponds to a random sequence generator 210, so that the random number sequence input to each analog-to-digital conversion unit 110 can be random. By transmitting the random number sequence output by the random sequence generator 210 to each analog-to-digital conversion unit 110 of the first m analog-to-digital conversion units, the quantization errors of the first m analog-to-digital conversion units 110 are randomized, and the output errors of the first m analog-to-digital conversion units 110 are reduced. The analog-to-digital conversion units 110 after the m-th analog-to-digital conversion unit 110 perform analog-to-digital conversion based on the outputs of the first m analog-to-digital conversion units 110, so after reducing the output errors of the first m analog-to-digital conversion units 110, the errors of the analog-to-digital conversion units 110 after the m-th analog-to-digital conversion unit 110 will also be reduced, so that the analog-to-digital conversion units after the m-th analog-to-digital conversion unit do not need to be connected to the random sequence generator 210. In this way, the number of random sequence generators 210 can be reduced while ensuring that errors are reduced, which can reduce circuit costs and calculation time, and is conducive to improving the speed of analog-to-digital conversion.

[0055] The digital calibration module 30 can calibrate the digital codes output by the first m-stage analog-to-digital conversion units according to the random number sequence and the calibration parameters based on the order in which the multiple digital codes are received, and calibrate the digital codes output by the remaining analog-to-digital conversion units after the m-th stage analog-to-digital conversion unit according to the calibration parameters. The digital codes that arrive at the digital calibration module 30 first can be calibrated first, so there is no need to set a delay circuit, reduce the delay time, and provide a faster data conversion speed, so that the response time of the entire pipeline analog-to-digital conversion circuit is shorter, and higher real-time performance can be achieved, which is conducive to the application of the pipeline analog-to-digital conversion circuit in an instant response system, such as a real-time control system, a real-time image processing system, or a high-speed communication system. For example, after the first-stage analog-to-digital conversion unit 110 outputs the first digital code, the digital calibration module 30 calibrates the first digital code, and at the same time, the second-stage analog-to-digital conversion unit 110 can perform analog-to-digital conversion, which can reduce the duration of the analog-to-digital conversion, that is, reduce the operation time, increase the clock frequency, and reduce the total delay of data processing, thereby improving the overall performance of the pipeline analog-to-digital conversion circuit. In addition, the digital calibration module 30 calibrates the digital code output by the first m-stage analog-to-digital conversion units 110 according to the random number sequence and the calibration parameters, and calibrates the digital code output by the remaining analog-to-digital conversion units after the m-th-stage analog-to-digital conversion unit according to the calibration parameters. It can not only use the random number sequence to reduce the error, but also use the calibration parameters for calibration, which can improve the accuracy of the calibration.

[0056] For example, the pipeline analog-to-digital conversion module 10 includes n-stage analog-to-digital conversion units 110, where n is an integer greater than m, and the first m-stage analog-to-digital conversion units 110 are the first-stage analog-to-digital conversion unit 110 to the m-th-stage analog-to-digital conversion unit 110, and the first-stage analog-to-digital conversion unit 110 is the analog-to-digital conversion unit connected to the input signal VIN. The remaining analog-to-digital conversion units after the m-th-stage analog-to-digital conversion unit are the m+1-th-stage analog-to-digital conversion unit to the n-th-stage analog-to-digital conversion unit.

[0057] The technical solution of this embodiment is to transmit the random number sequence output by the random sequence generator to each level of analog-to-digital conversion unit of the first m levels of analog-to-digital conversion units, so that the quantization errors of the first m levels of analog-to-digital conversion units are randomized, and the output errors of the first m levels of analog-to-digital conversion units are reduced. After reducing the output errors of the first m levels of analog-to-digital conversion units, the errors of the analog-to-digital conversion units after the mth level of analog-to-digital conversion units will also be reduced, so that the analog-to-digital conversion units after the mth level of analog-to-digital conversion units do not need to be connected to the random sequence generator. In this way, the number of random sequence generators can be reduced on the basis of ensuring the reduction of errors, which can reduce circuit costs and reduce calculation time. The digital calibration module can calibrate the digital codes output by the first m-stage analog-to-digital conversion units according to the random number sequence and the calibration parameters based on the order in which the multiple digital codes are received, and calibrate the digital codes output by the remaining analog-to-digital conversion units after the m-th stage analog-to-digital conversion unit according to the calibration parameters. The digital codes that arrive at the digital calibration module first can be calibrated first, so there is no need to set a delay circuit, reduce the delay time, and provide a faster data conversion speed, so that the response time of the entire pipeline analog-to-digital conversion circuit is shorter, and higher real-time performance can be achieved, which is conducive to the application of the pipeline analog-to-digital conversion circuit in an instant response system. And while the digital calibration module is calibrating, the subsequent analog-to-digital conversion unit can perform analog-to-digital conversion, which can reduce the duration of the analog-to-digital conversion, that is, reduce the operation time, increase the clock frequency, and reduce the total delay of data processing, thereby improving the overall performance of the pipeline analog-to-digital conversion circuit.

[0058] On the basis of the above technical solution, optionally, the digital calibration module 30 is specifically used to subtract the random number sequence corresponding to each analog-to-digital conversion unit 110 from each digital code corresponding to the first m analog-to-digital conversion units 110 to obtain m first digital values; and multiply the first digital values ​​corresponding to the second to mth analog-to-digital conversion units 110 by the corresponding calibration parameters to obtain m-1 second digital values; add the digital codes corresponding to the remaining analog-to-digital conversion units 110 after the mth analog-to-digital conversion unit to obtain a first sum value, and multiply the first sum value by the corresponding calibration parameters to obtain a third digital value; and add the first digital value corresponding to the first-stage analog-to-digital conversion unit 110, m-1 second digital values, and the third digital value to obtain a target digital value.

[0059] Specifically, because the first m-stage analog-to-digital conversion units 110 generate digital codes based on random number sequences, for example, the signal input to each analog-to-digital conversion unit 110 in the first m-stage analog-to-digital conversion units 110 is added with the corresponding random number sequence, and then analog-to-digital conversion is performed to obtain the digital code. Alternatively, the digital code after analog-to-digital conversion is added with the random number sequence, and then digital-to-analog conversion and difference are performed and sent to the next-stage analog-to-digital conversion unit 110. Therefore, each digital code corresponding to the first m-stage analog-to-digital conversion units 110 is subtracted from the random number sequence corresponding to each analog-to-digital conversion unit 110 to obtain m first digital values, and the digital code can be calibrated based on the random number sequence to avoid the random number sequence from affecting the accuracy of the output result, and the error of the output result can be reduced.

[0060] There is no analog-to-digital conversion process before the first-stage analog-to-digital conversion unit, so the inter-stage error is small, and there is no need to use calibration parameters for calibration, which can simplify the circuit and reduce the operation time. The first digital value corresponding to the second to m-th stage analog-to-digital conversion unit 110 is multiplied by the corresponding calibration parameter to obtain m-1 second digital values, and calibration is performed using the calibration parameter to improve the accuracy of the analog-to-digital conversion. In this way, the circuit can be simplified and the operation time can be reduced.

[0061] Because the first m analog-to-digital conversion units are calibrated using a random number sequence, the errors of the remaining analog-to-digital conversion units 110 after the m-th analog-to-digital conversion unit (the m+1-th analog-to-digital conversion unit to the n-th analog-to-digital conversion unit) are relatively small, and the digital codes corresponding to the remaining analog-to-digital conversion units 110 after the m-th analog-to-digital conversion unit can be summed to obtain a first sum value, and then the first sum value is multiplied by the corresponding calibration parameter to obtain a third digital value. Then, the first digital value corresponding to the first-stage analog-to-digital conversion unit 110, m-1 second digital values, and the third digital value are summed to obtain the target digital value corresponding to the input signal VIN.

[0062] In this way, both random number sequences and calibration parameters can be used for calibration to improve calibration accuracy. The first m-stage analog-to-digital conversion units are calibrated using random number sequences, which can reduce circuit operation time and improve data conversion speed.

[0063] Optionally, the calibration parameter corresponding to the second-stage analog-to-digital conversion unit 110 is the first calibration parameter, and the calibration parameter corresponding to the k-th-stage analog-to-digital conversion unit 110 is the product of the calibration parameters corresponding to all analog-to-digital conversion units 110 from the second stage to the k-th stage; wherein k is an integer greater than or equal to 3 and less than or equal to m;

[0064] The calibration parameters corresponding to the remaining analog-to-digital conversion units 110 after the m-th analog-to-digital conversion unit 110 are the products of all the calibration parameters from the first calibration parameter to the m-th calibration parameter.

[0065] Exemplarily, the first calibration parameter is, for example, G1, that is, the calibration parameter corresponding to the second-level analog-to-digital conversion unit 110 is G1, the calibration coefficient corresponding to the third-level analog-to-digital conversion unit 110 is G1*G2, the calibration coefficient corresponding to the fourth-level analog-to-digital conversion unit 110 is G1*G2*G3, and so on. The calibration coefficient corresponding to the m-th-level analog-to-digital conversion unit 110 is G1*G2*…*G m-1 Similarly, it can be known that the calibration parameters corresponding to the remaining analog-to-digital conversion units 110 after the m-th analog-to-digital conversion unit 110 (the m+1-th analog-to-digital conversion unit to the n-th analog-to-digital conversion unit) are G1*G2*…*G m In this way, it is convenient to calibrate according to the corresponding calibration parameters, thereby improving the accuracy of digital calibration.

[0066] The calibration parameters may be pre-set or obtained by iterative optimization based on pre-set initial values, which is not limited in this embodiment.

[0067] On the basis of the above technical solutions, Figure 2 is a schematic diagram of the structure of another pipeline analog-to-digital conversion circuit provided by an embodiment of the present invention. Figure 2 , the digital calibration module 30 includes m subtractors 310 and a first adder 320;

[0068] A first input end of the subtractor 310 is connected to the random sequence generator 210, and a second input end of the subtractor 310 is connected to the corresponding analog-to-digital conversion unit 110. The subtractor 310 is used to subtract the random number sequence corresponding to each analog-to-digital conversion unit 110 from each digital code corresponding to the first m analog-to-digital conversion units 110 to obtain m first digital values;

[0069] The input end of the first adder 320 is connected to the remaining analog-to-digital conversion units 110 after the m-th stage analog-to-digital conversion unit 110, and the first adder 320 is used to add the digital codes output by the remaining analog-to-digital conversion units 110 after the m-th stage analog-to-digital conversion unit 110 to obtain a first sum value.

[0070] For example, if the first digital code output by the first-stage analog-to-digital conversion unit 110 is D1, and the random number sequence corresponding to the first-stage analog-to-digital conversion unit 110 is di1, then the first digital value corresponding to the first-stage analog-to-digital conversion unit 110 is D1-di1. Similarly, if the second digital code output by the second-stage analog-to-digital conversion unit 110 is D2, and the random number sequence corresponding to the second-stage analog-to-digital conversion unit 110 is di2, then the first digital value corresponding to the second-stage analog-to-digital conversion unit 110 is D2-di2. This is repeated until the first digital value corresponding to the m-th-stage analog-to-digital conversion unit 110 is D m -di mIn this way, m first digital values ​​can be obtained, which is convenient for subtracting the random number sequence introduced during analog-to-digital conversion.

[0071] For example, the pipeline analog-to-digital conversion module 10 includes n-stage analog-to-digital conversion units 110, where n is an integer greater than m, and the remaining analog-to-digital conversion units 110 after the m-th stage analog-to-digital conversion unit 110 are the m+1-th stage analog-to-digital conversion unit 110 to the n-th stage analog-to-digital conversion unit 110. The digital code output by the m+1-th stage analog-to-digital conversion unit 110 is D m+1 The digital code output by the m+2-th analog-to-digital conversion unit 110 is D m+2 , and so on, the digital code output by the n-th stage analog-to-digital conversion unit 110 is D n The digital codes outputted from the m+1th analog-to-digital conversion unit 110 to the nth analog-to-digital conversion unit 110 are added together to obtain a first sum value D m+1 +D m+2 +…D n .

[0072] Optionally, refer to Figure 2 , the digital calibration module 30 further includes m multipliers 330;

[0073] The input end of the i-th multiplier 330 is connected to the output end of the subtractor 310 corresponding to the i+1-th analog-to-digital conversion unit 110; wherein i is an integer greater than or equal to 1 and less than or equal to m-1; the first m-1 multipliers 330 are used to multiply the first digital values ​​corresponding to the second to m-th analog-to-digital conversion units 110 by the corresponding calibration parameters to obtain m-1 second digital values;

[0074] An input terminal of the m-th multiplier 330 is connected to an output terminal of the first adder 320 , and the m-th multiplier 330 is used to multiply the first added value by a corresponding calibration parameter to obtain a third digital value.

[0075] Exemplarily, the first multiplier 330 multiplies the first digital value D2-di2 output by the subtractor 310 corresponding to the second-stage analog-to-digital conversion unit 110 by the corresponding calibration coefficient G1 to obtain a second digital value (D2-di2)*G1. Similarly, the second multiplier 330 multiplies the first digital value D3-di3 output by the subtractor 310 corresponding to the third-stage analog-to-digital conversion unit 110 by the corresponding calibration coefficient G1*G2 to obtain a second digital value (D3-di3)*G1*G2. Similarly, the m-1th multiplier 330 multiplies the first digital value D3-di3 output by the subtractor 310 corresponding to the m-th-stage analog-to-digital conversion unit 110 by the corresponding calibration coefficient G1*G2 to obtain a second digital value (D3-di3)*G1*G2. m -di m And the corresponding calibration coefficient G1*G2*…*G m-1 Multiply them to get the second digital value (D m -dim )*G1*G2*…*G m-1 In this way, m-1 second digital values ​​can be obtained. The m-th multiplier 330 adds the first sum value D m+1 +D m+2 +…D n And the corresponding calibration coefficient G1*G2*…*G m-1 *G m Multiply them to get the third digital value (D m+1 +D m+2 +…D n )*G1*G2*…*G m-1 *G m In this way, calibration is performed using the calibration coefficient, which facilitates improving the accuracy of analog-to-digital conversion.

[0076] Optionally, refer to Figure 2 , the digital calibration module 30 further includes m second adders 340;

[0077] A first input terminal of the first second adder 340 is connected to the output terminal of the first multiplier 330 , and a second input terminal of the first second adder 340 is connected to the output terminal of the first subtractor 310 ;

[0078] The first input terminal of the jth second adder 340 is connected to the output terminal of the jth multiplier 330, and the second input terminal of the jth second adder 340 is connected to the output terminal of the j-1th second adder 340; wherein j is an integer greater than or equal to 2 and less than or equal to m.

[0079] Exemplarily, the first second adder 340 adds the first digital value D1-di1 output by the first subtractor 310 and the second digital value (D2-di2)*G1 output by the first multiplier 330, and outputs (D1-di1)+(D2-di2)*G1. The second second adder 340 adds the second digital value (D3-di3)*G1*G2 output by the second multiplier 330 and (D1-di1)+(D2-di2)*G1 output by the first second adder 340, and obtains (D1-di1)+(D2-di2)*G1+(D3-di3)*G1*G2. This is repeated in the same manner until the mth second adder 340 adds the third digital value (D1-di1) output by the mth multiplier 330. m+1 +D m+2 +…D n )*G1*G2*…*G m-1 *G m and (D1-di1)+(D2-di2)*G1+(D3-di3)*G1*G2+…(D m -dim )*G1*G2*…*G m-1 Add together to get the target digital value Dout = (D1-di1) + (D2-di2)*G1 + (D3-di3)*G1*G2 + ... (D m -di m )*G1*G2*…*G m-1 +(D m+1 +D m+2 +…D n )*G1*G2*…*G m-1 *G m In this way, the first digital value corresponding to the first-stage analog-to-digital conversion unit 110, m-1 second digital values ​​and the third digital value can be added to obtain the target digital value, and the digital code output by the analog-to-digital conversion unit 110 can be calibrated, which is beneficial to improving the accuracy of analog-to-digital conversion.

[0080] On the basis of the above technical solutions, Figure 3 is a schematic diagram of the structure of another pipeline analog-to-digital conversion circuit provided by an embodiment of the present invention. Figure 3 , the digital calibration module 30 further includes m+1 registers 350;

[0081] The first register 350 is connected between the output terminal of the first subtractor 310 and the second input terminal of the first second adder 340;

[0082] The j-th register 350 is connected between the output terminal of the j-1-th second adder 340 and the second input terminal of the j-th second adder 340;

[0083] An input end of the (m+1)th register 350 is connected to an output end of the (m)th second adder 340 , and an output end of the (m+1)th register 350 is an output end of the digital calibration module 30 .

[0084] Specifically, the first register 350 can store the first digital value output by the first subtractor 310. The second register 350 can store the output value of the first second adder 340, the third register 350 can store the output value of the second second adder 340, and so on. The m-th register 350 can store the output value of the m-th second adder 340. The m+1-th register 350 can store the target digital value and output the target digital value. In this way, for example, after the j-1-th second adder 340 outputs the value, it is first stored, and after the j-th multiplier outputs the value, the output value of the j-1-th second adder 340 is added to the output value of the j-th multiplier, so as to facilitate calibration according to the output order of the digital code, thereby reducing the delay of data processing.

[0085] Optionally, refer to Figure 3 , the pipeline analog-to-digital conversion circuit also includes a calibration parameter calculation module 40;

[0086] The calibration parameter calculation module 40 is connected to the digital calibration module 30, and is used to calculate the calibration parameters corresponding to the second-level analog-to-digital conversion unit 110 to the m-th-level analog-to-digital conversion unit 110, and calculate the calibration parameters corresponding to the remaining analog-to-digital conversion units 110 after the m-th-level analog-to-digital conversion unit 110.

[0087] Specifically, the calibration parameter calculation module 40 can be implemented by a plurality of multipliers, so that the calibration coefficient G1*G2 corresponding to the third-level analog-to-digital conversion unit 110, the calibration coefficient G1*G2*G3 corresponding to the fourth-level analog-to-digital conversion unit 110, and so on can be calculated. The calibration coefficient G1*G2*…*G3 corresponding to the m-th-level analog-to-digital conversion unit 110 can be calculated. m-1 Similarly, a multiplier may be used to calculate the calibration parameters G1*G2*…*G corresponding to the remaining analog-to-digital conversion units 110 after the m-th analog-to-digital conversion unit 110 (the m+1-th analog-to-digital conversion unit to the n-th analog-to-digital conversion unit). m In this way, it is easy to calculate the calibration parameters, so that calibration can be performed using the calibration parameters, which is beneficial to improving the accuracy of analog-to-digital conversion.

[0088] On the basis of the above technical solutions, Figure 4 is a schematic diagram of the structure of a pipeline analog-to-digital conversion unit provided by an embodiment of the present invention. Figure 4 , the analog-to-digital conversion unit 110 includes an analog-to-digital converter 111, a third adder 112, a digital-to-analog converter 113, a fourth adder 114 and an operational amplifier 115;

[0089] The input end of the analog-to-digital converter 111 in the first-stage analog-to-digital conversion unit 110 is connected to the input signal VIN, the input end of the analog-to-digital converter 111 in the k-1th-stage analog-to-digital conversion unit 110 is connected to the k-2th-stage analog-to-digital conversion unit 110, and the analog-to-digital converter 111 is used to output a digital code;

[0090] The third adder 112 is connected to the output end of the analog-to-digital converter 111 and the random sequence generator 210 respectively;

[0091] An input terminal of the digital-to-analog converter 113 is connected to an output terminal of the third adder 112;

[0092] The first input end of the fourth adder 114 in the first-stage analog-to-digital conversion unit 110 is connected to the input signal VIN, the first input end of the fourth adder 114 in the k-1-th stage analog-to-digital conversion unit 110 is connected to the k-2-th stage analog-to-digital conversion unit 110, and the second input end of the fourth adder 114 is connected to the output end of the digital-to-analog converter 113;

[0093] The operational amplifier 115 is connected to the output terminal of the fourth adder 114 .

[0094] Specifically, the analog-to-digital converter 111 can convert the analog quantity input to it to obtain a corresponding digital code, and output the digital code to the digital calibration module 30. The third adder 112 can add the digital code to the random number series, and the digital-to-analog converter 113 can perform digital-to-analog conversion on the result of adding the digital code to the random number series to obtain an updated analog quantity. The fourth adder 114 can make a difference between the analog quantity input to the analog-to-digital converter 111 and the updated analog quantity to obtain a difference value, and the operational amplifier 115 amplifies the difference value to obtain Vres, and outputs it to the next-level analog-to-digital conversion unit 110. This is repeated until the last-level analog-to-digital converter outputs the last digital code to the digital calibration module 30, thereby realizing pipeline analog-to-digital conversion.

[0095] It should be noted that Figure 4 The input and output of the first-stage analog-to-digital conversion unit 110 are used as an example, but are not limiting. It should also be noted that the last-stage analog-to-digital conversion unit 110 may only include the analog-to-digital converter 111 .

[0096] Optionally, refer to Figure 3 The pipeline conversion module 10 further includes a sample holder 120, the input end of the sample holder 120 is connected to the input signal VIN, and the output end of the sample holder 120 is connected to the first-stage analog-to-digital conversion unit 110. The sample holder 120 can perform sampling and holding, which is beneficial to improving the reliability and stability of the pipeline analog-to-digital conversion circuit.

[0097] Optionally, refer to Figure 3 The pipeline conversion module 10 further includes an output interface 50 , which is connected to the output end of the digital calibration module 30 , and is used to output the target digital value output by the digital calibration module 30 .

[0098] An embodiment of the present invention further provides a pipeline analog-to-digital conversion method, which is implemented by the pipeline analog-to-digital conversion circuit provided by any of the above implementation schemes. Figure 5 is a flow chart of a pipeline analog-to-digital conversion method provided by an embodiment of the present invention, with reference to Figure 5 , the pipeline analog-to-digital conversion method includes:

[0099] S101. A random sequence generator generates a random number sequence and sends the random number sequence to the first m-stage analog-to-digital conversion unit and the digital calibration module.

[0100] Specifically, refer to Figure 1 , the random sequence generator 210 can generate a random number sequence, and the random number sequence can contain multiple numbers, and the value of each number can be 1 or -1, for example, but it is not limited. The random number sequence output by the random sequence generator 210 can be transmitted to each analog-to-digital conversion unit 110 of the first m-level analog-to-digital conversion unit, so that the first m-level analog-to-digital conversion unit 110 performs multiple analog-to-digital conversions based on multiple random number sequences and outputs multiple digital codes. In this way, the quantization error can be randomized, thereby reducing the harmonic distortion caused by fixed step quantization, that is, reducing the digital code distortion problem caused by fixed errors between each level of analog-to-digital conversion unit 110. In addition, the random number sequence generated by the random sequence generation module 20 is not related to the input signal VIN, and can correct the offset and inter-stage gain error of the entire pipeline conversion module 10 channel, expand the effective dynamic range of the analog-to-digital conversion unit 110 in the pipeline conversion module 10, and improve the linearity of the signal in the pipeline conversion module 10.

[0101] S102 , the pipeline conversion module performs multi-stage analog-to-digital conversion on the input signal based on the random number sequence, and outputs multiple digital codes to the digital calibration module.

[0102] Specifically, refer to Figure 1 , the pipeline conversion module 10 may include a multi-stage analog-to-digital conversion unit 110, and the pipeline conversion module 10 may perform analog-to-digital conversion on the input signal VIN and output multiple digital codes. For example, the first-stage analog-to-digital conversion unit 110 performs analog-to-digital conversion on the input signal VIN to obtain a first digital code, and outputs it to the digital calibration module 30; and performs digital-to-analog conversion on the first digital code, and the obtained analog value is subtracted from the input signal VIN of the first-stage analog-to-digital conversion unit 110, and the difference is amplified and output to the second-stage analog-to-digital conversion unit 110. The second-stage analog-to-digital conversion unit 110 performs analog-to-digital conversion on the amplified difference output by the first-stage analog-to-digital conversion unit 110 to obtain a second digital code, and outputs it to the digital calibration module 30; and performs digital-to-analog conversion on the second digital code, and the obtained analog value is subtracted from the signal input by the second-stage analog-to-digital conversion unit 110 (the amplified difference output by the first-stage analog-to-digital conversion unit 110), and the difference is amplified and output to the third-stage analog-to-digital conversion unit 110. This process is repeated until the last analog-to-digital conversion unit 110 outputs the last digital code to the digital calibration module 30. In this way, the analog input (input signal VIN) can be converted into a digital code output, and the digital calibration module 30 calibrates and sums all the digital codes to obtain an accurate analog-to-digital conversion result, that is, the digital value corresponding to the input signal VIN.

[0103] Each analog-to-digital conversion unit 110 of the first m analog-to-digital conversion units corresponds to a random sequence generator 210, so that the random number sequence input to each analog-to-digital conversion unit 110 can be random. By transmitting the random number sequence output by the random sequence generator 210 to each analog-to-digital conversion unit 110 of the first m analog-to-digital conversion units, the quantization errors of the first m analog-to-digital conversion units 110 are randomized, and the output errors of the first m analog-to-digital conversion units 110 are reduced. The analog-to-digital conversion units 110 after the m-th analog-to-digital conversion unit 110 perform analog-to-digital conversion based on the outputs of the first m analog-to-digital conversion units 110, so after reducing the output errors of the first m analog-to-digital conversion units 110, the errors of the analog-to-digital conversion units 110 after the m-th analog-to-digital conversion unit 110 will also be reduced, so that the analog-to-digital conversion units after the m-th analog-to-digital conversion unit do not need to be connected to the random sequence generator 210. In this way, the number of random sequence generators 210 can be reduced while ensuring that errors are reduced, which can reduce circuit costs and calculation time, and is conducive to improving the speed of analog-to-digital conversion.

[0104] S103 , the digital calibration module calibrates the digital codes output by the first m-stage analog-to-digital conversion units based on the random number sequence and the calibration parameters, and obtains a target digital value according to the calibration result.

[0105] Specifically, the digital calibration module 30 can calibrate the digital codes output by the first m-stage analog-to-digital conversion units according to the random number sequence and the calibration parameters based on the order in which the multiple digital codes are received, and calibrate the digital codes output by the remaining analog-to-digital conversion units after the m-th stage analog-to-digital conversion unit according to the calibration parameters. The digital codes that first arrive at the digital calibration module 30 can be calibrated first, so there is no need to set a delay circuit, reduce the delay time, and provide a faster data conversion speed, so that the response time of the entire pipeline analog-to-digital conversion circuit is shorter, and higher real-time performance can be achieved, which is conducive to the application of the pipeline analog-to-digital conversion circuit in an instant response system, such as a real-time control system, a real-time image processing system, or a high-speed communication system. For example, after the first-stage analog-to-digital conversion unit 110 outputs the first digital code, the digital calibration module 30 calibrates the first digital code, and at the same time, the second-stage analog-to-digital conversion unit 110 can perform analog-to-digital conversion, which can reduce the duration of the analog-to-digital conversion, that is, reduce the operation time, increase the clock frequency, and reduce the total delay of data processing, thereby improving the overall performance of the pipeline analog-to-digital conversion circuit. In addition, the digital calibration module 30 calibrates the digital code output by the first m-stage analog-to-digital conversion units 110 according to the random number sequence and the calibration parameters, and calibrates the digital code output by the remaining analog-to-digital conversion units after the m-th-stage analog-to-digital conversion unit according to the calibration parameters. It can not only use the random number sequence to reduce the error, but also use the calibration parameters for calibration, which can improve the accuracy of the calibration.

[0106] The technical solution of this embodiment is to transmit the random number sequence output by the random sequence generator to each level of analog-to-digital conversion unit of the first m levels of analog-to-digital conversion units, so that the quantization errors of the first m levels of analog-to-digital conversion units are randomized, and the output errors of the first m levels of analog-to-digital conversion units are reduced. After reducing the output errors of the first m levels of analog-to-digital conversion units, the errors of the analog-to-digital conversion units after the mth level of analog-to-digital conversion units will also be reduced, so that the analog-to-digital conversion units after the mth level of analog-to-digital conversion units do not need to be connected to the random sequence generator. In this way, the number of random sequence generators can be reduced on the basis of ensuring the reduction of errors, which can reduce circuit costs and reduce calculation time. The digital calibration module can calibrate the digital codes output by the first m-stage analog-to-digital conversion units according to the random number sequence and the calibration parameters based on the order in which the multiple digital codes are received, and calibrate the digital codes output by the remaining analog-to-digital conversion units after the m-th stage analog-to-digital conversion unit according to the calibration parameters. The digital codes that arrive at the digital calibration module first can be calibrated first, so there is no need to set a delay circuit, reduce the delay time, and provide a faster data conversion speed, so that the response time of the entire pipeline analog-to-digital conversion circuit is shorter, and higher real-time performance can be achieved, which is conducive to the application of the pipeline analog-to-digital conversion circuit in an instant response system. And while the digital calibration module is calibrating, the subsequent analog-to-digital conversion unit can perform analog-to-digital conversion, which can reduce the duration of the analog-to-digital conversion, that is, reduce the operation time, increase the clock frequency, and reduce the total delay of data processing, thereby improving the overall performance of the pipeline analog-to-digital conversion circuit.

[0107] Based on the above technical solutions, Figure 6 is a flowchart of another pipeline analog-to-digital conversion method provided by an embodiment of the present invention. Optionally, refer to Figure 6 , the pipeline analog-to-digital conversion method includes:

[0108] S201. A random sequence generator generates a random number sequence and sends the random number sequence to the first m-stage analog-to-digital conversion units and digital calibration modules.

[0109] S202 , the pipeline conversion module performs multi-stage analog-to-digital conversion on the input signal based on the random number sequence, and outputs multiple digital codes to the digital calibration module.

[0110] S203 , the digital calibration module subtracts the random number sequence corresponding to each analog-to-digital conversion unit from each digital code corresponding to the first m stages of analog-to-digital conversion units to obtain m first digital values.

[0111] Specifically, because the first m-stage analog-to-digital conversion units 110 generate digital codes based on random number sequences, for example, after adding the corresponding random number sequence to the signal input to each analog-to-digital conversion unit 110 in the first m-stage analog-to-digital conversion units 110, analog-to-digital conversion is performed to obtain digital codes. Therefore, the random number sequence corresponding to each analog-to-digital conversion unit 110 is subtracted from each digital code corresponding to the first m-stage analog-to-digital conversion units 110 to obtain m first digital values, and the digital code can be calibrated based on the random number sequence to avoid the random number sequence from affecting the accuracy of the output result, and the error of the output result can be reduced.

[0112] S204 , the digital calibration module multiplies the first digital values ​​corresponding to the 2nd to mth analog-to-digital conversion units by corresponding calibration parameters to obtain m-1 second digital values.

[0113] Specifically, there is no analog-to-digital conversion process before the first-stage analog-to-digital conversion unit, so the inter-stage error is small, and there is no need to use calibration parameters for calibration, which can simplify the circuit and reduce the operation time. The first digital values ​​corresponding to the second to m-th stage analog-to-digital conversion units 110 are multiplied by the corresponding calibration parameters to obtain m-1 second digital values, so as to realize calibration using calibration parameters and improve the accuracy of analog-to-digital conversion.

[0114] S205 , the digital calibration module sums the digital codes corresponding to the remaining analog-to-digital conversion units after the m-th analog-to-digital conversion unit to obtain a first sum value, and multiplies the first sum value by a corresponding calibration parameter to obtain a third digital value.

[0115] Specifically, because the first m-level analog-to-digital conversion units are calibrated using a random number sequence, the errors of the remaining analog-to-digital conversion units 110 after the m-th level analog-to-digital conversion unit (the m+1-th level analog-to-digital conversion unit to the n-th level analog-to-digital conversion unit) are relatively small, and the digital codes corresponding to the remaining analog-to-digital conversion units 110 after the m-th level analog-to-digital conversion unit can be summed to obtain a first sum value, and then the first sum value is multiplied by the corresponding calibration parameter to obtain a third digital value. In this way, the circuit can be simplified and the operation time can be reduced.

[0116] S206 , the digital calibration module adds the first digital value corresponding to the first-stage analog-to-digital conversion unit, m-1 second digital values, and the third digital value to obtain a target digital value.

[0117] Specifically, the first digital value corresponding to the first-stage analog-to-digital conversion unit 110 , m−1 second digital values, and the third digital value are added together to obtain the target digital value corresponding to the input signal VIN.

[0118] In this way, the technical solution of this embodiment can use both random number sequences and calibration parameters for calibration to improve the accuracy of calibration, and the first m stages of analog-to-digital conversion units use random number sequences for calibration, which can reduce circuit operation time and improve data conversion speed.

[0119] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0120] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A pipeline analog-to-digital conversion circuit, characterized in that: include: A pipeline conversion module, a random sequence generation module and a digital calibration module; the pipeline conversion module includes multiple stages of interconnected analog-to-digital conversion units; The random sequence generation module includes a plurality of random sequence generators, the number of which is less than the number of stages of the analog-to-digital conversion units; in the first m stages of the analog-to-digital conversion units, each of the analog-to-digital conversion units is connected to a random sequence generator; m is an integer greater than 1; the random sequence generation module is also connected to the digital calibration module; the random sequence generator is used to generate a random number sequence, and send the random number sequence to the first m stages of the analog-to-digital conversion units and the digital calibration module; The pipeline conversion module receives an input signal and is connected to the digital calibration module; the pipeline conversion module is used to perform multi-stage analog-to-digital conversion on the input signal based on the random number sequence, and output a plurality of digital codes to the digital calibration module; The digital calibration module is used to calibrate the digital codes output by the first m-stage analog-to-digital conversion units according to the random number sequence and the calibration parameters based on the order in which the multiple digital codes are received, calibrate the digital codes output by the remaining analog-to-digital conversion units after the m-th stage analog-to-digital conversion unit according to the calibration parameters, and obtain the target digital value according to the calibration result; The digital calibration module is specifically used to subtract the random number sequence corresponding to each analog-to-digital conversion unit from each digital code corresponding to the first m analog-to-digital conversion units to obtain m first digital values; and multiply the first digital values ​​corresponding to the analog-to-digital conversion units from the second to the mth level by the corresponding calibration parameters to obtain m-1 second digital values; add the digital codes corresponding to the remaining analog-to-digital conversion units after the mth level analog-to-digital conversion unit to obtain a first sum value, and multiply the first sum value by the corresponding calibration parameters to obtain a third digital value; and add the first digital value corresponding to the first-level analog-to-digital conversion unit, m-1 second digital values, and the third digital value to obtain the target digital value.

2. The pipeline analog-to-digital conversion circuit according to claim 1, characterized in that: The calibration parameter corresponding to the second-level analog-to-digital conversion unit is the first calibration parameter, and the calibration parameter corresponding to the k-th-level analog-to-digital conversion unit is the product of the calibration parameters corresponding to all analog-to-digital conversion units from the second level to the k-th level; wherein k is an integer greater than or equal to 3 and less than or equal to m; The calibration parameters corresponding to the remaining analog-to-digital conversion units after the m-th stage analog-to-digital conversion unit are the products of all the calibration parameters from the first calibration parameter to the m-th calibration parameter.

3. The pipeline analog-to-digital conversion circuit according to claim 1, characterized in that: The digital calibration module includes m subtractors and a first adder; The first input end of the subtractor is connected to the random sequence generator, the second input end of the subtractor is connected to the corresponding analog-to-digital conversion unit, and the subtractor is used to subtract the random number sequence corresponding to each analog-to-digital conversion unit from each digital code corresponding to the first m stages of analog-to-digital conversion units to obtain m first digital values; The input end of the first adder is connected to the remaining analog-to-digital conversion units after the mth stage analog-to-digital conversion unit, and the first adder is used to add the digital codes output by the remaining analog-to-digital conversion units after the mth stage analog-to-digital conversion unit to obtain a first sum value.

4. The pipeline analog-to-digital conversion circuit according to claim 3, characterized in that: The digital calibration module also includes m multipliers; The input end of the i-th multiplier is connected to the output end of the subtractor corresponding to the i+1-th analog-to-digital conversion unit; wherein i is an integer greater than or equal to 1 and less than or equal to m-1; the first m-1 multipliers are used to multiply the first digital values ​​corresponding to the second to m-th analog-to-digital conversion units by the corresponding calibration parameters to obtain m-1 second digital values; The input end of the m-th multiplier is connected to the output end of the first adder, and the m-th multiplier is used to multiply the first added value by the corresponding calibration parameter to obtain a third digital value.

5. The pipeline analog-to-digital conversion circuit according to claim 4, characterized in that: The digital calibration module also includes m second adders; A first input terminal of the first second adder is connected to the output terminal of the first multiplier, and a second input terminal of the first second adder is connected to the output terminal of the first subtractor; The first input terminal of the jth second adder is connected to the output terminal of the jth multiplier, and the second input terminal of the jth second adder is connected to the output terminal of the j-1th second adder; wherein j is an integer greater than or equal to 2 and less than or equal to m.

6. The pipeline analog-to-digital conversion circuit according to claim 5, characterized in that: The digital calibration module also includes m+1 registers; The first register is connected between the output terminal of the first subtractor and the second input terminal of the first second adder; The j-th register is connected between the output terminal of the j-1-th second adder and the second input terminal of the j-th second adder; The input end of the m+1th register is connected to the output end of the mth second adder, and the output end of the m+1th register is the output end of the digital calibration module.

7. The pipeline analog-to-digital conversion circuit according to claim 1, characterized in that: The pipeline analog-to-digital conversion circuit also includes a calibration parameter calculation module; The calibration parameter calculation module is connected to the digital calibration module, and is used to calculate the calibration parameters corresponding to the second-level analog-to-digital conversion unit to the m-th-level analog-to-digital conversion unit, and calculate the calibration parameters corresponding to the remaining analog-to-digital conversion units after the m-th-level analog-to-digital conversion unit.

8. A pipeline analog-to-digital conversion method, characterized in that: The pipeline analog-to-digital conversion method is implemented by the pipeline analog-to-digital conversion circuit according to any one of claims 1 to 7; The pipeline analog-to-digital conversion method comprises: The random sequence generator generates a random number sequence and sends the random number sequence to the first m-stage analog-to-digital conversion unit and the digital calibration module; The pipeline conversion module performs multi-stage analog-to-digital conversion on the input signal based on the random number sequence, and outputs a plurality of digital codes to the digital calibration module; The digital calibration module calibrates the digital codes output by the first m-stage analog-to-digital conversion units based on the random number sequence and the calibration parameters, and obtains a target digital value according to the calibration result.

9. The method according to claim 8, characterized in that The digital calibration module calibrates the digital code output by the first m-stage analog-to-digital conversion unit based on the random number sequence and the calibration parameter, and obtains the target digital value according to the calibration result, including: The digital calibration module subtracts the random number sequence corresponding to each analog-to-digital conversion unit from each digital code corresponding to the first m analog-to-digital conversion units to obtain m first digital values; The digital calibration module multiplies the first digital values ​​corresponding to the 2nd to mth analog-to-digital conversion units by corresponding calibration parameters to obtain m-1 second digital values; The digital calibration module adds up the digital codes corresponding to the remaining analog-to-digital conversion units after the m-th analog-to-digital conversion unit to obtain a first sum value, and multiplies the first sum value by a corresponding calibration parameter to obtain a third digital value; The digital calibration module adds the first digital value corresponding to the first-stage analog-to-digital conversion unit, m-1 second digital values, and the third digital value to obtain the target digital value.

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