An incremental Σ-Δ modulator

Abstract

The invention discloses an improved bilinear integrator and an incremental Σ-Δ modulator using the same. The improved bilinear integrator further comprises, on the basis of a fully floating bilinear integrator, a sampling capacitor Cs3 and a sampling capacitor Cs4; wherein, two ends of Cs3 are respectively connected to a positive input end of the integrator and an inverting input end of an amplifier, and two ends of Cs4 are respectively connected to a negative input end of the integrator and a non-inverting input end of the amplifier; a fully differential double-sampling incremental Σ-Δ modulator comprises: a first-stage switched capacitor integration circuit, a second-stage switched capacitor integration circuit, a feedforward branch, a timing generation circuit, a quantizer and a digital-to-analog converter.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and particularly to an incremental Σ-Δ modulator. Background Art

[0002] The incremental Σ-Δ modulator is one of many Σ-Δ modulators. The difference in its circuit structure from a general Σ-Δ modulator lies in that: the former is equipped with reset switches in each stage of integrator and quantizer for periodic reset operations, while the latter does not. The incremental Σ-Δ modulator mainly consists of the following parts: a multi-stage differential amplifier integration circuit with a reset switch, which is used to amplify and integrate the differential signal between the input analog signal and the feedback analog signal; a multi-bit quantizer with a reset switch, which is used to digitally quantize the output of the previous-stage integration circuit; a digital-to-analog converter, which is used to generate a feedback analog signal according to the digital code output by the multi-bit quantizer. The digital filter mainly consists of the following parts: a decimation filter and an interpolation filter, both of which are used to perform decimation and interpolation operations on the digital signal output by the Σ-Δ modulator and output the final analog / digital conversion value. The performance of the Σ-Δ modulator is an important factor affecting the accuracy and resolution of the analog-to-digital converter. The traditional dual-sampling incremental Σ-Δ modulator consists of parts such as multi-stage cascaded dual-sampling integrators and quantizers. This traditional dual-sampling integrator circuit has a problem of mismatch. This mismatch will cause a signal with a frequency of to fold back into the baseband. In this process, the shaped quantization noise is also folded back into the signal band, thereby affecting the signal-to-noise ratio of the modulator.

[0003] To solve this problem, a fully floating bilinear integrator circuit is proposed, which has two fully floating cross-coupled dual-sampling input branches with matching capacitors . The differential-mode signal output eliminates the error component caused by capacitor mismatch and solves the problem of noise folding. However, by deriving its transfer function expression, it can be obtained that . Therefore, a modulator using the existing fully floating bilinear integrator circuit will introduce additional poles, seriously affecting the stability of the system, increasing the complexity of circuit design and system architecture, and resulting in a loss of the signal-to-noise ratio of the modulator. Summary of the Invention

[0004] In view of this, the present invention provides an incremental Σ-Δ modulator to at least solve the problem that the modulator using the existing fully floating bilinear integrator introduces additional poles, affecting the system stability.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] An improved bilinear integrator, based on a fully floating bilinear integrator, the fully floating bilinear integrator includes a sampling capacitor Cs1, a sampling capacitor Cs2 and an amplifier. A switch k1 is arranged between the positive input terminal of the integrator and Cs1, a switch k2 is arranged between the negative input terminal of the integrator and Cs2, a switch k3 is arranged between the switch k1 and the switch k2, a switch k4 is arranged between the positive input terminal of the integrator and the output terminal of the switch k2. The other end of Cs1 is connected to the inverting input terminal of the amplifier through a switch k5, the other end of Cs2 is connected to the non-inverting input terminal of the amplifier through a switch k6, a switch k7 is arranged between Cs1 and the non-inverting input terminal, a switch k8 is arranged between Cs2 and the inverting input terminal. An integrating capacitor Cu1 is connected between the inverting input terminal and the non-inverting output terminal of the amplifier, and an integrating capacitor Cu2 is connected between the non-inverting input terminal and the inverting output terminal of the amplifier. It further includes: a sampling capacitor Cs3 and a sampling capacitor Cs4;

[0007] Wherein, two ends of Cs3 are respectively connected to the positive input terminal of the integrator and the inverting input terminal of the amplifier, and two ends of Cs4 are respectively connected to the negative input terminal of the integrator and the non-inverting input terminal of the amplifier.

[0008] An incremental Σ-Δ modulator, including: a first-stage switched-capacitor integration circuit, a second-stage switched-capacitor integration circuit, a feedforward branch, a passive summing circuit, a quantizer and a digital-to-analog converter;

[0009] The first-stage switched-capacitor integration circuit is respectively connected to the second-stage switched-capacitor integration circuit and the analog-to-digital converter. The first-stage switched-capacitor integration circuit adopts an improved bilinear integrator structure, and is used to control the actions of corresponding switches according to a clock signal, and correspondingly control the sampling capacitors to sample the input analog signal and the feedback signal output by the digital-to-analog converter and perform a summation operation to obtain a summation analog signal, and integrate the summation analog signal;

[0010] The second-stage switched-capacitor integration circuit is also connected to the quantizer. The second-stage switched-capacitor integration circuit adopts a floating switched-capacitor integration structure, and is used to sample and integrate the analog signal output by the first-stage switched-capacitor integration circuit, and input the output signal to the passive summing circuit;

[0011] The feedforward branch is used to input the analog signal output by the first-stage switched-capacitor integration circuit to the passive summing circuit to compensate the analog signal output by the second-stage switched-capacitor integration circuit;

[0012] The passive summing circuit is used to perform a summation operation on the analog signal output by the feedforward branch and the analog signal output by the second-stage switched-capacitor integration circuit and then input the result to the quantizer;

[0013] The quantizer is used to compare the two-way analog signals at the positive and negative output terminals of the second-stage switched-capacitor integration circuit and convert the comparison result into high and low levels, and finally obtain a digital signal;

[0014] The digital-to-analog converter is respectively connected to the quantizer and the first-stage switched-capacitor integrating circuit, and is used to perform digital-to-analog conversion on the digital signal output by the quantizer to output a feedback analog signal, and obtain a clock signal. Finally, according to the clock signal, the corresponding switch action is controlled to input the feedback analog signal into the first-stage switched-capacitor integrating circuit.

[0015] Preferably, the specific content of obtaining the transfer function of the first-stage switched-capacitor integrating circuit in the Z domain includes:

[0016] Assume that there is a mismatch between capacitors Cs1 and Cs2 Cs, and let Cs3 + Cs4 = Cs1 + Cs2. The charge input amounts of the four branches where Cs1 - Cs4 is located are respectively:

[0017] ;

[0018] ;

[0019] ;

[0020] ;

[0021] Then the charge input amount under the differential structure:

[0022] ;

[0023] From the above formula, it can be obtained that the transfer function of the first-stage switched-capacitor integrating circuit is , and the transfer function of the second-stage switched-capacitor integrating circuit is , where , that is, the transfer function coefficient.

[0024] Preferably, the transfer function of the overall loop is:

[0025] ;

[0026] Since , then:

[0027] .

[0028] Preferably, the digital-to-analog converter includes four switched-capacitor branches, and feedback capacitors C f1 , feedback capacitor C f2 , feedback capacitor C f3 and feedback capacitor C f4 are respectively arranged on the four switched-capacitor branches;

[0029] The positive input terminal of the digital-to-analog converter is connected to Cf1 A switch K9 is set between them, and the inverting input terminal of the digital-to-analog converter and C f2 A switch K10 is set between them, and a switch K11 is set between the switch K9 and the switch K10. and C f2 A switch K12 is set between them, and the other end of C f1 is connected to the inverting input terminal of the amplifier in the first-stage switched-capacitor integrating circuit as the non-inverting output terminal Vop of the digital-to-analog converter through a switch K13, and the other end of C f2 is connected to the inverting input terminal of the amplifier in the first-stage switched-capacitor integrating circuit as the inverting output terminal Von of the digital-to-analog converter through a switch K14, and C f1 A switch K15 is set between Von, and C f2 A switch K16 is set between Vop;

[0030] and the capacitor C f3 A switch K17 is set between them, and the capacitor C f4 A switch K18 is set between them, and C f3 A switch K19 is set between it and the switch K13, and C f4 A switch K20 is set between it and the switch K14, and a switch K21 is set between the switch K17 and the switch K11. and the capacitor C f4 A switch K22 is set between them, and C f3 A switch K23 is set between it and Von, and C f4 A switch K24 is set between it and Vop;

[0031] Reference level is respectively connected to the capacitors C f1 -C f4 through the switches K25 - K28.

[0032] Preferably, the timing generation circuit generates two groups of clock signals with opposite phases and non-overlapping pairwise and , and the clock signals are respectively subjected to NAND operations with the digital signals output by the quantizer to generate two groups of timing control signals with opposite phases and non-overlapping pairwise and , where the timing control signals and are used to control the actions of the corresponding switches on the right side of the feedback capacitors C f1 -C f4 in the digital-to-analog converter, and the corresponding switches are closed when the timing control signals are at high level and opened when the timing control signals are at low level.

[0033] Preferably, the quantizer adopts a dynamic comparator structure with an RS latch stage. The dynamic comparator is used to compare the differential signal output by the adder at each falling edge of the timing control signal, and finally outputs a digital signal. 。

[0034] As can be seen from the above technical solutions, compared with the prior art, the present invention discloses an incremental Σ-Δ modulator, which has the following beneficial effects:

[0035] In the modulator disclosed in the present invention, the first-stage switched-capacitor integration circuit adopts an improved fully floating bilinear integrator circuit, and two matching capacitor branches are added to the previous structure. On the one hand, the signal-to-noise ratio is effectively improved while the power consumption of the modulator remains unchanged. On the other hand, the transfer function of the improved fully floating bilinear integrator circuit becomes , in advanced processes, , achieving the maximum weakening effect on the introduced additional poles. And the improved bilinear integrator has a floating characteristic, so the common-mode level at the input terminal of the operational amplifier is in an undetermined state, and the access of the digital-to-analog converter stabilizes the common-mode level at this point, thereby enhancing the system stability and reducing the circuit design complexity;

[0036] The second-stage switched-capacitor integration circuit samples and integrates the analog differential signal output by the previous stage, and performs a summation operation on the analog signals output by the two-stage integration circuits to compensate for the output amplitude of the second-stage switched-capacitor integrator, further reducing the overall loop noise; the four feedback capacitor branches in the digital-to-analog converter are alternately connected to the input terminal of the operational amplifier in cooperation with the timing control signal, eliminating the capacitor mismatch noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0038] Figure 1 is a circuit diagram of an improved bilinear integrator provided by the present invention;

[0039] Figure 2 is a circuit diagram of the existing fully floating bilinear integrator provided by the present invention;

[0040] Figure 3 is a system-level block diagram of an incremental Σ-Δ modulator provided by the present invention;

[0041] Figure 4The working principle diagram of an incremental Σ-Δ modulator provided by the present invention;

[0042] Figure 5 The circuit diagram of the digital-to-analog converter in an incremental Σ-Δ modulator provided by the present invention;

[0043] Figure 6 The circuit diagram of the connection between the first-stage switched-capacitor integrator and the analog-to-digital converter in an incremental Σ-Δ modulator provided by the present invention;

[0044] Figure 7 The timing waveform diagram of the timing control signal provided by the embodiment of the present invention. Detailed implementation manners

[0045] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] The present invention provides an improved bilinear integrator, as Figure 1 shown, based on a fully floating bilinear integrator, as Figure 2 shown. The fully floating bilinear integrator includes a sampling capacitor Cs1, a sampling capacitor Cs2, and an amplifier. A switch k1 is provided between the positive input terminal of the integrator and Cs1, a switch k2 is provided between the negative input terminal of the integrator and Cs2, a switch k3 is provided between the switch k1 and the switch k2, a switch k4 is provided between the positive input terminal of the integrator and the output terminal of the switch k2. The other end of Cs1 is connected to the inverting input terminal of the amplifier through a switch k5, the other end of Cs2 is connected to the non-inverting input terminal of the amplifier through a switch k6, a switch k7 is provided between Cs1 and the non-inverting input terminal, a switch k8 is provided between Cs2 and the inverting input terminal. An integrating capacitor Cu1 is connected between the inverting input terminal and the non-inverting output terminal of the amplifier, and an integrating capacitor Cu2 is connected between the non-inverting input terminal and the inverting output terminal of the amplifier. It further includes: a sampling capacitor Cs3 and a sampling capacitor Cs4;

[0047] Wherein, both ends of Cs3 are respectively connected to the positive input terminal of the integrator and the inverting input terminal of the amplifier, and both ends of Cs4 are respectively connected to the negative input terminal of the integrator and the non-inverting input terminal of the amplifier.

[0048] An incremental Σ-Δ modulator, as Figure 3 and 4 shown, includes: a first-stage switched-capacitor integrator, a second-stage switched-capacitor integrator, a feedforward branch, a passive summing circuit, a quantizer, and a digital-to-analog converter;

[0049] The first - stage switched - capacitor integration circuit is connected to the second - stage switched - capacitor integration circuit and the analog - to - digital converter respectively. The first - stage switched - capacitor integration circuit adopts an improved bilinear integrator structure, which is used to control the actions of corresponding switches according to the clock signal, and correspondingly control the sampling capacitors to sample the input analog signal and the feedback signal output by the digital - to - analog converter, and perform a summation operation to obtain a summation analog signal, and integrate the summation analog signal.

[0050] The second - stage switched - capacitor integration circuit is also connected to the quantizer. The second - stage switched - capacitor integration circuit adopts a floating - type switched - capacitor integration structure, and the specific structure is as Figure 4 shown, which is used to sample and integrate the analog signal output by the first - stage switched - capacitor integration circuit, and input the output signal to the passive summing circuit.

[0051] The feed - forward branch is used to input the analog signal output by the first - stage switched - capacitor integration circuit to the passive summing circuit to compensate for the analog signal output by the second - stage switched - capacitor integration circuit.

[0052] The passive summing circuit is used to perform a summation operation on the analog signal output by the feed - forward branch and the analog signal output by the second - stage switched - capacitor integration circuit, and then input the result to the quantizer.

[0053] The quantizer is used to compare the two - path analog signals at the positive and negative output terminals of the second - stage switched - capacitor integration circuit and convert the comparison result into high and low levels, and finally obtain a digital signal.

[0054] The digital - to - analog converter is connected to the quantizer and the first - stage switched - capacitor integration circuit respectively. It is used to perform digital - to - analog conversion on the digital signal output by the quantizer to output a feedback analog signal, and obtain a clock signal. Finally, it controls the actions of corresponding switches according to the clock signal and inputs the feedback analog signal into the first - stage switched - capacitor integration circuit.

[0055] To further implement the above - mentioned technical solution, the specific content of obtaining the transfer function of the first - stage switched - capacitor integration circuit in the Z - domain includes:

[0056] Assume that there are mismatches in capacitors Cs1 and Cs2 Cs, and let Cs3 + Cs4 = Cs1 + Cs2. The charge input amounts of the four branches where Cs1 - Cs4 is located are respectively:

[0057] ;

[0058] ;

[0059] ;

[0060] ;

[0061] Then the charge input under the differential structure:

[0062] ;

[0063] From the above formula, it can be obtained that the transfer function of the first-stage switched-capacitor integrator is , and the transfer function of the second-stage switched-capacitor integrator is , where , that is, the transfer function coefficient.

[0064] As Figure 3 shown, a proposed incremental Σ-Δ modulator is a second-order one-bit integrator cascaded feedforward structure.

[0065] To further implement the above technical solution, the transfer function of the overall loop is:

[0066] ;

[0067] Since , then:

[0068] .

[0069] It should be noted that:

[0070] The extra poles are weakened, enhancing the stability of the system. The integrator cascaded feedforward structure adopted by the modulator enables the gain of the first-stage integrator to be set relatively large to effectively suppress the noise and nonlinearity generated by the subsequent integrator. And each stage of the integrator does not need to process the feedback signal carrying high-frequency noise, reducing the bandwidth design requirements of the subsequent operational amplifier.

[0071] To further implement the above technical solution, as Figure 5 shown, the digital-to-analog converter includes four switched-capacitor branches, and feedback capacitors C f1 , feedback capacitor C f2 , feedback capacitor C f3 and feedback capacitor C f4 are respectively arranged on the four switched-capacitor branches;

[0072] A switch k9 is arranged between the non-inverting input terminal of the digital-to-analog converter and C f1 , a switch k10 is arranged between the inverting input terminal of the digital-to-analog converter and C f2 , a switch k11 is arranged between switch k9 and switch k10, A switch k12 is arranged between f2 and C f1The other end of which is connected to the inverting input terminal of the amplifier in the first-stage switched-capacitor integrating circuit as the positive-phase output terminal Vop of the digital-to-analog converter through the switch k13, C f2 The other end of which is connected to the inverting input terminal of the amplifier in the first-stage switched-capacitor integrating circuit as the inverting output terminal Von of the digital-to-analog converter through the switch k14, C f1 A switch k15 is provided between and Von, C f2 A switch k16 is provided between and Vop;

[0073] A switch k17 is provided between and the capacitor C f3 ; A switch k18 is provided between and the capacitor C f4 ; C f3 A switch k19 is provided between and the switch k13, C f4 A switch k20 is provided between and the switch k14, and a switch k21 is provided between the switch k17 and the switch k11, A switch k22 is provided between and the capacitor C f4 ; C f3 A switch k23 is provided between and Von, C f4 A switch k24 is provided between and Vop;

[0074] Reference level Is respectively connected to the capacitor C through the switches k25 - k28 f1 - capacitor C f4 .

[0075] It should be noted that:

[0076] The connection relationship between the digital-to-analog converter and the first switched-capacitor integrating circuit is as Figure 6 shown.

[0077] In order to further implement the above technical solution, the timing generation circuit generates two groups of clock signals with opposite phases and non-overlapping pairwise and , and the clock signals are respectively subjected to a NAND operation with the digital signals output by the quantizer to generate two groups of timing control signals with opposite phases and non-overlapping pairwise and , where the timing control signals and are used to control the actions of the corresponding switches on the right side of the feedback capacitors C f1 -C f4 in the digital-to-analog converter. The corresponding switches are closed when the timing control signal is at a high level and opened when the timing control signal is at a low level. The switch group accesses the reset signal for resetting the integrating capacitor .

[0078] It should be noted that:

[0079] When the timing control signal and are in the high - level stage and and are in the low - level stage, the sampling capacitors and in the first - stage switched - capacitor integrator are respectively connected to the input analog signals and , and the sampling operation is completed through the action of the switch group. The feedback capacitors of the two feedback branches in the digital - to - analog converter are respectively connected to the feedback analog signals and , and the sampling operation is completed through the action of the switch group. The switch groups of the other two feedback branches are actuated by the timing signals and controlled by the digital code stream output by the quantizer, and the feedback capacitors are connected to the first - stage switched - capacitor integration circuit. Subsequently, the two analog signals complete the addition operation via the adder. Finally, the integration capacitors and in the first - stage switched - capacitor integration circuit perform the integration operation on this signal, and the operational amplifier in the first - stage switched - capacitor integration circuit amplifies the differential signal and outputs it to the second - stage switched - capacitor integration circuit.

[0080] Before starting an analog - to - digital conversion, the reset switch is turned off to clear the residual value retained during the previous analog - to - digital conversion. Subsequently, the reset switch is disconnected, and the modulator starts the analog - to - digital conversion.

[0081] To further implement the above - mentioned technical solution, the quantizer adopts a dynamic comparator structure with an RS - latch stage. The dynamic comparator is used to compare the differential signal output by the adder at each falling edge of the timing control signal, and finally outputs the digital signal .

[0082] It should be noted that:

[0083] In this embodiment, the number of bits of the quantizer is one, and a dynamic comparator with an RS - latch stage is used to implement the quantization operation. Without increasing the circuit design complexity, the error caused by capacitor mismatch is minimized to the greatest extent.

[0084] The working principle of the circuit of the present invention will be described below in conjunction with specific timing control signals:

[0085] The timing waveform diagram of the timing control signal in this embodiment is as shown in Figure 7 . At time T1, the clock and is at a high level. After a very short time interval, at time T2, the clock and become low level. Switches k1, k2 and k5, k6 in the first-stage switched-capacitor integrating circuit close, and k3, k4 and k7, k8 open. Sampling capacitors and respectively sample the input analog signals and . The quantizer outputs the digital signals and of the previous cycle. This digital signal and the clock perform a NAND operation to generate a timing control signal to control the corresponding switches on the right side of the feedback capacitor C f1 -C f4 in the digital-to-analog converter. At time T2, the digital signal is at a high level, is at a low level. Therefore, at this moment, the clock is at a high level, is at a low level. In the digital-to-analog converter circuit, the switches connected to the left ends of and , as well as switches k25 and k28, all close, and the rest of the switches open. Due to the actions of the switches connected to the left ends of and , the left ends of the feedback capacitors and are respectively connected to voltages and , and the right ends are both connected to the reference level to complete the sampling of the feedback voltage; due to the actions of switches k25 and k28, the feedback capacitors and are respectively connected to the positive and negative input terminals of the operational amplifier, and the charges accumulated in the previous cycle are transferred to the integrating capacitor of the first-stage switched-capacitor integrating circuit. The adder adds the voltages input to the positive and negative input terminals of the operational amplifier in the first-stage switched-capacitor integrating circuit at this moment. The integrating capacitors and of the first-stage switched-capacitor integrating circuit integrate the added signal and accumulate charges.

[0086] After a very short time interval from T3 to T4, the clock becomes low level, and the clock becomes high level. The operation of the modulator enters the second stage of the timing cycle. Since the digital signal output by the quantizer circuit remains unchanged, the clock becomes high level, goes low. In the digital-to-analog converter circuit in the digital-to-analog converter circuit and the switches connected to the left ends of switch k26 and k27 are closed, and the remaining switches are open. Since and due to the actions of the switches connected to the left ends, the feedback capacitors and are respectively connected to voltages and at their left ends, and to the reference level at their right ends, completing the sampling of the feedback voltage; due to the actions of switches k26 and k27, the feedback capacitors and are respectively connected to the positive and negative input terminals of the operational amplifier, transferring the charge accumulated in the previous cycle to the integration capacitor of the first-stage switched-capacitor integration circuit. In the first-stage switched-capacitor integration circuit, k3, k4 and k7, k8 are closed, and the sampling capacitors and complete the switching operation in the second stage, cooperating with the circuits of the other modules to form an orderly-switching fully differential double-sampling input structure, which on the one hand effectively eliminates the noise folding effect caused by capacitor mismatch, and on the other hand weakens the unstable effect generated by the introduced additional poles, improving the signal-to-noise ratio of the modulator.

[0087] The above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An incremental sigma-delta modulator, characterized in that: include: A first-stage switched capacitor integration circuit, a second-stage switched capacitor integration circuit, a feedforward branch, a passive summing circuit, a quantizer, and a digital-to-analog converter; The first-stage switched capacitor integration circuit is respectively connected to the second-stage switched capacitor integration circuit and the analog-to-digital converter, wherein the first-stage switched capacitor integration circuit adopts an improved bilinear integrator structure, which is used to control the action of the corresponding switch according to the clock signal, and the corresponding control sampling capacitor samples the input analog signal and the feedback signal output by the digital-to-analog converter and performs sum operation to obtain a summed analog signal, and integrates the summed analog signal; The second-stage switched capacitor integration circuit is also connected to the quantizer, wherein the second-stage switched capacitor integration circuit adopts a floating switched capacitor integrator structure, and is used to sample and integrate the analog signal output by the first-stage switched capacitor integration circuit, and input the output signal to the passive summing circuit; The feedforward branch is used to input the analog signal output by the first-stage switched capacitor integration circuit into the passive summing circuit to compensate the analog signal output by the second-stage switched capacitor integration circuit; The passive summing circuit is used for summing the analog signal outputted by the feedforward branch and the analog signal outputted by the second-stage switched capacitor integration circuit and then inputting the summed signals into the quantizer; The quantizer is used to compare the two analog signals of the positive and negative output terminals of the second-stage switched capacitor integration circuit and convert the comparison result into high and low levels to finally obtain a digital signal; The digital-to-analog converter is respectively connected to the quantizer and the first-stage switched capacitor integration circuit, and is used to perform digital-to-analog conversion on the digital signal output by the quantizer to output a feedback analog signal, and obtain a clock signal, and finally control the corresponding switch action according to the clock signal to input the feedback analog signal into the first-stage switched capacitor integration circuit; The improved bilinear integrator structure includes a fully floating bilinear integrator, a sampling capacitor Cs3 and a sampling capacitor Cs4, wherein the fully floating bilinear integrator includes a sampling capacitor Cs1, a sampling capacitor Cs2 and an amplifier; The two ends of Cs3 are respectively connected to the positive input end of the integrator and the inverting input end of the amplifier, and the two ends of Cs4 are respectively connected to the negative input end of the integrator and the non-inverting input end of the amplifier; The digital-to-analog converter includes four switch capacitor branches, and feedback capacitors C are respectively set on the four switch capacitor branches. f1 , feedback capacitor C f2 , feedback capacitor C f3 and feedback capacitor C f4 ; The positive input terminal of the digital-to-analog converter V refn With C f1 Set switch k9 between the inverting input terminal V refp With C f2 Set switch k10 between switches k9 and k10, set switch k11 between switches k9 and k10, V refn With C f2 Set switch k12 between C f1 The other end of the digital-to-analog converter is connected to the inverting input end of the amplifier in the first-stage switched capacitor integration circuit through switch k13 as the positive-phase output end Vop of the digital-to-analog converter. f2 The other end of the digital-to-analog converter is connected to the inverting input end of the amplifier in the first-stage switched capacitor integration circuit through switch k14 as the inverting output end Von of the digital-to-analog converter. f1 Set switch k15 between C and Von f2 Set switch k16 between Vop; V refn With capacitor C f3 Set switch k17 between V refp With capacitor C f4 Set switch k18 between C f3 Set switch k19 between switch k13, C f4 Set switch k20 between switch k17 and switch k14, set switch k21 between switch k17 and switch k11, V refn With capacitor C f4 Set switch k22 between C f3 Set switch k23 between C and Von f4 Set switch k24 between Vop; The reference level Vcm is connected to the capacitor C through switches k25-k28 respectively. f1 -Capacitor C f4 .

2. The incremental Σ-Δ modulator according to claim 1, characterized in that: A switch k1 is set between the positive input terminal of the integrator and Cs1, a switch k2 is set between the negative input terminal of the integrator and Cs2, a switch k3 is set between switch k1 and switch k2, a switch k4 is set between the positive input terminal of the integrator and the output terminal of switch k2, the other end of Cs1 is connected to the inverting input terminal of the amplifier through switch k5, the other end of Cs2 is connected to the non-inverting input terminal of the amplifier through switch k6, a switch k7 is set between Cs1 and the non-inverting input terminal, a switch k8 is set between Cs2 and the inverting input terminal, an integrating capacitor Cu1 is connected between the inverting input terminal and the non-inverting output terminal of the amplifier, and an integrating capacitor Cu2 is connected between the non-inverting input terminal and the inverting output terminal of the amplifier.

3. The incremental Σ-Δ modulator according to claim 1, characterized in that: The specific contents of obtaining the transfer function of the first-stage switched capacitor integrator circuit in the Z domain include: Assume that there is a mismatch of 1 / 2ΔCs between capacitors Cs1 and Cs2, and let Cs3+Cs4=Cs1+Cs2. The charge inputs of the four branches where Cs1-Cs4 are located are: Q1=U(Z)(1+z -1 )(Cs1-1 / 2ΔCs) <h2 style=";text-align:left;direction:ltr">Q2 = -U(Z)(1+z<h2 style=";text-align:left;direction:ltr"> -1 <h2 style=";text-align:left;direction:ltr"> (Cs2+1 / 2ΔCs) Q3=U(Z)(1-z -1 )Cs3 Q4=-U(Z)(1-z -1 )Cs4 Then the charge input under the differential structure is: dQ=(Q1+Q3)-(Q2+Q4) =U(Z)[(Cs1+Cs2+Cs3+Cs4)+(Cs1+Cs2-Cs3-CS4)Z -1 ] From the above formula, we can get: The transfer function of the first-stage switched capacitor integrator circuit is The transfer function of the second-stage switched capacitor integrator circuit is: in That is, the transfer function coefficient.

4. The incremental Σ-Δ modulator according to claim 3, characterized in that: The transfer function of the overall loop is: because but:

5. The incremental Σ-Δ modulator according to claim 1, characterized in that: The timing generation circuit generates two sets of clock signals s, sd, s1 and s1d with opposite phases and non-overlapping in pairs. The clock signals are then respectively AND-inverted with the digital signals output by the quantizer to generate two sets of timing control signals A, B, C and D with opposite phases and non-overlapping in two phases. The timing control signals A, B, C and D are used to control the feedback capacitor C in the digital-to-analog converter. f1 -C f4 The corresponding switches on the right side are closed when the timing control signal is at a high level and opened when the timing control signal is at a low level.

6. The incremental Σ-Δ modulator according to claim 1, characterized in that: The quantizer adopts a dynamic comparator structure with an RS latch stage. The dynamic comparator is used to compare the differential signal output by the adder when each falling edge of the timing control signal arrives, and finally outputs a digital signal Q.

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