Semiconductor structure and method of manufacturing the same

Abstract

Embodiments of the present disclosure relate to a semiconductor structure and a method for fabricating the same. The method includes providing a substrate; forming a vertical stack structure on the substrate; the vertical stack structure includes a transistor region and a bit line region and a capacitor region respectively located on opposite sides of the transistor region in a first direction and spaced apart from the transistor region; the vertical stack structure includes alternately stacked patterned sacrificial layers and patterned active layers; forming a first trench between the transistor region and the bit line region and the capacitor region, the first trench exposes a sidewall of the vertical stack structure of the transistor region perpendicular to the first direction; removing at least part of the patterned sacrificial layers of the transistor region along the first trench; forming a word line structure, the word line structure extends in a vertical direction and is in contact with the patterned active layers of the transistor region. The semiconductor structure and the method for fabricating the same provided by the present disclosure can obtain a good etching profile, thereby effectively improving the production yield and product reliability of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] As the semiconductor industry enters nanometer technology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional (3D) semiconductor device designs.

[0003] However, while traditional preparation methods improve the integration density of semiconductor structures, it is difficult to obtain a good etching profile during the process, resulting in a decrease in the production yield and product reliability of semiconductor structures. This poses a huge challenge to further miniaturization of semiconductor structure sizes. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the deficiencies in the prior art.

[0005] To achieve the above objectives, the present disclosure provides, in accordance with some embodiments, a method for fabricating a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming a vertical stack structure on the substrate; the vertical stack structure comprising a transistor region and a bit line region and a capacitor region located on opposite sides of the transistor region in a first direction and spaced apart from the transistor region; the vertical stack structure comprising alternatingly stacked patterned sacrificial layers and patterned active layers;

[0008] forming a first trench between the transistor region, the bit line region, and the capacitor region, wherein the first trench exposes a sidewall of the vertical stack structure of the transistor region that is perpendicular to the first direction;

[0009] removing at least a portion of the patterned sacrificial layer in the transistor region along the first trench;

[0010] A word line structure is formed, where the word line structure extends in a vertical direction and contacts the patterned active layer of the transistor region.

[0011] In some embodiments, the vertical stack structure further includes a first connection region located between the transistor region and the bit line region and a second connection region located between the transistor region and the capacitor region; and the preparation method further includes:

[0012] converting the patterned active layer in the first connection region into a bit line contact structure;

[0013] removing the patterned active layer in the bit line region and forming a bit line structure; the bit line structure is connected to the patterned active layer in the transistor region via the bit line contact structure;

[0014] converting the patterned active layer in the second connection region into a capacitor contact structure;

[0015] The patterned active layer in the capacitor region is removed, and a capacitor structure is formed; the capacitor structure is connected to the patterned active layer in the transistor region via the capacitor contact structure.

[0016] In some embodiments, the bit line region extends along the second direction, and before forming the first trench between the transistor region, the bit line region, and the capacitor region, the preparation method further includes:

[0017] forming a first isolation structure; the first isolation structure filling the gaps between the bit line region and the plurality of transistor regions, the gaps between the transistor region and the capacitor region, the gaps between adjacent transistor regions along the second direction, and the gaps between adjacent capacitor regions along the second direction;

[0018] Forming the first trench between the transistor region, the bit line region, and the capacitor region includes: removing a first isolation structure between the transistor region, the bit line region, and the capacitor region in the first direction.

[0019] In some embodiments, after removing at least a portion of the patterned sacrificial layer in the transistor region along the first trench, the preparation method further comprises:

[0020] forming an isolation sidewall, wherein the isolation sidewall at least covers the exposed surface of the patterned active layer;

[0021] A second isolation structure is formed, where the second isolation structure covers the surface of the isolation sidewall and fills the gaps between the transistor region, the bit line region, and the capacitor region.

[0022] In some embodiments, the transistor region includes a channel region and source and drain regions located on opposite sides of the channel region along the first direction; and forming the word line structure includes:

[0023] removing a portion of the first isolation structure between the transistor regions to expose a sidewall of the vertical stack structure of the channel region that is perpendicular to the second direction;

[0024] Removing the remaining patterned sacrificial layer in the transistor region to form a word line through hole, wherein the word line through hole exposes the patterned active layer in the channel region;

[0025] A word line dielectric layer is formed on the surface of the patterned active layer in the channel region exposed in the word line through hole, and a word line conductive layer is filled therein. The word line dielectric layer and the word line conductive layer constitute the word line structure.

[0026] In some embodiments, the transistor region includes a channel region and source and drain regions located on opposite sides of the channel region along the first direction; and forming the word line structure includes:

[0027] removing a portion of the vertical stack structure in the channel region to form a word line through-hole penetrating the vertical stack structure;

[0028] A word line dielectric layer is formed on the surface of the patterned active layer in the channel region exposed in the word line through hole, and a word line conductive layer is filled therein. The word line dielectric layer and the word line conductive layer constitute the word line structure.

[0029] In some embodiments, after removing at least a portion of the patterned sacrificial layer in the transistor region along the first trench, the preparation method further comprises:

[0030] Ion implantation is performed in the patterned active layer exposed in the transistor region to form a source and a drain.

[0031] In some embodiments, the vertical stack structure includes a plurality of transistor regions spaced apart along the second direction;

[0032] Converting the graphic active layer of the first connection area into a bit line contact structure includes: converting the graphic active layers of multiple first connection areas into bit line contact structures; and connecting the bit line structure to the graphic active layers in each transistor area via the multiple bit line contact structures.

[0033] On the other hand, the present disclosure further provides a semiconductor structure according to some embodiments, including:

[0034] substrate;

[0035] A vertically stacked device structure; the vertically stacked device structure includes a graphic device structure spaced apart from one another, the graphic device structure including a transistor structure and a bit line structure and a capacitor structure located on opposite sides of the transistor structure in a first direction, the bit line structure and the capacitor structure being spaced apart from the transistor structure.

[0036] In some embodiments, the semiconductor structure further includes a bit line contact structure located between the transistor structure and the bit line structure, and a capacitor contact structure located between the transistor structure and the capacitor structure;

[0037] Among them, one end of the bit line contact structure is connected to the first side wall of the transistor structure perpendicular to the second direction and the other end is connected to the bit line structure, one end of the capacitor contact structure is connected to the second side wall of the transistor structure perpendicular to the second direction and the other end is connected to the capacitor structure, and the first side wall and the second side wall are side walls on the same side of the transistor structure or side walls on opposite sides.

[0038] In some embodiments, the semiconductor structure further includes a first isolation structure; the first isolation structure fills the gaps between the transistor regions adjacent to each other along the second direction and the gaps between the capacitor regions adjacent to each other along the second direction.

[0039] In some embodiments, the transistor structure includes an active layer, and the semiconductor structure further includes an isolation sidewall and a second isolation structure; the isolation sidewall and the second isolation structure are located in the gap between the transistor structure, the bit line structure, and the capacitor structure; the isolation sidewall at least covers the sidewall of the active layer perpendicular to the first direction.

[0040] In some embodiments, the semiconductor structure further includes a word line structure; the word line structure extends along a vertical direction and penetrates the active layer, or the word line structure surrounds a sidewall of the active layer extending along the second direction.

[0041] In some embodiments, the bit line structure is arranged in a vertical direction and extends along the second direction, and the vertically stacked device structure includes a plurality of transistor structures arranged at intervals along the second direction and a plurality of capacitor structures arranged at intervals along the second direction; the bit line structure is respectively connected to each of the transistor structures via a plurality of the bit line contact structures.

[0042] In some embodiments, a projection of the bit line contact structure on the substrate is L-shaped, and a projection of the capacitor contact structure on the substrate is U-shaped.

[0043] The semiconductor structure and the method for preparing the same provided by the present disclosure have at least the following beneficial effects:

[0044] The semiconductor structure and preparation method provided by the present disclosure form a vertical stacking structure having a transistor region, a bit line region and a capacitor region on a substrate, and form a first trench between the transistor region and the bit line region and the capacitor region. The first trench exposes the sidewall of the vertical stacking structure of the transistor region perpendicular to a first direction. In this way, the exposed sidewall can be used as an etching surface to remove part of the patterned sacrificial layer of the transistor region, thereby obtaining a good etching profile, thereby effectively improving the production yield and product reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0047] Figure 2 A schematic flow chart of a method for preparing a semiconductor structure provided in some other embodiments of the present disclosure;

[0048] Figure 3 A schematic diagram of a process after removing at least a portion of a patterned sacrificial layer in a transistor region in a method for fabricating a semiconductor structure provided in some embodiments of the present disclosure;

[0049] Figure 4 A schematic flow chart of step S15 in the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0050] Figure 5 A schematic flow chart of step S15 in a method for preparing a semiconductor structure provided in other embodiments of the present disclosure;

[0051] Figure 6 A schematic diagram of the three-dimensional structure of the structure obtained in step S11 of the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0052] Figure 7 A schematic diagram of the three-dimensional structure of the structure obtained in step S12 of the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0053] Figure 8 A schematic diagram of the three-dimensional structure of a structure obtained after forming a first isolation structure in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0054] Figure 9 A schematic diagram of the three-dimensional structure of a structure obtained after forming a first trench in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0055] Figure 10 Figure (a) is a schematic diagram of the three-dimensional structure of the structure obtained in step S14 of the method for preparing a semiconductor structure provided by some embodiments of the present disclosure; Figure 10 Figure (b) is Figure 10 Schematic diagram of the three-dimensional structure of the structure shown in Figure (a) taken along AA'; Figure 10 Figure (c) in the figure is Figure 10 (a) is a schematic diagram of the three-dimensional structure of the structure shown in FIG. 1 taken along BB';

[0056] Figure 11 A schematic diagram of the three-dimensional structure of the structure obtained in step S41 of the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0057] Figure 12 A schematic diagram of the three-dimensional structure of the structure obtained in step S42 of the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0058] Figure 13 A schematic diagram of the three-dimensional structure of a structure obtained after forming a patterned photoresist layer in the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0059] Figure 14 A schematic diagram of the three-dimensional structure of the structure obtained in step S511 of the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0060] Figure 15 A schematic diagram of the three-dimensional structure of the structure obtained in step S512 of the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0061] Figure 16 A schematic diagram of the three-dimensional structure of the structure obtained in step S512 of the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0062] Figure 17 A schematic diagram of the three-dimensional structure of the structure obtained in step S24 of the method for preparing a semiconductor structure provided in some embodiments of the present disclosure; Figure 17 It is also a schematic diagram of the three-dimensional structure of a semiconductor structure provided by some embodiments of the present disclosure;

[0063] Figure 18 A schematic diagram of the three-dimensional structure of two patterned active layers in the vertical stacked structure obtained in step S24 of the method for preparing a semiconductor structure provided by some embodiments of the present disclosure; Figure 18 It is also a schematic diagram of the three-dimensional structure of two active layers in a vertically stacked device structure in a semiconductor structure provided by some embodiments of the present disclosure;

[0064] Figure 19 A schematic diagram of the three-dimensional structure of a patterned active layer in a vertical stacked structure obtained in step S24 of the method for preparing a semiconductor structure provided in some embodiments of the present disclosure; Figure 19 It is also a schematic diagram of the three-dimensional structure of an active layer of a vertically stacked device structure in a semiconductor structure provided by some embodiments of the present disclosure;

[0065] Figure 20Schematic diagram of the three-dimensional structure of two active layers in a vertically stacked device structure in a semiconductor structure provided in some other embodiments of the present disclosure.

[0066] Description of reference numerals:

[0067] 1. Substrate; 21. Transistor structure; 211. Active layer; 21A. Transistor region; 212. Patterned sacrificial layer; 22. Bit line structure; 22A. Bit line region; 23. Capacitor structure; 23A. Capacitor region; 24. First trench; 3. Bit line contact structure; 3A. First connection region; 4. Capacitor contact structure; 4A. Second connection region; 5. First isolation structure; 6. Isolation sidewall; 7. Second isolation structure; 8. Word line structure; 81. Word line dielectric layer; 82. Word line conductive layer; 9. Source; 10. Drain; PR, patterned photoresist layer; c, channel region; V, word line via. DETAILED DESCRIPTION

[0068] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0070] It should be understood that when an element or layer is referred to as being "on," "adjacent," or "connected to," it can be directly on, adjacent, or connected to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first isolation structure may be referred to as a second isolation structure, and similarly, a second isolation structure may be referred to as a first isolation structure; the first isolation structure and the second isolation structure are different isolation structures.

[0071] Spatially relative terms such as "the upper surface of...", "on...", "the lower surface of...", etc., may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "the upper surface of..." will be oriented to be "on the lower surface" of other elements or features. Therefore, the exemplary terms "the upper surface of...", "on..." may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0072] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0073] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances are to be expected. The embodiments of the present disclosure should not be limited to the specific shapes illustrated but are to include deviations in shapes that result, for example, from manufacturing techniques. Thus, the figures are schematic in nature and their shapes are not intended to represent actual shapes of devices and are not intended to limit the scope of the present disclosure.

[0074] As the semiconductor industry enters nanometer technology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional (3D) semiconductor device designs.

[0075] However, while traditional preparation methods improve the integration density of semiconductor structures, it is difficult to obtain a good etching profile during the process, resulting in a decrease in the production yield and product reliability of semiconductor structures. This poses a huge challenge to further miniaturization of semiconductor structure sizes.

[0076] In view of the above-mentioned deficiencies in the prior art, the present disclosure provides a semiconductor structure and a method for manufacturing the same according to some embodiments, the details of which will be described in subsequent embodiments.

[0077] In one aspect, the present disclosure provides a method for fabricating a semiconductor structure according to some embodiments.

[0078] See also Figure 1 In some embodiments, the method for preparing the semiconductor structure may include the following steps:

[0079] S11: providing a substrate.

[0080] S12: forming a vertical stacking structure on the substrate; the vertical stacking structure includes a transistor region and a bit line region and a capacitor region respectively located on opposite sides of the transistor region in a first direction and spaced apart from the transistor region; the vertical stacking structure includes alternately stacked graphic sacrificial layers and graphic active layers.

[0081] S13: forming a first trench between the transistor region, the bit line region, and the capacitor region, wherein the first trench exposes a sidewall of the vertical stacking structure of the transistor region that is perpendicular to the first direction.

[0082] S14: removing at least a portion of the patterned sacrificial layer in the transistor region along the first trench.

[0083] S15: forming a word line structure, where the word line structure extends in a vertical direction and contacts the patterned active layer of the transistor region.

[0084] The preparation method provided in the above embodiment forms a vertical stacking structure having a transistor region, a bit line region and a capacitor region on a substrate, and forms a first trench between the transistor region and the bit line region and the capacitor region. The first trench exposes the sidewall of the vertical stacking structure of the transistor region perpendicular to the first direction. In this way, the exposed sidewall can be used as an etching surface to remove part of the patterned sacrificial layer of the transistor region, thereby obtaining a good etching profile, thereby effectively improving the production yield and product reliability of the semiconductor structure.

[0085] See also Figure 2 In some embodiments, the vertical stack structure further includes a first connection region located between the transistor region and the bit line region and a second connection region located between the transistor region and the capacitor region. The method for preparing the semiconductor structure may further include the following steps:

[0086] S21: transforming the patterned active layer in the first connection region into a bit line contact structure.

[0087] S22: removing the patterned active layer in the bit line region and forming a bit line structure; the bit line structure is connected to the patterned active layer in the transistor region via a bit line contact structure.

[0088] S23: transforming the patterned active layer in the second connection region into a capacitor contact structure.

[0089] S24: removing the patterned active layer in the capacitor region and forming a capacitor structure; the capacitor structure is connected to the patterned active layer in the transistor region via a capacitor contact structure.

[0090] In some embodiments, the bit line region extends along the second direction, before forming the first trench between the transistor region, the bit line region, and the capacitor region. The method for fabricating the semiconductor structure may further include the following steps: forming a first isolation structure; the first isolation structure filling the gaps between the bit line region and the plurality of transistor regions, the gaps between the transistor region and the capacitor region, the gaps between adjacent transistor regions along the second direction, and the gaps between adjacent capacitor regions along the second direction.

[0091] In some embodiments, forming the first trench between the transistor region and the bit line region and the capacitor region includes: removing a first isolation structure between the transistor region and the bit line region and the capacitor region in the first direction.

[0092] See also Figure 3 In some embodiments, after removing at least a portion of the patterned sacrificial layer in the transistor region along the first trench, the method for preparing the semiconductor structure may further include the following steps:

[0093] S41: forming an isolation spacer; the isolation spacer at least covers the surface of the exposed patterned active layer.

[0094] S42: forming a second isolation structure, where the second isolation structure covers the surface of the isolation sidewall and fills the gaps between the transistor region, the bit line region, and the capacitor region.

[0095] See also Figure 4 In some embodiments, the transistor region includes a channel region and source / drain regions located on opposite sides of the channel region along the first direction. Step S15 of forming a word line structure may include the following steps:

[0096] S511: removing a portion of the first isolation structure between the transistor regions to expose the sidewalls of the vertical stacking structure of the channel region perpendicular to the second direction.

[0097] S512: removing the remaining patterned sacrificial layer in the transistor region to form a word line through hole, wherein the word line through hole exposes the patterned active layer in the channel region.

[0098] S513: forming a word line dielectric layer on the surface of the patterned active layer in the channel region exposed in the word line through hole, and filling the word line conductive layer. The word line dielectric layer and the word line conductive layer constitute a word line structure.

[0099] See also Figure 5 In some embodiments, the transistor region includes a channel region and source / drain regions located on opposite sides of the channel region along the first direction. Step S15 of forming a word line structure may include the following steps:

[0100] S521: removing a portion of the vertical stack structure in the channel region to form a word line through-hole penetrating the vertical stack structure.

[0101] S522: forming a word line dielectric layer on the surface of the patterned active layer in the channel region exposed in the word line through hole, and filling the word line conductive layer. The word line dielectric layer and the word line conductive layer constitute a word line structure.

[0102] It should be understood that although Figures 1 to 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figures 1 to 5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0103] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 6 to 20 Understand some embodiments of the present disclosure.

[0104] See also Figure 6 , in step S11 , a substrate 1 is provided.

[0105] The present disclosure does not specifically limit the material of the substrate 1. In some embodiments, the substrate 1 includes a silicon substrate.

[0106] See also Figure 7 In step S12 , a vertical stacking structure is formed on the substrate 1 .

[0107] like Figure 7 As shown, the vertical stack structure may include a transistor region 21A, and a bit line region 22A and a capacitor region 23A located on opposite sides of the transistor region 21A in a first direction (e.g., the X direction) and spaced apart from the transistor region 21A. The vertical stack structure may include alternatingly stacked patterned sacrificial layers 212 and patterned active layers 211.

[0108] The present disclosure does not specifically limit the materials of the patterned active layer 211 and the patterned sacrificial layer 212 in the vertical stack structure. In some embodiments, the material of the patterned active layer 211 includes silicon germanium (SiGe), and the material of the patterned sacrificial layer 212 includes silicon.

[0109] As an example, the bit line region 22A can extend along the second direction (for example, the Y direction), the transistor region 21A is multiple and is arranged in sequence along the second direction (for example, the Y direction), and the spacing between any two adjacent transistor regions 21A can be basically the same, and the capacitor region 23A is multiple and is arranged in sequence along the second direction (for example, the Y direction), and the spacing between any two adjacent capacitor regions 23A can be basically the same.

[0110] As an example, in a first direction (eg, X direction), transistor regions 21A correspond one to one with capacitor regions 23A, bit line regions 22A are located on the same side of the transistor regions 21A, and capacitor regions 23A are located on the other side of the transistor regions 21A.

[0111] In other examples, the semiconductor structure can also be a symmetrical structure with the central axis of the bit line region 22A as the symmetry axis, and a first storage area and a second storage area are respectively arranged on both sides of the bit line region 22A along the first direction, and multiple transistor areas 21A and multiple capacitor areas 23A are respectively arranged in the first storage area and the second storage area, and the first storage area and the second storage area can share the bit line region 22A.

[0112] See also Figure 8 In some embodiments, before step S13, the method for fabricating the semiconductor structure may further include the following step: forming a first isolation structure 5. The first isolation structure 5 fills the gaps between the bit line region 22A and the plurality of transistor regions 21A, the gaps between the transistor region 21A and the capacitor region 23A, the gaps between adjacent transistor regions 21A along the second direction, and the gaps between adjacent capacitor regions 23A along the second direction.

[0113] The present disclosure does not specifically limit the material of the first isolation structure 5. As an example, the first isolation structure 5 may include but is not limited to an oxide isolation structure; for example, the first isolation structure 5 may include silicon dioxide (SiO2).

[0114] It should be noted that the gap is a space defined by the vertical stacking structure of the transistor region 21A, the bit line region 22A and the capacitor region 23A, and the surface of the substrate 1 is exposed in the gap. The first isolation structure 5 can fill the gap and cover the exposed surface of the substrate 1.

[0115] In step S13, Figure 9 As shown, a first trench 24 is formed. The first trench 24 is located between the transistor region 21A and the bit line region 22A and between the transistor region 21A and the capacitor region 23A. The first trench 24 exposes the sidewalls of the vertical stack structure of the transistor region 21A perpendicular to the first direction.

[0116] As an example, step S13 of forming the first trench 24 between the transistor region 21A and the bit line region 22A and the capacitor region 23A can be specifically performed by removing the first isolation structure 5 between the transistor region 21A and the bit line region 22A and the capacitor region 23A in the first direction to form the first trench 24.

[0117] In step S14, Figure 10 Figure (a) in Figure 10 Figure (b) and Figure 10 As shown in FIG. 5( c ), at least a portion of the patterned sacrificial layer 212 in the transistor region 21A is removed along the first trench 24 .

[0118] In some embodiments, step S14 may be performed as follows: removing a portion of the patterned sacrificial layer 212 in the transistor region 21A along the first trench 24. It should be emphasized that the patterned sacrificial layer 212 is not completely etched here to avoid convection effect.

[0119] In some other embodiments, step S14 may be performed as follows: removing the entire patterned sacrificial layer 212 of the transistor region 21A along the first trench 24 and replacing it with an isolation material such as silicon dioxide, silicon nitride and / or silicon carbide.

[0120] In some embodiments, after step S14 , the method for preparing the semiconductor structure may further include the following steps S41 - S42 .

[0121] In step S41, an isolation spacer 6 is formed. Figure 11 As shown, the isolation spacer 6 at least covers the exposed patterned active layer 211. As an example, the isolation spacer 6 may also cover the exposed substrate 1.

[0122] In step S42, a second isolation structure 7 is formed. Figure 12 As shown, the second isolation structure 7 covers the surface of the isolation spacer 6 and fills the gaps between the transistor region 21A and the bit line region 22A and between the transistor region 21A and the capacitor region 23A.

[0123] The present disclosure does not specifically limit the material of the isolation spacer 6 formed in step S41. In some embodiments, the isolation spacer 6 may include but is not limited to silicon nitride (SiN) isolation spacers.

[0124] The present disclosure does not specifically limit the material of the second isolation structure 7 formed in step S42. As an example, the material of the second isolation structure 7 can be the same as or similar to the material of the first isolation structure 5. In some embodiments, the material of the second isolation structure 7 includes silicon dioxide.

[0125] As an example, the isolation spacer 6 and the second isolation structure 7 may be formed by a deposition process (eg, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or other suitable deposition processes).

[0126] In some embodiments, after forming the isolation sidewall 6 and the second isolation structure 7, a planarization process may be performed to remove the isolation sidewall 6 and the second isolation structure 7 at the top of the vertical stack structure and expose the patterned active layer 211 at the top layer.

[0127] In step S15, a word line structure 8 is formed. Figures 13 to 16 As shown, the word line structure 8 extends in a vertical direction and contacts the patterned active layer 211 of the transistor region 21A.

[0128] In some embodiments, step S15 of forming the word line structure 8 may be performed as follows: steps S511 - S513 .

[0129] In step S511, Figures 13 and 14 Part of the first isolation structure 5 between the transistor regions 21A is removed to expose the sidewalls of the vertical stack structure of the channel region c perpendicular to the second direction.

[0130] In step S512, Figure 15 As shown, the remaining patterned sacrificial layer 212 of the transistor region 21A is removed to form a word line through hole V, which exposes the patterned active layer 211 of the channel region c.

[0131] In step S513, if Figure 16 As shown, a word line dielectric layer 81 is formed on the surface of the patterned active layer 211 in the channel region c exposed in the word line through hole V, and a word line conductive layer 82 is filled therein. The word line dielectric layer 81 and the word line conductive layer 82 constitute a word line structure 8.

[0132] The present disclosure does not specifically limit the method of removing part of the first isolation structure 5 in step S511. As an example, the following steps can be used to remove part of the first isolation structure 5: Figure 13 As shown, a patterned photoresist layer PR is formed on the upper surface of the obtained structure. An opening is formed on the patterned photoresist layer PR to expose a portion of the transistor region 21A. The opening can expose a portion of the patterned active layer 211 of the transistor region 21A, or can only expose a portion of the first isolation structure 5 on both sides of the patterned active layer 211; Figure 14As shown, the first isolation structure 5 between the transistor regions 21A is etched using the patterned photoresist layer PR as a mask, thereby transferring the pattern of the patterned photoresist layer PR to the first isolation structure 5, forming a word line opening in the first isolation structure 5, and exposing the sidewall of the vertical stacking structure of the channel region c perpendicular to the second direction through the word line opening. The remaining patterned sacrificial layer 212 in the vertical stacking structure of the channel region c can be removed along the word line opening, or the isolation material replacing the patterned sacrificial layer 212 can be removed to obtain the word line through hole V and the patterned active layer 211 suspended in the channel region c.

[0133] The present disclosure does not specifically limit the material of the wordline dielectric layer 81 formed in step S513. In some embodiments, the wordline dielectric layer 81 comprises a silicon dioxide dielectric layer. The present disclosure also does not specifically limit the material of the wordline conductive layer 82 formed in step S513. In some embodiments, the wordline conductive layer 82 comprises at least one of a metal silicide conductive layer, a titanium nitride conductive layer, and a metal conductive layer such as tungsten, cobalt, or copper.

[0134] Furthermore, in some other embodiments, step S15 of forming the word line structure may also be performed as the following steps S521 - S522 .

[0135] In step S521 , a portion of the vertical stack structure in the channel region c is removed to form a word line through-hole V penetrating the vertical stack structure.

[0136] In step S522 , a word line dielectric layer 81 is formed on the surface of the patterned active layer 211 in the channel region c exposed in the word line through hole V, and a word line conductive layer 82 is filled therein. The word line dielectric layer 81 and the word line conductive layer 82 constitute a word line structure 8 .

[0137] Please continue reading Figure 7 In some embodiments, the vertical stack structure may further include a first connection region 3A located between the transistor region 21A and the bit line region 22A, and a second connection region 4A located between the transistor region 21A and the capacitor region 23A.

[0138] As an example, Figures 17 and 18 As shown, the method for preparing the semiconductor structure may further include the following steps S21 to S24.

[0139] In step S21 , the patterned active layer 211 of the first connection region 3A is transformed into a bit line contact structure 3 .

[0140] In step S22 , the patterned active layer 211 in the bit line region 22A is removed, and a bit line structure 22 is formed. The bit line structure 22 is connected to the patterned active layer 211 in the transistor region 21A via the bit line contact structure 3 .

[0141] In step S23 , the patterned active layer 211 of the second connection region 4A is transformed into a capacitor contact structure 4 .

[0142] In step S24 , the patterned active layer 211 of the capacitor region 23A is removed, and a capacitor structure 23 is formed. The capacitor structure 23 is connected to the patterned active layer 211 of the transistor region 21A via the capacitor contact structure 4 .

[0143] The present disclosure does not specifically limit the method for converting the patterned active layer 211 into the bitline contact structure 3 in step S21. As an example, the patterned active layer 211 can be converted into the bitline contact structure 3 by metallizing the patterned active layer 211. As an example, the material of the bitline contact structure 3 can include, but is not limited to, a silicide of at least one of cobalt (Co), nickel (Ni), molybdenum (Mo), titanium (Ti), tungsten (W), tantalum (Ta), or platinum (Pt). Alternatively, the patterned active layer 211 can be directly or indirectly replaced with a metal material to convert it into the bitline contact structure 3. The present disclosure also does not specifically limit the material of the bitline contact structure 3. As an example, the material of the bitline contact structure 3 can include, but is not limited to, at least one of cobalt (Co), nickel (Ni), molybdenum (Mo), titanium (Ti), tungsten (W), tantalum (Ta), or platinum (Pt). The bitline contact structure 3 can also be a combination of a metal and a metal silicide.

[0144] The present disclosure does not specifically limit the material of the bitline structure 22 formed in step S22. As an example, the material of the bitline structure 22 can be the same as or similar to that of the bitline contact structure 3, such as metal, or other materials such as doped polysilicon.

[0145] Please continue reading Figure 7 In some embodiments, the vertical stack structure may include a plurality of transistor regions 21A spaced apart along the second direction.

[0146] As an example, Figure 19 As shown, step S21 can be specifically expressed as the following steps: the patterned active layer 211 of multiple first connection areas 3A is converted into a bit line contact structure 3, and the bit line structure 22 is connected to the patterned active layer 211 in each transistor area 21A via multiple bit line contact structures 3.

[0147] Also, see Figures 18 and 19 In some embodiments, the method for preparing the semiconductor structure may further include the following steps: performing ion implantation in the patterned active layer 211 exposed in the transistor region 21A to form a source electrode 9 and a drain electrode 10 .

[0148] According to some embodiments, the present disclosure also provides a semiconductor structure.

[0149] Please continue reading Figures 17 to 19 In some embodiments, the semiconductor structure may include a substrate 1 and a vertically stacked device structure.

[0150] The vertically stacked device structure may include a patterned device structure spaced apart from one another, the patterned device structure including a transistor structure 21 and a bit line structure 22 and a capacitor structure 23 located on opposite sides of the transistor structure 21 in a first direction (e.g., X direction), the bit line structure 22 and the capacitor structure 23 being spaced apart from the transistor structure 21.

[0151] The semiconductor structure provided by the present disclosure can be manufactured using the semiconductor structure manufacturing method provided by any of the aforementioned embodiments. Therefore, the present semiconductor structure can also achieve the technical effects achieved by the aforementioned semiconductor structure manufacturing method. Furthermore, the transistor structure has a good channel morphology, thereby ensuring the uniformity of the semiconductor structure and improving the electrical performance of the semiconductor structure.

[0152] Please continue reading Figures 17 to 19 In some embodiments, the semiconductor structure further includes a bit line contact structure 3 located between the transistor structure 21 and the bit line structure 22 , and a capacitor contact structure 4 located between the transistor structure 21 and the capacitor structure 23 .

[0153] Among them, one end of the bit line contact structure 3 is connected to the first side wall of the transistor structure 21 perpendicular to the second direction (for example, the Y direction) and the other end is connected to the bit line structure 22, one end of the capacitor contact structure 4 is connected to the second side wall of the transistor structure 21 perpendicular to the second direction and the other end is connected to the capacitor structure 23, and the first side wall and the second side wall are side walls on the same side of the transistor structure 21 or side walls on opposite sides.

[0154] Please continue reading Figure 17 In some embodiments, the semiconductor structure may further include a first isolation structure 5. The first isolation structure 5 fills the gaps between adjacent transistor regions 21A along the second direction and the gaps between adjacent capacitor regions 23A along the second direction.

[0155] As an example, Figures 17 to 19 As shown, the transistor structure 21 may include a patterned active layer 211 (for ease of description, the patterned active layer is also referred to as an active layer).

[0156] Please continue reading Figure 17In some embodiments, the semiconductor structure may further include an isolation spacer 6 and a second isolation structure 7. The isolation spacer 6 and the second isolation structure 7 are located in the gap between the transistor structure 21 and the bit line structure 22 and the capacitor structure 23. The isolation spacer 6 at least covers the sidewall of the active layer 211 perpendicular to the first direction.

[0157] See also Figures 17 to 20 In some embodiments, the semiconductor structure may further include a word line structure 8 .

[0158] As an example, Figure 18 As shown, the word line structure 8 may extend in the vertical direction and penetrate the active layer 211, that is, the projection of the word line structure 8 in the vertical direction on the substrate is located within the projection of the channel region c in the vertical direction on the substrate; or Figure 20 As shown, the word line structure 8 surrounds the sidewall of the active layer 211 extending along the second direction, that is, the projection of the channel region c along the vertical direction on the substrate is located within the projection of the word line structure 8 along the vertical direction on the substrate.

[0159] As an example, Figures 18 to 20 As shown, the active layer 211 may include a source electrode 9 and a drain electrode 10 , and the source electrode 9 and the drain electrode 10 are respectively located on two opposite sides of the word line structure 8 in the first direction.

[0160] It should be noted that, in the semiconductor structure provided in the above embodiment, the isolation spacer 6 can be used to isolate the sources 9 of adjacent transistor structures 21 in the vertical direction, and to isolate the drains 10 of adjacent transistor structures 21 in the vertical direction.

[0161] As an example, Figures 17 to 20 As shown, the bit line structures 22 may be arranged in a vertical direction and extend along the second direction.

[0162] Please continue reading Figure 19 In some embodiments, the vertically stacked device structure may include a plurality of transistor structures 21 spaced apart along the second direction and a plurality of capacitor structures 23 spaced apart along the second direction. The bitline structure 22 is connected to each transistor structure 21 via a plurality of bitline contact structures 3, and the capacitor structure 23 is connected to each transistor structure 21 via a plurality of capacitor contact structures 4. In the same transistor structure 21, the bitline contact structure 3 and the capacitor contact structure 4 may be located on the same side or different sides of the transistor structure 21 along the second direction. Of two adjacent transistor structures 21, one transistor structure 21 may be connected to the bitline contact structure 3 and the capacitor contact structure 4 via a first side, and the other transistor structure 21 may be connected to the bitline contact structure 3 and the capacitor contact structure 4 via a second side.

[0163] The present disclosure does not specifically limit the shape of the bit line contact structure 3. As an example, the projection of the bit line contact structure 3 on the substrate 1 may be L-shaped or other shapes.

[0164] The present disclosure does not specifically limit the shape of the capacitor contact structure 4. As an example, the projection of the capacitor contact structure 4 on the substrate 1 can be U-shaped or other shapes.

[0165] It should be noted that the semiconductor structures in the embodiments of the present disclosure can all be prepared using the corresponding semiconductor structure preparation methods. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that those skilled in the art can understand the technical content of the present disclosure.

[0166] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0167] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; A vertical stacking structure is formed on the substrate; the vertical stacking structure includes a transistor region, a bit line region and a capacitor region located on opposite sides of the transistor region in a first direction and spaced apart from the transistor region, a first connection region located between the transistor region and the bit line region, and a second connection region located between the transistor region and the capacitor region; the vertical stacking structure includes alternatingly stacked patterned sacrificial layers and patterned active layers; forming a first trench between the transistor region, the bit line region, and the capacitor region, wherein the first trench exposes a sidewall of the vertical stack structure of the transistor region that is perpendicular to the first direction; removing at least a portion of the patterned sacrificial layer in the transistor region along the first trench; forming a word line structure, wherein the word line structure extends in a vertical direction and contacts the patterned active layer of the transistor region; converting the patterned active layer in the first connection region into a bit line contact structure; removing the patterned active layer in the bit line region and forming a bit line structure; the bit line structure is connected to the patterned active layer in the transistor region via the bit line contact structure; converting the patterned active layer in the second connection region into a capacitor contact structure; The patterned active layer in the capacitor region is removed, and a capacitor structure is formed; the capacitor structure is connected to the patterned active layer in the transistor region via the capacitor contact structure.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The bit line region extends along the second direction, and before forming a first trench between the transistor region, the bit line region, and the capacitor region, the preparation method further includes: forming a first isolation structure; the first isolation structure filling the gaps between the bit line region and the plurality of transistor regions, the gaps between the transistor region and the capacitor region, the gaps between adjacent transistor regions along the second direction, and the gaps between adjacent capacitor regions along the second direction; Forming the first trench between the transistor region, the bit line region, and the capacitor region includes: removing a first isolation structure between the transistor region, the bit line region, and the capacitor region in the first direction.

3. The method for preparing a semiconductor structure according to claim 2, wherein: After removing at least a portion of the patterned sacrificial layer in the transistor region along the first trench, the preparation method further includes: forming an isolation sidewall, wherein the isolation sidewall at least covers the exposed surface of the patterned active layer; A second isolation structure is formed, where the second isolation structure covers the surface of the isolation sidewall and fills the gaps between the transistor region, the bit line region, and the capacitor region.

4. The method for preparing a semiconductor structure according to claim 2, wherein: The transistor region includes a channel region and source and drain regions located on two opposite sides of the channel region along the first direction; The forming of the word line structure includes: removing a portion of the first isolation structure between the transistor regions to expose a sidewall of the vertical stack structure of the channel region that is perpendicular to the second direction; removing the remaining patterned sacrificial layer in the transistor region to form a word line through hole, wherein the word line through hole exposes the patterned active layer in the channel region; A word line dielectric layer is formed on the surface of the patterned active layer in the channel region exposed in the word line through hole, and a word line conductive layer is filled therein. The word line dielectric layer and the word line conductive layer constitute the word line structure.

5. The method for preparing a semiconductor structure according to claim 2, wherein: The transistor region includes a channel region and source and drain regions located on two opposite sides of the channel region along the first direction; The forming of the word line structure includes: removing a portion of the vertical stack structure in the channel region to form a word line through-hole penetrating the vertical stack structure; A word line dielectric layer is formed on the surface of the patterned active layer in the channel region exposed in the word line through hole, and a word line conductive layer is filled therein. The word line dielectric layer and the word line conductive layer constitute the word line structure.

6. The method for preparing a semiconductor structure according to claim 1, wherein: After removing at least a portion of the patterned sacrificial layer in the transistor region along the first trench, the preparation method further includes: Ion implantation is performed in the patterned active layer exposed in the transistor region to form a source and a drain.

7. The method for preparing a semiconductor structure according to claim 1, wherein: The vertical stacking structure includes a plurality of transistor regions spaced apart and arranged along a second direction; Converting the patterned active layer of the first connection region into a bit line contact structure, comprising: converting the patterned active layer of a plurality of the first connection regions into a bit line contact structure; The bit line structure is connected to the patterned active layer in each of the transistor regions via a plurality of bit line contact structures.

8. A semiconductor structure prepared according to the preparation method according to any one of claims 1 to 7, characterized in that: include: substrate; A vertically stacked device structure; the vertically stacked device structure includes a patterned device structure arranged with an upper and lower spacing, the patterned device structure includes a transistor structure, a bit line structure and a capacitor structure located on opposite sides of the transistor structure in a first direction, a bit line contact structure located between the transistor structure and the bit line structure, and a capacitor contact structure located between the transistor structure and the capacitor structure, the bit line structure and the capacitor structure being spaced apart from the transistor structure.

9. The semiconductor structure according to claim 8, wherein: One end of the bit line contact structure is connected to the first side wall of the transistor structure perpendicular to the second direction and the other end is connected to the bit line structure. One end of the capacitor contact structure is connected to the second side wall of the transistor structure perpendicular to the second direction and the other end is connected to the capacitor structure. The first side wall and the second side wall are side walls on the same side of the transistor structure or side walls on opposite sides.

10. The semiconductor structure according to claim 9, wherein: The semiconductor structure further includes a first isolation structure; the first isolation structure fills the gaps between the transistor structures adjacent to each other along the second direction and the gaps between the capacitor structures adjacent to each other along the second direction.

11. The semiconductor structure according to claim 10, wherein: The transistor structure includes an active layer, and the semiconductor structure further includes an isolation spacer and a second isolation structure; the isolation spacer and the second isolation structure are located in a gap between the transistor structure, the bit line structure, and the capacitor structure; The isolation spacer at least covers the sidewall of the active layer perpendicular to the first direction.

12. The semiconductor structure according to claim 11, wherein: The semiconductor structure further includes a word line structure; the word line structure extends in a vertical direction and penetrates the active layer, or the word line structure surrounds a sidewall of the active layer extending along the second direction.

13. The semiconductor structure according to claim 9, wherein: The bit line structure is arranged in a vertical direction and extends along the second direction. The vertically stacked device structure includes a plurality of transistor structures arranged at intervals along the second direction and a plurality of capacitor structures arranged at intervals along the second direction. The bit line structure is connected to each of the transistor structures via a plurality of bit line contact structures.

14. The semiconductor structure according to claim 13, wherein: The projection of the bit line contact structure on the substrate is L-shaped, and the projection of the capacitor contact structure on the substrate is U-shaped.

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