Signal processing method for clock receiving circuit and clock receiving circuit

Abstract

The present application relates to the field of computer technology and provides a signal processing method and a clock receiving circuit for a clock receiving circuit. The method includes: converting a current mode logic level signal into a first output differential signal through a differential amplifier circuit; converting the first output differential signal into a second output differential signal through a first level conversion circuit; and converting the second output differential signal into a complementary metal oxide semiconductor level signal through a second level conversion circuit. Both the first and second level conversion circuits adopt a DC coupling method, and the second level conversion circuit includes a complementary input pair tube structure composed of a first complementary circuit and a second complementary circuit. The conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal is determined based on the bias state of the first complementary circuit and the bias state of the second complementary circuit. This is conducive to amplifying the signal, taking into account multiple protocols and multiple frequencies, and improving the duty cycle.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a signal processing method for a clock receiving circuit and a clock receiving circuit. Background Art

[0002] In the application field of high-speed digital transmission and communication, in order to meet the integrity requirements of high-speed data signals, the received signal needs to be amplified at the high-speed data receiving end, and in order to meet the complex and changeable practical application requirements, it is necessary to be compatible with multiple protocols and support multiple different frequencies. One way in the prior art is to first increase the level amplitude through a differential amplifier, and then obtain the AC component, decouple the DC working point, and eliminate the interference of the DC common mode level of the previous circuit to the subsequent circuit through AC coupling; however, the AC coupling-based method relies on the selection of capacitor values ​​to support different frequencies, and due to the presence of capacitors, it takes a certain amount of time to complete the self-built common mode level to maintain the appropriate voltage, which results in the poor performance of the duty cycle of the clock recovery in the first few cycles, making it difficult to achieve fast response, and unable to adapt to the protocol requiring fast response for transceiver requirements. Another way in the prior art is to use a differential amplifier to amplify the level amplitude and then use an inverter to complete the level conversion, but due to the need to be compatible with multiple protocols, the received signal may be in a different voltage domain from the signal recovered by the inverter, and the voltage difference between the two voltage domains may fluctuate over a large range, which will cause duty cycle deviation.

[0003] To this end, the present application provides a signal processing method for a clock receiving circuit and a clock receiving circuit, which are used to address the technical difficulties in the prior art. Summary of the invention

[0004] In a first aspect, the present application provides a signal processing method for a clock receiving circuit. The signal processing method includes: converting a current mode logic level signal into a first output differential signal through a differential amplifier circuit, wherein the differential amplifier circuit retains the DC common mode component of the current mode logic level signal through a DC coupling method and includes a first-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal; converting the first output differential signal into a second output differential signal through a first level conversion circuit, wherein the DC common mode component of the first output differential signal is located in a first voltage domain, and the DC common mode component of the second output differential signal is located in a second voltage domain; converting the second output differential signal into a complementary metal oxide semiconductor level signal through a second level conversion circuit, wherein the first level conversion circuit and the second level conversion circuit both adopt a DC coupling method, and the second level conversion circuit includes a complementary input pair structure composed of a first complementary circuit and a second complementary circuit, and the conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal is determined based on the bias state of the first complementary circuit and the bias state of the second complementary circuit.

[0005] Through the first aspect of the present application, the demand for amplifying current mode logic level signals under high channel attenuation is met, while taking into account the application of multiple protocols and multiple frequencies as well as the application of different rates and different channel attenuations. This effectively overcomes the interference of the front-stage circuit on the rear-stage circuit when the front-stage circuit and the rear-stage circuit are at different power supply voltages, improves the duty cycle performance, and facilitates rapid response.

[0006] In a possible implementation of the first aspect of the present application, the bias state of the first complementary circuit is determined based on a first bias voltage and the second output differential signal, and the bias state of the second complementary circuit is determined based on a second bias voltage and the second output differential signal. The signal processing method also includes adjusting the DC common mode component of the complementary metal oxide semiconductor level signal by increasing or reducing the gap between the first bias voltage and the second bias voltage.

[0007] In a possible implementation of the first aspect of the present application, the second level conversion circuit includes a first field effect transistor pair and a second field effect transistor pair, the first field effect transistor pair and the second field effect transistor pair satisfy a complementary relationship, the control electrode of the first field effect transistor pair is electrically connected to the second output differential signal, the load electrode of the first field effect transistor pair is electrically connected to the first end point and the second end point of the first complementary circuit, the bias electrode of the first field effect transistor pair is commonly grounded, the control electrode of the second field effect transistor pair is electrically connected to the second output differential signal, the load electrode of the second field effect transistor pair is electrically connected to the first end point and the second end point of the second complementary circuit, the bias electrode of the second field effect transistor pair is commonly electrically connected to the second bias voltage, the third end point of the first complementary circuit is electrically connected to the first bias voltage, and the third end point of the second complementary circuit is grounded.

[0008] In a possible implementation of the first aspect of the present application, the bias state of the first complementary circuit is jointly determined based on the first bias voltage and the load pole of the first field effect transistor pair, and the bias state of the second complementary circuit is jointly determined based on the second bias voltage and the load pole of the second field effect transistor pair.

[0009] In a possible implementation of the first aspect of the present application, the DC levels of the first terminal and the second terminal of the first complementary circuit are respectively determined based on the first bias voltage and the DC common mode component of the second output differential signal, the DC levels of the first terminal and the second terminal of the second complementary circuit are respectively determined based on the second bias voltage and the DC common mode component of the second output differential signal, and the DC common mode component of the complementary metal oxide semiconductor level signal is jointly determined based on the DC level of the second terminal of the first complementary circuit and the DC level of the second terminal of the second complementary circuit.

[0010] In a possible implementation manner of the first aspect of the present application, the level of the second terminal of the first complementary circuit is superimposed with the level of the second terminal of the second complementary circuit and then output through a single-ended output or through a single-ended to differential circuit output to obtain the complementary metal oxide semiconductor level signal.

[0011] In a possible implementation of the first aspect of the present application, the greater the difference between the first bias voltage and the second bias voltage, the greater the difference between the DC common-mode component of the second output differential signal and the DC common-mode component of the complementary metal oxide semiconductor level signal.

[0012] In a possible implementation of the first aspect of the present application, the first field effect transistor pair is a P-type field effect transistor pair, and the control electrode, load electrode, and bias electrode of the first field effect transistor pair are respectively the gate, drain, and source of the P-type field effect transistor pair; the second field effect transistor pair is an N-type field effect transistor pair, and the control electrode, load electrode, and bias electrode of the second field effect transistor pair are respectively the gate, source, and drain of the N-type field effect transistor pair.

[0013] In a possible implementation manner of the first aspect of the present application, a turn-on threshold voltage of the first field effect transistor pair is the same as or different from a turn-on threshold voltage of the second field effect transistor pair.

[0014] In a possible implementation of the first aspect of the present application, the greater the difference between the on-threshold voltage of the first field effect transistor pair and the on-threshold voltage of the second field effect transistor pair, the greater the difference between the DC common-mode component of the second output differential signal and the DC common-mode component of the complementary metal oxide semiconductor level signal.

[0015] In a possible implementation manner of the first aspect of the present application, the signal processing method further includes configuring a turn-on threshold voltage of the first field effect transistor pair based on the amplitude of a DC common mode component of the second output differential signal.

[0016] In a possible implementation of the first aspect of the present application, the second level conversion circuit includes a plurality of field effect transistor pairs connected in parallel and having different turn-on voltage thresholds, and the signal processing method further includes, based on the amplitude of the DC common-mode component of the second output differential signal, enabling a given field effect transistor pair among the plurality of field effect transistor pairs as the first field effect transistor pair.

[0017] In a possible implementation of the first aspect of the present application, the first complementary circuit includes a first resistor and a second resistor, the first resistor and the second resistor are respectively electrically connected to the load terminal of the first field effect transistor pair, and the first resistor and the second resistor are commonly connected to the first bias voltage.

[0018] In a possible implementation of the first aspect of the present application, the first complementary circuit includes a third field effect transistor pair, the type of the third field effect transistor pair is different from the type of the first field effect transistor pair, the control electrode of the third field effect transistor pair is commonly electrically connected to the third bias voltage, the load electrode of the third field effect transistor pair is electrically connected to the load electrode of the first field effect transistor pair, and the bias electrode of the third field effect transistor pair is commonly electrically connected to the first bias voltage.

[0019] In a possible implementation of the first aspect of the present application, the first complementary circuit includes a third field effect transistor pair, the type of the third field effect transistor pair is different from the type of the first field effect transistor pair, the control electrodes of the third field effect transistor pair are electrically connected to the first end point of the first complementary circuit, the load electrodes of the third field effect transistor pair are electrically connected to the first end point and the second end point of the first complementary circuit, and the bias electrodes of the third field effect transistor pair are electrically connected to the first bias voltage.

[0020] In a possible implementation manner of the first aspect of the present application, a power supply voltage of the differential amplifier circuit is consistent with a power supply voltage of a transmitting end that provides the current mode logic level signal.

[0021] In a possible implementation manner of the first aspect of the present application, the first level conversion circuit is used to ensure that the output voltage of the second output differential signal does not exceed the tolerable voltage upper limit of the second level conversion circuit.

[0022] In a possible implementation manner of the first aspect of the present application, the differential amplifier circuit includes a multi-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal.

[0023] In a possible implementation manner of the first aspect of the present application, the first level conversion circuit includes a source follower structure for adjusting a DC common mode component of the first output differential signal from the first voltage domain to the second voltage domain.

[0024] In a second aspect, an embodiment of the present application further provides a clock receiving circuit. The clock receiving circuit includes: a differential amplifier circuit for converting a current mode logic level signal into a first output differential signal, wherein the differential amplifier circuit retains the DC common mode component of the current mode logic level signal through a DC coupling method and includes a first-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal; a first level conversion circuit for converting the first output differential signal into a second output differential signal, wherein the DC common mode component of the first output differential signal is located in a first voltage domain, and the DC common mode component of the second output differential signal is located in a second voltage domain; a second level conversion circuit for converting the second output differential signal into a complementary metal oxide semiconductor level signal, wherein the first level conversion circuit and the second level conversion circuit both adopt a DC coupling method, and the second level conversion circuit includes a complementary input pair structure composed of a first complementary circuit and a second complementary circuit, and the conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal is determined based on the bias state of the first complementary circuit and the bias state of the second complementary circuit.

[0025] Through the second aspect of the present application, the demand for amplifying current mode logic level signals under high channel attenuation is met, and the application of multi-protocol and multi-frequency points as well as the application of different rates and different channel attenuations are taken into account. The interference of the front-stage circuit to the subsequent circuit when the front-stage circuit and the subsequent circuit are at different power supply voltages is effectively overcome, the duty cycle performance is improved, and rapid response is facilitated.

[0026] In a possible implementation of the first aspect of the present application, the bias state of the first complementary circuit is determined based on a first bias voltage and the second output differential signal, and the bias state of the second complementary circuit is determined based on a second bias voltage and the second output differential signal, and the DC common mode component of the complementary metal oxide semiconductor level signal is adjusted by increasing or reducing the gap between the first bias voltage and the second bias voltage.

[0027] In a possible implementation of the first aspect of the present application, the second level conversion circuit includes a first field effect transistor pair and a second field effect transistor pair, the first field effect transistor pair and the second field effect transistor pair satisfy a complementary relationship, the control electrode of the first field effect transistor pair is electrically connected to the second output differential signal, the load electrode of the first field effect transistor pair is electrically connected to the first end point and the second end point of the first complementary circuit, the bias electrode of the first field effect transistor pair is commonly grounded, the control electrode of the second field effect transistor pair is electrically connected to the second output differential signal, the load electrode of the second field effect transistor pair is electrically connected to the first end point and the second end point of the second complementary circuit, the bias electrode of the second field effect transistor pair is commonly electrically connected to the second bias voltage, the third end point of the first complementary circuit is electrically connected to the first bias voltage, and the third end point of the second complementary circuit is grounded.

[0028] In a possible implementation of the first aspect of the present application, the DC levels of the first terminal and the second terminal of the first complementary circuit are respectively determined based on the first bias voltage and the DC common mode component of the second output differential signal, the DC levels of the first terminal and the second terminal of the second complementary circuit are respectively determined based on the second bias voltage and the DC common mode component of the second output differential signal, and the DC common mode component of the complementary metal oxide semiconductor level signal is jointly determined based on the DC level of the second terminal of the first complementary circuit and the DC level of the second terminal of the second complementary circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 is a schematic diagram of a high-speed data receiving end;

[0031] Figure 2 A flowchart of a signal processing method for a clock receiving circuit provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of a clock receiving circuit provided in an embodiment of the present application;

[0033] Figure 4 Provided in the embodiments of this application Figure 3 A schematic diagram of a second level conversion circuit in a clock receiving circuit shown;

[0034] Figure 5 Provided in the embodiments of this application Figure 4 A schematic diagram of a first complementary circuit of a first implementation manner in a second level conversion circuit shown;

[0035] Figure 6 Provided in the embodiments of this application Figure 4 A schematic diagram of a first complementary circuit of a second implementation manner in a second level conversion circuit shown;

[0036] Figure 7 Provided in the embodiments of this application Figure 4 FIG. 1 is a schematic diagram of a first complementary circuit in a third implementation manner of a second level conversion circuit. DETAILED DESCRIPTION

[0037] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0038] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0039] Figure 1 FIG. 1 is a schematic diagram of a high-speed data receiving end. Figure 1As shown, the high-speed data receiving end includes a current mode logic level transmission circuit 110 and a clock receiving circuit 112. The current mode logic level transmission circuit 110 outputs a current mode logic level signal A102, and the clock receiving circuit 112 receives the current mode logic level signal A102 and outputs a complementary metal oxide semiconductor level signal A104. In the application field of high-speed digital transmission and communication, the high-speed data receiving end not only needs to amplify the received signal to meet the integrity requirements of the high-speed data signal, but also needs to be compatible with multiple protocols and support multiple different frequencies to meet the complex and changeable practical application requirements. Generally, high-speed signals are transmitted through a current mode logic (CML) level transmission circuit, such as Figure 1The current mode logic level transmission circuit 110 shown in the figure is used for transmission and has good resistance matching characteristics. The current mode logic level transmission circuit 110 mainly relies on current drive, and the matching of its input and output is integrated inside the chip. The current mode logic level signal A102 outputted by it is in the form of a differential pair, so the current mode logic level signal A102 is a differential voltage signal. The clock receiving circuit 112 is used to amplify the received current mode logic level signal A102, and then convert it into a complementary metal oxide semiconductor level signal A104 for use in subsequent circuits. Here, the level amplitude of the current mode logic level signal A102 is smaller than the level amplitude of the complementary metal oxide semiconductor level signal A104, and may only be tens of millivolts after channel attenuation. The circuit structure design and related details of the clock receiving circuit 112 must not only meet the requirements of amplifying the current mode logic level signal A102 under high channel attenuation, but also take into account the application of multiple protocols and multiple frequencies and the application of different rates and different channel attenuation. It is also necessary to consider the interference of the front-stage circuit to the rear-stage circuit when the front-stage circuit and the rear-stage circuit are at different power supply voltages. In addition, it is also necessary to consider the performance of the duty cycle, such as reducing the duty cycle deviation and fast response. Here, the duty ratio refers to the proportion of the power-on time to the total time in a pulse cycle. If the duty ratio performance of the clock recovery signal in the first few cycles is poor, it is difficult to achieve a fast response, and it is impossible to adapt to the protocol that requires a fast response to the transceiver requirements, such as the double data rate synchronous dynamic random access memory (doubledata rate SDRAM, DDR) protocol requires a burst mode. The following detailed description is given in conjunction with the specific embodiments of the present application of a signal processing method for a clock receiving circuit and a clock receiving circuit provided by the present application, which achieves: meeting the demand for amplifying current mode logic level signals under high channel attenuation, taking into account the application of multiple protocols and multiple frequencies as well as the application of different rates and different channel attenuations, effectively overcoming the interference of the front-stage circuit on the rear-stage circuit when the front-stage circuit and the rear-stage circuit are at different power supply voltages, improving the duty cycle performance, and facilitating rapid response.

[0040] Figure 2 A flow chart of a signal processing method for a clock receiving circuit provided in an embodiment of the present application. Figure 2 As shown, the signal processing method for a clock receiving circuit includes the following steps.

[0041] Step S202: Convert the current mode logic level signal into a first output differential signal through a differential amplifier circuit, wherein the differential amplifier circuit retains the DC common mode component of the current mode logic level signal through DC coupling and includes a first-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal.

[0042] Step S204: converting the first output differential signal into a second output differential signal through a first level conversion circuit, wherein a DC common mode component of the first output differential signal is located in a first voltage domain, and a DC common mode component of the second output differential signal is located in a second voltage domain.

[0043] Step S206: converting the second output differential signal into a complementary metal oxide semiconductor level signal through a second level conversion circuit, wherein the first level conversion circuit and the second level conversion circuit both adopt a DC coupling mode, the second level conversion circuit includes a complementary input pair structure consisting of a first complementary circuit and a second complementary circuit, and the conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal is jointly determined based on the bias state of the first complementary circuit and the bias state of the second complementary circuit.

[0044] See also Figure 2 , in step S202, the current mode logic level signal is converted into a first output differential signal through a differential amplifier circuit. The differential amplifier circuit retains the DC common mode component of the current mode logic level signal through a DC coupling method and includes a first-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal. Here, the differential amplifier circuit retains the DC common mode component of the current mode logic level signal through a DC coupling method, which means that the differential amplifier circuit adopts a DC coupling method so that the received signal, that is, the DC common mode component of the current mode logic level signal, can be retained, so that amplification can be performed on the basis of retaining the DC operating point. It should be understood that if an AC coupling method is adopted, it means decoupling the DC common mode component of the current mode logic level signal, that is, decoupling the DC operating point, so that the DC common mode level of the previous circuit can be eliminated. Interference to the subsequent circuit by the DC common mode level, but the subsequent circuit needs to maintain a suitable voltage by self-building the common mode level. Therefore, if the differential amplifier circuit adopts AC coupling instead of DC coupling, it must rely on capacitors to build common-mode levels and must rely on the selection of capacitor values ​​to support different frequencies. The existence of capacitors requires a certain amount of time to complete the self-built common-mode level to maintain the appropriate voltage, which results in a very poor duty cycle of the clock recovery in the first few cycles, making it difficult to achieve fast response and unable to adapt to protocols that require fast response for transceiver requirements. For this reason, Figure 2The signal processing method for a clock receiving circuit shown in step S202 converts the current mode logic level signal into a first output differential signal through a differential amplifier circuit, and the differential amplifier circuit retains the DC common mode component of the current mode logic level signal through a DC coupling method and includes a first-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal. In this way, the use of capacitor devices to self-build common mode levels and support corresponding frequencies is avoided, which helps to achieve fast response and adapt to protocols that require fast response and transceiver requirements. It should be understood that the differential amplifier circuit can adopt any suitable circuit structure design as long as it can achieve the design purpose of retaining the DC common mode component of the current mode logic level signal and amplifying the level amplitude through a DC coupling method. In general, the differential amplifier circuit includes a first-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal, which helps to reduce power consumption and control delay. If a multi-stage amplifier structure is adopted, such as a circuit for amplifying the level amplitude of the current mode logic level signal, it may bring greater power consumption and increase delay. Therefore, in some embodiments, for certain protocols that require low power consumption and low delay, such as parallel port protocols, the differential amplifier circuit only includes a first-stage amplifier structure. In some other embodiments, the differential amplifier circuit may include more than one stage of amplifier structure to amplify the level amplitude.

[0045] Continue reading Figure 2, in step S204, the first output differential signal is converted into a second output differential signal through a first level conversion circuit. The DC common mode component of the first output differential signal is located in the first voltage domain, and the DC common mode component of the second output differential signal is located in the second voltage domain. As mentioned above, in step S202, because the differential amplifier circuit adopts a DC coupling method, the differential amplifier circuit retains the DC common mode component of the current mode logic level signal through a DC coupling method. Considering that the signal received by the clock receiving circuit and the signal output by the clock receiving circuit are generally in different voltage domains, in other words, the clock receiving circuit needs to cope with the situation where the front-stage circuit and the rear-stage circuit are in different power supply voltages. When the voltage difference between the two voltage domains where the two signals, the signal received by the clock receiving circuit and the signal output by the clock receiving circuit, respectively, fluctuate in a wide range, duty cycle deviation may also occur. Therefore, a two-stage level conversion circuit design is adopted, and the conversion from the first voltage domain to the second voltage domain is first realized through the first level conversion circuit. In this way, the first-stage level conversion circuit, that is, the first level conversion circuit, is first used to ensure that the output voltage of the first level conversion circuit meets the level requirements of the subsequent circuit for the input signal, avoiding the risk of device overvoltage, and then the second-stage level conversion circuit is used to achieve further wide-range input level conversion, thereby overcoming the interference of the DC common mode level of the previous circuit on the subsequent circuit. Here, the first level conversion circuit can adopt any suitable circuit structure design, such as a source follower structure, while realizing the level conversion from the DC common mode component of the first output differential signal located in the first voltage domain to the DC common mode component of the second output differential signal located in the second voltage domain, it can also provide a certain signal amplification capability. It should be understood that step S202 is performed first and then step S204 is performed, that is, the level amplitude of the current mode logic level signal is first amplified by the differential amplifier circuit and then the DC common mode component is adjusted by the first level conversion circuit, which helps to meet the application of multi-protocol, multi-frequency, and high channel attenuation, and can also take into account the application of different rates and different channel attenuation. If the common-mode voltage is adjusted first and then the amplitude is amplified, it can only be applied to the case of a single frequency and a large input amplitude, and cannot meet the application of multiple protocols, multiple frequencies, and high channel attenuation. With the development of high-speed data communications, the data transmission rate is getting higher and higher, and the channel attenuation is getting greater and greater. If the input amplitude is small and the inter-symbol interference (ISI) effect is obvious, adjusting the common-mode voltage first, that is, performing voltage domain conversion first, may introduce new noise, deteriorate the signal-to-noise ratio, and even lose the clock information of the previous few cycles, making it difficult to complete clock recovery. For this reason, Figure 2The signal processing method for a clock receiving circuit shown in the figure first amplifies the level amplitude of the current mode logic level signal through a differential amplifier circuit and then adjusts the DC common mode component through a first level conversion circuit. This avoids the introduction of new noise, is beneficial to improving the signal-to-noise ratio and overcoming the inter-symbol interference effect, helps to meet the applications of multi-protocol, multi-frequency, and high channel attenuation, and can also take into account applications of different rates and different channel attenuations.

[0046] Continue reading Figure 2, in step S206, the second output differential signal is converted into a complementary metal oxide semiconductor level signal through a second level conversion circuit. The first level conversion circuit and the second level conversion circuit both adopt a DC coupling method, and the second level conversion circuit includes a complementary input pair structure composed of a first complementary circuit and a second complementary circuit. The conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal is determined based on the bias state of the first complementary circuit and the bias state of the second complementary circuit. As mentioned above, the differential amplifier circuit retains the DC common mode component of the current mode logic level signal through a DC coupling method, thus avoiding the use of capacitor devices to self-build common mode levels and support corresponding frequencies, which helps to achieve fast response and adapt to protocols that require fast response for transceiver requirements. In order to cope with the voltage difference between the two voltage domains where the signals received by the clock receiving circuit and the signals output by the clock receiving circuit are respectively located, a two-stage level conversion circuit design is adopted. First, the conversion from the first voltage domain to the second voltage domain is realized through the first level conversion circuit to ensure that the output voltage of the first level conversion circuit meets the level requirements of the input signal of the subsequent circuit to avoid the risk of device overvoltage. Then, the second output differential signal is converted into a complementary metal oxide semiconductor level signal through the second level conversion circuit, thereby effectively overcoming the interference of the DC common mode level of the previous circuit on the subsequent circuit by providing a wide range of input level conversion. The first level conversion circuit and the second level conversion circuit both adopt a DC coupling mode, so from the differential amplifier circuit to the first level conversion circuit and then to the second level conversion circuit, the entire path is completed in a DC coupling mode, which can achieve a fast response of the clock. Furthermore, the first-stage level conversion circuit in the design of the two-stage level conversion circuit, namely the first level conversion circuit, is used to realize the conversion of the voltage domain, that is, the level conversion from the DC common mode component of the first output differential signal located in the first voltage domain to the DC common mode component of the second output differential signal located in the second voltage domain, thereby ensuring that the output voltage of the first level conversion circuit meets the level requirement of the second level conversion circuit for the input signal, and effectively avoiding the risk of device overvoltage in the second level conversion circuit. Furthermore, because the differential amplifier circuit is used to amplify the level amplitude of the received current mode logic level signal, it can adapt to applications such as small level amplitude, small input amplitude, and high channel attenuation.Taking into account that the high-speed signal rate of the high-speed interface circuit is getting faster and faster, the input amplitude is getting smaller and smaller, and the channel attenuation is getting larger and larger, which leads to a more obvious inter-symbol interference effect. For this reason, the level amplitude of the current mode logic level signal is first amplified by a differential amplifier circuit and then the DC common mode component is adjusted by a first level conversion circuit. This avoids the introduction of new noise, is beneficial to improving the signal-to-noise ratio and overcoming the inter-symbol interference effect, helps to meet the applications of multi-protocol, multi-frequency, and high channel attenuation, and can also take into account applications with different rates and different channel attenuations. Further, the second level conversion circuit includes a complementary input pair tube structure composed of a first complementary circuit and a second complementary circuit. The conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal is determined based on the bias state of the first complementary circuit and the bias state of the second complementary circuit. In this way, by changing the bias state of the first complementary circuit and the bias state of the second complementary circuit in the complementary input pair tube structure, the conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal can be affected, which helps to support a wide range of input common mode levels and provides a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, and, combined with the advantage of fast response brought by the above-mentioned DC coupling method, a better duty cycle performance can be achieved. In addition, the design of a two-stage level conversion circuit can better achieve circuit optimization. On the one hand, the first level conversion circuit is used to achieve switching between different voltage domains, so that the front-stage circuit and the back-stage circuit with different power supply voltages can be flexibly adapted. On the other hand, the second level conversion circuit supports a large input common mode range, so that it can be compatible with multi-protocol scenario requirements.

[0047] In conclusion, Figure 2The signal processing method for a clock receiving circuit shown in the figure is completed in a DC coupling manner from the differential amplifier circuit to the first level conversion circuit and then to the second level conversion circuit, which is helpful to achieve fast response and adapt to the protocol of the receiving and transmitting requirements requiring fast response; through the design of a two-stage level conversion circuit composed of a first level conversion circuit and a second level conversion circuit, switching between different voltage domains is achieved, ensuring that the output voltage of the first level conversion circuit meets the level requirement of the second level conversion circuit for the input signal, and effectively avoiding the risk of device overvoltage in the second level conversion circuit, so that the front-stage circuit and the rear-stage circuit at different power supply voltages can be flexibly adapted; it supports a wide range of input common mode levels and provides a large signal amplification capability, meets the needs of amplifying current mode logic level signals under high channel attenuation, takes into account the application of multiple protocols and multiple frequencies and the application of different rates and different channel attenuations, effectively overcomes the interference of the front-stage circuit on the rear-stage circuit when the front-stage circuit and the rear-stage circuit are at different power supply voltages, improves the performance of the duty cycle, and helps to respond quickly.

[0048] In a possible implementation manner, the bias state of the first complementary circuit is determined based on the first bias voltage and the second output differential signal, the bias state of the second complementary circuit is determined based on the second bias voltage and the second output differential signal, and the signal processing method further includes adjusting the DC common mode component of the complementary metal oxide semiconductor level signal by increasing or reducing the gap between the first bias voltage and the second bias voltage. In this way, by changing the bias state of the first complementary circuit and the bias state of the second complementary circuit in the complementary input pair structure, the conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal can be affected, which helps to support a wide range of input common mode levels and provides a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, and combining the advantages of fast response brought by the above-mentioned DC coupling mode, a better duty cycle performance can be achieved. Moreover, in the face of multi-protocol and multi-frequency applications and applications with different rates and different channel attenuations, these can be reflected in the second output differential signal, and by changing the first bias voltage, the bias state of the first complementary circuit can be adjusted in combination with the second output differential signal, and by changing the second bias voltage, the bias state of the second complementary circuit can be adjusted in combination with the second output differential signal, thereby increasing or reducing the gap between the first bias voltage and the second bias voltage, and then adjusting the DC common-mode component of the complementary metal oxide semiconductor level signal, which helps to support the conversion from current mode logic level signal to complementary metal oxide semiconductor level signal in a large input common mode range, helps to meet the applications of multi-protocol, multi-frequency and high channel attenuation, and can also take into account applications with different rates and different channel attenuations.

[0049] Further, in a possible implementation, the second level conversion circuit includes a first field effect transistor pair and a second field effect transistor pair, the first field effect transistor pair and the second field effect transistor pair satisfy a complementary relationship, the control electrode of the first field effect transistor pair is electrically connected to the second output differential signal, the load electrode of the first field effect transistor pair is electrically connected to the first terminal and the second terminal of the first complementary circuit, the bias electrode of the first field effect transistor pair is commonly grounded, the control electrode of the second field effect transistor pair is electrically connected to the second output differential signal, the load electrode of the second field effect transistor pair is electrically connected to the first terminal and the second terminal of the second complementary circuit, the bias electrode of the second field effect transistor pair is commonly electrically connected to the second bias voltage, the third terminal of the first complementary circuit is electrically connected to the first bias voltage, and the third terminal of the second complementary circuit is grounded. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and also taking into account the application of different rates and different channel attenuation.

[0050] In some embodiments, the bias state of the first complementary circuit is determined based on the first bias voltage and the load of the first field effect transistor pair, and the bias state of the second complementary circuit is determined based on the second bias voltage and the load of the second field effect transistor pair. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and also taking into account the application of different rates and different channel attenuation.

[0051] In some embodiments, the DC level of each of the first terminal and the second terminal of the first complementary circuit is determined based on the first bias voltage and the DC common mode component of the second output differential signal, the DC level of each of the first terminal and the second terminal of the second complementary circuit is determined based on the second bias voltage and the DC common mode component of the second output differential signal, and the DC common mode component of the complementary metal oxide semiconductor level signal is jointly determined based on the DC level of the second terminal of the first complementary circuit and the DC level of the second terminal of the second complementary circuit. In the face of multi-protocol and multi-frequency applications and applications with different rates and different channel attenuation, these can be reflected in the second output differential signal, and by changing the first bias voltage, the DC level of the second terminal of the first complementary circuit can be combined with the DC common mode component of the second output differential signal to adjust the DC level, and by changing the second bias voltage, the DC level of the second terminal of the second complementary circuit can be combined with the DC common mode component of the second output differential signal to adjust the DC level, and then based on the DC level of the second terminal of the first complementary circuit and the DC level of the second terminal of the second complementary circuit, the DC common mode component of the complementary metal oxide semiconductor level signal is jointly determined. This helps support a wide range of input common-mode levels and provides greater signal amplification capabilities, which can better overcome the interference of the DC common-mode level of the previous circuit on the subsequent circuit, meet the applications of multi-protocol, multi-frequency, and high channel attenuation, and can also take into account applications with different rates and different channel attenuations.

[0052] In some embodiments, the level of the second terminal of the first complementary circuit is superimposed with the level of the second terminal of the second complementary circuit, and then the complementary metal oxide semiconductor level signal is obtained through single-end output or through single-end to differential circuit output. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and taking into account the application of different rates and different channel attenuation.

[0053] In some embodiments, the larger the difference between the first bias voltage and the second bias voltage, the larger the difference between the DC common mode component of the second output differential signal and the DC common mode component of the complementary metal oxide semiconductor level signal. In this way, by changing the bias state of the first complementary circuit and the bias state of the second complementary circuit in the complementary input pair structure, the conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal can be affected, which helps to support a wide range of input common mode levels and provides a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, and, combined with the advantage of fast response brought by the above-mentioned DC coupling method, a better duty cycle performance can be achieved.

[0054] In some embodiments, the first field effect transistor pair is a P-type field effect transistor pair, and the control electrode, load electrode, and bias electrode of the first field effect transistor pair are respectively the gate electrode, drain electrode, and source electrode of the P-type field effect transistor pair, and the second field effect transistor pair is an N-type field effect transistor pair, and the control electrode, load electrode, and bias electrode of the second field effect transistor pair are respectively the gate electrode, source electrode, and drain electrode of the N-type field effect transistor pair. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and also taking into account the application of different rates and different channel attenuation.

[0055] In some embodiments, the turn-on threshold voltage of the first field effect transistor pair is the same as or different from the turn-on threshold voltage of the second field effect transistor pair. As mentioned above, by changing the bias state of the first complementary circuit and the bias state of the second complementary circuit in the complementary input pair transistor structure, the conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal can be affected, which helps to support a wide range of input common mode levels and provides a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit. In some examples, the turn-on threshold voltage of the first field effect transistor pair is the same as the turn-on threshold voltage of the second field effect transistor pair. In other examples, the turn-on threshold voltage of the first field effect transistor pair is different from, for example, greater than or less than, the turn-on threshold voltage of the second field effect transistor pair. By changing the gap between the turn-on threshold voltage of the first field effect transistor pair and the turn-on threshold voltage of the second field effect transistor pair, the conversion of the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal can be affected, which helps to support a wide range of input common mode levels.

[0056] In some embodiments, the larger the difference between the turn-on threshold voltage of the first field effect transistor pair and the turn-on threshold voltage of the second field effect transistor pair, the larger the difference between the DC common mode component of the second output differential signal and the DC common mode component of the complementary metal oxide semiconductor level signal. In this way, by changing the difference between the turn-on threshold voltage of the first field effect transistor pair and the turn-on threshold voltage of the second field effect transistor pair, the conversion of the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal can be affected, which helps to support a wide range of input common mode levels.

[0057] In some embodiments, the signal processing method further includes configuring the turn-on threshold voltage of the first field effect transistor pair based on the amplitude of the DC common mode component of the second output differential signal. In this way, by configuring the turn-on threshold voltage of the first field effect transistor pair based on the amplitude of the DC common mode component of the second output differential signal, and then changing the difference between the turn-on threshold voltage of the first field effect transistor pair and the turn-on threshold voltage of the second field effect transistor pair, the front-stage circuit and the back-stage circuit at different power supply voltages can be flexibly adapted, and a large input common mode range can be supported, so as to be compatible with multi-protocol scenario requirements.

[0058] In some embodiments, the second level conversion circuit includes a plurality of field effect transistor pairs connected in parallel and having different conduction voltage thresholds, and the signal processing method further includes enabling a given field effect transistor pair among the plurality of field effect transistor pairs as the first field effect transistor pair based on the amplitude of the DC common mode component of the second output differential signal. Thus, by enabling a given field effect transistor, the conduction voltage threshold of the first field effect transistor pair can be flexibly configured, so that the field effect transistor can be selectively enabled according to the amplitude of the output common mode of the previous stage circuit, which helps to support a wide range of input common mode levels.

[0059] In some embodiments, the first complementary circuit includes a first resistor and a second resistor, the first resistor and the second resistor are respectively electrically connected to the load terminal of the first field effect tube pair, and the first resistor and the second resistor are commonly connected to the first bias voltage. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and also taking into account the application of different rates and different channel attenuation.

[0060] In some embodiments, the first complementary circuit includes a third field effect transistor pair, the type of the third field effect transistor pair is different from the type of the first field effect transistor pair, the control electrode of the third field effect transistor pair is electrically connected to a third bias voltage, the load electrode of the third field effect transistor pair is electrically connected to the load electrode of the first field effect transistor pair, and the bias electrode of the third field effect transistor pair is electrically connected to the first bias voltage. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and also taking into account the application of different rates and different channel attenuation.

[0061] In some embodiments, the first complementary circuit includes a third field effect transistor pair, the type of the third field effect transistor pair is different from the type of the first field effect transistor pair, the control electrode of the third field effect transistor pair is electrically connected to the first terminal of the first complementary circuit, the load electrode of the third field effect transistor pair is electrically connected to the first terminal and the second terminal of the first complementary circuit, and the bias electrode of the third field effect transistor pair is electrically connected to the first bias voltage. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and also taking into account the application of different rates and different channel attenuation.

[0062] In a possible implementation, the power supply voltage of the differential amplifier circuit is consistent with the power supply voltage of the transmitting end providing the current mode logic level signal. In this way, the situation where the front-stage circuit and the rear-stage circuit are at different power supply voltages can be effectively dealt with. From the differential amplifier circuit to the first level conversion circuit and then to the second level conversion circuit, the entire path is completed in a DC coupling manner, which is helpful to achieve fast response and adapt to the protocol of the transceiver requirement requiring fast response; through the design of a two-stage level conversion circuit composed of a first level conversion circuit and a second level conversion circuit, switching between different voltage domains is achieved, ensuring that the output voltage of the first level conversion circuit meets the level requirement of the second level conversion circuit for the input signal, and effectively avoiding the risk of device overvoltage in the second level conversion circuit, so that the front-stage circuit and the rear-stage circuit at different power supply voltages can be flexibly adapted; support a wide range of input common mode levels and provide a large signal amplification capability, meet the needs of amplifying current mode logic level signals under high channel attenuation, take into account the application of multiple protocols and multiple frequencies and the application of different rates and different channel attenuation, effectively overcome the interference of the front-stage circuit to the rear-stage circuit when the front-stage circuit and the rear-stage circuit are at different power supply voltages, improve the performance of the duty cycle, and help fast response.

[0063] In a possible implementation, the first level conversion circuit is used to ensure that the output voltage of the second output differential signal does not exceed the upper voltage limit of the second level conversion circuit. In this way, switching between different voltage domains is achieved, ensuring that the output voltage of the first level conversion circuit meets the level requirement of the second level conversion circuit for the input signal, and effectively avoiding the risk of overvoltage of the second level conversion circuit, so that the front-stage circuit and the back-stage circuit at different power supply voltages can be flexibly adapted.

[0064] In a possible implementation, the differential amplifier circuit includes a multi-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal, thereby achieving retention of the DC common mode component and amplification of the level amplitude of the current mode logic level signal through DC coupling.

[0065] In a possible implementation, the first level conversion circuit includes a source follower structure for adjusting the DC common mode component of the first output differential signal from the first voltage domain to the second voltage domain. In this way, the first-stage level conversion circuit, that is, the first level conversion circuit, is first used to ensure that the output voltage of the first level conversion circuit meets the level requirement of the subsequent circuit for the input signal, thereby avoiding the risk of device overvoltage, and then the second-stage level conversion circuit is used to achieve further wide-range input level conversion, thereby overcoming the interference of the DC common mode level of the previous circuit on the subsequent circuit.

[0066] Figure 3 A schematic diagram of a clock receiving circuit provided in an embodiment of the present application. Figure 3As shown, the clock receiving circuit includes: a differential amplifier circuit 310, used to convert the current mode logic level signal B302 into a first output differential signal B306, wherein the differential amplifier circuit 310 retains the DC common mode component of the current mode logic level signal B302 through DC coupling and includes a first-level amplifier structure for amplifying the level amplitude of the current mode logic level signal B302; a first level conversion circuit 320, used to convert the first output differential signal B306 into a second output differential signal B308, wherein the DC common mode component of the first output differential signal B306 is located in the first voltage domain, and the DC common mode component of the second output differential signal B308 is located in the second voltage domain; a second level conversion circuit 330, used to convert the second output differential signal B308 into a complementary metal oxide semiconductor level signal B304. Among them, the first level conversion circuit 320 and the second level conversion circuit 330 both adopt a DC coupling method, and the second level conversion circuit 330 includes a complementary input pair structure composed of a first complementary circuit and a second complementary circuit. The conversion from the DC common mode component of the second output differential signal B308 to the DC common mode component of the complementary metal oxide semiconductor level signal B304 is jointly determined based on the bias state of the first complementary circuit and the bias state of the second complementary circuit.

[0067] Figure 3 The clock receiving circuit shown, from the differential amplifier circuit 310 to the first level conversion circuit 320 and then to the second level conversion circuit 330, the entire path is completed in a DC coupling manner, which is helpful to achieve fast response and adapt to the protocol requiring fast response for transceiver requirements; through the design of a two-stage level conversion circuit composed of the first level conversion circuit 320 and the second level conversion circuit 330, switching between different voltage domains is achieved, ensuring that the output voltage of the first level conversion circuit 320 meets the level requirement of the second level conversion circuit 330 for the input signal, and effectively avoiding the risk of device overvoltage in the second level conversion circuit 330, so that the front-stage circuit and the rear-stage circuit at different power supply voltages can be flexibly adapted; support a wide range of input common mode levels and provide a large signal amplification capability, meet the needs of amplifying the current mode logic level signal B302 under high channel attenuation, take into account the application of multiple protocols and multiple frequencies and the application of different rates and different channel attenuations, effectively overcome the interference of the front-stage circuit on the rear-stage circuit when the front-stage circuit and the rear-stage circuit are at different power supply voltages, improve the performance of the duty cycle, and help fast response.

[0068] In a possible implementation, the bias state of the first complementary circuit is determined based on the first bias voltage and the second output differential signal, and the bias state of the second complementary circuit is determined based on the second bias voltage and the second output differential signal. The DC common mode component of the complementary metal oxide semiconductor level signal B304 is adjusted by increasing or reducing the gap between the first bias voltage and the second bias voltage. In this way, by changing the bias state of the first complementary circuit and the bias state of the second complementary circuit in the complementary input pair structure, the conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal can be affected, which helps to support a wide range of input common mode levels and provides a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, and, combined with the advantage of fast response brought by the above-mentioned DC coupling method, a better duty cycle performance can be achieved. Moreover, in the face of multi-protocol and multi-frequency applications and applications with different rates and different channel attenuations, these can be reflected in the second output differential signal B308, and by changing the first bias voltage, the bias state of the first complementary circuit can be adjusted in combination with the second output differential signal B308, and by changing the second bias voltage, the bias state of the second complementary circuit can be adjusted in combination with the second output differential signal B308, thereby increasing or reducing the gap between the first bias voltage and the second bias voltage, and then adjusting the DC common-mode component of the complementary metal oxide semiconductor level signal B304, which helps to support the conversion from the current mode logic level signal B302 to the complementary metal oxide semiconductor level signal B304 in a large input common mode range, helps to meet the applications of multi-protocol, multi-frequency and high channel attenuation, and can also take into account applications with different rates and different channel attenuations.

[0069] Figure 4 Provided for the embodiments of this application Figure 3 Schematic diagram of the second level conversion circuit in the clock receiving circuit shown in FIG. Figure 4 As shown, the second level conversion circuit includes a first field effect transistor pair (field effect transistor A410 and field effect transistor B420) and a second field effect transistor pair (field effect transistor C430 and field effect transistor D440). The first field effect transistor pair (field effect transistor A410 and field effect transistor B420) and the second field effect transistor pair (field effect transistor C430 and field effect transistor D440) satisfy a complementary relationship. Figure 4It is schematically shown that the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) is a P-type field effect transistor or a P-type metal oxide semiconductor transistor (PMOS), and the second field effect transistor pair (field effect transistor C430 and field effect transistor D440) is an N-type field effect transistor or an N-type metal oxide semiconductor transistor (NMOS). The first field effect transistor pair is a P-type field effect transistor pair, and the control electrode, load electrode, and bias electrode of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) are respectively the gate, drain, and source of the P-type field effect transistor pair, and the second field effect transistor pair is an N-type field effect transistor pair, and the control electrode, load electrode, and bias electrode of the second field effect transistor pair (field effect transistor C430 and field effect transistor D440) are respectively the gate, source, and drain of the N-type field effect transistor pair.

[0070] Continue reading Figure 4 The control electrode of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) is electrically connected to the second output differential signal C408, the control electrode 414 of field effect transistor A410 is electrically connected to the first signal of the second output differential signal C408, and the control electrode 424 of field effect transistor B420 is electrically connected to the second signal of the second output differential signal C408. The load electrode of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) is electrically connected to the first terminal (terminal A452) and the second terminal (terminal B454) of the first complementary circuit 450, the load electrode 416 of field effect transistor A410 is electrically connected to the first terminal (terminal A452) of the first complementary circuit 450, and the load electrode 426 of field effect transistor B420 is electrically connected to the second terminal (terminal B454) of the first complementary circuit 450. The bias electrodes of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) are grounded together, and the bias electrode 412 of the field effect transistor A410 and the bias electrode 422 of the field effect transistor B420 are grounded together.

[0071] Continue reading Figure 4The control electrode of the second field effect transistor pair (field effect transistor C430 and field effect transistor D440) is electrically connected to the second output differential signal C408, the control electrode 434 of the field effect transistor C430 is electrically connected to the first signal of the second output differential signal C408, and the control electrode 444 of the field effect transistor D440 is electrically connected to the second signal of the second output differential signal C408. The load electrode of the second field effect transistor pair (field effect transistor C430 and field effect transistor D440) is electrically connected to the first terminal (terminal C462) and the second terminal (terminal D464) of the second complementary circuit 460, the load electrode 436 of the field effect transistor C430 is electrically connected to the first terminal (terminal C462) of the second complementary circuit 460, and the load electrode 446 of the field effect transistor D440 is electrically connected to the second terminal (terminal D464) of the second complementary circuit 460. The bias electrodes of the second FET pair (FET C430 and FET D440) are electrically connected to the second bias voltage 466, and the bias electrodes 432 of FET C430 and 442 of FET D440 are electrically connected to the second bias voltage 466. A third terminal (not labeled) of the first complementary circuit 450 is electrically connected to the first bias voltage 456, and a third terminal (not labeled) of the second complementary circuit 460 is grounded.

[0072] Continue reading Figure 4 The bias state of the first complementary circuit 450 is jointly determined based on the first bias voltage 456 and the load electrode of the first field effect transistor pair (the load electrode 416 of the field effect transistor A410 and the load electrode 426 of the field effect transistor B420), and the bias state of the second complementary circuit 460 is jointly determined based on the second bias voltage 466 and the load electrode of the second field effect transistor pair (the load electrode 436 of the field effect transistor C430 and the load electrode 446 of the field effect transistor D440).

[0073] Continue reading Figure 4 The DC levels of the first terminal (terminal A452) and the second terminal (terminal B454) of the first complementary circuit 450 are determined based on the first bias voltage 456 and the DC common mode component of the second output differential signal C408. The DC levels of the first terminal (terminal C462) and the second terminal (terminal D464) of the second complementary circuit 460 are determined based on the second bias voltage 466 and the DC common mode component of the second output differential signal C408. The DC common mode component of the complementary metal oxide semiconductor level signal C404 is jointly determined based on the DC level of the second terminal (terminal B454) of the first complementary circuit 450 and the DC level of the second terminal (terminal D464) of the second complementary circuit 460.

[0074] Figure 4It is also shown that the first complementary circuit 450 includes a submodule 451 of the first complementary circuit 450, which is used to implement the bias state of the first complementary circuit 450. The second complementary circuit 460 includes a submodule 461 of the second complementary circuit 460, which is used to implement the bias state of the second complementary circuit 460. The implementation of the submodule 451 of the first complementary circuit 450 is further described in detail below in conjunction with specific embodiments.

[0075] In this way, by changing the bias state of the first complementary circuit 450 and the bias state of the second complementary circuit 460 in the complementary input pair structure, the conversion from the DC common mode component of the second output differential signal C408 to the DC common mode component of the complementary metal oxide semiconductor level signal C404 can be affected, which helps to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous circuit on the subsequent circuit, and, combined with the advantage of fast response brought by the above-mentioned DC coupling method, a better duty cycle performance can be achieved. In the face of multi-protocol and multi-frequency applications and applications with different rates and different channel attenuations, these can be reflected in the second output differential signal C408, and by changing the first bias voltage 456, the bias state of the first complementary circuit 450 can be adjusted in combination with the second output differential signal C408, and by changing the second bias voltage 466, the bias state of the second complementary circuit 460 can be adjusted in combination with the second output differential signal C408, thereby increasing or reducing the gap between the first bias voltage 456 and the second bias voltage 466, and then adjusting the DC common-mode component of the complementary metal oxide semiconductor level signal C404, which helps to support the conversion from the current mode logic level signal to the complementary metal oxide semiconductor level signal C404 in a large input common mode range, helps to meet the applications of multi-protocol, multi-frequency and high channel attenuation, and can also take into account applications with different rates and different channel attenuations.

[0076] See also Figure 4 In a possible implementation, the level of the second terminal (terminal B454) of the first complementary circuit 450 is superimposed with the level of the second terminal (terminal D464) of the second complementary circuit 460, and then the complementary metal oxide semiconductor level signal C404 is obtained through single-end output or through single-end to differential circuit output. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous stage circuit on the subsequent stage circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and also taking into account the application of different rates and different channel attenuation.

[0077] In some embodiments, the turn-on threshold voltage of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) is the same as or different from the turn-on threshold voltage of the second field effect transistor pair (field effect transistor C430 and field effect transistor D440). In some examples, the turn-on threshold voltage of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) is the same as the turn-on threshold voltage of the second field effect transistor pair (field effect transistor C430 and field effect transistor D440). In other examples, the turn-on threshold voltage of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) is different from, for example, greater than or less than, the turn-on threshold voltage of the second field effect transistor pair (field effect transistor C430 and field effect transistor D440). By changing the difference between the turn-on threshold voltage of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) and the turn-on threshold voltage of the second field effect transistor pair (field effect transistor C430 and field effect transistor D440), the conversion of the DC common mode component of the second output differential signal C408 to the DC common mode component of the complementary metal oxide semiconductor level signal C404 can be affected, which helps to support a wide range of input common mode levels.

[0078] In some embodiments, the greater the difference between the turn-on threshold voltage of the first FET pair (FET A410 and FET B420) and the turn-on threshold voltage of the second FET pair (FET C430 and FET D440), the greater the difference between the DC common mode component of the second output differential signal C408 and the DC common mode component of the complementary metal oxide semiconductor level signal C404. In this way, by changing the difference between the turn-on threshold voltage of the first FET pair (FET A410 and FET B420) and the turn-on threshold voltage of the second FET pair (FET C430 and FET D440), the conversion of the DC common mode component of the second output differential signal C408 to the DC common mode component of the complementary metal oxide semiconductor level signal C404 can be affected, which helps to support a wide range of input common mode levels.

[0079] In some embodiments, the turn-on threshold voltage of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) is configured based on the amplitude of the DC common mode component of the second output differential signal C408. In this way, by configuring the turn-on threshold voltage of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) based on the amplitude of the DC common mode component of the second output differential signal C408, and then changing the gap between the turn-on threshold voltage of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) and the turn-on threshold voltage of the second field effect transistor pair (field effect transistor C430 and field effect transistor D440), the front-stage circuit and the back-stage circuit at different power supply voltages can be flexibly adapted, and a large input common mode range is supported, so that it can be compatible with multi-protocol scenario requirements.

[0080] In some embodiments, the second level conversion circuit includes a plurality of field effect transistor pairs (not shown) connected in parallel and having different turn-on voltage thresholds. Based on the amplitude of the DC common mode component of the second output differential signal C408, a given field effect transistor pair among the plurality of field effect transistor pairs is enabled as the first field effect transistor pair (field effect transistor A410 and field effect transistor B420). In this way, by enabling a given field effect transistor, the turn-on voltage threshold of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420) can be flexibly configured, so that the field effect transistor can be selectively enabled according to the amplitude of the output common mode of the previous stage circuit, which helps to support a wide range of input common mode levels.

[0081] Figure 5 Provided for the embodiments of this application Figure 4 Schematic diagram of the first complementary circuit of the first embodiment of the second level conversion circuit shown in FIG. Figure 5 As shown, the first complementary circuit 450 includes a first resistor (resistor A470) and a second resistor (resistor B472), and the first resistor (resistor A470) and the second resistor (resistor B472) are respectively electrically connected to the load electrode of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420). The first resistor (resistor A470) is electrically connected to the load electrode 416 of the field effect transistor A410, and the second resistor (resistor B472) is electrically connected to the load electrode 426 of the field effect transistor B420. The first resistor (resistor A470) and the second resistor (resistor B472) are commonly connected to the first bias voltage 456. Refer to the above Figure 4As mentioned, the first complementary circuit 450 includes a submodule 451 of the first complementary circuit 450, which is used to realize the bias state of the first complementary circuit 450. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous circuit on the subsequent circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and also taking into account the application of different rates and different channel attenuation.

[0082] Figure 6 Provided for the embodiments of this application Figure 4 Schematic diagram of the first complementary circuit of the second implementation mode in the second level conversion circuit shown in FIG. Figure 6 As shown, the first complementary circuit 450 includes a third field effect transistor pair (field effect transistor E474 and field effect transistor F476), and the type of the third field effect transistor pair (field effect transistor E474 and field effect transistor F476) is different from the type of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420). The control electrodes of the third field effect transistor pair (field effect transistor E474 and field effect transistor F476) are electrically connected to a third bias voltage 478, the load electrodes of the third field effect transistor pair (field effect transistor E474 and field effect transistor F476) are electrically connected to the load electrodes of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420), and the bias electrodes of the third field effect transistor pair (field effect transistor E474 and field effect transistor F476) are electrically connected to the first bias voltage 456. In addition, a DC power supply 477 is also provided to cooperate with the first complementary circuit 450. Refer to the above Figure 4 As mentioned, the first complementary circuit 450 includes a submodule 451 of the first complementary circuit 450, which is used to realize the bias state of the first complementary circuit 450. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous circuit on the subsequent circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and also taking into account the application of different rates and different channel attenuation.

[0083] Figure 7 Provided for the embodiments of this application Figure 4 Schematic diagram of the first complementary circuit of the third embodiment of the second level conversion circuit shown in FIG. Figure 7 As shown, the first complementary circuit 450 includes a third field effect transistor pair (field effect transistor E474 and field effect transistor F476). The type of the third field effect transistor pair (field effect transistor E474 and field effect transistor F476) is different from the type of the first field effect transistor pair (field effect transistor A410 and field effect transistor B420). Figure 6 The difference is that in Figure 7In the illustrated embodiment, the control electrodes of the third field effect transistor pair (field effect transistor E474 and field effect transistor F476) are electrically connected to the first terminal (terminal A452) of the first complementary circuit 450. The load electrodes of the third field effect transistor pair (field effect transistor E474 and field effect transistor F476) are electrically connected to the first terminal (terminal A452) and the second terminal (terminal B454) of the first complementary circuit 450, and the bias electrodes of the third field effect transistor pair (field effect transistor E474 and field effect transistor F476) are electrically connected to the first bias voltage 456. Figure 4 As mentioned, the first complementary circuit 450 includes a submodule 451 of the first complementary circuit 450, which is used to realize the bias state of the first complementary circuit 450. In this way, it is helpful to support a wide range of input common mode levels and provide a larger signal amplification capability, thereby better overcoming the interference of the DC common mode level of the previous circuit on the subsequent circuit, meeting the application of multi-protocol, multi-frequency, and high channel attenuation, and also taking into account the application of different rates and different channel attenuation.

[0084] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0085] The present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0086] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0087] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0088] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A signal processing method for a clock receiving circuit, characterized in that: The signal processing method comprises: Converting the current mode logic level signal into a first output differential signal through a differential amplifier circuit, wherein the differential amplifier circuit retains the DC common mode component of the current mode logic level signal through DC coupling and includes a first-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal; Converting the first output differential signal into a second output differential signal through a first level conversion circuit, wherein a DC common mode component of the first output differential signal is located in a first voltage domain, and a DC common mode component of the second output differential signal is located in a second voltage domain; The second output differential signal is converted into a complementary metal oxide semiconductor level signal by a second level conversion circuit, Wherein, the first level conversion circuit and the second level conversion circuit both adopt a DC coupling mode, the second level conversion circuit includes a complementary input pair structure composed of a first complementary circuit and a second complementary circuit, and the conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal is determined based on the bias state of the first complementary circuit and the bias state of the second complementary circuit. The bias state of the first complementary circuit is determined based on a first bias voltage and the second output differential signal, and the bias state of the second complementary circuit is determined based on a second bias voltage and the second output differential signal. The signal processing method further includes adjusting a DC common mode component of the complementary metal oxide semiconductor level signal by increasing or reducing a difference between the first bias voltage and the second bias voltage. The first level conversion circuit is used to ensure that the output voltage of the second output differential signal does not exceed the upper limit of the tolerable voltage of the second level conversion circuit.

2. The signal processing method according to claim 1, characterized in that: The second level conversion circuit includes a first field effect transistor pair and a second field effect transistor pair, the first field effect transistor pair and the second field effect transistor pair are in a complementary relationship, the control electrode of the first field effect transistor pair is electrically connected to the second output differential signal, the load electrode of the first field effect transistor pair is electrically connected to the first end point and the second end point of the first complementary circuit, the bias electrode of the first field effect transistor pair is commonly grounded, the control electrode of the second field effect transistor pair is electrically connected to the second output differential signal, the load electrode of the second field effect transistor pair is electrically connected to the first end point and the second end point of the second complementary circuit, the bias electrode of the second field effect transistor pair is commonly electrically connected to the second bias voltage, the third end point of the first complementary circuit is electrically connected to the first bias voltage, and the third end point of the second complementary circuit is grounded.

3. The signal processing method according to claim 2, characterized in that: The bias state of the first complementary circuit is determined based on the first bias voltage and the load terminal of the first field effect transistor pair, and the bias state of the second complementary circuit is determined based on the second bias voltage and the load terminal of the second field effect transistor pair.

4. The signal processing method according to claim 2, characterized in that: The DC levels of the first terminal and the second terminal of the first complementary circuit are respectively determined based on the first bias voltage and the DC common mode component of the second output differential signal, the DC levels of the first terminal and the second terminal of the second complementary circuit are respectively determined based on the second bias voltage and the DC common mode component of the second output differential signal, and the DC common mode component of the complementary metal oxide semiconductor level signal is jointly determined based on the DC level of the second terminal of the first complementary circuit and the DC level of the second terminal of the second complementary circuit.

5. The signal processing method according to claim 4, characterized in that: The level of the second terminal of the first complementary circuit and the level of the second terminal of the second complementary circuit are superimposed and then output through a single end or through a single end to differential circuit to obtain the complementary metal oxide semiconductor level signal.

6. The signal processing method according to claim 2, characterized in that: The greater the difference between the first bias voltage and the second bias voltage, the greater the difference between the DC common mode component of the second output differential signal and the DC common mode component of the complementary metal oxide semiconductor level signal.

7. The signal processing method according to claim 2, characterized in that: The first field effect transistor pair is a P-type field effect transistor pair, and the control electrode, load electrode, and bias electrode of the first field effect transistor pair are respectively the gate, drain, and source of the P-type field effect transistor pair; the second field effect transistor pair is an N-type field effect transistor pair, and the control electrode, load electrode, and bias electrode of the second field effect transistor pair are respectively the gate, source, and drain of the N-type field effect transistor pair.

8. The signal processing method according to claim 2, characterized in that: The turn-on threshold voltage of the first field effect transistor pair is the same as or different from the turn-on threshold voltage of the second field effect transistor pair.

9. The signal processing method according to claim 2, characterized in that: The greater the difference between the on-threshold voltage of the first field effect transistor pair and the on-threshold voltage of the second field effect transistor pair, the greater the difference between the DC common mode component of the second output differential signal and the DC common mode component of the complementary metal oxide semiconductor level signal.

10. The signal processing method according to claim 9, characterized in that: The signal processing method further includes configuring a turn-on threshold voltage of the first field effect transistor pair based on the amplitude of a DC common mode component of the second output differential signal.

11. The signal processing method according to claim 10, characterized in that: The second level conversion circuit includes a plurality of field effect transistor pairs connected in parallel and having different turn-on voltage thresholds. The signal processing method also includes, based on the amplitude of the DC common mode component of the second output differential signal, enabling a given field effect transistor pair among the plurality of field effect transistor pairs as the first field effect transistor pair.

12. The signal processing method according to claim 2, characterized in that: The first complementary circuit includes a first resistor and a second resistor, the first resistor and the second resistor are respectively electrically connected to the load terminal of the first field effect transistor pair, and the first resistor and the second resistor are commonly connected to the first bias voltage.

13. The signal processing method according to claim 2, characterized in that: The first complementary circuit includes a third field effect transistor pair, the type of the third field effect transistor pair is different from the type of the first field effect transistor pair, the control electrodes of the third field effect transistor pair are electrically connected to a third bias voltage, the load electrodes of the third field effect transistor pair are electrically connected to the load electrodes of the first field effect transistor pair, and the bias electrodes of the third field effect transistor pair are electrically connected to the first bias voltage.

14. The signal processing method according to claim 2, characterized in that: The first complementary circuit includes a third field effect transistor pair, the type of the third field effect transistor pair is different from the type of the first field effect transistor pair, the control electrodes of the third field effect transistor pair are electrically connected to the first end point of the first complementary circuit, the load electrodes of the third field effect transistor pair are electrically connected to the first end point and the second end point of the first complementary circuit, and the bias electrodes of the third field effect transistor pair are electrically connected to the first bias voltage.

15. The signal processing method according to claim 1, characterized in that: The power supply voltage of the differential amplifier circuit is consistent with the power supply voltage of the transmitting end that provides the current mode logic level signal.

16. The signal processing method according to claim 1, characterized in that: The differential amplifier circuit includes a multi-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal.

17. The signal processing method according to claim 1, characterized in that: The first level conversion circuit includes a source follower structure for adjusting a DC common mode component of the first output differential signal from the first voltage domain to the second voltage domain.

18. A clock receiving circuit, characterized in that: The clock receiving circuit comprises: A differential amplifier circuit, used for converting a current mode logic level signal into a first output differential signal, wherein the differential amplifier circuit retains a DC common mode component of the current mode logic level signal by DC coupling and includes a first-stage amplifier structure for amplifying the level amplitude of the current mode logic level signal; A first level conversion circuit, configured to convert the first output differential signal into a second output differential signal, wherein a DC common mode component of the first output differential signal is located in a first voltage domain, and a DC common mode component of the second output differential signal is located in a second voltage domain; a second level conversion circuit, configured to convert the second output differential signal into a complementary metal oxide semiconductor level signal, Wherein, the first level conversion circuit and the second level conversion circuit both adopt a DC coupling mode, the second level conversion circuit includes a complementary input pair structure composed of a first complementary circuit and a second complementary circuit, and the conversion from the DC common mode component of the second output differential signal to the DC common mode component of the complementary metal oxide semiconductor level signal is determined based on the bias state of the first complementary circuit and the bias state of the second complementary circuit. The bias state of the first complementary circuit is determined based on a first bias voltage and the second output differential signal, and the bias state of the second complementary circuit is determined based on a second bias voltage and the second output differential signal, and the DC common mode component of the complementary metal oxide semiconductor level signal is adjusted by increasing or reducing the difference between the first bias voltage and the second bias voltage. The first level conversion circuit is used to ensure that the output voltage of the second output differential signal does not exceed the upper limit of the tolerable voltage of the second level conversion circuit.

19. The clock receiving circuit according to claim 18, characterized in that: The second level conversion circuit includes a first field effect transistor pair and a second field effect transistor pair, the first field effect transistor pair and the second field effect transistor pair are in a complementary relationship, the control electrode of the first field effect transistor pair is electrically connected to the second output differential signal, the load electrode of the first field effect transistor pair is electrically connected to the first end point and the second end point of the first complementary circuit, the bias electrode of the first field effect transistor pair is commonly grounded, the control electrode of the second field effect transistor pair is electrically connected to the second output differential signal, the load electrode of the second field effect transistor pair is electrically connected to the first end point and the second end point of the second complementary circuit, the bias electrode of the second field effect transistor pair is commonly electrically connected to the second bias voltage, the third end point of the first complementary circuit is electrically connected to the first bias voltage, and the third end point of the second complementary circuit is grounded.

20. The clock receiving circuit according to claim 19, characterized in that: The DC levels of the first terminal and the second terminal of the first complementary circuit are respectively determined based on the first bias voltage and the DC common mode component of the second output differential signal, the DC levels of the first terminal and the second terminal of the second complementary circuit are respectively determined based on the second bias voltage and the DC common mode component of the second output differential signal, and the DC common mode component of the complementary metal oxide semiconductor level signal is jointly determined based on the DC level of the second terminal of the first complementary circuit and the DC level of the second terminal of the second complementary circuit.

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