Voltage stabilization circuits, power supply modules and electronic equipment

Abstract

The present application provides a voltage stabilization circuit, a power module and an electronic device, and relates to the technical field of electronic circuits. The voltage stabilization circuit includes: a feedback control circuit, an output control circuit and a first switch; the first end of the first switch is configured to be connected to a power supply; the feedback control circuit is respectively connected to the enable end and the second end of the first switch, and the feedback control circuit is used to adjust the enable end voltage of the first switch to reduce the output voltage of the first switch when the output voltage of the first switch is greater than a first preset threshold; the input end of the output control circuit is connected to the second end of the first switch, and the output control circuit is used to: output the output voltage of the first switch when the output voltage of the first switch is greater than a second preset threshold; output the reference ground voltage when the voltage output at the second end of the first switch is less than the second preset threshold; wherein the second preset threshold is less than the first preset threshold.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a voltage stabilization circuit, a power supply module and an electronic device. Background Art

[0002] As electronic devices become more sophisticated, the voltage requirements of electronic devices are getting higher and higher. Voltage fluctuations may cause performance degradation of electronic devices, data loss, electromagnetic interference and other problems. Summary of the invention

[0003] The present application provides a voltage stabilization circuit, a power supply module and an electronic device to achieve the effect of stabilizing the power supply voltage.

[0004] In a first aspect, the present application provides a voltage stabilization circuit, comprising: a feedback control circuit, an output control circuit and a first switch; the first end of the first switch is configured to be connected to a power supply; the feedback control circuit is respectively connected to an enable end and a second end of the first switch, and the feedback control circuit is used to adjust the enable end voltage of the first switch to reduce the output voltage of the first switch when the output voltage of the first switch is greater than a first preset threshold; the input end of the output control circuit is connected to the second end of the first switch, and the output control circuit is used to: output the output voltage of the first switch when the output voltage of the first switch is greater than a second preset threshold; output a reference ground voltage when the voltage outputted from the second end of the first switch is less than a second preset threshold; wherein the second preset threshold is less than the first preset threshold.

[0005] In the embodiment of the present application, the output voltage of the first switch can be kept stable by the feedback control circuit, so that the output voltage of the first switch will not be too large. The output control circuit will output the output voltage of the first switch only when the output voltage of the first switch is greater than the second preset threshold value. Thus, the final output voltage value is maintained between the first preset threshold value and the second preset threshold value, and the final output voltage is stable.

[0006] In combination with the technical solution provided in the first aspect above, in some possible implementations, the feedback control circuit includes: a mirror circuit and a current generating circuit; the input end of the current generating circuit is connected to the second end of the first switch, and the current generating circuit is used to generate a first current when the output voltage of the first switch is greater than a first preset threshold; the first end of the mirror circuit is connected to the current generating circuit, and the second end of the mirror circuit is connected to the enable end of the first switch, and the mirror circuit is used to generate a mirror current of the first current, and adjust the enable end voltage of the first switch according to the mirror current.

[0007] In the embodiment of the present application, the current generating circuit is used to generate the first current when the output voltage of the first switch is greater than the first preset threshold, and the mirror circuit can generate a mirror current of the first current, thereby adjusting the voltage of the enable terminal of the first switch through the mirror current. In this way, the pull-up capability of the first switch is reduced, thereby achieving the effect of reducing the output voltage of the first switch, so that the output voltage of the first switch will not be too large.

[0008] In combination with the technical solution provided in the first aspect above, in some possible implementations, the current generating circuit includes: a first clamping circuit, the first clamping circuit includes a plurality of transistors connected in series according to a diode connection method, the first ends of the plurality of transistors connected in series are connected to the second end of the first switch, the second ends of the plurality of transistors are grounded, and the third ends of the plurality of transistors are connected to the first end of the mirror circuit; the on-voltage of the first clamping circuit is equal to the first preset threshold.

[0009] In the embodiment of the present application, since the clamping circuit will only be turned on when the voltage value at its two ends is greater than the turn-on voltage, when the first clamping circuit is not turned on, the first current will not be generated in the current generating circuit, thereby achieving the effect of generating the first current only when the output voltage of the first switch is greater than the first preset threshold.

[0010] In combination with the technical solution provided in the first aspect above, in some possible implementations, the current generating circuit further includes: a second clamping circuit, wherein the first end of the second clamping circuit is connected to the second end of the first switch, the second end of the second clamping circuit is connected to the first end of a specified transistor in the first clamping circuit, and the second end of the second clamping circuit is not connected to the reference ground and the second end of the first switch; wherein the second clamping circuit includes a plurality of transistors connected in diode connection and connected in series in sequence, and the on-voltage of the second clamping circuit is equal to the first preset threshold.

[0011] In combination with the technical solution provided in the first aspect above, in some possible implementations, the first clamping circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series in accordance with a diode connection method; wherein the first end of the first transistor is connected to the second end of the first switch, the second end of the fourth transistor is grounded, and the third end of the fourth transistor is connected to the first end of the mirror circuit; correspondingly, the second clamping circuit includes: a fifth transistor, a sixth transistor, and a seventh transistor connected in series in accordance with a diode connection method; wherein the first end of the fifth transistor is connected to the second end of the first switch, and the second end of the seventh transistor is connected to the first end of the third transistor.

[0012] In combination with the technical solution provided in the first aspect above, in some possible implementations, the mirror circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, and a first resistor; the second end of the eighth transistor is connected to the current generating circuit, the third end of the eighth transistor is grounded, and the first end of the eighth transistor is respectively connected to the second end and the third end of the ninth transistor; the first end of the ninth transistor is configured to be connected to a power supply; the first end of the tenth transistor is connected to the first end of the ninth transistor, the second end of the tenth transistor is connected to the second end of the ninth transistor, the third end of the tenth transistor is grounded through the first resistor, and the third end of the tenth transistor is connected to the enable end of the first switch.

[0013] In the embodiment of the present application, a mirror current of the first current is generated by the eighth transistor, and the mirror current is mirrored to the branch where the first resistor is located through the ninth transistor and the tenth transistor, thereby forming a voltage drop on the first resistor, thereby increasing the voltage at the enable end of the first switch, thereby reducing the pull-up capability of the first switch to reduce the output voltage of the first switch.

[0014] In combination with the technical solution provided in the first aspect above, in some possible implementations, the output control circuit includes: an indication voltage circuit and a selection circuit; the first end of the indication voltage circuit is connected to the second end of the first switch, the second end of the indication voltage circuit is grounded, and the third end of the indication voltage circuit is connected to the first end of the selection circuit; the indication voltage circuit is used to output a first signal when the output voltage of the first switch is greater than the second preset threshold value; and to output a second signal when the output voltage of the first switch is less than or equal to the second preset threshold value; the second end of the selection circuit is connected to the second end of the first switch, the third end of the selection circuit is grounded, and the selection circuit is used to output the output voltage of the first switch when the first signal is received; and to output a reference ground voltage when the second signal is received.

[0015] In the embodiment of the present application, the indicating voltage circuit generates the first signal and the second signal respectively in two cases, so as to control the selection circuit to output the reference ground voltage or the output voltage of the first switch through the first signal and the second signal. Therefore, the final output voltage will not be less than the voltage of the second preset threshold value, and the final output voltage is kept stable.

[0016] In combination with the technical solution provided in the first aspect above, in some possible implementations, the output control circuit further includes: a voltage shaping circuit, the third end of the indication voltage circuit is connected to the first end of the selection circuit through the voltage shaping circuit; the voltage shaping circuit is used to output a low-level signal when the indication voltage circuit outputs a first signal; and output a high-level signal when the indication voltage circuit outputs a second signal; accordingly, the selection circuit is used to output the output voltage of the first switch when the low-level signal is received; and output a reference ground voltage when the high-level signal is received.

[0017] In an embodiment of the present application, the signal output by the indication voltage circuit is shaped by a voltage shaping circuit, so that the difference between the signals received by the control circuit for indication is more obvious, thereby reducing the possibility of misidentifying the second signal as the first signal and misidentifying the first signal as the second signal.

[0018] In combination with the technical solution provided in the first aspect above, in some possible implementations, the voltage shaping circuit includes: a Schmitt trigger and an inverter; the second end of the Schmitt trigger is connected to the second end of the first switch, the third end of the Schmitt trigger is grounded, and the fourth end of the Schmitt trigger is connected to the input end of the inverter; the Schmitt trigger is used to output a high-level signal when the indication voltage circuit outputs a first signal; and output a low-level signal when the indication voltage circuit outputs a second signal; the second end of the inverter is connected to the second end of the first switch, the third end of the inverter is grounded, and the fourth end of the inverter is connected to the first end of the selection circuit.

[0019] In combination with the technical solution provided in the first aspect above, in some possible implementations, the indication voltage circuit includes: a third clamping circuit, a second switch, a second resistor, and a third resistor; the first end of the third clamping circuit is connected to the second end of the first switch, and the second end of the third clamping circuit is grounded through the second resistor; the second end of the third clamping circuit is also connected to the enable end of the second switch; the first end of the second switch is connected to the second end of the first switch through the third resistor, the first end of the second switch is also connected to the first end of the selection circuit, and the second end of the second switch is grounded.

[0020] In the embodiment of the present application, the third clamping circuit can be used to realize that the second switch will be turned on only when the output voltage of the first switch can turn on the third clamping circuit, thereby pulling the voltage of the first end of the second switch down to a low voltage state (i.e., the first signal). When the third clamping circuit is not turned on, the voltage of the first end of the second switch will be a relatively high voltage state (i.e., the second signal), thereby realizing the effect of identifying whether the output voltage of the first switch is greater than the second threshold.

[0021] In combination with the technical solution provided in the first aspect above, in some possible implementations, the indication voltage circuit further includes: a third switch, a first end of the third switch is connected to the first end of the second switch, a second end of the third switch is grounded, and an enable end of the third switch is used to receive a third switch enable signal; wherein, when the voltage stabilization circuit outputs the output voltage of the first switch, the third switch is enabled.

[0022] In the embodiment of the present application, since the third switch is enabled when the voltage stabilization circuit outputs the output voltage of the first switch, the first end of the third switch (that is, the first end of the second switch) is pulled down to a low voltage state (that is, the first signal), so that the output state of the entire voltage stabilization circuit can be maintained in the state of outputting the output voltage of the first switch.

[0023] In combination with the technical solution provided in the first aspect above, in some possible implementations, the selection circuit includes: a fourth switch and a fifth switch; the first end of the fourth switch is connected to the second end of the first switch, and the enable end of the fourth switch is connected to the third end of the indication voltage circuit; wherein the fourth switch is a low voltage enabled switch; the enable end of the fifth switch is connected to the third end of the indication voltage circuit, the second end of the fifth switch is connected to the second end of the fourth switch, and the first end of the fifth switch is grounded; wherein the fifth switch is a high voltage enabled switch.

[0024] In the embodiment of the present application, since the enable terminals of the fourth switch and the fifth switch are both connected to the third terminal of the indication voltage circuit, and the fourth switch is a low voltage enabled switch, and the fifth switch is a high voltage enabled switch, when the first signal is received, the fourth switch is turned on and the fifth switch is turned off, so that the output voltage is the output voltage of the first switch. When the second voltage is received, the fourth switch is turned off and the fifth switch is turned on, so that the output voltage is the reference ground voltage.

[0025] In combination with the technical solution provided in the first aspect above, in some possible implementations, the voltage stabilization circuit further includes: a fourth clamping circuit, a first end of the fourth clamping circuit being configured to be connected to the power supply, and a second end of the fourth clamping circuit being connected to an enable end of the first switch; wherein a turn-on voltage of the fourth clamping circuit is higher than the first preset threshold.

[0026] In the embodiment of the present application, the fourth clamping circuit can be turned on when the power supply voltage is too large, thereby increasing the voltage at the enable end of the first switch and reducing the gate-source voltage of the first switch so that it will not be too large, thereby ensuring that the first switch can work normally.

[0027] In combination with the technical solution provided in the first aspect above, in some possible implementations, the voltage stabilization circuit further includes: a filter circuit, and the filter circuit is connected to the output end of the output control circuit.

[0028] In the embodiment of the present application, the voltage finally output by the voltage stabilization circuit is filtered by the filtering circuit, so that the burrs on the final output voltage can be filtered out, making the final output voltage more stable.

[0029] In a second aspect, the present application provides a power supply module, comprising: a voltage stabilization circuit as described in the first aspect above and / or in combination with any possible implementation of the first aspect above.

[0030] In a third aspect, the present application provides an electronic device, comprising: a power module as described in the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A structural block diagram of a voltage stabilization circuit shown in an embodiment of the present application;

[0033] Figure 2 A connection diagram of a plurality of transistors connected in series in a diode connection manner according to an embodiment of the present application;

[0034] Figure 3 A circuit structure diagram of a current generating circuit shown in an embodiment of the present application;

[0035] Figure 4A circuit structure diagram of a voltage stabilization circuit shown in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The terms “first”, “second”, “third”, etc. are only used for distinguishing descriptions and do not indicate the order of arrangement, nor can they be understood as indicating or implying relative importance.

[0037] In the description of this application, unless otherwise clearly specified and limited, the terms "set", "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection.

[0038] The technical solution of the present application will be described in detail below with reference to the accompanying drawings.

[0039] See also Figure 1 , Figure 1 This is a structural block diagram of a voltage stabilization circuit shown in an embodiment of the present application. The voltage stabilization circuit includes a feedback control circuit, an output control circuit and a first switch.

[0040] like Figure 1 As shown, the feedback control circuit is connected to the enable terminal and the second terminal of the first switch respectively, and the feedback control circuit is used to adjust the voltage of the enable terminal of the first switch to reduce the output voltage of the first switch when the output voltage of the first switch is greater than the first preset threshold. The input terminal of the output control circuit is connected to the second terminal of the first switch, and the output control circuit is used to: output the output voltage of the first switch when the output voltage of the first switch is greater than the second preset threshold; and output the reference ground voltage when the voltage output at the second terminal of the first switch is less than the second preset threshold.

[0041] The second preset threshold is smaller than the first preset threshold.

[0042] The output voltage of the first switch can be kept stable by the feedback control circuit, so that the output voltage of the first switch will not be too large. The output control circuit will output the output voltage of the first switch only when the output voltage of the first switch is greater than the second preset threshold value. Thus, the final output voltage value is kept between the first preset threshold value and the second preset threshold value, so as to achieve the stability of the final output voltage.

[0043] The output voltage of the first switch is the voltage output by the second end of the first switch.

[0044] In one implementation, the first switch may be a PMOS tube, in which case the source of the first switch is configured to be connected to a power source, the drain and gate of the first switch are respectively connected to a feedback control circuit, and the second end of the first switch is a drain end.

[0045] Alternatively, the first switch may also be any other circuit or electronic component that can realize the function of the first switch, or the first switch may also be realized through a software function.

[0046] In one implementation, the feedback control circuit may include a mirror circuit and a current generating circuit.

[0047] The input end of the current generating circuit is connected to the second end of the first switch, and the current generating circuit is used to generate a first current when the output voltage of the first switch is greater than a first preset threshold. The first end of the mirror circuit is connected to the current generating circuit, and the second end of the mirror circuit is connected to the enable end of the first switch. The mirror circuit is used to generate a mirror current of the first current and adjust the enable end voltage of the first switch according to the mirror current.

[0048] The current generating circuit can generate the first current when the output voltage of the first switch is greater than the first preset threshold, and the mirror circuit can generate a mirror current of the first current, so as to adjust the voltage of the enable terminal of the first switch through the mirror current, thereby reducing the pull-up capability of the first switch, thereby achieving the effect of reducing the output voltage of the first switch, so that the output voltage of the first switch will not be too large.

[0049] In one embodiment, the current generating circuit may include a first clamping circuit, which includes a plurality of transistors connected in series according to a diode connection method, wherein the first ends of the plurality of transistors connected in series are connected to the second end of the first switch, the second ends of the plurality of transistors are grounded, and the third ends of the plurality of transistors are connected to the first end of the mirror circuit; the on-voltage of the first clamping circuit is equal to a first preset threshold value.

[0050] Since the clamping circuit will only be turned on when the voltage value at its two ends is greater than the turn-on voltage, when the first clamping circuit is not turned on, the first current will not be generated in the current generating circuit, thereby achieving the effect of generating the first current only when the output voltage of the first switch is greater than the first preset threshold.

[0051] The diode-connected transistor is functionally equivalent to a diode. Specifically, if the transistor is a PMOS transistor, the diode connection is to connect the gate and drain of the PMOS transistor as the anode of the diode, and use the source of the PMOS transistor as the cathode of the diode.

[0052] A plurality of transistors connected in series in diode connection, that is, an end of each diode-connected transistor corresponding to the anode of the diode is connected to an end of the previous transistor corresponding to the cathode, can be equivalent to a plurality of diodes connected in series in circuit.

[0053] For ease of understanding, taking multiple transistors as PMOS tubes as an example, the specific connection method of multiple transistors connected in series in accordance with the diode connection method is as follows: Figure 2 shown.

[0054] Optionally, the current generating circuit may further include a second clamping circuit. The first end of the second clamping circuit is connected to the second end of the first switch, the second end of the second clamping circuit is connected to the first end of a specified transistor in the first clamping circuit, and the second end of the second clamping circuit is not connected to the reference ground and the second end of the first switch. The second clamping circuit includes a plurality of transistors connected in series in a diode connection, and the on-voltage of the second clamping circuit is equal to the first preset threshold.

[0055] The specific implementation method and principle of the second clamping circuit are consistent with the implementation method and principle of the aforementioned first clamping circuit, and are not repeated here for the sake of brief description.

[0056] By providing the second clamping circuit, the magnitude of the current generated by the current generating circuit can be increased.

[0057] Among them, the second end of the second clamping circuit is not connected to the reference ground and the second end of the first switch, that is, the second end of the second clamping circuit is not connected to the end corresponding to the anode of the first transistor in the current inflow direction of the first clamping circuit, and is not connected to the end corresponding to the cathode of the first transistor in the current outflow direction of the first clamping circuit.

[0058] To facilitate understanding of the specific implementation of the above-mentioned first clamping circuit and the second clamping circuit, the following is an example in which the first clamping circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and the second clamping circuit includes a fifth transistor, a sixth transistor, and a seventh transistor.

[0059] like Figure 3 As shown, the first clamping circuit includes first transistors (such as Figure 3 NM1 shown), the second transistor (such as Figure 3 NM2 shown), the third transistor (such as Figure 3 NM3 shown), the fourth transistor (such as Figure 3 The first end of the first transistor is connected to the second end of the first switch, the second end of the fourth transistor is grounded, and the third end of the fourth transistor is connected to the first end of the mirror circuit. The first transistor, the second transistor, the third transistor, and the fourth transistor are NMOS transistors.

[0060] The second clamping circuit includes a fifth transistor (such as Figure 3 PM9 shown), the sixth transistor (such as Figure 3NM11 shown), the seventh transistor (such as Figure 3 NM12 shown); wherein the first end of the fifth transistor is connected to the second end of the first switch, and the second end of the seventh transistor is connected to the first end of the third transistor. The sixth transistor and the seventh transistor can be PMOS transistors, and the fifth transistor can be an NMOS transistor.

[0061] Alternatively, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all PMOS transistors.

[0062] Specific implementations of the first clamping circuit and the second clamping circuit include but are not limited to the above-mentioned examples.

[0063] In one implementation manner, the mirror circuit may include: an eighth transistor, a ninth transistor, a tenth transistor, and a first resistor.

[0064] The second end of the eighth transistor is connected to the current generating circuit, the third end of the eighth transistor is grounded, and the first end of the eighth transistor is respectively connected to the second end and the third end of the ninth transistor; the first end of the ninth transistor is configured to be connected to a power supply; the first end of the tenth transistor is connected to the first end of the ninth transistor, the second end of the tenth transistor is connected to the second end of the ninth transistor, the third end of the tenth transistor is grounded through the first resistor, and the third end of the tenth transistor is connected to the enable end of the first switch.

[0065] A mirror current of the first current is generated through the eighth transistor, and the mirror current is mirrored to the branch where the first resistor is located through the ninth transistor and the tenth transistor, thereby forming a voltage drop on the first resistor, thereby increasing the voltage at the enable end of the first switch, thereby reducing the pull-up capability of the first switch, so as to reduce the output voltage of the first switch.

[0066] Optionally, when the current generating circuit includes a first clamping circuit, the second end of the eighth transistor may be connected to an end of the anode of a diode corresponding to any transistor in the first clamping circuit.

[0067] For example, in the specific implementation of the current generating circuit, Figure 3 In the case shown, the second terminal of the eighth transistor may be connected to the gate of the fourth transistor.

[0068] Optionally, the eighth transistor may be an NMOS transistor, and the ninth transistor and the tenth transistor may be PMOS transistors.

[0069] The specific resistance value of the first resistor can be set according to actual needs, and its specific value is not limited here.

[0070] The first resistor may be a single resistor, or the first resistor may be a resistor formed by connecting a plurality of resistors in series.

[0071] In one implementation, the output control circuit may include: an indication voltage circuit and a selection circuit.

[0072] The indicating voltage circuit generates the first signal and the second signal respectively in two cases, so as to control the selection circuit to output the reference ground voltage or the output voltage of the first switch through the first signal and the second signal, so that the final output voltage will not be less than the voltage of the second preset threshold value, and the final output voltage is kept stable.

[0073] The first end of the indicating voltage circuit is connected to the second end of the first switch, the second end of the indicating voltage circuit is grounded, and the third end of the indicating voltage circuit is connected to the first end of the selecting circuit; the indicating voltage circuit is used to output a first signal when the output voltage of the first switch is greater than a second preset threshold value; and output a second signal when the output voltage of the first switch is less than or equal to the second preset threshold value.

[0074] Optionally, the indication voltage circuit may include: a third clamping circuit, a second switch, a second resistor, and a third resistor.

[0075] Among them, the first end of the third clamping circuit is connected to the second end of the first switch, and the second end of the third clamping circuit is grounded through the second resistor; the second end of the third clamping circuit is also connected to the enable end of the second switch; the first end of the second switch is connected to the second end of the first switch through the third resistor, the first end of the second switch is also connected to the first end of the selection circuit, and the second end of the second switch is grounded.

[0076] The third clamping circuit can realize that the second switch will be turned on only when the output voltage of the first switch can turn on the third clamping circuit, thereby pulling the voltage of the first end of the second switch down to a low voltage state (i.e., the first signal). When the third clamping circuit is not turned on, the voltage of the first end of the second switch will be a relatively high voltage state (i.e., the second signal), thereby realizing the effect of identifying whether the output voltage of the first switch is greater than the second threshold.

[0077] The conduction voltage of the third clamp circuit is the second preset threshold. The specific implementation mode and principle of the third clamp circuit are the same as those of the first clamp circuit, and are not repeated here for the sake of brief description.

[0078] Optionally, the second switch may be an NMOS tube, or the second switch may be other circuits or electronic components that can realize the function of the second switch, or the second switch may be realized through a software function.

[0079] The specific resistance values ​​of the second resistor and the third resistor can be set according to actual needs, and their specific values ​​are not limited here.

[0080] Optionally, the indicating voltage circuit may further include: a third switch, wherein a first end of the third switch is connected to a first end of the second switch, a second end of the third switch is grounded, and an enable end of the third switch is used to receive a third switch enable signal; wherein the third switch is enabled when the voltage stabilization circuit outputs the output voltage of the first switch.

[0081] Since the third switch is enabled when the voltage stabilization circuit outputs the output voltage of the first switch, the first end of the third switch (that is, the first end of the second switch) is pulled down to a low voltage state (that is, the first signal), so that the output state of the entire voltage stabilization circuit can be maintained in the state of outputting the output voltage of the first switch.

[0082] The third switch may be an NMOS tube, or the third switch may be other circuits or electronic components that can realize the function of the third switch, or the third switch may be realized through a software function.

[0083] When the voltage stabilization circuit outputs the output voltage of the first switch, the third switch is enabled, that is, when the voltage stabilization circuit outputs the output voltage of the first switch, the enable terminal of the third switch receives an enable signal to turn on the third switch.

[0084] The second end of the selection circuit is connected to the second end of the first switch, and the third end of the selection circuit is grounded. The selection circuit is used to output the output voltage of the first switch when receiving the first signal; and output the reference ground voltage when receiving the second signal.

[0085] In one implementation manner, the selection circuit includes a fourth switch and a fifth switch.

[0086] A first end of the fourth switch is connected to the second end of the first switch, and an enable end of the fourth switch is connected to the third end of the indication voltage circuit; wherein the fourth switch is a low voltage enabled switch.

[0087] The enable terminal of the fifth switch is connected to the third terminal of the indication voltage circuit, the second terminal of the fifth switch is connected to the second terminal of the fourth switch, and the first terminal of the fifth switch is grounded; wherein the fifth switch is a high voltage enabled switch.

[0088] Since the enable terminals of the fourth switch and the fifth switch are both connected to the third terminal of the indicating voltage circuit, and the fourth switch is a low voltage enabled switch, and the fifth switch is a high voltage enabled switch, when the first signal is received, the fourth switch is turned on and the fifth switch is turned off, so that the final output voltage is the output voltage of the first switch. When the second signal is received, the fourth switch is turned off and the fifth switch is turned on, so that the final output voltage is the reference ground voltage.

[0089] The first signal is a signal that can turn on the fourth switch but not the fifth switch; the second signal is a signal that can turn on the fifth switch but not the fourth switch.

[0090] Optionally, the fourth switch may be a PMOS tube, or the fourth switch may be other circuits or electronic components that can realize the function of the fourth switch, or the fourth switch may be realized through a software function.

[0091] Optionally, the fifth switch may be an NMOS tube, or the fifth switch may be other circuits or electronic components that can realize the function of the fifth switch, or the fifth switch may be realized through a software function.

[0092] In one implementation, the output control circuit may further include a voltage shaping circuit.

[0093] Among them, the third end of the indicating voltage circuit is connected to the first end of the selecting circuit through the voltage shaping circuit; the voltage shaping circuit is used to output a low level signal when the indicating voltage circuit outputs the first signal; and output a high level signal when the indicating voltage circuit outputs the second signal.

[0094] The selection circuit is used to output the output voltage of the first switch when a low-level signal is received, and to output the reference ground voltage when a high-level signal is received.

[0095] The signal output by the indicating voltage circuit is shaped by the voltage shaping circuit, so that the difference between the signals for indication received by the control circuit is more obvious, and the situation of misidentifying the second signal as the first signal and misidentifying the first signal as the second signal is reduced.

[0096] For example, if the first signal is a signal with a voltage value in the range of 0 to 1V, and the second signal is a signal in the range of 1 to 3V, then the voltage shaping circuit outputs a low-level signal (for example, 0V, 0.1V, etc., and the specific value can be set according to actual needs) when receiving a signal in the range of 0 to 1V. When receiving a signal in the range of 1 to 3V, a high-level signal (for example, 3V, 5V, etc., and the specific value can be set according to actual needs) is output. The examples here are only for ease of understanding and should not be used as limitations on this application.

[0097] Optionally, the voltage shaping circuit may include a Schmitt trigger and an inverter.

[0098] The second end of the Schmitt trigger is connected to the second end of the first switch, the third end of the Schmitt trigger is grounded, and the fourth end of the Schmitt trigger is connected to the input end of the inverter; the Schmitt trigger is used to output a high level signal when the indication voltage circuit outputs the first signal; and output a low level signal when the indication voltage circuit outputs the second signal.

[0099] The second end of the inverter is connected to the second end of the first switch, the third end of the inverter is grounded, and the fourth end of the inverter is connected to the first end of the selection circuit.

[0100] Among them, the Schmitt trigger under this implementation mode is a negative phase output (that is, the input and output are in opposite phases; for example, the input signal is a low level signal, and the output signal is a high level signal), but the specific working principle and implementation method of the Schmitt trigger and the inverter are well known to technical personnel in this field, and for the sake of brief description, they will not be repeated here.

[0101] Alternatively, the voltage shaping circuit may include only a Schmitt trigger.

[0102] The second end of the Schmitt trigger is connected to the second end of the first switch, the third end of the Schmitt trigger is grounded, and the fourth end of the Schmitt trigger is connected to the first end of the selection circuit.

[0103] The Schmitt trigger is used to output a low level signal when the indication voltage circuit outputs a first signal; and to output a high level signal when the indication voltage circuit outputs a second signal.

[0104] The Schmitt trigger in this embodiment has a positive phase output (i.e., the input and output are in phase; for example, the input signal is a low-level signal, and the output signal is a low-level signal). The specific working principle and implementation method of the Schmitt trigger are well known to those skilled in the art, and will not be repeated here for the sake of brief description.

[0105] In one implementation manner, the voltage stabilization circuit may further include: a fourth clamping circuit.

[0106] The first end of the fourth clamp circuit is configured to be connected to a power source, and the second end of the fourth clamp circuit is connected to an enable end of the first switch, wherein a turn-on voltage of the fourth clamp circuit is higher than a first preset threshold.

[0107] The specific implementation method and principle of the fourth clamping circuit are consistent with the specific implementation method and principle of the first clamping circuit described above, and are not repeated here for the sake of brief description.

[0108] The fourth clamping circuit can be turned on when the power supply voltage is too large, thereby increasing the voltage at the enable end of the first switch and reducing the gate-source voltage of the first switch from being too large, thereby ensuring that the first switch can work normally.

[0109] In one implementation, the voltage stabilization circuit further includes a filter circuit, wherein the filter circuit is connected to the output end of the output control circuit.

[0110] The voltage finally output by the voltage stabilization circuit is filtered by the filtering circuit, so that the burrs on the final output voltage can be filtered out, making the final output voltage more stable.

[0111] Optionally, the filter circuit may be any type of circuit that can implement a filtering function, such as an RC filter circuit.

[0112] Optionally, the filter circuit may include an eleventh transistor and a twelfth transistor, wherein the gate of the eleventh transistor is connected to the output end of the output control circuit, and the source and drain of the eleventh transistor are grounded; the gate of the twelfth transistor is connected to the output end of the output control circuit, and the source and drain of the twelfth transistor are grounded.

[0113] To understand the voltage stabilization circuit above, please refer to Figure 4 .

[0114] like Figure 4 As shown, the source of the first switch PM1 is configured to be connected to the power supply (eg Figure 4 The fourth clamping circuit includes PM5, PM6, PM7, and PM8. Among them, the four transistors PM5, PM6, PM7, and PM8 are all connected in a diode connection mode. Specifically, the source of PM5 is connected to the source of PM1, the gate and drain of PM5 are connected to the source of PM6, the gate and drain of PM6 are connected to the source of PM7, the gate and drain of PM7 are connected to the source of PM8, and the gate and drain of PM8 are grounded through the resistor R1.

[0115] The current generating circuit includes a first clamping circuit and a second clamping circuit.

[0116] The first clamping circuit includes four transistors NM1, NM2, NM3, and NM4, wherein the four transistors NM1, NM2, NM3, and NM4 are all connected in a diode connection mode. Specifically, the gate and drain of NM1 are connected, and the gate of NM1 is connected to the drain of the first switch PM1. The source of NM1 is connected to the drain and gate of NM2; the source of NM2 is connected to the drain and gate of NM3; the source of NM3 is connected to the drain and gate of NM4, and the source of NM4 is grounded.

[0117] The second clamping circuit includes three transistors PM9, NM11, and NM12 (the second clamping circuit may also be composed entirely of NMOS transistors, or entirely of PMOS transistors), wherein the three transistors PM9, NM11, and NM12 are all connected in a diode connection manner. Specifically, the gate and drain of PM9 are connected, and the source of PM9 is connected to the drain of the first switch PM1. The drain of PM9 is connected to the drain and gate of NM11, the source of NM11 is connected to the gate and drain of NM12, and the source of NM12 is connected to the gate and drain of NM3.

[0118] The mirror circuit includes three transistors, namely NM5 (i.e., the eighth transistor), PM4 (i.e., the ninth transistor), and PM3 (i.e., the tenth transistor), and a resistor R1 (i.e., the first resistor). The gate of NM5 is connected to the gate of NM4, the source of NM5 is grounded, and the drain of NM5 is connected to the drain of PM4. The source of PM4 is configured to be connected to a power supply, and the gate of PM4 is connected to the gate of PM3. The source of PM3 is configured to be connected to a power supply, and the drain of PM3 is connected to the gates of resistors R1 and PM1, respectively. The other end of resistor R1 is grounded.

[0119] The output control circuit includes an indication voltage circuit, a selection circuit, and a voltage shaping circuit.

[0120] The indication voltage circuit includes PM10, PM11, NM6 (also known as the second switch), NM7 (also known as the third switch), R3 (also known as the second resistor), and R2 (also known as the third resistor). Among them, PM10 and PM11 constitute a third clamping circuit. Specifically, the source of PM10 is connected to the drain of PM1, the gate and drain of PM10 are connected to the source of PM11, and the gate and drain of PM11 are grounded through R3. The gate and drain of PM11 are also connected to the gate of NM6, the source of NM6 is grounded, and the drain of NM6 is connected to the drain of PM1 through R2. The gate of NM7 is used to receive an enable signal (such as Figure 4 As shown in S1), the source of NM7 is grounded, and the drain of NM7 is connected to the drain of NM6.

[0121] Voltage shaping circuits include Schmitt triggers (such as Figure 4 Schmitt) and inverter (as shown Figure 4 Inverter shown in the figure), the input end of the Schmitt trigger is connected to the drain of PM6, and the output end of the Schmitt trigger is connected to the input end of the inverter.

[0122] The selection circuit includes PM12 (also known as the fourth switch) and NM8 (also known as the fifth switch). The gate of PM12 is connected to the output end of the inverter, and the source of PM12 is connected to the drain of PM1. The gate of NM8 is connected to the output end of the inverter, and the source of NM8 is grounded. The drain of NM8 is also connected to the gate of NM9 and the gate of NM10 included in the filter circuit.

[0123] Figure 4 The specific working principle of the circuit shown is: when VCC is too small, the gate-source voltage of PM1 is less than the on-voltage, and PM1 is cut off.

[0124] VCC increases, the gate-source voltage of PM1 is greater than the turn-on voltage, and PM1 is turned on; the net2 voltage is less than the total voltage of NM1, NM2, NM3, and NM4 (that is, the first preset threshold) and the total voltage of PM9, NM11, and NM12 when they are turned on, so no mirror current is generated.

[0125] If the voltage of net2 is greater than the total voltage of NM1, NM2, NM3, NM4 and the total voltage of PM9, NM11, NM12, then NM1, NM2, NM3, NM4 and PM9, NM11, NM12 are turned on. Therefore, there is a current in NM4, which causes the current to appear in PM4 and PM3 of the mirror circuit. A voltage drop occurs on R1, which pulls up the voltage of net1, reduces the pull-up capability of PM1, and thus reduces the voltage of net2.

[0126] If the voltage of net2 is less than the conduction voltage of PM10 and PM11 (i.e., the second preset voltage), net4 is at a low voltage, NM6 is not conducting, and therefore, the voltage of net3 is pulled up by net2 (NM7 is not conducting, and the voltage of the enable terminal changes with the output). The Schmitt trigger and the inverter are reversed, so net5 is at a high level, and NM8 is conducting, outputting the reference ground voltage.

[0127] If the voltage of net2 is greater than the turn-on voltage of PM10 and PM11, PM10 and PM11 are turned on, the voltage of net4 increases, NM6 is turned on, and net3 is pulled low. Therefore, the Schmitt trigger and the inverter are reversed respectively, net5 is at a low level, PM12 is turned on, and the voltage at net2 is output.

[0128] The voltage stabilization circuit shown in the embodiment of the present application includes but is not limited to Figure 4 The embodiment shown.

[0129] Based on the same technical concept, the present application also provides a power supply module, which includes the above-mentioned voltage stabilization circuit.

[0130] The specific implementation method and principle of the voltage stabilization circuit have been clearly described in the previous text, and will not be repeated here for the sake of brief description.

[0131] A power module is a power supply that can be mounted directly on a printed circuit board. It can provide power for application-specific integrated circuits (ASICs), digital signal processors (DSPs), microprocessors, memories, field-programmable gate arrays (FPGAs) and other digital or analog loads.

[0132] In one implementation manner, the present application also provides an electronic device, which includes the above-mentioned power module.

[0133] The electronic device may be, for example, a charger, a charging pile, a car or other electronic device.

[0134] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A voltage stabilization circuit, characterized in that: include: A feedback control circuit, an output control circuit and a first switch; The first end of the first switch is configured to be connected to a power source; The feedback control circuit is connected to the enable terminal and the second terminal of the first switch respectively, and the feedback control circuit is used to adjust the enable terminal voltage of the first switch to reduce the output voltage of the first switch when the output voltage of the first switch is greater than a first preset threshold; The input end of the output control circuit is connected to the second end of the first switch, and the output control circuit is used to: output the output voltage of the first switch when the output voltage of the first switch is greater than the second preset threshold; output the reference ground voltage when the voltage outputted from the second end of the first switch is less than the second preset threshold; Wherein, the second preset threshold is less than the first preset threshold; Wherein, the feedback control circuit includes: a mirror circuit and a current generating circuit; The input end of the current generating circuit is connected to the second end of the first switch, and the current generating circuit is used to generate a first current when the output voltage of the first switch is greater than a first preset threshold; The first end of the mirror circuit is connected to the current generating circuit, and the second end of the mirror circuit is connected to the enable end of the first switch. The mirror circuit is used to generate a mirror current of the first current and adjust the enable end voltage of the first switch according to the mirror current.

2. The voltage stabilization circuit according to claim 1, characterized in that: The current generating circuit comprises: A first clamping circuit, the first clamping circuit includes a plurality of transistors connected in series according to a diode connection method, the first ends of the plurality of transistors connected in series are connected to the second end of the first switch, the second ends of the plurality of transistors are grounded, and the third ends of the plurality of transistors are connected to the first end of the mirror circuit; the on-voltage of the first clamping circuit is equal to the first preset threshold.

3. The voltage stabilization circuit according to claim 2, characterized in that: The current generating circuit further includes: a second clamp circuit, wherein a first end of the second clamp circuit is connected to a second end of the first switch, a second end of the second clamp circuit is connected to a first end of a specified transistor in the first clamp circuit, and a second end of the second clamp circuit is not connected to a reference ground and the second end of the first switch; The second clamping circuit includes a plurality of transistors connected in diode connection and connected in series in sequence, and the on-voltage of the second clamping circuit is equal to the first preset threshold.

4. The voltage stabilization circuit according to claim 3, characterized in that: The first clamping circuit comprises: a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series in a diode connection; wherein a first end of the first transistor is connected to a second end of the first switch, a second end of the fourth transistor is grounded, and a third end of the fourth transistor is connected to a first end of the mirror circuit; Accordingly, the second clamping circuit comprises: A fifth transistor, a sixth transistor, and a seventh transistor are connected in series in a diode connection method; wherein the first end of the fifth transistor is connected to the second end of the first switch, and the second end of the seventh transistor is connected to the first end of the third transistor.

5. The voltage stabilization circuit according to claim 1, characterized in that: The mirror circuit comprises: an eighth transistor, a ninth transistor, a tenth transistor, and a first resistor; The second end of the eighth transistor is connected to the current generating circuit, the third end of the eighth transistor is grounded, and the first end of the eighth transistor is respectively connected to the second end and the third end of the ninth transistor; the first end of the ninth transistor is configured to be connected to a power supply; the first end of the tenth transistor is connected to the first end of the ninth transistor, the second end of the tenth transistor is connected to the second end of the ninth transistor, the third end of the tenth transistor is grounded through the first resistor, and the third end of the tenth transistor is connected to the enable end of the first switch.

6. The voltage stabilization circuit according to claim 1, characterized in that: The output control circuit comprises: Indicating voltage circuit, selecting circuit; The first end of the indicating voltage circuit is connected to the second end of the first switch, the second end of the indicating voltage circuit is grounded, and the third end of the indicating voltage circuit is connected to the first end of the selecting circuit; the indicating voltage circuit is used to output a first signal when the output voltage of the first switch is greater than the second preset threshold value; and output a second signal when the output voltage of the first switch is less than or equal to the second preset threshold value; The second end of the selection circuit is connected to the second end of the first switch, and the third end of the selection circuit is grounded. The selection circuit is used to output the output voltage of the first switch when the first signal is received; and output the reference ground voltage when the second signal is received.

7. The voltage stabilization circuit according to claim 6, characterized in that: The output control circuit further includes: a voltage shaping circuit, wherein the third end of the indicating voltage circuit is connected to the first end of the selecting circuit through the voltage shaping circuit; the voltage shaping circuit is used to output a low level signal when the indicating voltage circuit outputs a first signal; and to output a high level signal when the indicating voltage circuit outputs a second signal; Correspondingly, the selection circuit is used to output the output voltage of the first switch when receiving the low-level signal; and output the reference ground voltage when receiving the high-level signal.

8. The voltage stabilization circuit according to claim 7, characterized in that: The voltage shaping circuit comprises: Schmitt triggers and inverters; The second end of the Schmitt trigger is connected to the second end of the first switch, the third end of the Schmitt trigger is grounded, and the fourth end of the Schmitt trigger is connected to the input end of the inverter; the Schmitt trigger is used to output a high level signal when the indication voltage circuit outputs a first signal; and output a low level signal when the indication voltage circuit outputs a second signal; The second end of the inverter is connected to the second end of the first switch, the third end of the inverter is grounded, and the fourth end of the inverter is connected to the first end of the selection circuit.

9. The voltage stabilization circuit according to claim 6, characterized in that: The indicating voltage circuit comprises: A third clamping circuit, a second switch, a second resistor, and a third resistor; The first end of the third clamp circuit is connected to the second end of the first switch, and the second end of the third clamp circuit is grounded through the second resistor; the second end of the third clamp circuit is also connected to the enable end of the second switch; the first end of the second switch is connected to the second end of the first switch through the third resistor, the first end of the second switch is also connected to the first end of the selection circuit, and the second end of the second switch is grounded.

10. The voltage stabilization circuit according to claim 9, characterized in that: The indicating voltage circuit further comprises: A third switch, wherein the first end of the third switch is connected to the first end of the second switch, the second end of the third switch is grounded, and the enable end of the third switch is used to receive a third switch enable signal; wherein, when the voltage stabilization circuit outputs the output voltage of the first switch, the third switch is enabled.

11. The voltage stabilization circuit according to claim 6, characterized in that: The selection circuit comprises: The fourth switch and the fifth switch; The first end of the fourth switch is connected to the second end of the first switch, and the enable end of the fourth switch is connected to the third end of the indication voltage circuit; wherein the fourth switch is a low voltage enabled switch; The enable terminal of the fifth switch is connected to the third terminal of the indication voltage circuit, the second terminal of the fifth switch is connected to the second terminal of the fourth switch, and the first terminal of the fifth switch is grounded; wherein the fifth switch is a high voltage enabled switch.

12. The voltage stabilization circuit according to claim 1, characterized in that: The voltage stabilization circuit further includes: A fourth clamp circuit, wherein a first end of the fourth clamp circuit is configured to be connected to the power supply, and a second end of the fourth clamp circuit is connected to an enable end of the first switch; wherein a turn-on voltage of the fourth clamp circuit is higher than the first preset threshold.

13. The voltage stabilization circuit according to any one of claims 1 to 12, characterized in that: The voltage stabilization circuit further includes: A filter circuit is connected to the output end of the output control circuit.

14. A power module, characterized in that: include: A voltage stabilization circuit as claimed in any one of claims 1 to 13.

15. An electronic device, characterized in that: include: The power module as claimed in claim 14.

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