A flip-chip packaging structure of gallium nitride with low thermal resistance

Abstract

This invention discloses a low thermal resistance gallium nitride flip-chip package structure. The device structure includes an isolation layer, an active layer, a passivation layer, and a dielectric slot array. The two ends of the upper surface of the active layer are connected to a source electrode and a drain electrode, respectively. A gate metal is deposited on the upper surface of the active layer between the source and drain electrodes to form a gate electrode. A passivation layer of a predetermined thickness is deposited on the upper surface of the active layer, except at the locations connecting the source, drain, and gate electrodes, and on the upper surfaces of the source, drain, and gate electrodes. A slot array is disposed within the passivation layer, placed between the gate and drain electrodes. The slot array includes multiple slots arranged in a row, and the slots are filled with dielectric material. By adopting the structure of this invention based on flip-chip packaging, a near 50°C reduction in the device peak temperature is achieved while maintaining the device's output capability, making it widely applicable in various fields.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power devices, and proposes a low thermal resistance gallium nitride flip-chip package structure that reduces junction temperature. Background Technology

[0002] Gallium nitride (GaN), as a third-generation semiconductor material, exhibits enormous application potential in the field of power devices due to its wide bandgap, high breakdown voltage, and high electron mobility. Compared to traditional silicon (Si) devices, GaN power devices have lower on-resistance and higher operating frequencies, giving them significant advantages in high-efficiency and high-density power conversion.

[0003] As the performance of GaN HEMTs continues to improve, the operating temperature of these devices inevitably rises, bringing a series of unavoidable reliability issues. At high temperatures, the electron mobility of GaN HEMTs decreases, hindering electron flow and affecting the device's conductivity and speed. The gate voltage and gate current characteristics of GaN HEMTs drift, causing changes in the device's operating point. Increased resistance leads to increased power consumption. In high-power applications, this can cause thermal problems and performance degradation. Simultaneously, thermal management becomes more difficult at high temperatures, severely impacting the device's heat dissipation efficiency and reliability. Furthermore, GaN HEMT materials are prone to oxidation and degradation at high temperatures, resulting in shortened device lifespan. Thermal stress can also cause material damage and device failure. Especially in specialized applications such as aerospace, aerospace devices typically operate in vacuum or low-pressure environments, rendering traditional heat dissipation methods (such as air cooling) infeasible. This necessitates more complex and efficient thermal management solutions, such as thermoelectric cooling, liquid cooling systems, or highly efficient thermal interface materials, to ensure stable operation of GaN HEMTs at high temperatures. In aerospace environments, GaN HEMT devices also face the challenge of radiation. The combined effects of high temperatures and radiation environments can exacerbate the degradation of device materials and structures. For example, radiation can cause ionization damage and displacement damage, effects that may be more pronounced under high-temperature conditions, leading to deterioration of the device's electrical performance. Addressing the heat generation problem in GaN HEMT devices is essential to meet aerospace-grade reliability requirements.

[0004] In the existing technical solution of low thermal resistance silicon-based gallium nitride microwave and millimeter-wave device material structure and preparation method (Zhang Jincheng, Hao Lu, Liu Zhihong et al. Low thermal resistance silicon-based gallium nitride microwave and millimeter-wave device material structure and preparation method [P]. Shaanxi Province: CN112216739B, 2022-08-12.), the device material structure includes: a silicon substrate layer (1); a high thermal conductivity dielectric layer (2) located on the upper surface of the silicon substrate layer (1) and forming a first patterned interface with the silicon substrate layer (1); a buffer layer (3) located on the upper surface of the high thermal conductivity dielectric layer (2) and forming a second patterned interface with the high thermal conductivity dielectric layer (2); a channel layer (4) located on the upper surface of the buffer layer (3); and a composite barrier layer (5) located on the upper surface of the channel layer (4). The fabrication method of the device material structure includes the following steps: obtaining an initial substrate, wherein the initial substrate is a silicon substrate with a target crystal orientation; sequentially fabricating a nucleation layer and a transition layer on the initial substrate; sequentially fabricating a buffer layer, a channel layer, and a composite barrier layer on the transition layer; flipping the sample and fabricating a transition substrate on the lower surface of the flipped composite barrier layer using wafer bonding technology; removing the initial substrate, the nucleation layer, and the transition layer to expose the buffer layer; etching the surface of the buffer layer to form a second patterned surface; and depositing a high thermal conductivity material on the second patterned surface of the buffer layer to form a high thermal conductivity dielectric layer. A portion of the high thermal conductivity dielectric layer is formed by etching the surface of another silicon substrate layer with a target crystal orientation to form a first patterned surface; the high thermal conductivity material is deposited on the first patterned surface of the silicon substrate layer to form a second portion of the high thermal conductivity dielectric layer; the first portion of the high thermal conductivity dielectric layer is bonded to the second portion of the high thermal conductivity dielectric layer using wafer bonding technology to form the high thermal conductivity dielectric layer, wherein an uneven first patterned interface is formed between the high thermal conductivity dielectric layer and the silicon substrate layer and an uneven second patterned interface is formed between the high thermal conductivity dielectric layer and the buffer layer; the transition substrate is removed to obtain a low thermal resistance silicon-based gallium nitride microwave and millimeter-wave device material structure.

[0005] The existing technology involves fabricating a groove structure on the substrate, which requires pattern transfer and etching before epitaxy. This is not only difficult to implement technically, but also cannot guarantee against defects after epitaxy. Furthermore, this technology is a purely heat-conducting solution that increases the contact area; the dielectric material determines the heat conduction effect, which has significant limitations and cannot achieve substantial cooling.

[0006] Flip chip technology is a common technique in integrated circuit packaging. Its main purpose is to directly invert and connect a chip to a substrate to achieve high-density, high-performance, and reliable electronic devices. In high-performance processors, flip chip technology allows for a tight connection between the processor chip and the heat dissipation device. The short circuit path of the flip chip connection helps reduce thermal resistance in the circuit, and the heat dissipation contact surface is close to the temperature center for more efficient heat conduction, thereby reducing temperature and improving performance. Therefore, flip chip structure chips exhibit higher performance and reliability in high-temperature environments. As the temperature reliability requirements of GaN HEMT power electronic devices become increasingly stringent, devices using a single flip chip structure are insufficient to achieve adequate heat dissipation. Summary of the Invention

[0007] The purpose of this invention is to address the heat generation problem of GaN HEMT devices. Based on existing planar GaN HEMT devices, an improvement is made by proposing a low thermal resistance GaN flip-chip package structure. Without reducing the device's saturation current output capability, multiple low thermal resistance heat dissipation channels are provided by introducing a slot array with high thermal conductivity in the passivation layer, thereby reducing the device's peak temperature by nearly 50°C. At the same time, a highly uniform temperature distribution is obtained, improving the device's temperature stability.

[0008] The objective of this invention is achieved by at least one of the following technical solutions.

[0009] A low thermal resistance gallium nitride flip-chip package structure includes an isolation layer, an active layer, a source electrode, a drain electrode, a gate electrode, a passivation layer, and a dielectric slot array.

[0010] The isolation layer comprises a substrate, a nucleation layer, and a buffer layer stacked sequentially from bottom to top;

[0011] The active layer consists of an intrinsic layer, an insertion layer, and a barrier layer stacked sequentially from bottom to top;

[0012] The active layer is located on the upper surface of the isolation layer, and the width of the isolation layer is greater than that of the active layer, forming a boss structure;

[0013] The two ends of the upper surface of the active layer are connected to the source electrode and the drain electrode, respectively; gate metal is deposited on the upper surface of the active layer between the source electrode and the drain electrode to form the gate electrode;

[0014] Except for the locations where the source electrode, drain electrode, and gate electrode connect, as well as the upper surfaces of the source electrode, drain electrode, and gate electrode, a passivation layer of a specified thickness is deposited on the upper surface of the active layer to protect the active layer.

[0015] A slot array is provided within the passivation layer. The slot array is placed in the passivation layer between the gate electrode and the drain electrode. The slot array includes multiple slots arranged in a row, and the slots in the slot array are filled with dielectric material.

[0016] Furthermore, the substrate is a silicon carbide substrate or a silicon substrate.

[0017] Furthermore, the intrinsic layer and the barrier layer in the active layer form a heterojunction with polarization effect, including gallium nitride / aluminum gallium nitride.

[0018] Furthermore, using reactive ion etching or inductively coupled plasma etching equipment, fluorine-based plasma is employed to form slot arrays.

[0019] Furthermore, the slot array is located within the passivation layer, and its area accounts for 1% to 99% of the passivation layer area between the gate electrode and the drain electrode.

[0020] Furthermore, the structural pattern of the slots in the slot array can be any shape or combination thereof, including rectangular.

[0021] Furthermore, the spacing between the slots in the slot array may be different.

[0022] Furthermore, the depth of each slot in the slot array may be different.

[0023] Furthermore, the filling material of the slots in the slot array is a dielectric material with low thermal resistance and polarization effect, including aluminum nitride or aluminum gallium nitride.

[0024] Furthermore, the source and drain electrodes are multilayer metal stacks, consisting of Ti / Al / Ni / Au from bottom to top, with thicknesses of 20 / 100 / 10 / 100 nm, respectively; the gate electrode is a multilayer metal stack, consisting of Ni / Au from bottom to top, with thicknesses of 50 / 200 nm.

[0025] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0026] 1. This invention achieves a device with high temperature reliability by introducing a dielectric slot array with low thermal resistance. Under the structure of the invention, the peak temperature of the device is reduced and the self-heating effect is greatly improved.

[0027] 2. When introducing the slot array, keeping it away from the active layer not only avoids damage to it, but also improves its saturation current capability.

[0028] 3. In terms of process implementation, compared with conventional HEMT devices, only one more photolithography, etching and deposition process is required for the passivation layer, making the process steps simple. Attached Figure Description

[0029] Figure 1 This is a structural diagram of the isolation layer in an embodiment of the present invention;

[0030] Figure 2 This is a diagram of the active layer structure in an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of a conventional HEMT device in an embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of a low thermal resistance gallium nitride flip package structure in an embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of a low thermal resistance gallium nitride flip package structure in an embodiment of the present invention;

[0034] Figure 6 This is a schematic diagram of a low thermal resistance gallium nitride flip package structure in an embodiment of the present invention;

[0035] Figure 7 This is a temperature distribution diagram along the gate direction of a patented HEMT device with a low thermal resistance gallium nitride flip-chip package structure in different media and a conventional HEMT device in an embodiment of the present invention.

[0036] Figure 8 This is a comparison of the output curves of the patented HEMT device with low thermal resistance gallium nitride flip-chip package structure and conventional HEMT device under gate voltage of 0.5V and drain voltage of 20V in the embodiments of the present invention. Detailed Implementation

[0037] The specific implementation of the present invention will be further described below with reference to the accompanying drawings and embodiments. However, the implementation and protection of the present invention are not limited thereto. It should be noted that any processes or process parameters that are not described in particular below are those that can be implemented by those skilled in the art with reference to the prior art.

[0038] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “described,” and “the” as used in one or more embodiments of this specification and in the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0039] Comparative example:

[0040] Conventional HEMT devices such as Figure 3 As shown, it includes an isolation layer 1, an active layer 2, a source electrode 3, a drain electrode 4, a gate electrode 5, a passivation layer 6, and a dielectric slot array 7.

[0041] like Figure 1 As shown, the isolation layer 1 includes a substrate 01, a nucleation layer 02 and a buffer layer 03 stacked sequentially from bottom to top;

[0042] like Figure 2 As shown, the active layer 2 includes an intrinsic layer 04, an insertion layer 05, and a barrier layer 06 stacked sequentially from bottom to top;

[0043] The active layer 2 is located on the upper surface of the isolation layer 1. The width of the isolation layer 1 is greater than that of the active layer 2, forming a boss structure.

[0044] The two ends of the upper surface of the active layer 2 are connected to the source electrode 3 and the drain electrode 4, respectively; gate metal is deposited on the upper surface of the active layer 2 between the source electrode 3 and the drain electrode 4 to form the gate electrode 5;

[0045] Except for the positions where the source electrode 3, drain electrode 4 and gate electrode 5 are connected, and the upper surfaces of the source electrode 3, drain electrode 4 and gate electrode 5, a passivation layer 6 of a set thickness is deposited on the upper surface of the active layer 2 to protect the active layer 2.

[0046] Example:

[0047] A low thermal resistance gallium nitride flip-chip package structure, in one embodiment, such as Figure 4 As shown, it includes an isolation layer 1, an active layer 2, a source electrode 3, a drain electrode 4, a gate electrode 5, a passivation layer 6, and a dielectric slot array 7.

[0048] like Figure 1 As shown, the isolation layer 1 includes a substrate 01, a nucleation layer 02 and a buffer layer 03 stacked sequentially from bottom to top;

[0049] like Figure 2 As shown, the active layer 2 includes an intrinsic layer 04, an insertion layer 05, and a barrier layer 06 stacked sequentially from bottom to top;

[0050] The active layer 2 is located on the upper surface of the isolation layer 1. The width of the isolation layer 1 is greater than that of the active layer 2, forming a boss structure.

[0051] The two ends of the upper surface of the active layer 2 are connected to the source electrode 3 and the drain electrode 4, respectively; gate metal is deposited on the upper surface of the active layer 2 between the source electrode 3 and the drain electrode 4 to form the gate electrode 5;

[0052] Except for the positions where the source electrode 3, drain electrode 4 and gate electrode 5 are connected, and the upper surfaces of the source electrode 3, drain electrode 4 and gate electrode 5, a passivation layer 6 of a set thickness is deposited on the upper surface of the active layer 2 to protect the active layer 2.

[0053] A slot array 7 is provided in the passivation layer 6. The slot array 7 is placed in the passivation layer 6 between the gate electrode 5 and the drain electrode 4. The slots in the slot array 7 are filled with dielectric material.

[0054] In one embodiment, a low thermal resistance gallium nitride flip-chip package structure, such as Figure 5 As shown, in Figure 4 Based on this, the spacing of the slot array and the area of ​​the buffer layer 6 interface it occupies are changed. The number of slots is determined according to the actual application. The height of the slot from the surface of the buffer layer 6 gradually increases, decreases, or remains the same along the direction from the gate electrode 5 to the drain electrode 4.

[0055] In one embodiment, a low thermal resistance gallium nitride flip-chip package structure, such as Figure 6 As shown, in Figure 4 Based on this, the slot array 7 with a rectangular slot cross-section is replaced with a slot array 7 with a triangular slot cross-section. The slot cross-section includes, but is not limited to, rectangles, triangles, trapezoids and other shapes.

[0056] In one embodiment, the source electrode 3 and the drain electrode 4 are multilayer metal stacks, which are Ti / Al / Ni / Au from bottom to top, with thicknesses of 20 / 100 / 10 / 100nm respectively; the gate electrode 5 is a multilayer metal stack, which is Ni / Au from bottom to top, with thicknesses of 50 / 200nm.

[0057] In the Silvaco simulation example Figure 7 This diagram shows the temperature distribution along the gate direction of a HEMT device employing the low thermal resistance gallium nitride flip-chip package structure of this invention and a conventional HEMT device. Due to the gate length being set to 2 micrometers, all devices exhibit a temperature peak near the drain side of the gate. The lattice temperature distribution diagram shows that the peak temperature of the conventional HEMT device is 423.7 K, indicating an excessively high lattice temperature. Strong lattice scattering degrades device parameters and severely impacts performance. In contrast, the invented HEMT device, using a high thermal conductivity material as the dielectric, leverages the high thermal conductivity of the dielectric slot and increases the heat dissipation area to rapidly dissipate heat accumulated near the gate. Compared to the conventional structure, the peak temperature under the patented structure is only 381.7 K, achieving a temperature reduction of nearly 50 K. This significantly alleviates the self-heating effect and greatly improves the device's temperature reliability. Furthermore, the invented HEMT device using a polarization effect material as the dielectric exhibits a relatively uniform temperature near the array. By introducing a dielectric material with a polarization effect, a second temperature center point appears in the device's temperature distribution, both approaching 372.0 K, resulting in a uniform temperature distribution near the array. With this dielectric material, the peak temperature is further reduced, further improving the device's temperature reliability.

[0058] In the Silvaco simulation example Figure 8This chart compares the output curves of HEMT devices with different low thermal resistance gallium nitride flip-chip packages and conventional HEMT devices after drain current saturation. With a gate voltage of 0.5V and a drain voltage ranging from 0V to 20V, the patented HEMT device with the low thermal resistance gallium nitride flip-chip package exhibits a slightly higher saturation current than the conventional structure. The conventional HEMT device deteriorates significantly as the gate voltage continues to increase, and the gap between the conventional structure and the structure of this invention widens considerably.

[0059] The above embodiments are merely preferred examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, can make various modifications and changes in form and detail according to the method of the present invention without departing from the principles and scope of the present invention. However, these modifications and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims

1. A low thermal resistance gallium nitride flip-chip package structure, characterized in that, It includes an isolation layer (1), an active layer (2), a source electrode (3), a drain electrode (4), a gate electrode (5), a passivation layer (6), and a dielectric slot array (7). The isolation layer (1) includes a substrate (01), a nucleation layer (02) and a buffer layer (03) stacked sequentially from bottom to top; The active layer (2) includes an intrinsic layer (04), an insertion layer (05) and a barrier layer (06) stacked sequentially from bottom to top. The active layer (2) is located on the upper surface of the isolation layer (1), and the width of the isolation layer (1) is greater than that of the active layer (2), forming a boss structure; The two ends of the upper surface of the active layer (2) are connected to the source electrode (3) and the drain electrode (4), respectively; gate metal is deposited on the upper surface of the active layer (2) between the source electrode (3) and the drain electrode (4) to form the gate electrode (5). Except for the positions where the source electrode (3), drain electrode (4) and gate electrode (5) are connected, and the upper surfaces of the source electrode (3), drain electrode (4) and gate electrode (5) are also deposited, a passivation layer (6) of a set thickness is deposited on the upper surface of the active layer (2) to protect the active layer (2). The passivation layer (6) contains the dielectric slot array (7), which is placed in the passivation layer (6) between the gate electrode (5) and the drain electrode (4). The dielectric slot array (7) includes multiple slots arranged in a row. The cross-section of the slots is rectangular. The spacing between the slots in the dielectric slot array (7) is different, and the depth of each slot in the dielectric slot array (7) is different. The filling material of the slots in the dielectric slot array (7) is a dielectric material with low thermal resistance and polarization effect, including aluminum gallium nitride.

2. The low thermal resistance gallium nitride flip-chip package structure according to claim 1, characterized in that, The substrate (01) is a silicon carbide substrate or a silicon substrate.

3. The low thermal resistance gallium nitride flip-chip package structure according to claim 1, characterized in that, In the active layer (2), the intrinsic layer (04) and the barrier layer (06) form a heterojunction with polarization effect, including gallium nitride / aluminum gallium nitride.

4. The low thermal resistance gallium nitride flip-chip package structure according to claim 1, characterized in that, Using reactive ion etching or inductively coupled plasma etching equipment, a fluorine-based plasma is used to form a slot array (7).

5. The low thermal resistance gallium nitride flip-chip package structure according to claim 1, characterized in that, The slot array (7) is located in the passivation layer (6), and its area accounts for 1% to 99% of the area of ​​the passivation layer (6) between the gate electrode (5) and the drain electrode (4).

6. The low thermal resistance gallium nitride flip-chip package structure according to claim 1, characterized in that, The source electrode (3) and drain electrode (4) are multilayer metal stacks, which are Ti / Al / Ni / Au from bottom to top; the gate electrode (5) is multilayer metal stacks, which are Ni / Au from bottom to top.

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