Mask and correction method thereof and electronic equipment
By modifying the pattern of the mask and increasing the area or width of the connecting pattern, the problem of connecting lines in semiconductor device manufacturing is solved, the yield and process window are improved, and the continuity is achieved.
Patent Information
- Application Number
- CN202411089933.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2044-08-09
AI Technical Summary
In semiconductor manufacturing processes, due to process deviations in lithography and etching steps, the smaller connecting pattern cannot be fully opened, resulting in broken connections of semiconductor devices, affecting yield.
By modifying the original pattern of the mask, increasing the area or width of the small connecting pattern of the feature size, and using an outward-expanding method to ensure that the connecting pattern can be fully opened during the lithography process and reducing the risk of disconnection.
It effectively improves the continuity and yield of semiconductor devices, reduces the occurrence of line breakage, and increases the size of the process window.
Smart Images
Figure CN118625591B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a mask and a correction method thereof and electronic equipment. Background Art
[0002] In the semiconductor manufacturing process, photolithography and etching are both key steps in patterning. Photolithography is used to transfer the mask pattern to the resist layer to form a mask pattern, and then etching is used to transfer the mask pattern to the silicon wafer to form the structure of the semiconductor device.
[0003] The semiconductor device is, for example, a CMOS (Complementary Metal Oxide Semiconductor) device. In the manufacturing process of the CMOS device, a "Damascene process" is used to form a connection, including forming a connection hole in the intermediate dielectric layer of the semiconductor device through the patterning step described above and subsequently filling the connection hole with a conductive material to form a connection channel for connecting the wiring layer and the active area, and forming a wiring groove in the wiring layer of the semiconductor device through the patterning step described above and subsequently filling the wiring groove with a conductive material to form a wiring in the wiring layer specifically for connecting the above-mentioned connection channel.
[0004] However, due to process deviations in the above-mentioned patterning step, connection holes or wiring grooves formed by some smaller wiring patterns on the mask used in the patterning step are not fully opened, resulting in disconnection of connection channels or wirings formed subsequently, which adversely affects the yield of semiconductor devices. Summary of the invention
[0005] In view of the above problems, the purpose of the present application is to provide a mask and a correction method and electronic equipment thereof, so as to modify the original pattern of the mask to expand the process window, thereby improving the yield of semiconductor devices.
[0006] According to a first aspect of the present application, a mask correction method is provided, wherein the mask is formed with a connection pattern, and the correction method comprises:
[0007] Obtaining the original pattern of the mask;
[0008] Modifying the shape of the target wiring pattern in the original pattern of the mask to increase the feature size of the target wiring pattern to generate a revised pattern of the mask;
[0009] The target connection pattern is a connection pattern whose characteristic size is smaller than a threshold value, and the characteristic size affects the continuity of the connection lines formed by the connection pattern.
[0010] Optionally, the characteristic size includes an area of a wiring pattern, the threshold includes an area threshold, and modifying the shape of a target wiring pattern in an original pattern of the mask includes:
[0011] Selecting a target line pattern whose area is smaller than the area threshold in the original pattern;
[0012] The selected target connection pattern is processed to expand outward so as to increase the area of the target connection pattern.
[0013] Optionally, the outward edge expansion process includes:
[0014] Determining whether there is a first sub-boundary in the boundary of the target connection line pattern whose spacing with an adjacent connection line pattern is less than a preset value;
[0015] In the case where the first sub-boundary exists, the sub-boundaries of the boundary of the target connection pattern except the first sub-boundary are expanded.
[0016] Optionally, the outward edge expansion process includes:
[0017] Expanding the boundary of the determined target connection pattern to obtain an intermediate pattern;
[0018] Determine whether there is a second sub-boundary in the boundary of the middle pattern that is expanded outward and has a spacing with the adjacent connection pattern that is less than a preset value;
[0019] In the case where the second sub-boundary exists, the expansion process of the second sub-boundary is canceled.
[0020] Optionally, the outward expansion process is performed at least once, and the outward expansion process is performed at least once in a decreasing order of outward expansion distances.
[0021] Optionally, the characteristic size includes a width of a wiring pattern, the threshold includes a first width threshold, and modifying the shape of a target wiring pattern in an original pattern of the mask includes:
[0022] Selecting a target line pattern from the original pattern, the target line pattern having a spacing with an adjacent line pattern less than a spacing threshold, a width less than the first width threshold, and an adjacent line pattern with a width greater than a second width threshold, wherein the second width threshold is greater than the first width threshold;
[0023] The width of the selected target connection line pattern is increased and the width of the adjacent connection line pattern is reduced.
[0024] Optionally, a first side of the target wiring pattern is adjacent to a second side of an adjacent wiring pattern, and the first side is a side defining a width of the target wiring pattern, and the second side is a side defining a width of an adjacent wiring pattern of the target wiring pattern;
[0025] Increasing the width of the determined target line pattern includes: moving the first side edge by a first distance in a direction of an adjacent line pattern close to the target line pattern;
[0026] Reducing the width of the adjacent connection pattern includes: moving the second side edge by a second distance in a direction away from the target connection pattern, and the second distance is equal to the first distance.
[0027] Optionally, the line pattern in the original pattern is in a rectangular shape, and the target line pattern is a line pattern in the original pattern in a rectangular shape;
[0028] Alternatively, the connection pattern in the original pattern is in a non-rectangular shape but is composed of a plurality of rectangular patterns, and the target connection pattern is the rectangular pattern.
[0029] According to a second aspect of the present application, a mask is provided, wherein a connection pattern is formed on the mask, and the connection pattern is a pattern corrected by any one of the mask correction methods described in the first aspect.
[0030] According to a third aspect of the present application, an electronic device is provided, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, any one of the mask correction methods described in the first aspect is implemented.
[0031] The unexpected technical effects of this application are:
[0032] According to the mask correction method of the embodiment of the present application, the shape of the target wiring pattern is modified in the original pattern of the mask to increase the characteristic size of the target wiring pattern to generate a corrected pattern of the mask, wherein the target wiring pattern is a wiring pattern whose characteristic size is smaller than a threshold value, and the characteristic size affects the continuity of the wiring formed by the wiring pattern. Therefore, the wiring formed based on the corrected pattern of the mask can be improved in terms of continuity, thereby reducing the risk of broken wires in semiconductor devices and improving the yield of semiconductor devices.
[0033] Furthermore, the mask correction method selects different correction strategies according to the characteristic size of the connection pattern.
[0034] In the case where the characteristic size includes the area of the wiring pattern, the threshold includes an area threshold, and a target wiring pattern whose area is smaller than the area threshold is selected from the original pattern, and the selected target wiring pattern is expanded outward to change its shape so as to increase the area of the target wiring pattern. This can effectively avoid the risk of wire breakage caused by the inability of a wiring pattern with a smaller area to form a fully opened wiring groove; and because the area increase is not limited to relying on one side of the target wiring pattern, it is beneficial to meet the area increase requirement without causing the risk of adjacent wiring bridging, thereby improving the yield of semiconductor devices.
[0035] In the case where the characteristic size includes the width of the connection pattern, the threshold includes a first width threshold, and a target connection pattern whose spacing with adjacent connection patterns is less than the spacing threshold and whose width is less than the first width threshold and whose adjacent connection pattern width is greater than the second width threshold is selected in the original pattern, and the shape is changed by increasing the width of the target connection pattern while the width of its adjacent connection pattern is also reduced, so that not only the width of the target connection pattern is increased, but also the width difference between the target connection pattern and the adjacent connection pattern is reduced, so that the target connection pattern is less affected by the adjacent connection pattern during the lithography process, so that the corrected pattern of the target connection pattern can form a basically fully opened connection groove, effectively avoiding the risk of disconnection of the small connection pattern formed when the spacing between the small connection pattern and the large connection pattern is close, thereby improving the yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:
[0037] Figure 1 A schematic cross-sectional view of a semiconductor device is shown;
[0038] Figure 2 A schematic cross-sectional view showing a patterning process for forming a connection hole in a semiconductor device manufacturing process;
[0039] Figure 3 A schematic cross-sectional view showing a patterning process for forming a wiring layer in a semiconductor device manufacturing process;
[0040] Figure 4 A flowchart showing a mask correction method according to an embodiment of the present application is shown;
[0041] Figure 5 A cross-sectional view showing a semiconductor device manufactured based on a mask original pattern;
[0042] Figure 6 A cross-sectional view of a semiconductor device manufactured based on another mask original pattern is shown;
[0043] Figure 7a An original pattern of a mask is shown;
[0044] Figure 7b A schematic diagram showing a first outward expansion process to determine a first update pattern boundary according to an embodiment of the present application;
[0045] Figure 7c A schematic diagram showing a method of performing a second outward expansion process to determine the boundary of an intermediate pattern according to an embodiment of the present application;
[0046] Figure 7d A schematic diagram showing a correction pattern determined by performing a third outward edge expansion process according to an embodiment of the present application;
[0047] Figure 7e A schematic diagram showing a correction pattern generated according to an embodiment of the present application;
[0048] Figure 8a Another original pattern of a mask is shown;
[0049] Figure 8b A schematic diagram showing determination of a new boundary of a target connection pattern and a new boundary of an adjacent connection pattern according to an embodiment of the present application is shown;
[0050] Figure 8c A schematic diagram showing another correction pattern generated according to an embodiment of the present application is shown.
[0051] Description of reference numerals: 100-semiconductor device; 101-semiconductor layer; 102-shallow trench structure; 103-source region; 104-drain region; 105-gate dielectric layer; 106-gate conductor; 107-interlayer dielectric layer; 108-wiring layer; 111-first connection channel; 112-second connection channel; 121-first wiring; 122-second wiring; 131-first connection hole; 132-second connection hole; 141-first wiring groove; 142-second wiring groove; 10-connection hole mask; 11-hole light shielding area; 12-first hole light-transmitting area; 13-second hole light-transmitting area; 20-wiring groove mask; 21-groove light-shielding area; 22-first groove light-transmitting area; 23-second groove light-transmitting area; 210-first connection pattern; 210'-first updated pattern; 210''-second updated pattern; 210'''-first revised pattern; 220-first adjacent connection pattern; 230-second adjacent connection pattern; 310-second connection pattern; 310'-second revised pattern; 320-third connection pattern; 320'-third revised pattern. DETAILED DESCRIPTION
[0052] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.
[0053] This application may be presented in a variety of forms, some examples of which are described below.
[0054] Figure 1 A schematic cross-sectional view of a semiconductor device is shown. The semiconductor device 100 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but is not limited thereto. In a preferred embodiment, the semiconductor device is, for example, an N-type MOSFET. For the sake of clarity, the interconnection structure and the main structure of the semiconductor device 100 are separated and shown in the figure along the vertical direction.
[0055] like Figure 1 As shown, the semiconductor device 100 includes a semiconductor layer 101 and a shallow trench structure 102 located in the semiconductor layer 101. The semiconductor layer 101 can be composed of any one selected from a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. For example, for an N-type MOSFET, the semiconductor layer 101 is P-type doped; for a P-type MOSFET, the semiconductor layer 101 is N-type doped. The shallow trench structure 102 extends downward from the surface of the semiconductor layer 101 to form an isolation structure surrounding the active area of the semiconductor device 100, which is used to separate the semiconductor device 100 from adjacent semiconductor devices. The shallow trench structure 102 can be composed of any one selected from silicon oxide, silicon nitride, and silicon oxynitride.
[0056] Furthermore, the semiconductor device 100 includes a source region 103 and a drain region 104 located in the semiconductor layer 101, and a gate stack located above the semiconductor layer 101. The source region 103 and the drain region 104 are doped regions in the semiconductor layer 101. For example, for an N-type MOSFET, the source region 103 and the drain region 104 are N-type doped; for a P-type MOSFET, the source region 103 and the drain region 104 are P-type doped. The gate stack of the semiconductor device 100 includes a gate dielectric layer 105 and a gate conductor 106, and the gate dielectric layer 105 is sandwiched between the semiconductor layer 101 and the gate conductor 106. The gate dielectric layer 105 is, for example, composed of silicon oxide, and the gate conductor 106 is, for example, composed of doped polysilicon.
[0057] Furthermore, the semiconductor device 100 includes an interlayer dielectric layer 107 located above the gate stack and the source region 103 and the drain region 104, a wiring layer 108 located above the interlayer dielectric layer 107, and an interconnection structure connected to the gate stack and the source region 103 and the drain region 104. The interlayer dielectric layer 107 and the wiring layer 108 are composed of, for example, silicon oxide, the interlayer dielectric layer 107 is used to isolate the active region of the semiconductor device 100 from the wiring layer 108, and the wiring layer 108 is used to isolate different wirings formed therein. The interconnection structure of the semiconductor device 100 includes a first connection channel 111 and a second connection channel 112 penetrating the interlayer dielectric layer 107, and wirings located in the wiring layer 108. For example, the wirings in the wiring layer 108 include a first wiring 121 connected to the first connection channel 111 and a second wiring 122 connected to the second connection channel 112. The first connection channels 111 and the second connection channels 112 , and the first wirings 121 and the second wirings 122 may be made of conductive materials, for example, metals such as copper and aluminum.
[0058] The manufacturing process of the semiconductor device 100 includes a front-end process and a back-end process, wherein the front-end process includes thin film deposition, ion implantation, and patterning, which are mainly used to form a source region 103, a drain region 104, and a gate stack of the semiconductor device 100; the back-end process includes thin film deposition and patterning, which are mainly used to form an interconnection structure of the semiconductor device 100, including forming a first connection channel 111 and a second connection channel 112, as well as a first wiring 121 and a second wiring 122 of the semiconductor device 100.
[0059] The mask correction method according to the embodiment of the present application is applied to the mask used in the patterning process of the back-end process. In the back-end process, the "Damascene process" is used to form the first connection channel 111 and the second connection channel 112, including forming the first connection hole 131 and the second connection hole 132 penetrating the interlayer dielectric layer 107 in the above-mentioned patterning process, and subsequently filling the first connection hole 131 and the second connection hole 132 with a conductive material to form the first connection channel 111 and the second connection channel 112. In the subsequent process, the "Damascene process" is also used to form the first wiring 121 and the second wiring 122, including forming the first wiring groove 141 and the second wiring groove 142 in the wiring layer 108 in the above-mentioned patterning process, and subsequently filling the first wiring groove 141 and the second wiring groove 142 with a conductive material to form the first wiring 121 and the second wiring 122. The patterning process of the back-end process of the semiconductor device 100 will be described in detail below.
[0060] Figure 2A schematic cross-sectional view showing a patterning process for forming a connection hole in a semiconductor device manufacturing process. In a semiconductor process, the photolithography step and the etching step for patterning are independent of each other. Figure 2 The sequential steps of lithography and etching are combined together to clearly illustrate the principle of the patterning process for forming the connection holes.
[0061] The interlayer dielectric layer 107 of the semiconductor device 100 covers the source region 103, the drain region 104, and the gate stack. A resist layer PR1 is formed on the interlayer dielectric layer 107, and a contact hole mask 10 is disposed above the resist layer PR1.
[0062] According to the reaction mode of the resist layer PR1, it can be divided into positive resist and negative resist. The exposed part of the positive resist is removed during development to form an opening area, and the exposed part of the negative resist is retained during development to form a shielding area. It can be understood that in the case of using a negative resist, the pattern of the mask for forming the connection hole is a complementary pattern using a positive resist.
[0063] In this embodiment, a positive resist is used as an example for description. Figure 2 The connection hole mask 10 includes a hole light shielding region 11 and a first hole light transmitting region 12 and a second hole light transmitting region 13. In the photolithography step, the resist layer PR1 is exposed through the connection hole mask 10, and the exposed portion of the resist layer PR1 is removed during development, thereby forming an opening region corresponding to the first hole light transmitting region 12 and the second hole light transmitting region 13 of the connection hole mask 10 in the resist layer PR1. In the etching step, the resist layer PR1 is used as a mask to remove the exposed portion of the interlayer dielectric layer 107 through the opening region of the resist layer PR1. Since the selective etching of the etchant stops at the source region 103 and the drain region 104 of the semiconductor device 100 and the surface of the gate conductor 106, the first connection hole 131 and the second connection hole 132 corresponding to the first hole light transmitting region 12 and the second hole light transmitting region 13 of the connection hole mask 10 are formed.
[0064] Figure 3 A schematic cross-sectional view showing a patterning process for forming wiring in a semiconductor device manufacturing process. Figure 2 Similar, in Figure 3 The sequential steps of lithography and etching are combined together to clearly illustrate the principles of the patterning process to form wiring.
[0065] The wiring layer 108 of the semiconductor device 100 covers the interlayer dielectric layer 107. A resist layer PR2 is formed on the wiring layer, and a wiring groove mask 20 is disposed above the resist layer PR2.
[0066] In this embodiment, a positive resist is used as an example for description. Figure 3 The wiring groove mask 20 includes a groove light shielding area 21 and a first groove light-transmitting area 22 and a second groove light-transmitting area 23. In the photolithography step, the resist layer PR2 is exposed through the wiring groove mask 20, and the exposed portion of the resist layer PR2 is removed during development, thereby forming an opening area corresponding to the first groove light-transmitting area 22 and the second groove light-transmitting area 23 of the wiring groove mask 20 in the resist layer PR2. In the etching step, the resist layer PR2 is used as a mask to remove the exposed portion of the wiring layer through the opening area of the resist layer PR2. Since the selective etching of the etchant stops at the surface of the interlayer dielectric layer 107 and the first connection channel 111 and the second connection channel 112, the first wiring groove 141 and the second wiring groove 142 corresponding to the first groove light-transmitting area 22 and the second groove light-transmitting area 23 of the wiring groove mask 20 are formed.
[0067] In the embodiments of the present application, the connection channels and wirings in the semiconductor device are collectively referred to as wirings, the connection holes formed in the process of forming the connection channels and the wiring grooves formed in the process of forming the wirings are collectively referred to as wiring grooves, and the patterns for forming the connection holes and the patterns for forming the wiring grooves set on the mask are collectively referred to as wiring patterns. However, it should be understood that the wiring patterns described in the embodiments of the present application are not limited to the patterns for forming the connection holes and the patterns for forming the wiring grooves, and can also be the patterns for forming the wiring grooves required for manufacturing other wiring structures of various semiconductor devices.
[0068] At present, the mask used in the patterning process of the 55nm process has some small wiring patterns. Due to the process deviation in the patterning process, the wiring grooves formed by these small wiring patterns cannot be fully opened, which affects the size of the product process window, resulting in the phenomenon of disconnection of the wiring formed later, causing the failure of the semiconductor device. The original mask pattern generated by the existing mask design tool does not correct the small wiring patterns that cause disconnection, so the yield of the semiconductor device is low.
[0069] Therefore, an embodiment of the present application provides a mask correction method, wherein the mask is formed with a connection pattern. Figure 4 A flow chart of the correction method is shown. Figure 4 , the correction method comprises:
[0070] Step S110, obtaining the original pattern of the mask;
[0071] Step S120 , modifying the shape of the target connection pattern in the original pattern of the mask to increase the feature size of the target connection pattern to generate a modified pattern of the mask.
[0072] Specifically, the target wiring pattern is a wiring pattern having a characteristic size less than a threshold value in step S120, and the characteristic size affects the continuity of the wiring formed by the wiring pattern. Therefore, when the shape of the target wiring pattern is modified to increase the characteristic size of the target wiring pattern, the wiring formed based on the mask correction pattern can be improved in continuity, thereby reducing the risk of broken wires in the semiconductor device and improving the yield of the semiconductor device.
[0073] In practice, the connection patterns that can lead to disconnected connections can be roughly divided into two categories. The first category is a connection pattern with a smaller area, such as Figure 5 Referring to the first wiring pattern 210 shown in FIG. Figure 5 The first wiring pattern 210 forms a wiring groove within the black dotted circle indicated by the arrow. The formed wiring groove is gray, indicating that it is not fully opened. The wiring groove is almost missing, so there is a risk of disconnection. Figure 5 There are multiple such nearly missing wiring slots in each of the two black dotted rectangles in . The second type is a small wiring pattern that is close to the large wiring pattern, such as Figure 6 The second wiring pattern 310 is shown. Figure 6 The second wiring pattern 310 has an adjacent third wiring pattern 320 with a closer spacing and is a smaller wiring pattern than the third wiring pattern 320. The second wiring pattern 310 and the third wiring pattern 320 form two wiring grooves of different sizes in the black dotted rectangular frame, wherein the second wiring pattern 310 forms a wiring groove in the black dotted circle indicated by the arrow, and because the exposure during photolithography is affected by the larger third wiring pattern 320 nearby, the wiring groove in the black dotted circle formed by the second wiring pattern 310 is discontinuous, and there is a risk of disconnection.
[0074] For the first type of wiring pattern mentioned above, the characteristic size in step S120 includes the area of the wiring pattern, and the threshold value mentioned above includes the area threshold value correspondingly. Step S120, modifying the shape of the target wiring pattern in the original pattern of the mask, includes: selecting a target wiring pattern whose area is smaller than the area threshold value in the original pattern; and performing an outward expansion process on the selected target wiring pattern to increase the area of the target wiring pattern. Among them, the area threshold value is the boundary value of whether the wiring groove formed by the wiring pattern is open, so the target wiring pattern whose area is smaller than the area threshold value needs to be corrected and the area is increased. By increasing the area of the target wiring pattern by outward expansion process, the risk of wire breakage caused by the inability of the wiring pattern with a smaller area to form a fully open wiring groove can be effectively avoided; and because it is not limited to relying on one side of the target wiring pattern to achieve area increase, it is beneficial to meet the area increase requirement without causing the risk of adjacent wiring bridging, thereby improving the yield of semiconductor devices.
[0075] Figures 7a to 7e Show Figure 5 The first connection pattern 210 shown is a schematic diagram of a process of obtaining a first correction pattern 210''' by performing multiple outward expansion processing as the target connection pattern, wherein Figure 7a In the original pattern of the mask shown, the first connecting line pattern 210 has a first adjacent connecting line pattern 220 and a second adjacent connecting line pattern 230, the extension line of the sub-boundary B2B3 of the first adjacent connecting line pattern 220 and the sub-boundary A1A5 of the first connecting line pattern 210 are compared to point A6, and the extension line of the sub-boundary C2C3 of the second adjacent connecting line pattern 230 and the sub-boundary A2A4 of the first connecting line pattern 210 are compared to point A3.
[0076] Figure 7a , the spacing between the first connection pattern 210 and adjacent connection patterns includes: a spacing X1 with a subboundary B1B2 of the first adjacent connection pattern 220 , a spacing X2 with a subboundary C1C2 of the second adjacent connection pattern 230 , and a spacing X3 with a subboundary B3B4 of the first adjacent connection pattern 220 .
[0077] Figure 7b to Figure 7c The process of obtaining the first updated pattern 210' by the first outward expansion process of the first connection pattern 210 is illustrated. In the first outward expansion process, the above-mentioned spacings X1, X2 and X3 are first compared with the preset value L0 to determine that there is a first sub-boundary A5A6 in the boundary of the first connection pattern 210 whose spacing with the first adjacent connection pattern 220 is less than the preset value L0. Then, as Figure 7b As shown in FIG. 1 , the sub-boundaries A1A2, A2A4, A4A5 and A6A1 of the boundary of the first connection pattern 210 except the first sub-boundary A5A6 are expanded to obtain the following Figure 7b The new boundary of the first connection pattern 210 is shown in the dotted line frame. Then, the boundary of the first connection pattern 210 is expanded to Figure 7b The new boundary shown in the midpoint line box is obtained as Figure 7c A first update pattern 210' is shown. Figure 7c The first update pattern 210 ′ has vertices A7 ′ and A6 ′ along the extension line of the side B2B3 of the first adjacent connection pattern 220 . That is, the first update pattern 210 ′ has one more vertex than the first connection pattern 210 because the first sub-boundary A5A6 does not extend outward.
[0078] The distance between the first updated pattern 210' and the adjacent connection pattern is as follows: Figure 7bThe midpoint line frame includes: a spacing X1' with the sub-boundary B1B2 of the first adjacent wiring pattern 220, a spacing X2' with the sub-boundary C1C2 of the second adjacent wiring pattern 230, and a spacing X3' with the sub-boundary B3B4 of the first adjacent wiring pattern 220. It should be understood that the spacing X1' is smaller than the spacing X1, the spacing X2' is smaller than the spacing X2, and the spacing X3' is equal to the spacing X3.
[0079] During the first outward expansion process, since the first sub-boundary A5A6 does not expand outward under the limit of the preset value L0, the risk of bridging the connection formed by the modified pattern of the first connection pattern 210 due to being too close to the connection formed by the first adjacent connection pattern 220 can be avoided.
[0080] Figure 7c to Figure 7d The process of obtaining the second updated pattern 210'' by the second outward expansion process of the first updated pattern 210' is illustrated. In the second outward expansion process, the above-mentioned spacings X1', X2' and X3' are first compared with the preset value L0 to determine that there is a first sub-boundary A5'A6' in the boundary of the first updated pattern 210', the spacing between which is smaller than the preset value L0 with the first adjacent connection pattern 220. Then, as Figure 7c As shown in FIG. 1 , the sub-boundaries A1′A2′, A2′A4′, A4′A5′ and A7′A1′ of the boundary of the first update pattern 210′ except the first sub-boundary A5′A6′ are expanded to obtain the following Figure 7c The new boundary of the first updated pattern 210' is shown in the dotted box in the middle. The line pattern defined by the new boundary of the first updated pattern 210' is recorded as the middle pattern.
[0081] The distance between the boundary of the above-mentioned intermediate pattern and the adjacent connection pattern is as follows: Figure 7c The dashed box includes: a spacing X1'' with the sub-boundary B1B2 of the first adjacent wiring pattern 220, a spacing X2'' with the sub-boundary C1C2 of the second adjacent wiring pattern 230, and a spacing X3'' with the sub-boundary B3B4 of the first adjacent wiring pattern 220. It should be understood that the spacing X1'' is smaller than the spacing X1', the spacing X2'' is smaller than the spacing X2', and the spacing X3'' is equal to the spacing X3'. Figure 7c In the figure, the side of the middle pattern adjacent to the second adjacent line pattern 230 and the extension line of the side C2C3 of the second adjacent line pattern 230 are compared to the point Ap, and the sub-boundary A2'A4' of the first updated pattern 210' is expanded outward, and the vertex A2' corresponds to the vertex Aq of the middle pattern. .
[0082] Further, the spacings X1'' and X2'' can be compared with the preset value L0 to determine that there is a second sub-boundary ApAq in the expanded boundary of the intermediate pattern, the spacing between which and the second adjacent connection pattern 230 is less than the preset value L0, and then the expansion process of the second sub-boundary ApAq is canceled, that is, the second sub-boundary ApAq is retracted to the position where the sub-boundary A2'A3' of the first update pattern 210' is located, thereby obtaining the following: Figure 7d A second update pattern 210 ″ is shown. Figure 7d The second updated pattern 210 ″ has vertices A3 ″ and A8 ″ along the extension line of the side C2C3 of the second adjacent connection pattern 230 , that is, the second updated pattern 210 ″ has one more vertex than the first updated pattern 210 ′ due to cancellation of the expansion of the second sub-boundary ApAq.
[0083] During the second outward expansion process, since the first sub-boundary A5'A6' does not expand outward under the limitation of the preset value L0, the risk of bridging the connection formed by the correction pattern of the first connection pattern 210 due to being too close to the connection formed by the first adjacent connection pattern 220 can be avoided; and the cancellation of the outward expansion of the second sub-boundary ApAq can avoid the risk of bridging the connection formed by the correction pattern of the first connection pattern 210 due to being too close to the connection formed by the second adjacent connection pattern 230.
[0084] Figure 7d to Figure 7e The process of obtaining the first corrected pattern 210'' by the second updated pattern 210'' through the third outward expansion process is illustrated. It should be understood that since the outward expansion of the second sub-boundary ApAq is cancelled, the spacing between the second updated pattern 210'' and the adjacent connection pattern includes the spacings X1'', X2' and X3'' as described above. During the third outward expansion process, the above spacings X1'', X2' and X3'' are first compared with the preset value L0 to determine that there is a first sub-boundary A5''A6'' in the boundary of the second updated pattern 210'', the spacing between which and the first adjacent connection pattern 220 is less than the preset value L0. Then, as Figure 7d As shown in FIG. 1 , the sub-boundaries A1′A2′′, A2′A3′′, A8′A4′′, A4′A5′′ and A7′A1′′ of the boundary of the second update pattern 210′′ except the first sub-boundary A5′A6′′ are expanded to obtain the following Figure 7d The new boundary of the second update pattern 210'' is shown in the dotted line frame. Then, the boundary of the second update pattern 210'' is expanded to Figure 7d The new boundary shown in the dotted line box is obtained as Figure 7e A first modified pattern 210 ′″ is shown.
[0085] It should be noted that the first outward expansion process can also be performed after determining the Figure 7b After the boundary shown in the midpoint line frame is determined, it is determined whether there is a second sub-boundary in the determined boundary whose spacing with the adjacent connection pattern is less than the preset value L0. If so, the expansion of the second sub-boundary is cancelled. In the above embodiment, since the spacings X1' and X2' are both greater than the preset value L0, there is no second sub-boundary. The above third outward expansion process is similar, that is, it can also be determined that Figure 7d After determining the boundary shown by the dotted line box, it is determined whether there is a second sub-boundary in the boundary whose spacing with the adjacent connection pattern is less than the preset value L0. If so, the expansion of the second sub-boundary is cancelled. In the above embodiment, since the spacings X1''' and X2''' are both greater than the preset value L0, there is no second sub-boundary.
[0086] Further, the outward expansion process described in step S120 is performed at least once, and the outward expansion process is performed in the order of decreasing outward expansion distances. In this way, if there is a second sub-boundary that has not been expanded in the previous outward expansion process, then in the current or subsequent outward expansion process, the second sub-boundary can be expanded with a smaller outward expansion distance and the distance from the adjacent connection pattern is greater than the preset value L0, such as Figure 7c The second sub-boundary ApAq shown is expanded outward at a smaller expansion distance to a position at a spacing X2''' not greater than a preset value L0 from the second adjacent connection pattern 230 after the third outward expansion process, thereby being able to achieve the expansion of the target connection pattern boundary as much as possible while avoiding the risk of bridging, thereby meeting the requirement that the target connection pattern area is increased to be greater than the area threshold.
[0087] It should be noted that the preset value L0 used in the outward expansion process is to ensure that the connection formed by the correction pattern of the target connection pattern does not bridge the connection formed by the adjacent connection pattern. In the case of a large process error (such as an over-etching error), the preset value L0 can be set to be larger. In addition, the outward expansion distance used in each outward expansion process varies depending on the density of the semiconductor device structure, and the number of times the outward expansion process is performed can also be adjusted according to demand and is not limited to the three times described in the above example.
[0088] For the above-mentioned second type of wiring pattern, the characteristic size in step S120 includes the width of the wiring pattern, and correspondingly the above-mentioned threshold includes a first width threshold. Step S120, modifying the shape of the target wiring pattern in the original pattern of the mask, includes: selecting a target wiring pattern in the original pattern whose spacing with an adjacent wiring pattern is less than the spacing threshold, whose width is less than the first width threshold, and whose adjacent wiring pattern width is greater than the second width threshold, increasing the width of the selected target wiring pattern and reducing the width of its adjacent wiring pattern, so that not only the width of the target wiring pattern is increased, but also the width difference between the target wiring pattern and the adjacent wiring pattern is reduced, so that the target wiring pattern is less affected by the adjacent wiring pattern during the lithography process, so that the corrected pattern of the target wiring pattern can form a wiring groove that is basically fully opened, effectively avoiding the risk of disconnection of the wiring formed by the small wiring pattern when the spacing between the small wiring pattern and the large wiring pattern is close, thereby improving the yield of the semiconductor device.
[0089] It should be noted that the above-mentioned spacing threshold is the dividing value for whether there is mutual influence between adjacent connection patterns during the photolithography process, and the above-mentioned first width threshold and second width threshold are the dividing values for whether the mutual influence between adjacent connection patterns during the photolithography process causes the smaller wiring pattern to form a broken line. Therefore, if a smaller connection pattern with a width less than the first width threshold in the original pattern has a connection pattern with a width greater than the second width threshold at a position less than the spacing threshold, then the smaller connection pattern needs to be corrected.
[0090] In addition, the wiring pattern on the mask is usually rectangular, and thus has two dimensions, length and the width mentioned above, wherein the width dimension is not greater than the length dimension. In this case, the target wiring pattern can be the rectangular wiring pattern selected from the original pattern. It should be understood that even if the wiring pattern on the mask is non-rectangular, it will be as follows. Figure 7a As shown in the first adjacent line pattern 220, it can be regarded as composed of multiple rectangular patterns. Therefore, the rectangular pattern included in a line pattern in the original pattern can be used as an independent pattern to determine whether the width is less than the first width threshold and whether it can be regarded as a target line pattern for subsequent width increase processing. Therefore, in this case, the target line pattern can be the rectangular pattern selected in the original pattern to form the line pattern.
[0091] Figures 8a to 8c Show Figure 6 The second connection pattern 310 shown in FIG. 1 is a schematic diagram of a process of obtaining a second correction pattern 310′ by increasing the width of the target connection pattern. Figure 8aIn the original pattern of the mask shown, the second wiring pattern 310 has an adjacent third wiring pattern 320, the first side C1C2 of the second wiring pattern 310 is adjacent to the second side D1D2 of the adjacent third wiring pattern 320, and the spacing between the first side C1C2 and the second side D1D2 is Y1, the second wiring pattern 310 has a width Y2 under the definition of the first side C1C2 and the opposite side, the third wiring pattern 320 has a width Y3 under the definition of the second side D1D2 and the opposite side, and the spacing Y1 is less than the spacing threshold L1, the width Y2 is less than the first width threshold L2, and the width Y3 is greater than the second width threshold L3, and the second width threshold L3 is greater than the first width threshold L2. Figure 8b As shown, the first side C1C2 is moved a first distance B1 in a direction close to the third connection pattern 320, so that the second connection pattern 310 has a newly added area shown in a dotted box, so that the width of the second connection pattern 310 increases from Y2 to Y2', and the Figure 8c The second modified pattern 310' having the boundary C1'C2' shown in FIG. 1 is shown; the second side D1D2 is moved a second distance B2 in the direction away from the second wiring pattern 310, so that the third wiring pattern 320 is reduced in the area shown in the dotted line frame, so that the width of the third wiring pattern 320 is reduced from Y3 to Y3', and the Figure 8c The third modified pattern 320' with the boundary D1'D2' is shown. The first distance B1 and the second distance B2 are equal, so in the process of increasing the width of the second wiring pattern 310 and reducing the width of the adjacent third wiring pattern 320, the spacing between the two wiring patterns is not changed by the width transfer, so that the upper and lower related layers are not affected, and the risk of bridging caused by the modification is avoided.
[0092] It should be noted that the first side C1C2 moves the first distance B1 and the second side D1D2 moves the second distance B2 in order to eliminate the influence of the adjacent third connection pattern 320 on the second connection pattern 310 during photolithography, and thus the values of the first distance B1 and the second distance B2 are set based on this requirement.
[0093] The mask correction method provided above does not involve position movement for the correction of the two types of wiring patterns, and thus does not affect the upper and lower related layers nor the previous and subsequent processes. For example, since the correction of the wiring pattern does not move the position, it has no effect on the layout position of the connection channel in the intermediate dielectric layer and will not affect the process of the intermediate dielectric layer. In addition, it does not cause the risk of bridging between adjacent wirings, and the implementation process is easier than modifying the process. Therefore, the mask correction method provided above is suitable for improving the process window to solve the problem of broken wires, which is of great significance to improving the yield of semiconductor devices.
[0094] Corresponding to the mask correction method provided in the above embodiment, another embodiment of the present application further provides a mask, wherein the mask is formed with a wiring pattern, and the wiring pattern is a pattern corrected by any of the mask correction methods described in the above embodiment. The wiring formed based on the corrected pattern will not have a disconnection phenomenon, thereby improving the yield and electrical performance of the semiconductor device. Figure 7e The mask pattern shown and Figure 8c The mask pattern shown is an exemplary pattern on the mask in the embodiment of the present application. It should be understood that Figure 7e and Figure 8c The pattern shown does not constitute a limitation on the mask pattern in the embodiments of the present application.
[0095] Another embodiment of the present application also provides an electronic device, which includes a memory and a processor, and a program stored in the memory and executable on the processor, and when the program is executed by the processor, each process in each embodiment of the above-mentioned mask correction method can be implemented and the same technical effect can be achieved. In some examples, the electronic device may also include auxiliary sub-devices such as a power supply component, a network interface, and an input / output interface.
[0096] A person of ordinary skill in the art can understand that all or part of the steps of the above method embodiments can be completed by executing a computer program. To this end, another embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each process of each embodiment of the above mask correction method can be implemented and the same technical effect can be achieved. Among them, computer-readable storage media, such as mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks, and other media that can store program codes.
[0097] Finally, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. According to the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that technicians in the relevant technical field can make good use of the present application and the modified use based on the present application. The present application is only limited by the claims and their full scope and equivalents.
Claims
1. A mask correction method, wherein the mask is formed with a connection pattern, and the correction method comprises: Obtaining the original pattern of the mask; Modifying the shape of the target wiring pattern in the original pattern of the mask to increase the feature size of the target wiring pattern to generate a revised pattern of the mask; Wherein, the target connection pattern is a connection pattern whose characteristic size is smaller than a threshold value, and the characteristic size affects the continuity of the connection formed by the connection pattern; The characteristic size includes the width of the connection pattern, the threshold includes a first width threshold, and modifying the shape of the target connection pattern in the original pattern of the mask includes: selecting the target connection pattern in the original pattern, which has a spacing with an adjacent connection pattern less than a spacing threshold, a width less than the first width threshold, and a width of an adjacent connection pattern greater than a second width threshold, the second width threshold being greater than the first width threshold; and increasing the width of the selected target connection pattern and reducing the width of its adjacent connection pattern.
2. The correction method according to claim 1, wherein: The characteristic size includes an area of the wiring pattern, the threshold includes an area threshold, and modifying the shape of the target wiring pattern in the original pattern of the mask includes: Selecting the target line pattern whose area is smaller than the area threshold in the original pattern; The selected target connection pattern is processed to expand outward so as to increase the area of the target connection pattern.
3. The correction method according to claim 2, wherein: The outward edge expansion process includes: Determining whether there is a first sub-boundary in the boundary of the target connection line pattern whose spacing with an adjacent connection line pattern is less than a preset value; In the case where the first sub-boundary exists, the sub-boundaries of the boundary of the target connection pattern except the first sub-boundary are expanded.
4. The correction method according to claim 2, wherein: The outward edge expansion process includes: Expanding the boundary of the determined target connection pattern to obtain an intermediate pattern; Determine whether there is a second sub-boundary in the boundary of the middle pattern that is expanded outward and has a spacing with the adjacent connection pattern that is less than a preset value; In the case where the second sub-boundary exists, the expansion process of the second sub-boundary is canceled.
5. The correction method according to claim 4, wherein: The outward expansion process is performed at least once, and the outward expansion process is performed at least once in a decreasing order of outward expansion distances.
6. The correction method according to claim 1, wherein: The first side of the target wiring pattern is adjacent to the second side of its adjacent wiring pattern, and the first side is a side defining the width of the target wiring pattern, and the second side is a side defining the width of an adjacent wiring pattern of the target wiring pattern; Increasing the width of the determined target line pattern includes: moving the first side edge by a first distance in a direction of an adjacent line pattern close to the target line pattern; Reducing the width of the adjacent connection pattern includes: moving the second side edge by a second distance in a direction away from the target connection pattern, and the second distance is equal to the first distance.
7. The correction method according to claim 1, wherein: The line pattern in the original pattern is in a rectangular shape, and the target line pattern is a line pattern in the original pattern in a rectangular shape; Alternatively, the connection pattern in the original pattern is in a non-rectangular shape but is composed of a plurality of rectangular patterns, and the target connection pattern is the rectangular pattern.
8. An electronic device comprising: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the mask correction method according to any one of claims 1 to 7.