A thermal evaluation method and thermal evaluation device for chip layout

Abstract

The present application discloses a thermal evaluation method and a thermal evaluation device for chip layout, and relates to the technical field of chip performance evaluation. The thermal evaluation method comprises: establishing a layout model of the chip, wherein the layout model comprises: a layout area; a circuit function module located in the layout area and arranged according to a preset position; a set of power consumption parameter points, wherein the layout area and the circuit function module are characterized by the distribution of each of the power consumption parameter points; obtaining characteristic parameters of the layout model according to the power consumption parameter distribution of the layout model under the preset position layout, wherein the characteristic parameters are positively correlated with the uniformity of the power consumption parameter distribution of the layout model; and evaluating the thermal performance of the layout model according to the characteristic parameters.

Description

Technical Field

[0001] The present application relates to the technical field of chip performance evaluation, and in particular to a thermal evaluation method and a thermal evaluation device for chip layout. Background Art

[0002] For a chip, multiple circuit function modules are usually integrated on it to realize the various functions of the chip. However, the layout of the above-mentioned multiple circuit function modules on the chip has a direct impact on the operating temperature of the chip. If the layout of the circuit function modules is improper, it will not only be detrimental to the realization of the chip's functions, but will also affect the performance of the chip due to the excessively high operating temperature of the chip, or even damage the chip.

[0003] In chip design, the importance of chip thermal assessment cannot be ignored. With the continuous advancement of integrated circuit (IC) design, especially in the advanced node stage, the impact of heat on chips is increasing. Heat not only causes the leakage of electrons in DRAM, but also affects the timing and reliability of 3D-IC, and the accelerated aging problem unique to different workloads will also occur. These problems all show that accurate thermal assessment is crucial to ensure the success of chip design. Therefore, when designing a chip, it is necessary to perform a thermal assessment on the chip layout to determine whether the designed chip layout method can meet the performance requirements of the chip. Summary of the invention

[0004] In view of this, the present application provides a chip layout thermal evaluation method and a thermal evaluation device, the scheme is as follows:

[0005] A first aspect of the present application provides a thermal assessment method for chip layout, comprising:

[0006] Establishing a layout model of the chip, the layout model includes: a layout area; a circuit function module located in the layout area and arranged according to a preset position; a set of power consumption parameter points, the layout area and the circuit function module are characterized by the distribution of each power consumption parameter point;

[0007] According to the power consumption parameter distribution of the layout model under the preset position layout, characteristic parameters of the layout model are obtained, and the characteristic parameters are positively correlated with the uniformity of the power consumption parameter distribution of the layout model;

[0008] Based on the characteristic parameters, the thermal performance of the layout model is evaluated.

[0009] Optionally, in the thermal assessment method for chip layout, the method for obtaining characteristic parameters of the layout model includes:

[0010] Based on a set sampling window, randomly sampling the layout area to obtain power consumption parameters of a random sampling area in the layout area corresponding to the sampling window;

[0011] Based on the power consumption parameters of the randomly sampled area, characteristic parameters of the layout model are obtained.

[0012] Optionally, in the thermal assessment method of the chip layout, the method further includes:

[0013] By adjusting the coordinate position of the power consumption parameter point, the layout mode of the circuit function module in the layout area is changed;

[0014] Determine the characteristic parameters corresponding to the layout model after the layout mode is changed.

[0015] Optionally, in the thermal assessment method of the chip layout, the method further includes:

[0016] Acquire characteristic parameters corresponding to a plurality of different layout models; wherein the layout modes of circuit function modules in different layout models are different;

[0017] Based on the characteristic parameters, determine the junction temperature prediction value corresponding to the layout model;

[0018] Based on the junction temperature prediction values ​​corresponding to each layout model, a target layout model is selected for chip layout design.

[0019] Optionally, in the thermal assessment method for chip layout, determining the junction temperature prediction value corresponding to the layout model based on the characteristic parameter includes:

[0020] Obtaining simulation junction temperature values ​​and corresponding simulation characteristic parameters of multiple different layout models;

[0021] Establishing the corresponding relationship between the simulation characteristic parameters and the simulation junction temperature value;

[0022] Based on the corresponding relationship, the junction temperature prediction value of the layout model under the corresponding characteristic parameters is obtained.

[0023] Optionally, in the thermal assessment method for chip layout, a correspondence between simulation characteristic parameters and simulation junction temperature values ​​is pre-stored, and the thermal assessment method further includes:

[0024] Based on the corresponding relationship, the junction temperature prediction value of the layout model under the corresponding characteristic parameters is obtained.

[0025] Optionally, in the thermal assessment method for chip layout, the random sampling area includes a plurality of power consumption parameter points; wherein the method for obtaining the characteristic parameters includes:

[0026] Based on the simulated power consumption of the power consumption parameter points, the relative entropy value of the random sampling area is calculated;

[0027] Based on the relative entropy values ​​of the randomly sampled areas, the characteristic parameters of the layout model are calculated.

[0028] Optionally, in the thermal assessment method for the chip layout, the relative entropy value of the random sampling area is calculated based on the simulated power consumption of the power consumption parameter point, including:

[0029] Obtain the sum of simulated power consumption of power consumption parameter points in the random sampling area;

[0030] Based on the sum of the simulated power consumption, the relative entropy value is calculated.

[0031] Optionally, in the thermal assessment method for chip layout, calculating characteristic parameters of the layout model based on the relative entropy value of the random sampling area includes:

[0032] Calculate the average relative entropy value of all randomly sampled random sampling areas, and use the average relative entropy value as the feature parameter.

[0033] A second aspect of the present application further provides a chip layout thermal evaluation device, comprising:

[0034] Establishing a module, the establishing module is used to establish a layout model of the chip, the layout model includes: a layout area; a circuit function module located in the layout area and arranged according to a preset position; a set of power consumption parameter points, the layout area and the circuit function module are characterized by the distribution of each power consumption parameter point;

[0035] The processing module is used to obtain characteristic parameters of the layout model according to the power consumption parameter distribution of the layout model under the preset position layout, and the characteristic parameters are positively correlated with the uniformity of the power consumption parameter distribution of the layout model; and the thermal performance of the layout model is evaluated according to the characteristic parameters.

[0036] From the above description, it can be seen that in the thermal evaluation method and thermal evaluation device of the chip layout provided by the technical solution of the present application, the characteristic parameters under the corresponding layout model can be obtained through the power consumption parameter distribution of the established layout model. The characteristic parameters are positively correlated with the uniformity of the power consumption parameter distribution of the layout model. The thermal performance of the layout model can be evaluated based on the characteristic parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0038] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0039] Figure 1 A schematic diagram of a thermal evaluation method for chip layout provided in an embodiment of the present application;

[0040] Figure 2 A flow chart of a method for obtaining characteristic parameters of a layout model provided in an embodiment of the present application;

[0041] Figure 3 A schematic flow chart of another chip layout thermal assessment method provided in an embodiment of the present application;

[0042] Figure 4 A flow chart of a method for determining a junction temperature prediction value based on characteristic parameters provided in an embodiment of the present application;

[0043] Figure 5 A schematic flow chart of another chip layout thermal evaluation method provided in an embodiment of the present application;

[0044] Figure 6 A flow chart of another method for obtaining characteristic parameters of a layout model provided in an embodiment of the present application;

[0045] Figure 7 A flow chart of a method for calculating the relative entropy value of a random sampling area based on simulated power consumption of power consumption parameter points provided in an embodiment of the present application;

[0046] Figure 8 A power consumption distribution diagram corresponding to a chip layout model having two circuit function modules provided in an embodiment of the present application;

[0047] Fig. 9 A schematic diagram of the principle of randomly sampling a random sampling area in a layout area provided in an embodiment of the present application;

[0048] Figure 10-12 The power consumption distribution diagrams corresponding to the three chip layout models provided in the embodiments of the present application;

[0049] Figure 13-Figure 16 In order Figure 8 , Figure 10-12 Chip junction temperature simulation diagram under the corresponding chip layout model;

[0050] Fig.17A schematic diagram of the structure of a thermal evaluation device for chip layout provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments of the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0052] Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. The terms used in the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0053] As chip functions continue to increase, more and more circuit function modules are integrated inside the chip. Taking SOC (system-on-chip) as an example, a SOC integrates multiple circuit function modules, such as GPU (Graphics Processing Unit), CPU (Central Processing Unit) and NPU (Neural Network Processing Unit). In addition, different circuit function modules inside the chip also include multiple sub-function modules. For example, the CPU in the SOC can be a 3-core structure, including large, medium and small cores with different performance and power consumption. The position layout of each circuit function module in the chip will directly affect the junction temperature value of the chip, and the junction temperature value of the chip has a direct impact on the performance of the chip.

[0054] Among them, the chip junction temperature, also known as the junction temperature, is the temperature that the internal "junction" or the core area of ​​the chip can reach when the semiconductor chip (such as CPU, GPU, etc.) is in normal operation or maximum load state. This temperature is a key indicator for judging the heat dissipation efficiency of electronic equipment, which is crucial to ensure the stable operation of the equipment and extend its service life.

[0055] Therefore, thermal evaluation of the layout of the circuit functional modules in the chip during the design phase is an important part of the chip manufacturing process. Thermal evaluation of the chip layout can be used to determine whether the designed chip layout can efficiently and reliably achieve the designed performance of the chip.

[0056] A conventional thermal assessment method for chip layout is to select a chip layout, estimate the power consumption of each circuit function module in the chip under this layout, intuitively increase the distance between circuit function modules with high power consumption, or refer to the layout of competing chips to layout the circuit function modules in the chip. This thermal assessment method cannot quantify the power consumption distribution at different locations of the chip, and it is difficult to refine the power consumption distribution optimization of sub-function modules in the circuit function module.

[0057] With the continuous advancement of simulation technology, thermal evaluation of chip layout can be performed through thermal simulation. In conventional thermal simulation methods, it is necessary to first establish a thermal model of the floorplan of the chip layout method, use thermal simulation tools to input the power consumption of each circuit functional module and sub-functional module under a given chip layout method, and simulate the maximum junction temperature of the chip under different layout methods for comparison. Then, based on the power consumption distribution of each circuit functional module, thermal evaluation is performed according to the power distribution map. This method of simulation solution has a large amount of calculation and takes a long time.

[0058] In view of this, an embodiment of the present application provides a thermal assessment method for chip layout, comprising:

[0059] Establishing a layout model of the chip, the layout model includes: a layout area; a circuit function module located in the layout area and arranged according to a preset position; a set of power consumption parameter points, the layout area and the circuit function module are characterized by the distribution of each power consumption parameter point;

[0060] According to the power consumption parameter distribution of the layout model under the preset position layout, characteristic parameters of the layout model are obtained, and the characteristic parameters are positively correlated with the uniformity of the power consumption parameter distribution of the layout model;

[0061] Based on the characteristic parameters, the thermal performance of the layout model is evaluated.

[0062] The thermal evaluation method for chip layout provided by the technical solution of the present application can obtain characteristic parameters under the corresponding layout model through the power consumption parameter distribution of the established layout model. The characteristic parameters are positively correlated with the uniformity of the power consumption parameter distribution of the layout model. The thermal performance of the layout model can be evaluated based on the characteristic parameters.

[0063] It can be seen that in the thermal evaluation method provided in the embodiment of the present application, under a given layout model, the layout model can be thermally evaluated through characteristic parameters that can characterize the uniformity of the power consumption parameter distribution. The power consumption parameters are directly related to the position layout of the circuit functional module and its sub-functional modules. Therefore, the thermal evaluation method can accurately quantify the power consumption distribution at different positions of the chip, and can also be refined to the power consumption distribution of the sub-functional modules in the circuit functional module, and can be used to optimize the power consumption distribution of the sub-functional modules in the circuit functional module.

[0064] Optionally, the thermal evaluation method provided in the embodiment of the present application can also improve the efficiency of thermal evaluation by adjusting the position of the power consumption parameter point, changing the layout method of the circuit functional modules in the layout model, simplifying the modeling method of the layout model, and reducing the amount of data processing for simulation solution.

[0065] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0066] refer to Figure 1 , Figure 1 A schematic flow chart of a thermal evaluation method for chip layout provided in an embodiment of the present application, the thermal evaluation method comprising:

[0067] Step S11: Establishing a layout model of the chip, the layout model includes: a layout area; a circuit function module located in the layout area and arranged according to a preset position; a set of power consumption parameter points, the layout area and the circuit function module are characterized by the distribution of each power consumption parameter point.

[0068] The layout area is a functional area in the layout model, which is the entire layout area in the layout model that can be used to set circuit function modules.

[0069] Step S12: acquiring characteristic parameters of the layout model according to the power consumption parameter distribution of the layout model under the preset position layout, wherein the characteristic parameters represent the uniformity of the power consumption parameter distribution.

[0070] Step S13: Evaluate the thermal performance of the layout model according to the characteristic parameters.

[0071] In the thermal evaluation method provided in the embodiment of the present application, under a given layout model, the layout model can be thermally evaluated through characteristic parameters that can characterize the uniformity of the power consumption parameter distribution. The power consumption parameters are directly related to the position layout of the circuit functional module and its sub-functional modules. Therefore, the thermal evaluation method can not only accurately quantify the power consumption distribution at different positions of the chip, but also be refined to the power consumption distribution of the sub-functional modules in the circuit functional module, and can be used to optimize the power consumption distribution of the sub-functional modules in the circuit functional module.

[0072] In one implementation of the present application, a method for obtaining characteristic parameters of a chip layout model may be as follows: Figure 2 shown.

[0073] refer to Figure 2 , Figure 2 A flow chart of a method for obtaining characteristic parameters of a layout model provided in an embodiment of the present application, the method comprising:

[0074] Step S21: Based on the set sampling window, randomly sampling the layout area to obtain the power consumption parameters of the random sampling area in the layout area corresponding to the sampling window.

[0075] When performing random sampling, for a random sampling area, the power consumption parameters of each power consumption parameter point in the random sampling area are sampled, that is, the power consumption parameters of all power consumption parameter points in the random sampling area are obtained as the power consumption parameters of the random sampling area.

[0076] Step S22: Acquire characteristic parameters of the layout model based on the power consumption parameters of the random sampling area.

[0077] Each time sampling is performed, the sampling window defines a random sampling area opposite to the sampling window in the relative area of ​​the layout area, so as to obtain the power consumption parameters of the random sampling area. For different sampling times, the random sampling area is randomly determined in the layout area through the sampling window. Based on the random sampling characteristics, the random sampling areas corresponding to different sampling times can overlap or not overlap in the layout area. As the number of sampling times increases, the overlap probability of different random sampling areas will increase.

[0078] In addition, as described below, in one implementation of the embodiment of the present application, the matrix entropy of the layout model can be calculated by the relative entropy value of the randomly sampled area, and the matrix entropy of the layout model is used as a characteristic parameter. Since the entropy value of a position depends on the power consumption value of the surrounding area at the position, it is necessary to randomly cover each area through random sampling.

[0079] When performing random sampling, you can use programming languages ​​or dedicated tools to randomly sample different random sampling areas in the layout area. Using the NumPy library in Python, you can easily generate random numbers that follow a specific distribution. If you are using a specific electronic design automation (EDA) tool, such as PrimeTime, you can also use its built-in commands to randomly sample power consumption parameters in different random sampling areas.

[0080] The power consumption parameters of the random sampling areas are randomly sampled to obtain the power consumption parameters of the random sampling areas, and the distribution of the power consumption parameters satisfies the random distribution. Based on the power consumption parameters of the random sampling areas, the characteristic parameters of the layout model can be obtained.

[0081] Optionally, the power consumption parameters of the random sampling area may be acquired based on the power consumption distribution diagram corresponding to the layout model.

[0082] based on Figure 2 In the manner shown, power consumption parameters of multiple random sampling areas can be obtained by performing random sampling in the layout area multiple times, so as to obtain characteristic parameters of the layout model based on the power consumption parameters of the random sampling areas.

[0083] exist Figure 2 In the method shown, by performing multiple random sampling on the layout area, randomness can be achieved between the sampling areas, and power consumption parameters of multiple random sampling areas can be obtained. The probability of sampling at any position in the layout area is the same, and random sampling areas will be randomly overlapped and sampled, which can better reflect the relationship between each sampling point and the surrounding points; the randomness of the characteristic parameters can be guaranteed, and the thermal distribution state of the chip can be effectively estimated from a large and complex probability space. Representative sample data can be extracted from actual and theoretical thermal distributions, and the thermal distribution probability density function can be reconstructed more accurately, which is convenient for more accurate calculation of characteristic parameters.

[0084] If the layout model of the chip is determined, that is, after the circuit function modules in a given layout area are laid out according to preset positions, the layout area has a determined power consumption distribution diagram. In the embodiment of the present application, the power consumption parameters of the random sampling area can be obtained according to the power consumption distribution diagram of the layout area.

[0085] Different points in the layout area have corresponding pixels in the power consumption distribution map corresponding to the layout area. When performing random sampling, for a random sampling area, the power consumption parameters of the randomly sampled area can be obtained according to the corresponding pixels of the random sampling area in the power consumption distribution map.

[0086] refer to Figure 3 , Figure 3 A schematic flow chart of another chip layout thermal evaluation method provided in an embodiment of the present application, based on any of the above implementation modes, Figure 3 The methods shown also include:

[0087] Step S31: acquiring characteristic parameters corresponding to a plurality of different layout models; wherein the layout modes of circuit functional modules in different layout models are different.

[0088] Step S32: determining a junction temperature prediction value corresponding to the layout model based on the characteristic parameters.

[0089] Step S33: Based on the junction temperature prediction values ​​corresponding to each layout model, a target layout model is selected to perform chip layout design.

[0090] based on Figure 3 The method shown can determine the junction temperature prediction value of the layout model through the characteristic parameters of the layout model. Based on the junction temperature prediction values ​​of each layout model, the thermal performance of the chip of different layout models can be predicted, so as to select the target layout model whose thermal performance meets the usage requirements to prepare the chip.

[0091] exist Figure 3 In the manner shown, based on the characteristic parameters, the method for determining the junction temperature prediction value corresponding to the layout model can be as follows: Figure 4 shown.

[0092] refer to Figure 4 , Figure 4 A flow chart of a method for determining a junction temperature prediction value based on a characteristic parameter provided in an embodiment of the present application, the method comprising:

[0093] Step S41: obtaining simulated junction temperature values ​​and corresponding simulation characteristic parameters of a plurality of different layout models.

[0094] Step S42: establishing a corresponding relationship between the simulation characteristic parameters and the simulation junction temperature values.

[0095] Step S43: based on the corresponding relationship, obtaining the junction temperature prediction value of the layout model under the corresponding characteristic parameters.

[0096] It is easy to know that for a given chip, the power consumption distribution diagram and the chip junction temperature value corresponding to the chip are determined. Correspondingly, in the thermal simulation model used for chip thermal evaluation, for a given chip layout model, the corresponding power consumption distribution diagram and chip junction temperature value are determined, and the power consumption distribution diagram and the chip junction temperature value have a mapping relationship, and the mapping relationship is related to the layout method of the circuit functional modules in the chip. Therefore, in the embodiment of the present application, the characteristic parameters that can characterize the uniformity of the power consumption parameter distribution have a corresponding relationship with the chip junction temperature value. Therefore, under the condition of determining the simulation characteristic parameters of the layout model, based on the above-mentioned corresponding relationship, the junction temperature prediction value of the layout model under the corresponding simulation characteristic parameters can be obtained, and the thermal performance of a variety of different chip layouts can be directly displayed through the junction temperature prediction value.

[0097] In another embodiment, a correspondence between simulation characteristic parameters and simulation junction temperature values ​​may be pre-stored, and the thermal assessment method further includes: based on the correspondence, obtaining a junction temperature prediction value of the layout model under the corresponding characteristic parameters. This method can directly determine the junction temperature prediction value of the layout model under the corresponding characteristic parameters based on the pre-stored correspondence. The junction temperature prediction value of the layout model under the corresponding characteristic parameters can be obtained by querying a data table calibrated with the correspondence.

[0098] In any implementation of the embodiments of the present application, the layout model of the chip includes a set of power consumption parameter points. The layout area and the circuit function module can be characterized by the distribution of each power consumption parameter point.

[0099] As mentioned above, after the layout model is determined, its corresponding power consumption distribution map is determined. The power consumption parameter points in the layout model correspond to the pixel points in the power consumption distribution map. Therefore, the layout area and the circuit function module can be represented by the set of power consumption parameter points in the layout model. In this way, when adjusting the chip layout method, the layout method of the circuit function module in the layout area can be changed by adjusting the position of the power consumption parameter points in the layout area, which is convenient for accelerating the design iteration of the chip layout method.

[0100] In the embodiment of the present application, the power consumption distribution diagram of the layout model can be processed by using simulation software to obtain the power consumption parameter distribution of the layout model, thereby determining the characteristic parameters of the layout model based on the power consumption parameter distribution.

[0101] In the embodiment of the present application, it is not limited to determining the power consumption parameter distribution of the layout model through the power consumption distribution diagram. In other ways, the power consumption parameter distribution of the layout model can also be determined by other parameters related to the power consumption parameters, such as the power consumption parameter distribution of the layout model can be determined by current parameters or voltage parameters, etc., which will not be further described in the embodiment of the present application.

[0102] For a certain layout area, if the size of the sampling window is smaller, the area of ​​the random sampling area is smaller, the number of samplings required is more, and the accuracy of the thermal evaluation is higher. Conversely, the larger the size of the sampling window, the larger the area of ​​the random sampling area, the fewer the number of samplings required, and the lower the accuracy of the thermal evaluation.

[0103] In one implementation, the size of the sampling window may be set to be fixed, and the accuracy of the thermal assessment method may be set to be fixed.

[0104] In other embodiments, the size of the sampling window can be set to be adjustable according to the accuracy requirements of the thermal assessment method. In this case, the thermal assessment method allows the user to set the size of the sampling window based on the requirements.

[0105] If the size of the sampling window can be set to be adjustable according to the accuracy requirements of the thermal assessment method, before starting random sampling, the user's setting instructions can be obtained to set the size of the sampling window based on the setting instructions, and random sampling is performed based on the sampling window of the set size.

[0106] refer to Figure 5 , Figure 5 A schematic flow chart of another chip layout thermal evaluation method provided in an embodiment of the present application is provided. Based on any of the above implementation modes, Figure 5 The methods shown also include:

[0107] Step S14: changing the layout of the circuit function modules in the layout area by adjusting the coordinate positions of the power consumption parameter points.

[0108] Step S15: determining the characteristic parameters corresponding to the layout model after the layout mode is changed.

[0109] exist Figure 5 In the manner shown, after the thermal performance evaluation of the previous layout model is completed, the layout mode of the circuit functional modules in the layout area can be adjusted by adjusting the coordinate position of the power consumption parameter point in the layout area to change the layout model, so that the thermal performance of the new layout model can be evaluated based on the characteristic parameters of the changed layout model. The change and switching of different layout models are simple, and the thermal performance of different layout models can be evaluated more quickly.

[0110] In the implementation of this application, the layout mode of the circuit module in the layout area can be changed by adjusting the coordinate position of the power consumption parameter point. When the coordinate position of the power consumption parameter point in the layout area changes, the corresponding power consumption distribution diagram also changes, and different power consumption distribution diagrams correspond to different circuit function module distribution modes.

[0111] By adjusting the coordinate position of the power consumption parameter point, at least one of the following methods can be achieved: 1) adjusting the layout parameters of at least one existing circuit function module in the layout area, and the adjustment of the layout parameters includes adjusting at least one of the position and orientation of the circuit function module in the layout area, so that the existing circuit function module can be rotated, or only translated, or translated and rotated at the same time without changing the position; 2) merging at least two existing circuit function modules into a new circuit function module; 3) deleting at least one existing circuit function module in the layout model; 4) adding a new circuit function module to the layout model.

[0112] refer to Figure 6 , Figure 6 A flowchart of another method for obtaining characteristic parameters of a layout model provided in an embodiment of the present application, wherein the random sampling area includes multiple power consumption parameter points. Figure 6 In the method shown, the method for obtaining characteristic parameters includes:

[0113] Step S51: Calculate the relative entropy value of the random sampling area based on the simulated power consumption of the power consumption parameter point.

[0114] In the embodiment of the present application, different chip layout models have different power consumption distribution maps, and all power consumption distribution maps can be imported. For a given layout model, the power consumption parameters of a random sampling area are obtained in the power consumption distribution map corresponding to its layout area.

[0115] Each random sampling area has a corresponding power consumption distribution area in the power consumption distribution map. For the power consumption distribution map with a determined resolution, the pixel points corresponding to the power consumption distribution area are determined, that is, the pixel points corresponding to the power consumption parameter points in the power consumption distribution area are determined. Therefore, the power consumption parameters of the random sampling area can be determined by the corresponding power consumption distribution area in the power consumption distribution map.

[0116] Optionally, the pixel points in the power consumption distribution area corresponding to the random sampling area can be merged and the average value can be taken to reduce the number of power consumption parameter points in the random sampling area, or the pixel points can be segmented, and the pixel samples after segmentation have the same power consumption parameters as the pixel samples before segmentation to increase the number of power consumption parameter points.

[0117] Step S52: Calculate characteristic parameters of the layout model based on the relative entropy value of the randomly sampled area.

[0118] In the embodiment of the present application, the simulated power consumption of the power consumption parameter points in the random sampling area can be determined according to the power consumption distribution diagram, so as to determine the relative entropy value of the random sampling area based on the simulated power consumption. The characteristic parameters of the layout model can be calculated through the relative entropy value.

[0119] Among them, the application of relative entropy value in chip thermal evaluation is to measure the difference between the chip layout model and the actual thermal distribution of the chip. The relative entropy value helps engineers optimize chip design and improve its reliability and performance.

[0120] In thermal evaluation, the relative entropy value (Kullback-Leibler divergence, referred to as KL divergence) is a core indicator that can measure the difference between two probability distributions. Specifically, KL divergence quantifies the amount of information loss when one distribution is used to approximate another distribution. In chip thermal evaluation, one distribution is the expected thermal distribution, and the other distribution is the thermal distribution measured during actual chip operation. The KL divergence between the two can provide a quantitative deviation indicator, and the chip layout can be adjusted based on this indicator to more effectively manage chip heat.

[0121] Among them, the above-mentioned expected heat distribution is obtained by modeling and simulation of the chip layout, such as the characteristic parameters in this application. This heat distribution is calculated in the chip design stage to predict the heat distribution that the chip may generate during operation. The heat distribution measured in actual operation can be obtained in the actual operation of the chip or experimental testing. The specific method includes arranging multiple temperature sensors on the surface of the chip and monitoring the temperature of each part in real time to obtain actual temperature distribution data.

[0122] exist Figure 6 In the manner shown, based on the simulated power consumption of the power consumption parameter point, the method for calculating the relative entropy value of the random sampling area can be as follows: Figure 7 shown.

[0123] refer to Figure 7 , Figure 7 A flow chart of a method for calculating the relative entropy value of a random sampling area based on simulated power consumption of power consumption parameter points provided in an embodiment of the present application, the method comprising:

[0124] Step S61: Obtain the sum of simulated power consumption of power consumption parameter points within a random sampling area.

[0125] For a determined random sampling area, it has a corresponding power consumption distribution area in the power consumption distribution map. For a power consumption distribution map with a determined resolution, the pixel points corresponding to the power consumption distribution area are determined, that is, the pixel points corresponding to the power consumption parameter points in the power consumption distribution area are determined, so the simulated power consumption of the power consumption parameter points in the random sampling area can be determined respectively by the corresponding pixel points. The sum of the simulated power consumption of all power consumption parameter points in the random sampling area can be automatically calculated by the power consumption distribution map processing software and software algorithms.

[0126] Step S62: Calculate the relative entropy value based on the sum of the simulated power consumption.

[0127] The sum of the simulated power consumption of all power consumption parameter points in the random sampling area is set to P total , the relative entropy value of the random sampling area is Entropy, which satisfies the following relationship:

[0128]

[0129] After the relative entropy value of the random sampling area is determined, the characteristic parameters of the layout model are calculated based on the relative entropy value of the random sampling area, including: calculating the average relative entropy value of all randomly sampled random sampling areas, and taking the average relative entropy value as the characteristic parameter. If a total of n random samplings are performed, the relative entropy values ​​of n random sampling areas will be generated accordingly. After calculating the sum of the relative entropy values ​​of the n random sampling areas, the sum is divided by n to obtain the average relative entropy value.

[0130] The implementation and effect of the thermal evaluation method provided in the embodiment of the present application are further described below in conjunction with a chip layout model having two circuit function modules.

[0131] Step 1: Establish a chip layout model based on two circuit functional modules and Figure 8 As shown in the figure, the power consumption distribution diagram under this layout model is created. Figure 8 A power consumption distribution diagram corresponding to a chip layout model with two circuit function modules provided in an embodiment of the present application. Figure 8 The two darker colored square-like areas in the middle area represent the power consumption distribution areas of the two circuit functional modules.

[0132] Step 2, such as Fig. 9 As shown, a random sampling is performed in the layout area of ​​the chip layout model, and the relative entropy of the corresponding random sampling area is calculated. Fig. 9 A schematic diagram of the principle of randomly sampling a random sampling area in a layout area provided in an embodiment of the present application.

[0133] Step 3, Fig. 9 Under the corresponding chip layout model, step 2 is repeated multiple times to sample power consumption parameters of multiple random sampling areas, and the average relative entropy value of all random sampling areas is calculated to obtain Fig. 9 The matrix entropy under the corresponding chip layout model is used as the characteristic parameter of the current chip layout model. The simulation data shows that Fig. 9 The corresponding matrix entropy is -13.775.

[0134] Step 4, changing the volume point heat source distribution in the chip layout model, that is, changing the layout parameters of the circuit functional module, thereby changing the chip layout model, and repeating the above steps 1 to 3 to obtain the matrix entropy under different chip layout models.

[0135] In step 4 above, by changing Figure 8 By using the layout parameters of the two circuit function modules in , three other different chip layout models can be obtained. The power consumption distribution diagrams corresponding to the three chip layout models are shown as follows: Figure 10-12 As shown, Figure 10-12 The power consumption distribution diagrams corresponding to the three chip layout models provided in the embodiments of the present application are shown.

[0136] Will Figure 10-12 Respectively Figure 8 By comparison, maintaining Figure 8 The circuit function module on the left side remains unchanged. Figure 8 The circuit function module on the right side of the middle is rotated 90° counterclockwise and moved below the circuit function module on the left side to obtain Fig.10 The corresponding chip layout model; keep Figure 8 The circuit function module on the left side remains unchanged, and the circuit function module on the right side is directly moved to the bottom of the circuit function module on the left side to obtain Fig.11 The corresponding chip layout model; keep Figure 8 The circuit function module on the left side remains unchanged, and the circuit module on the right side rotates 90° counterclockwise based on its own center position to obtain Fig.12 The corresponding chip layout model.

[0137] Simulation data show that Figure 10-12 The matrix entropy under the three methods is -13.748, -13.829, and -13.700 respectively. Figure 8 , Figure 10-12 The matrix entropies under the four methods are -13.775, -13.748, -13.829, and -13.700 respectively.

[0138] refer to Figure 13-Figure 16 , Figure 13-Figure 16 In order Figure 8 , Figure 10-12 The chip junction temperature simulation diagram under the corresponding chip layout model is based on Figure 13-Figure 16 As shown, Figure 8 , Figure 10-12 The chip simulation junction temperature values ​​under the four methods are 70.5°C, 70.2°C, 70.9°C, and 69.1°C, respectively. Based on the four different chip layout models, Table 1 can be established.

[0139] Table 1

[0140]

[0141] Based on Table 1, it can be seen that under different chip layout models, the simulated junction temperature value of the chip is inversely proportional to the matrix entropy, that is, the two are negatively correlated. The larger the matrix entropy, the smaller the simulated junction temperature value. Conversely, the smaller the matrix entropy, the larger the simulated junction temperature value. In other words, the matrix entropy and the chip junction temperature value have a corresponding relationship. The matrix entropy can be used to predict the relative size of the junction temperature values ​​of different chip layout models. Based on the size of the predicted chip junction temperature value, the advantages and disadvantages of the heat source distribution under different distribution models can be characterized, thereby providing guidance and suggestions for chip design.

[0142] From the above description, it can be seen that in the embodiment of the present application, the characteristic parameter is positively correlated with the uniformity of the power consumption parameter distribution of the layout model. The larger the characteristic parameter, the better the uniformity of the power consumption parameter distribution, and the lower the chip junction temperature value. Conversely, the smaller the characteristic parameter, the worse the uniformity of the power consumption parameter distribution, and the higher the chip junction temperature value.

[0143] In the embodiment of the present application, the number of random samplings needs to reach a set threshold so that the matrix entropy finally obtained can accurately represent the actual entropy value of the layout model. The set threshold can be set based on experience. Alternatively, when the sampled data obtained by random sampling makes the currently calculated matrix entropy no longer change with the increase of the number of random samplings or the change value is small, it is considered that the set threshold is reached.

[0144] In one implementation, a mapping relationship between matrix entropy and simulated junction temperature can be obtained through a large amount of data statistics. Subsequently, by obtaining the matrix entropy, the corresponding simulated junction temperature prediction value can be directly obtained to quickly predict the data value of the junction temperature.

[0145] based on Figure 13-Figure 16It can be seen from the simulation data verification that the thermal evaluation method provided by the embodiment of the present application can import the power consumption distribution diagram of all circuit function modules in the entire chip and optimize the chip layout. In addition, the thermal evaluation method can also be extended to the thermal evaluation of the distribution of body point heat sources in a three-dimensional system.

[0146] If the thermal assessment method is used for thermal assessment of point heat sources in a two-dimensional system, the layout area is a planar rectangular structure, the random sampling area is a rectangular sampling area in the planar rectangular structure, and random sampling is performed in the planar rectangular structure with a planar sampling window of a preset size to obtain characteristic parameters of the layout model based on the random sampling data.

[0147] If the thermal assessment method is used for thermal assessment of point heat sources in a three-dimensional system, the layout area is a cube structure, the random sampling area is a cube sub-area in the cube structure, and random sampling is performed in the cube structure with a cube sampling window of a preset size to obtain characteristic parameters of the layout model based on the random sampling data.

[0148] The thermal assessment method provided in the embodiments of the present application, whether used for thermal assessment of point heat sources in a two-dimensional system or for thermal assessment of point heat sources in a three-dimensional system, can optimize the design of a simplified floor plan in the early stages of chip design.

[0149] It can be known from the above description that the embodiment of the present application can calculate the relative entropy value of the sampled random sampling area based on the power consumption parameters of multiple random sampling areas, and use the average relative entropy value of the random sampling area as the characteristic parameter. The characteristic parameter used for thermal evaluation of the chip is the matrix entropy of the chip heat source distribution, which is a new solution for thermal evaluation of chip layout based on the heat source matrix entropy. Among them, the average relative entropy value of all random sampling areas is calculated through the relative entropy value of the random sampling area to characterize the characteristic parameters of the layout model. Based on the mathematical method related to the relative entropy, it can ensure that a reasonable and clear thermal evaluation of the entire layout surface model is made.

[0150] The simulation experimental data show that the characteristic parameters can characterize the uniformity of the power consumption parameters. The smaller the relative entropy of the random sampling area, the smaller the matrix entropy, indicating that the distribution of the body point heat source in the chip layout is more uneven, and the chip junction temperature value is larger. The high chip junction temperature value is due to the concentration of power consumption in the local area of ​​the chip layout, which leads to higher temperature.

[0151] In the thermal evaluation method for chip layout provided in the embodiment of the present application, the advantages and disadvantages of chip thermal performance under different layout models can be intuitively reflected through matrix entropy.

[0152] Moreover, compared with conventional thermal simulation methods, the thermal evaluation simulation solution based on matrix entropy in this application can greatly improve the calculation and solution speed.

[0153] In addition, compared with the conventional thermal simulation modeling method, the thermal evaluation method of the present application can adjust the layout methods such as increase, decrease, rotation and translation of circuit functional modules in the layout area by adjusting the coordinate position of the power consumption parameter points, which can speed up the design iteration of the chip layout and improve the work efficiency of thermal evaluation.

[0154] Based on the thermal evaluation method provided in the above embodiment, another embodiment of the present application further provides a thermal evaluation device for chip layout. Fig.17 shown.

[0155] refer to Fig.17 , Fig.17 A schematic diagram of a thermal evaluation device for chip layout provided in an embodiment of the present application is provided, wherein the thermal evaluation device comprises:

[0156] Establishing module 11, establishing module 11 is used to establish a layout model of the chip, the layout model includes: a layout area; a circuit function module located in the layout area and arranged according to a preset position; a set of power consumption parameter points, the layout area and the circuit function module are characterized by the distribution of each power consumption parameter point;

[0157] The processing module 12 is used to obtain characteristic parameters of the layout model according to the power consumption parameter distribution of the layout model under the preset position layout, and the characteristic parameters are positively correlated with the uniformity of the power consumption parameter distribution of the layout model; and evaluate the thermal performance of the layout model according to the characteristic parameters.

[0158] The thermal evaluation device can be used to execute the thermal evaluation method provided by any of the above-mentioned embodiments, so as to perform thermal evaluation on the layout model through characteristic parameters that can characterize the uniformity of power consumption parameter distribution. The power consumption parameters are directly related to the position layout of the circuit function module and its sub-function modules. Therefore, the thermal evaluation method can accurately quantify the power consumption distribution at different positions of the chip, and can also be refined to the power consumption distribution of the sub-function modules in the circuit function module, and can be used to optimize the power consumption distribution of the sub-function modules in the circuit function module.

[0159] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. The embodiments provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0160] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0161] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0162] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0163] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A thermal assessment method for chip layout, comprising: Establishing a layout model of the chip, the layout model comprising: a layout area; a circuit function module located in the layout area and arranged according to a preset position; a set of power consumption parameter points, the layout area and the circuit function module are characterized by the distribution of each of the power consumption parameter points; According to the power consumption parameter distribution of the layout model under the preset position layout, a characteristic parameter of the layout model is acquired, wherein the characteristic parameter is positively correlated with the uniformity of the power consumption parameter distribution of the layout model; evaluating the thermal performance of the layout model according to the characteristic parameters; Among them, the method for obtaining the characteristic parameters includes: obtaining the sum of simulated power consumption of multiple power consumption parameter points in a random sampling area; calculating the relative entropy value of the random sampling area based on the sum of the simulated power consumption; calculating the average relative entropy value of all randomly sampled random sampling areas, and using the average relative entropy value as the characteristic parameter.

2. According to the thermal evaluation method of chip layout according to claim 1, the method of obtaining the characteristic parameters of the layout model comprises: Based on a set sampling window, randomly sampling the layout area to obtain power consumption parameters of a random sampling area in the layout area corresponding to the sampling window; Based on the power consumption parameters of the random sampling area, characteristic parameters of the layout model are acquired.

3. The thermal evaluation method for chip layout according to claim 1, further comprising: By adjusting the coordinate position of the power consumption parameter point, the layout mode of the circuit function module in the layout area is changed; Determine the characteristic parameters corresponding to the layout model after the layout mode is changed.

4. The thermal evaluation method for chip layout according to claim 1 or 2, further comprising: Acquire characteristic parameters corresponding to a plurality of different layout models; wherein the layout modes of the circuit function modules in different layout models are different; Based on the characteristic parameters, determining a junction temperature prediction value corresponding to the layout model; Based on the junction temperature prediction values ​​corresponding to the respective layout models, a target layout model is selected to perform chip layout design.

5. The thermal assessment method for chip layout according to claim 4, determining the junction temperature prediction value corresponding to the layout model based on the characteristic parameter, comprising: Obtaining simulation junction temperature values ​​and corresponding simulation characteristic parameters of a plurality of different layout models; Establishing a corresponding relationship between the simulation characteristic parameter and the simulation junction temperature value; Based on the corresponding relationship, a junction temperature prediction value of the layout model under the corresponding characteristic parameters is obtained.

6. According to the thermal evaluation method for chip layout of claim 1 or 2, a correspondence between simulation characteristic parameters and simulation junction temperature values ​​is pre-stored, and the thermal evaluation method further comprises: Based on the corresponding relationship, a junction temperature prediction value of the layout model under the corresponding characteristic parameters is obtained.

7. A thermal evaluation device for chip layout, comprising: An establishment module, the establishment module is used to establish a layout model of the chip, the layout model includes: a layout area; a circuit function module located in the layout area and arranged according to a preset position; a set of power consumption parameter points, the layout area and the circuit function module are characterized by the distribution of each of the power consumption parameter points; A processing module, the processing module is used to obtain characteristic parameters of the layout model according to the power consumption parameter distribution of the layout model under the preset position layout, the characteristic parameters are positively correlated with the uniformity of the power consumption parameter distribution of the layout model; according to the characteristic parameters, the thermal performance of the layout model is evaluated; wherein the method for obtaining the characteristic parameters comprises: obtaining the sum of simulated power consumption of multiple power consumption parameter points in a random sampling area; calculating the relative entropy value of the random sampling area based on the sum of the simulated power consumption; calculating the average relative entropy value of all randomly sampled random sampling areas, and taking the average relative entropy value as the characteristic parameter.

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