Detection circuit and control method for phase alignment between multiple groups of multi-phase orthogonal clocks

Abstract

The present application relates to the field of integrated circuit technology and discloses a detection circuit and control method for phase alignment between multiple groups of multi-phase quadrature clock signals. The circuit includes: a first group of logic gates, first to third low-pass filters, an inversion switch, first and second comparators, and a threshold adjuster. The first group of logic gates includes first and second NOR gates and an XOR gate. The first NOR gate receives a first phase clock signal from the first group of multi-phase quadrature clock signals and a second phase clock signal from the second group of multi-phase quadrature clock signals. The second NOR gate receives a third phase clock signal from the first group of multi-phase quadrature clock signals and a second phase clock signal from the second group of multi-phase quadrature clock signals. The XOR gate receives a second phase clock signal from the first group of multi-phase quadrature clock signals and a second phase clock signal from the second group of multi-phase quadrature clock signals. The first to third low-pass filters are coupled to the outputs of each logic gate. The inversion switch is coupled between the outputs of the first and second low-pass filters and the first comparator, comparing the output signals of the first and second low-pass filters during forward and reverse rotation and outputting phase offset comparison results respectively. The second comparator is coupled to the output of the third low-pass filter and the threshold adjuster and outputs a phase shift polarity comparison result. This application can support high-frequency clock input, and the effective phase identification range is the entire clock cycle.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a detection circuit and control method suitable for phase alignment between multiple groups of multi-phase orthogonal clocks. Background Art

[0002] A high-speed phase detector (HPD) is a component that synchronizes the phase of a chip's internal clock chain. Its primary function is to compare the phase relationship between two input signals of the same frequency and generate an error signal, which is used to adjust the phase relationship between different sets of input clocks to maintain a consistent or fixed phase relationship. High-speed phase detectors are widely used in communication systems, frequency synthesizers, and clock recovery circuits. Traditional phase detection methods based on frequency detectors and conventional NAND (or NOT) phase detectors are limited in speed and range. Summary of the Invention

[0003] The purpose of this application is to provide a detection circuit and control method suitable for phase alignment between multiple groups of multi-phase orthogonal clocks. Compared with traditional detection methods, it can support high-frequency clock input, and the effective phase identification range is the entire clock cycle.

[0004] The present application discloses a detection circuit suitable for phase alignment between multiple groups of multi-phase orthogonal clock signals, comprising: a first group of logic gates, a first low-pass filter, a second low-pass filter, a third low-pass filter, an inverting switch, a first comparator, a second comparator, and a threshold adjuster;

[0005] The first group of logic gates includes a first NOR gate, a second NOR gate, and an XOR gate, wherein two input terminals of the first NOR gate receive a first phase clock signal in a first group of multi-phase quadrature clock signals and a second phase clock signal in a second group of multi-phase quadrature clock signals, respectively; two input terminals of the second NOR gate receive a third phase clock signal in the first group of multi-phase quadrature clock signals and a second phase clock signal in the second group of multi-phase quadrature clock signals, respectively; and two input terminals of the XOR gate receive a second phase clock signal in the first group of multi-phase quadrature clock signals and a second phase clock signal in the second group of multi-phase quadrature clock signals, respectively, wherein the first group of multi-phase quadrature clock signals and the second group of multi-phase quadrature clock signals each include sequential first to nth phase clock signals;

[0006] The first low-pass filter, the second low-pass filter and the third low-pass filter are respectively coupled to the outputs of the first NOR gate, the second NOR gate and the XOR gate;

[0007] The reversing switch is coupled to the outputs of the first low-pass filter and the second low-pass filter respectively and inputs the output signals of the first low-pass filter and the second low-pass filter in forward rotation and reverse rotation into two input terminals of the first comparator respectively. The first comparator compares the output signals of the first low-pass filter and the second low-pass filter in forward rotation and reverse rotation and outputs phase shift comparison results respectively.

[0008] Two input terminals of the second comparator are respectively coupled to the output of the third low-pass filter and the threshold adjuster and output a phase shift polarity comparison result.

[0009] In a preferred example, the first group of multi-phase orthogonal clock signals includes sequential first to fourth phase clock signals, wherein the first phase clock signal is a 0° phase, the second phase clock signal is a 90° phase, the third phase clock signal is a 180° phase, and the first phase clock signal is a 270° phase; the second group of multi-phase orthogonal clock signals includes sequential first to fourth phase clock signals, wherein the first phase clock signal is a 0° phase, the second phase clock signal is a 90° phase, the third phase clock signal is a 180° phase, and the first phase clock signal is a 270° phase.

[0010] In a preferred embodiment, the system further comprises: second to fourth groups of logic gates, each group of logic gates comprising a first NOR gate, a second NOR gate and an XOR gate, wherein:

[0011] In the second group of logic gates, the two input ends of the first NOR gate receive the second phase clock signal in the first group of multi-phase quadrature clock signals and the third phase clock signal in the second group of multi-phase quadrature clock signals respectively, the two input ends of the second NOR gate receive the fourth phase clock signal in the first group of multi-phase quadrature clock signals and the third phase clock signal in the second group of multi-phase quadrature clock signals respectively, and the two input ends of the XOR gate receive the third phase clock signal in the first group of multi-phase quadrature clock signals and the third phase clock signal in the second group of multi-phase quadrature clock signals respectively;

[0012] In the third group of logic gates, the two input ends of the first NOR gate receive the third phase clock signal in the first group of multi-phase quadrature clock signals and the fourth phase clock signal in the second group of multi-phase quadrature clock signals respectively, the two input ends of the second NOR gate receive the first phase clock signal in the first group of multi-phase quadrature clock signals and the fourth phase clock signal in the second group of multi-phase quadrature clock signals respectively, and the two input ends of the XOR gate receive the fourth phase clock signal in the first group of multi-phase quadrature clock signals and the fourth phase clock signal in the second group of multi-phase quadrature clock signals respectively;

[0013] In the fourth group of logic gates, the two input ends of the first NOR gate respectively receive the fourth phase clock signal in the first group of multi-phase orthogonal clock signals and the first phase clock signal in the second group of multi-phase orthogonal clock signals, the two input ends of the second NOR gate respectively receive the second phase clock signal in the first group of multi-phase orthogonal clock signals and the first phase clock signal in the second group of multi-phase orthogonal clock signals, and the two input ends of the XOR gate respectively receive the first phase clock signal in the first group of multi-phase orthogonal clock signals and the first phase clock signal in the second group of multi-phase orthogonal clock signals.

[0014] In a preferred embodiment, n is 4 or 8.

[0015] In a preferred embodiment, the device further includes: a first output buffer coupled to the output end of the first comparator.

[0016] In a preferred embodiment, the device further includes: a second output buffer coupled to the output end of the second comparator.

[0017] The present application also discloses a control method for phase alignment between multiple groups of multi-phase orthogonal clock signals, comprising:

[0018] Adjust the reversing switch to rotate forward, determine whether the phase shift comparison result jumps relative to the previous beat, whether the phase shift polarity comparison result is equal to 0, and whether the phase shift polarity comparison result jumps relative to the previous beat;

[0019] If the phase shift comparison result jumps relative to the previous beat, the phase shift polarity comparison result is equal to 0, and the phase shift polarity comparison result jumps relative to the previous beat, record the current forward adjustment code;

[0020] Adjust the reversing switch to reverse, determine whether the phase shift comparison result jumps relative to the previous beat, whether the phase shift polarity comparison result is equal to 0, and whether the phase shift polarity comparison result jumps relative to the previous beat;

[0021] If the phase shift comparison result jumps relative to the previous beat, the phase shift polarity comparison result is equal to 0, and the phase shift polarity comparison result jumps relative to the previous beat, record the current inversion adjustment code; and

[0022] The average value of the forward adjustment code and the reverse adjustment code is calculated and output as a final adjustment code.

[0023] In a preferred embodiment, it also includes:

[0024] If the phase shift comparison result does not jump relative to the previous beat; or, the phase shift polarity comparison result is not equal to 0; or, the phase shift polarity comparison result does not jump relative to the previous beat, then adjust the forward adjustment code or the reverse adjustment code, and re-compare to generate a new phase shift comparison result and a new phase shift polarity comparison result.

[0025] In a preferred embodiment, the method further includes: saving the adjustment code into a register.

[0026] In this embodiment, high-frequency clock input is supported, and comparator offset can be offset by calculating the average of two forward and reverse cycles. Furthermore, a threshold adjuster is used to change the output threshold level to control the range of valid polarity, extending the phase detection range to the entire clock cycle.

[0027] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural diagram of a detection circuit suitable for phase alignment between multiple groups of multi-phase orthogonal clock signals according to an embodiment of the present application.

[0029] Figure 2 This is a schematic diagram of the phase alignment relationship between different groups of high-speed four-phase quadrature clocks according to an embodiment of the present application.

[0030] Figure 3 It is a more detailed structural diagram of a phase alignment detection circuit according to an embodiment of the present application.

[0031] Figure 4 It is a flowchart of a control method for phase alignment between multiple groups of multi-phase orthogonal clock signals according to an embodiment of the present application.

[0032] Figure 5 It is a more detailed flowchart of the phase alignment control method according to one embodiment of the present application.

[0033] Figure 6 This is a waveform diagram of a node in a phase alignment detection process according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0035] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0036] In one embodiment of the present application, a detection circuit for phase alignment between multiple groups of multi-phase orthogonal clock signals is provided, wherein the structure of the detection circuit is as follows: Figure 1 As shown, the structure includes: a first group of logic gates Logic1, a first low-pass filter 104, a second low-pass filter 105, a third low-pass filter 109, an inverting switch 106, a first comparator 107, a second comparator 110, and a threshold adjuster 112.

[0037] The first group of logic gates Logic1 includes a first NOR gate 101, a second NOR gate 102, and an XOR gate 103. The two input terminals of the first NOR gate 101 respectively receive the first phase clock signal in the first group of multi-phase quadrature clock signals CLKA and the second phase clock signal in the second group of multi-phase quadrature clock signals CLKB. The two input terminals of the second NOR gate 102 respectively receive the third phase clock signal in the first group of multi-phase quadrature clock signals CLKA and the second phase clock signal in the second group of multi-phase quadrature clock signals CLKB. The two input terminals of the XOR gate 103 respectively receive the second phase clock signal in the first group of multi-phase quadrature clock signals CLKA and the second phase clock signal in the second group of multi-phase quadrature clock signals CLKB.

[0038] The first group of multi-phase quadrature clock signals CLKA and the second group of multi-phase quadrature clock signals CLKB each include sequential first to nth phase clock signals. In one embodiment, n is 4 or 8. For example, when n is 4, the first group of multi-phase quadrature clock signals CLKA and the second group of multi-phase quadrature clock signals CLKB each include four equally spaced phases, namely, 0, 90, 180, and 270. For example, when n is 8, the first group of multi-phase quadrature clock signals CLKA and the second group of multi-phase quadrature clock signals CLKB each include eight equally spaced phases, namely, 0, 45, 90, 135, 180, 225, 270, and 315. In this embodiment, n is 4 as an example, and the first group of multi-phase quadrature clock signals CLKA and the second group of multi-phase quadrature clock signals CLKB are each four-phase quadrature clock signals.

[0039] In one embodiment, the first group of four-phase quadrature clock signals CLKA includes sequential first to fourth phase clock signals, wherein the first phase clock signal is at a 0° phase, the second phase clock signal is at a 90° phase, the third phase clock signal is at a 180° phase, and the first phase clock signal is at a 270° phase, that is, the first phase clock signal CLKA_0, the second phase clock signal CLKA_90, the third phase clock signal CLKA_180, and the fourth phase clock signal CLKA_270. The second group of four-phase quadrature clock signals CLKB includes sequential first to fourth phase clock signals, wherein the first phase clock signal is at a 0° phase, the second phase clock signal is at a 90° phase, the third phase clock signal is at a 180° phase, and the first phase clock signal is at a 270° phase, that is, the first phase clock signal CLKB_0, the second phase clock signal CLKB_90, the third phase clock signal CLKB_180, and the fourth phase clock signal CLKB_270. The phase alignment relationship between the first group of four-phase quadrature clock signals CLKA and the second group of four-phase quadrature clock signals CLKB is as follows: Figure 2 shown.

[0040] like Figure 1 and Figure 2 As shown, the two input ends of the first NOR gate 101 respectively receive the first phase clock signal CLKA_0 in the first group of multi-phase quadrature clock signals CLKA and the second phase clock signal CLKB_90 in the second group of multi-phase quadrature clock signals CLKB, the two input ends of the second NOR gate 102 respectively receive the third phase clock signal CLKA_180 in the first group of multi-phase quadrature clock signals CLKA and the second phase clock signal CLKB_90 in the second group of multi-phase quadrature clock signals CLKB, and the two input ends of the XOR gate 103 respectively receive the second phase clock signal CLKA_90 in the first group of multi-phase quadrature clock signals CLKA and the second phase clock signal CLKB_90 in the second group of multi-phase quadrature clock signals CLKB.

[0041] First low-pass filter 104, second low-pass filter 105, and third low-pass filter 109 are coupled to the outputs of first NOR gate 101, second NOR gate 102, and XOR gate 103, respectively. Specifically, first low-pass filter 104 is coupled to the output of first NOR gate 101. Second low-pass filter 105 is coupled to the output of second NOR gate 102. Third low-pass filter 109 is coupled to the output of XOR gate 103.

[0042] The reversing switch 106 is coupled to the outputs of the first low-pass filter 104 and the second low-pass filter 105 respectively and inputs the output signals of the first low-pass filter 104 and the second low-pass filter 105 in forward rotation and reverse rotation to the two input terminals of the first comparator 107 respectively.

[0043] The first comparator 107 compares the output signals of the first low-pass filter 104 and the second low-pass filter 105 during forward and reverse rotation and outputs a phase shift comparison result Phdet_Shift, respectively. In one embodiment, the detection circuit further includes a first output buffer 108 coupled to the output terminal of the first comparator 107.

[0044] The second comparator 107 has two input terminals coupled to the output of the third low-pass filter 109 and the threshold regulator, and outputs a phase shift polarity comparison result Phdet_Polarity. In one embodiment, the detection circuit further includes a second output buffer 111 coupled to the output terminal of the second comparator 110.

[0045] Taking two sets of high-speed quadrature signals, CLKA_0 / CLKA_90 / CLKA_180 / CLKA_270 and CLKB_0 / CLKB_90 / CLKB_180 / CLKB_270, as examples, the detection circuit system includes a phase lead detection module between different signal sets. After CLKA_90 and CLKB_0, and CLKA_90 and CLKB_180, respectively, pass through NOR logic gates (e.g., NOR gates 101 and 102), low-pass resistor-capacitor filters (e.g., low-pass filters 104 and 105) convert the phase difference into a corresponding DC level. A post-comparator 107 compares the two sets of DC levels and outputs a comparison result (Phase shift 1'b) to indicate phase lead / lag. An input port inverting switch 106 is added to the input of comparator 107. The final comparison result is averaged twice, and the phase is then forward- and reverse-scanned to offset the comparator's offset.

[0046] The detection circuit system includes a phase polarity detection module for different signal groups. After passing CLKA_90 and CLKB_90 through an XOR logic gate (e.g., XOR gate 103), a low-pass resistor-capacitor filter (e.g., low-pass filter 109) converts the phase difference into a corresponding DC level. This level is then compared with the level generated by a polarity threshold control module (e.g., threshold adjuster 112) via a post-comparator 110. The comparison result (Phase Polarity 1'b) indicates whether the phase polarities of the two clock groups are consistent. The phase polarity threshold control module for different signal groups is designed to extend the phase detection range to the entire clock cycle. The phase polarity threshold control module controls the range of valid polarities by varying the output threshold level.

[0047] In each detection judgment cycle, the comparison results Phdet_shift and Phdet_Polarity are output and used in conjunction with each other. In the digital domain, Phdet_shift is continuously detected to see if it has jumped compared to the previous beat. When the level of Phdet_shift jumps and Phdet_Polarity == 0, the two sets of signals in the current state are in phase alignment. Record the register value in the current positive adjustment state (forward adjustment code), flip the output of the comparator, repeat the above judgment, and after obtaining the negative adjustment state register value (reverse adjustment code) and the positive result, average them, and the phase detection judgment process ends.

[0048] In order to avoid destroying the orthogonal characteristics of the multi-phase signal during phase detection, it is necessary to make the same OR logic and XOR logic load matching circuit for each phase signal path. Therefore, the detection circuit of the present application also includes a load balancing module (or redundancy) between different groups of signals. In one embodiment, the detection circuit also includes: a second group of logic gates Logic2, a third group of logic gates Logic3, and a fourth group of logic gates Logic4. The structure of each group of logic gates is the same as that of the first group of logic gates, and each group includes a first NOR gate, a second NOR gate and an XOR gate. Figure 3 It should be understood that the second group of logic gates Logic2, the third group of logic gates Logic3 and the fourth group of logic gates Logic4 are used for redundancy.

[0049] The second group of logic gates Logic2 includes a first NOR gate 113, a second NOR gate 114, and an XOR gate 115. The two input terminals of the first NOR gate 113 receive the second phase clock signal CLKA_90 in the first group of multi-phase quadrature clock signals CLKA and the third phase clock signal CLKB_180 in the second group of multi-phase quadrature clock signals CLKB, respectively. The two input terminals of the second NOR gate 115 receive the fourth phase clock signal CLKA_270 in the first group of multi-phase quadrature clock signals CLKA and the third phase clock signal CLKB_180 in the second group of multi-phase quadrature clock signals CLKB, respectively. The two input terminals of the XOR gate 116 receive the third phase clock signal CLKA_180 in the first group of multi-phase quadrature clock signals CLKA and the third phase clock signal CLKB_180 in the second group of multi-phase quadrature clock signals CLKB, respectively.

[0050] The third group of logic gates Logic2 includes a first NOR gate 116, a second NOR gate 117, and an XOR gate 118. The two input terminals of the first NOR gate 116 receive the third phase clock signal CLKA_180 in the first group of multi-phase quadrature clock signals CLKA and the fourth phase clock signal CLKB_270 in the second group of multi-phase quadrature clock signals CLKB, respectively. The two input terminals of the second NOR gate 117 receive the first phase clock signal CLKA_0 in the first group of multi-phase quadrature clock signals CLKA and the fourth phase clock signal CLKB_270 in the second group of multi-phase quadrature clock signals CLKB, respectively. The two input terminals of the XOR gate 118 receive the fourth phase clock signal CLKA_270 in the first group of multi-phase quadrature clock signals CLKA and the fourth phase clock signal CLKB_270 in the second group of multi-phase quadrature clock signals CLKB, respectively.

[0051] The fourth group of logic gates Logic2 includes a first NOR gate 119, a second NOR gate 120, and an XOR gate 121. The two input ends of the first NOR gate 119 respectively receive the fourth phase clock signal CLKA_270 in the first group of multi-phase quadrature clock signals CLKA and the first phase clock signal CLKB_0 in the second group of multi-phase quadrature clock signals CLKB. The two input ends of the second NOR gate 120 respectively receive the second phase clock signal CLKA_90 in the first group of multi-phase quadrature clock signals CLKA and the first phase clock signal CLKB_0 in the second group of multi-phase quadrature clock signals CLKB. The two input ends of the XOR gate 121 respectively receive the first phase clock signal CLKA_0 in the first group of multi-phase quadrature clock signals CLKA and the first phase clock signal CLKB_0 in the second group of multi-phase quadrature clock signals CLKB.

[0052] The embodiment of the present application also discloses a control method for phase alignment between multiple groups of multi-phase orthogonal clock signals, the flow chart of which is referenced as follows: Figure 4 As shown, the method includes the following steps:

[0053] Step 201 , adjust the reversing switch 106 to rotate forward, determine whether the phase shift comparison result Phdet_Shift jumps relative to the previous beat, whether the phase shift polarity comparison result Phdet_Polarity is equal to 0, and whether the phase shift polarity comparison result Phdet_Polarity jumps relative to the previous beat.

[0054] Step 202: If the phase shift comparison result Phdet_Shift changes relative to the previous beat, the phase shift polarity comparison result Phdet_Polarity is equal to 0, and the phase shift polarity comparison result Phdet_Polarity changes relative to the previous beat, record the current forward adjustment code.

[0055] In one embodiment, the method further includes: if the phase shift comparison result Phdet_Shift does not jump relative to the previous beat; or, the phase shift polarity comparison result Phdet_Polarity is not equal to 0; or, the phase shift polarity comparison result Phdet_Polarity does not jump relative to the previous beat, then adjusting the forward adjustment code, and re-comparing to generate a new phase shift comparison result Phdet_Shift and a new phase shift polarity comparison result Phdet_Polarity.

[0056] The conversion of the adjustment code to a specific physical waveform is achieved through a phase interpolator, which is a processing unit that converts changes in the digital domain control code into changes in the waveform phase.

[0057] Step 203 , adjust the reversal switch 106 to reverse, and determine whether the phase shift comparison result Phdet_Shift jumps relative to the previous beat, whether the phase shift polarity comparison result Phdet_Polarity is equal to 0, and whether the phase shift polarity comparison result Phdet_Polarity jumps relative to the previous beat.

[0058] Step 204 : If the phase shift comparison result Phdet_Shift changes relative to the previous beat, the phase shift polarity comparison result Phdet_Polarity is equal to 0, and the phase shift polarity comparison result Phdet_Polarity changes relative to the previous beat, record the current inversion adjustment code.

[0059] In one embodiment, the method further includes: if the phase shift comparison result Phdet_Shift does not jump relative to the previous beat; or, the phase shift polarity comparison result Phdet_Polarity is not equal to 0; or, the phase shift polarity comparison result Phdet_Polarity does not jump relative to the previous beat, then adjusting the inversion adjustment code, and re-comparing to generate a new phase shift comparison result Phdet_Shift and a new phase shift polarity comparison result Phdet_Polarity.

[0060] Step 205: Calculate the average value of the forward adjustment code and the reverse adjustment code and output it as the final adjustment code. In one embodiment, the method further includes: storing the adjustment code in a register.

[0061] like Figure 5 As shown, the control method comprises the following steps: Figure 6 A schematic diagram of the phase alignment detection process node waveform is shown. Figure 6 It describes the state changes of the phase detector outputs phdet_shift and phdet_polarity during the dynamic process of waveform phase alignment in the time domain. The dotted line represents the process of CLKB edge adjustment changes under the above control flow.

[0062] First, phase adjustment begins and the register outputs are initialized.

[0063] Next, the adjustment is prepared, the comparator input is reversed comp_input_swap = 0, the comparator generates a phase shift comparison result Phdet_Shift and a phase shift polarity comparison result Phdet_Polarity, and the forward adjustment is adjusted. After that, the phase alignment is detected (determine whether phdet_shift has jumped compared to the previous beat), the polarity is detected to be correct (determine whether phdet_polarity == 0), and the polarity is detected to be stable (determine whether phdet_polarity has jumped compared to the previous beat). When the above three conditions of phase alignment, correct polarity, and stable polarity are met at the same time, the current adjustment code1 value is recorded, that is, the forward adjustment is completed. It should be noted that when any of the above three conditions of phase alignment, correct polarity, and stable polarity are not met, the inverted adjustment code is adjusted, and a new phase shift comparison result Phdet_Shift and a new phase shift polarity comparison result Phdet_Polarity are re-compared and generated, and re-detected until the three adjustments are met.

[0064] Again, adjustment preparation, comparator input inversion comp_input_swap = 1, the comparator generates a phase shift comparison result Phdet_Shift and a phase shift polarity comparison result Phdet_Polarity, and adjusts the negative adjustment. After that, detect phase alignment (determine whether phdet_shift has jumped compared to the previous beat), detect correct polarity (determine phdet_polarity == 0), and detect polarity stability (determine whether phdet_polarity has jumped compared to the previous beat). When the above three phase alignment, correct polarity, and stable polarity conditions are met at the same time, the current adjustment code2 value is recorded, that is, the inversion adjustment is completed. It should be noted that when any of the above three phase alignment, correct polarity, and stable polarity conditions are not met, the inversion adjustment code is adjusted, and the new phase shift comparison result Phdet_Shift and the new phase shift polarity comparison result Phdet_Polarity are re-compared and generated, and re-detected until the three adjustments are met.

[0065] Finally, the average of code1 and code2 is calculated as the final output.

[0066] It should be noted that in this patent application, relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element specified by the phrase "comprising a" does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element. In this patent application, reference to performing an action in accordance with an element means performing the action in accordance with at least that element, including two situations: performing the action in accordance with that element alone, and performing the action in accordance with that element and other elements. Expressions such as "plurality," "multiple times," and "many" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0067] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0068] This specification includes combinations of the various embodiments described herein. Separate references to an embodiment (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as such or clear to one skilled in the art. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0069] All documents mentioned in this specification are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above description is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

[0070] In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. Additionally, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A detection circuit for phase alignment between multiple sets of multi-phase orthogonal clock signals, characterized in that: include: A first group of logic gates, a first low-pass filter, a second low-pass filter, a third low-pass filter, an inverting switch, a first comparator, a second comparator, and a threshold adjuster; The first group of logic gates includes a first NOR gate, a second NOR gate and an XOR gate, wherein two input ends of the first NOR gate receive a first phase clock signal in the first group of multi-phase quadrature clock signals and a second phase clock signal in the second group of multi-phase quadrature clock signals respectively, two input ends of the second NOR gate receive a third phase clock signal in the first group of multi-phase quadrature clock signals and a second phase clock signal in the second group of multi-phase quadrature clock signals respectively, and two input ends of the XOR gate receive a second phase clock signal in the first group of multi-phase quadrature clock signals and a second phase clock signal in the second group of multi-phase quadrature clock signals respectively, wherein the first group of multi-phase quadrature clock signals and the second group of multi-phase quadrature clock signals each include a first to an nth phase clock signal in sequence, wherein the first to nth phase clock signals are 0° phase, 360°*2 / n phase, 360°*3 / n phase, ..., 360°*(n-1) / n phase in sequence, and n is 4 or 8; The first low-pass filter, the second low-pass filter and the third low-pass filter are respectively coupled to the outputs of the first NOR gate, the second NOR gate and the XOR gate; The reversing switch is coupled to the outputs of the first low-pass filter and the second low-pass filter respectively and inputs the output signals of the first low-pass filter and the second low-pass filter in forward rotation and reverse rotation into two input terminals of the first comparator respectively. The first comparator compares the output signals of the first low-pass filter and the second low-pass filter in forward rotation and reverse rotation and outputs phase shift comparison results respectively. The two input ends of the second comparator are respectively coupled to the output of the third low-pass filter and the threshold regulator and output a phase shift polarity comparison result; the phase shift polarity comparison result is continuously detected in the digital domain and it is determined whether a jump occurs compared with the previous beat. When the phase offset comparison result has a level jump, the phase shift polarity comparison result has a level jump, and the phase shift polarity comparison result is ==0, the current forward adjustment code is recorded, the reverse switch is flipped, and the above judgment is repeated to obtain the reverse adjustment code and average it with the forward adjustment code.

2. The detection circuit according to claim 1, characterized in that The first group of multi-phase orthogonal clock signals includes sequential first to fourth phase clock signals, wherein the first phase clock signal is at a 0° phase, the second phase clock signal is at a 90° phase, the third phase clock signal is at a 180° phase, and the first phase clock signal is at a 270° phase; the second group of multi-phase orthogonal clock signals includes sequential first to fourth phase clock signals, wherein the first phase clock signal is at a 0° phase, the second phase clock signal is at a 90° phase, the third phase clock signal is at a 180° phase, and the first phase clock signal is at a 270° phase.

3. The detection circuit according to claim 2, characterized in that: Also includes: The second to fourth groups of logic gates, each group of logic gates includes a first NOR gate, a second NOR gate and an XOR gate, wherein: In the second group of logic gates, the two input ends of the first NOR gate receive the second phase clock signal in the first group of multi-phase quadrature clock signals and the third phase clock signal in the second group of multi-phase quadrature clock signals respectively, the two input ends of the second NOR gate receive the fourth phase clock signal in the first group of multi-phase quadrature clock signals and the third phase clock signal in the second group of multi-phase quadrature clock signals respectively, and the two input ends of the XOR gate receive the third phase clock signal in the first group of multi-phase quadrature clock signals and the third phase clock signal in the second group of multi-phase quadrature clock signals respectively; In the third group of logic gates, the two input ends of the first NOR gate receive the third phase clock signal in the first group of multi-phase quadrature clock signals and the fourth phase clock signal in the second group of multi-phase quadrature clock signals respectively, the two input ends of the second NOR gate receive the first phase clock signal in the first group of multi-phase quadrature clock signals and the fourth phase clock signal in the second group of multi-phase quadrature clock signals respectively, and the two input ends of the XOR gate receive the fourth phase clock signal in the first group of multi-phase quadrature clock signals and the fourth phase clock signal in the second group of multi-phase quadrature clock signals respectively; In the fourth group of logic gates, the two input ends of the first NOR gate respectively receive the fourth phase clock signal in the first group of multi-phase orthogonal clock signals and the first phase clock signal in the second group of multi-phase orthogonal clock signals, the two input ends of the second NOR gate respectively receive the second phase clock signal in the first group of multi-phase orthogonal clock signals and the first phase clock signal in the second group of multi-phase orthogonal clock signals, and the two input ends of the XOR gate respectively receive the first phase clock signal in the first group of multi-phase orthogonal clock signals and the first phase clock signal in the second group of multi-phase orthogonal clock signals.

4. The detection circuit according to claim 1, characterized in that: Also includes: A first output buffer is coupled to an output terminal of the first comparator.

5. The detection circuit according to claim 1, wherein: Also includes: A second output buffer is coupled to an output terminal of the second comparator.

6. A control method for phase alignment between multiple sets of multi-phase orthogonal clock signals, using the detection circuit for phase alignment between multiple sets of multi-phase orthogonal clock signals according to any one of claims 1 to 5, characterized in that: include: Adjust the reversing switch to rotate forward, determine whether the phase shift comparison result jumps relative to the previous beat, whether the phase shift polarity comparison result is equal to 0, and whether the phase shift polarity comparison result jumps relative to the previous beat; If the phase shift comparison result jumps relative to the previous beat, the phase shift polarity comparison result is equal to 0, and the phase shift polarity comparison result jumps relative to the previous beat, record the current forward adjustment code; Adjust the reversing switch to reverse, determine whether the phase shift comparison result jumps relative to the previous beat, whether the phase shift polarity comparison result is equal to 0, and whether the phase shift polarity comparison result jumps relative to the previous beat; If the phase shift comparison result jumps relative to the previous beat, the phase shift polarity comparison result is equal to 0, and the phase shift polarity comparison result jumps relative to the previous beat, record the current inversion adjustment code; as well as The average value of the forward adjustment code and the reverse adjustment code is calculated and output as a final adjustment code.

7. The control method according to claim 6, characterized in that: Also includes: If the phase shift comparison result does not jump relative to the previous beat; or, the phase shift polarity comparison result is not equal to 0; or, the phase shift polarity comparison result does not jump relative to the previous beat, then adjust the forward adjustment code or the reverse adjustment code, and re-compare to generate a new phase shift comparison result and a new phase shift polarity comparison result.

8. The control method according to claim 6, characterized in that: Also includes: The adjustment code is stored in a register.

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