Micro LEDs, Micro LED Array Panels and Their Manufacturing Methods

Abstract

A micro LED includes: a first type of semiconductor layer; and a light-emitting layer formed on the first type of semiconductor layer; wherein the first type of semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure by the trench, wherein the ion implantation fence is formed around the trench, and the trench is formed around the mesa structure; and the resistance of the ion implantation fence is higher than the resistance of the mesa structure.

Description

Technical Field

[0001] This disclosure generally relates to a light-emitting diode, and more specifically to a miniature light-emitting diode (LED), a miniature LED array panel, and a method of manufacturing the same. Background Technology

[0002] Inorganic micro-pixel light-emitting diodes (also known as micro-LEDs, micro-LEDs, or μ-LEDs) are becoming increasingly important due to their applications in a wide range of fields, including self-emitting microdisplays, visible light communication, and optogenetics. Micro-LEDs exhibit higher output performance than conventional LEDs due to better strain relaxation, improved light extraction efficiency, and uniform current spread. Compared to conventional LEDs, micro-LEDs also exhibit improved thermal effects, faster response rates, a wider operating temperature range, higher resolution, color gamut and contrast, lower power consumption, and the ability to operate at higher current densities.

[0003] Inorganic microLEDs are typically formed as a III-V group epitaxial layer with multiple mesa. In traditional microLED structures, spaces are formed between adjacent microLEDs to prevent carriers in the epitaxial layer from diffusing from one mesa to the next. However, these spaces can reduce the effective light-emitting area and decrease light extraction efficiency. If there are no spaces between adjacent microLEDs, the effective light-emitting area will increase, and carriers in the epitaxial layer will diffuse laterally to adjacent mesa, reducing the luminous efficiency of the microLED. Furthermore, if no spaces are formed between adjacent mesa, crosstalk will occur between adjacent microLEDs, interfering with their operation.

[0004] However, smaller microLEDs with higher current densities experience redshift, lower maximum efficiency, and non-uniform emission at high current densities, attributed to manufacturing process damage that leads to degraded current injection. Furthermore, peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) decrease significantly with decreasing chip size. The reduced EQE is due to nonradiative recombination caused by etching damage, while the reduced IQE is attributed to poor current injection and electron leakage current in the microLED.

[0005] The above discussion is provided only to help understand the technical problems overcome by this disclosure and does not constitute an admission that the above is prior art. Summary of the Invention

[0006] Embodiments of this disclosure provide a micro LED. The micro LED includes: a first type semiconductor layer; and a light-emitting layer formed on the first type semiconductor layer; wherein the first type semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure by the trench, wherein the ion implantation fence is formed around the trench, and the trench is formed around the mesa structure; and the resistance of the ion implantation fence is higher than the resistance of the mesa structure.

[0007] This disclosure provides a micro LED array panel. The micro LED array panel includes: a first type semiconductor layer formed therein; a light-emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light-emitting layer; wherein the first type semiconductor layer is P-type conductive and the second type semiconductor layer is N-type conductive; the first type semiconductor layer includes a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches; the top surface of the ion implantation fences is lower than the top surface of the first type semiconductor layer; the ion implantation fences are formed in the trenches between adjacent mesa structures; and the resistance of the ion implantation fences is higher than the resistance of the mesa structures.

[0008] Embodiments of this disclosure provide a method for manufacturing micro LEDs. The method includes: providing an epitaxial structure, wherein the epitaxial structure comprises, from top to bottom, a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer; patterning the first type semiconductor layer to form a mesa structure, trenches, and enclosures; depositing bottom contacts on the mesa structure; and performing an ion implantation process into the enclosures to form an ion-implanted enclosure.

[0009] Embodiments of this disclosure provide a micro LED. The micro LED includes: a first type semiconductor layer; a light-emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light-emitting layer; wherein the first type semiconductor layer is P-type conductive and the second type semiconductor layer is N-type conductive; the second type semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure; wherein the bottom surface of the ion implantation fence is higher than the bottom surface of the second type semiconductor layer; and the ion implantation fence is formed around the trench, the trench being formed around the mesa structure, wherein the resistance of the ion implantation fence is higher than the resistance of the mesa structure.

[0010] Embodiments of this disclosure provide a micro LED array panel. The micro LED array panel includes: a first type semiconductor layer formed therein; a light-emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light-emitting layer; wherein the first type semiconductor layer is P-type conductive and the second type semiconductor layer is N-type conductive; the second type semiconductor layer includes a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches; wherein the bottom surface of the ion implantation fences is higher than the bottom surface of the second type semiconductor layer; the ion implantation fences are formed in the trenches between adjacent mesa structures; and the resistance of the ion implantation fences is higher than the resistance of the mesa structures.

[0011] Embodiments of this disclosure provide a method for manufacturing micro LEDs. The method includes: providing an epitaxial structure, wherein the epitaxial structure comprises, from top to bottom, a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer; bonding the epitaxial structure to an integrated circuit (IC) backplane; patterning the second type semiconductor layer to form a mesa structure, trenches, and enclosures; depositing top contacts on the mesa structure; performing an ion implantation process into the enclosures; and depositing a top conductive layer on the top surface of the second type semiconductor layer, on the top contacts, and in the trenches.

[0012] This disclosure provides a micro LED. The micro LED includes: a first type semiconductor layer; a light-emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light-emitting layer; wherein the first type semiconductor layer is P-type conductive and the second type semiconductor layer is N-type conductive; the first type semiconductor layer includes a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure; wherein the top surface of the first ion implantation fence is lower than the top surface of the first type semiconductor layer; the second type semiconductor layer includes a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure; wherein the bottom surface of the second ion implantation fence is higher than the bottom surface of the second type semiconductor layer; the first ion implantation fence is formed around the first trench, and the first trench is formed around the first mesa structure, wherein the resistance of the first ion implantation fence is higher than the resistance of the first mesa structure; and the second ion implantation fence is formed around the second trench, and the second trench is formed around the second mesa structure, wherein the resistance of the second ion implantation fence is higher than the resistance of the second mesa structure.

[0013] This disclosure provides a micro LED array panel. The micro LED array panel includes: a first type semiconductor layer formed therein; a light-emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light-emitting layer; wherein the first type semiconductor layer is P-type and the second type semiconductor layer is N-type; the first type semiconductor layer includes a plurality of first mesa structures, a plurality of first trenches, and a plurality of first ion implantation fences separated from the first mesa structures by the first trenches; wherein the top surface of the first ion implantation fences is aligned with or lower than the top surface of the first type semiconductor layer; First ion implantation fences are formed in first trenches between adjacent first-type mesa structures, wherein the resistance of the first ion implantation fences is higher than the resistance of the first mesa structures; the second-type semiconductor layer includes a plurality of second mesa structures, a plurality of second trenches, and a plurality of second ion implantation fences separated from the second mesa structures by the second trenches; wherein the bottom surface of the second ion implantation fences is aligned with or higher than the bottom surface of the second-type semiconductor layer; and the second ion implantation fences are formed in second trenches between adjacent second mesa structures, wherein the resistance of the second ion implantation fences is higher than the resistance of the second mesa structures.

[0014] Embodiments of this disclosure provide a method for manufacturing micro LEDs. The method includes: process I, which includes patterning a first type of semiconductor layer and implanting a first ion into the first type of semiconductor layer; and process II, which includes patterning a second type of semiconductor layer and implanting a second ion into the second type of semiconductor layer. Attached Figure Description

[0015] Embodiments and aspects of this disclosure are illustrated in the following detailed description and accompanying drawings. The various features shown in the drawings are not drawn to scale.

[0016] Figures 1A to 1F This is a structural diagram showing various different variations of a first exemplary microLED according to some embodiments of this disclosure.

[0017] Figure 2 This is a structural diagram showing a bottom view of a first exemplary microLED according to some embodiments of this disclosure.

[0018] Figure 3 This is a structural diagram showing a side cross-sectional view of another variant of a first exemplary microLED according to some embodiments of this disclosure.

[0019] Figure 4 This is a structural diagram showing a side cross-sectional view of another variant of a first exemplary microLED according to some embodiments of this disclosure.

[0020] Figure 5 A flowchart is shown of a method for manufacturing a first exemplary microLED according to some embodiments of this disclosure.

[0021] Figures 6A to 6J This illustrates some embodiments according to this disclosure. Figure 5 A structural diagram of a side cross-sectional view of the micro-LED manufacturing process at each step of the method shown.

[0022] Figure 7 This illustrates some embodiments according to this disclosure. Figure 1A A structural diagram showing a side cross-sectional view of an adjacent microLED within a microLED.

[0023] Figure 8 This illustrates some embodiments according to this disclosure. Figure 7 The structural diagram of the bottom view of adjacent micro-LEDs.

[0024] Figure 9 This illustrates some embodiments according to this disclosure. Figure 3 A structural diagram showing a side cross-sectional view of an adjacent microLED within a microLED.

[0025] Figures 10A to 10F This is a structural diagram showing a side cross-sectional view of various different variants of a second exemplary microLED according to some embodiments of this disclosure.

[0026] Figure 11 This is a top view structural diagram showing a second exemplary microLED according to some embodiments of this disclosure.

[0027] Figure 12 This is a structural diagram showing a side cross-sectional view of another variant of a second exemplary microLED according to some embodiments of this disclosure.

[0028] Figure 13 This is a structural diagram showing a side cross-sectional view of another variant of a second exemplary microLED according to some embodiments of this disclosure.

[0029] Figure 14 A flowchart is shown of a method for manufacturing a second exemplary microLED according to some embodiments of this disclosure.

[0030] Figures 15A to 15F This illustrates some embodiments according to this disclosure. Figure 14 A structural diagram of a side cross-sectional view of the micro-LED manufacturing process at each step of the method shown.

[0031] Figure 16 This illustrates some embodiments according to this disclosure. Figure 10A A structural diagram showing a side cross-sectional view of an adjacent microLED within a microLED.

[0032] Figure 17 This illustrates some embodiments according to this disclosure. Figure 16 A top-view structural diagram of adjacent micro-LEDs.

[0033] Figure 18 This illustrates some embodiments according to this disclosure. Figure 13 A structural diagram showing a side cross-sectional view of an adjacent microLED within a microLED.

[0034] Figure 19 This is a structural diagram showing a side cross-sectional view of a variant of a third exemplary microLED according to some embodiments of this disclosure.

[0035] Figure 20 This is a structural diagram showing a side cross-sectional view of another variant of a third exemplary microLED according to some embodiments of this disclosure.

[0036] Figure 21 A flowchart is shown of a method for manufacturing a third exemplary microLED according to some embodiments of this disclosure.

[0037] Figures 22A to 22D This illustrates some embodiments according to this disclosure. Figure 21 The diagram shows a structural view of the micro-LED manufacturing process at steps 2110 to 2113 of the method shown.

[0038] Figure 23 This illustrates some embodiments according to this disclosure. Figure 19 A structural diagram showing a side cross-sectional view of an adjacent microLED within a microLED.

[0039] Figure 24 This illustrates some embodiments according to this disclosure. Figure 20 A structural diagram showing a side cross-sectional view of an adjacent microLED within a microLED. Detailed Implementation

[0040] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein the same numerals in different drawings denote the same or similar elements unless otherwise indicated. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the present invention. Rather, they are merely examples of devices and methods consistent with the aspects listed in the appended claims and relevant to the present invention. Specific aspects of this disclosure are described below in more detail. In the event of any conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall prevail.

[0041] This disclosure provides a micro-LED that avoids nonradiative recombination at the sidewalls of mesa by utilizing the structure of the semiconductor layer and the continuously formed light-emitting layer. Furthermore, compared to conventional micro-LEDs, the space between adjacent mesa can be significantly reduced due to ion implantation fencing. Therefore, the integration density of the micro-LED within the chip is increased, and the effective luminous efficiency is improved. In addition, the micro-LED provided by this disclosure can also increase the effective light-emitting area and improve image quality.

[0042] Implementation Plan 1

[0043] Figures 1A to 1F This is a structural diagram showing various different variations of a first exemplary microLED according to some embodiments of this disclosure.

[0044] refer to Figures 1A to 1F The micro LED includes a first type semiconductor layer 110, a light-emitting layer 130, and a second type semiconductor layer 120. The light-emitting layer 130 is formed on the first type semiconductor layer 110, and the second type semiconductor layer 120 is formed on the light-emitting layer 130. The thickness of the first type semiconductor layer 110 is greater than the thickness of the second type semiconductor layer 120.

[0045] The conductivity type of the first type semiconductor layer 110 differs from that of the second type semiconductor layer 120. In some embodiments, the conductivity type of the first type semiconductor layer 110 is P-type, and the conductivity type of the second type semiconductor layer 120 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 120 is P-type, and the conductivity type of the first type semiconductor layer 110 is N-type. For example, the material of the first type semiconductor layer 110 may be selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 120 may be selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0046] The first type of semiconductor layer 110 includes a mesa structure 111, a trench 112, and an ion implantation fence 113. The ion implantation fence 113 is separated from the mesa structure 111 by the trench 112. The trench 112 and the ion implantation fence 113 are annular around the mesa structure 111. Figure 2 This illustrates some embodiments according to this disclosure, such as... Figures 1A to 1F The diagram shows a structural view of the bottom of the first exemplary micro-LED. Figure 2 A bottom view of a first-type semiconductor layer 110 is shown, wherein an ion implantation fence 113 is separated from a mesa structure 111 by a trench 112. The ion implantation fence 113 is formed around the trench 112, and the trench 112 is formed around the mesa structure 111.

[0047] The ion implantation fence 113 includes a light-absorbing material for absorbing light from the mesa structure 111. The conductivity type of the light-absorbing material is the same as that of the first type semiconductor layer 110. Preferably, the light-absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. Furthermore, the ion implantation fence 113 is formed at least by implanting ions into the first type semiconductor layer 110. Preferably, the ion type implanted into the first type semiconductor layer 110 is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0048] Furthermore, the width of the ion implantation fence 113 is no greater than 50% of the diameter of the mesa structure 111. In some embodiments, the width of the ion implantation fence 113 is no greater than 10% of the diameter of the mesa structure 111. Preferably, the width of the ion implantation fence 113 is no greater than 200 nm, the diameter of the mesa structure 111 is no greater than 2500 nm, and the thickness of the first type semiconductor layer 110 is no greater than 300 nm.

[0049] In some embodiments, the width of the trench 112 is no greater than 50% of the diameter of the mesa structure 111. In some embodiments, the width of the trench 112 is no greater than 10% of the diameter of the mesa structure 111. Preferably, the width of the trench 112 is no greater than 200 nm.

[0050] There is no limitation on the depth of trench 112. In some embodiments, trench 112 may extend upward through the first type semiconductor layer 110 but not reach the light-emitting layer 130. In some embodiments, trench 112 may extend upward through the first type semiconductor layer 110 and reach the light-emitting layer 130. In some embodiments, trench 112 may extend upward through the first type semiconductor layer 110 and extend into the interior of the light-emitting layer 1030. In some embodiments, trench 112 may extend upward through both the first type semiconductor layer 110 and the light-emitting layer 130. Furthermore, trench 112 may extend upward through both the first type semiconductor layer 110 and the light-emitting layer 130, and extend upward into the interior of the second type semiconductor layer 120.

[0051] like Figure 1A As shown, in some embodiments, trench 112 extends upward without penetrating the top surface of the first type semiconductor layer 110. The top surface of trench 112 is lower than the top surface of the first type semiconductor layer 110. Therefore, the top surface of trench 112 does not contact the light-emitting layer 130.

[0052] In this embodiment, the top surface of the ion implantation fence 113 is lower than the top surface of the first type semiconductor layer 110. The top surface of the ion implantation fence 113 can be formed at any location within the first type semiconductor layer 110. Preferably, as Figure 1A As shown, the top surface of the ion implantation fence 113 is higher than the top surface of the trench 112. It should be noted that, as Figure 1B As shown, in some embodiments, the top surface of the ion implantation fence 113 is aligned with the top surface of the trench 112. For example... Figure 1C As shown, in some embodiments, the top surface of the ion implantation fence 113 is lower than the top surface of the trench 112. Additionally, the bottom surface of the ion implantation fence 113 can be formed at any location above or below the bottom surface of the first type semiconductor layer 110. Preferably, the bottom surface of the ion implantation fence 113 is aligned with the bottom surface of the first type semiconductor layer 110. Figure 1D As shown, in some embodiments, the bottom surface of the ion implantation fence 113 is higher than the bottom surface of the first type semiconductor layer 110. For example... Figure 1E As shown, in some embodiments, the bottom surface of the ion implantation fence 113 is lower than the bottom surface of the first type semiconductor layer 110.

[0053] In some implementation schemes, such as Figure 1F As shown, the platform structure 111 includes a stepped structure 111a. The platform structure 111 may have one or more stepped structures.

[0054] Figure 3This is a structural diagram showing a side cross-sectional view of another variant of a first exemplary microLED according to some embodiments of this disclosure. Figure 3 As shown, the micro-LED further includes a bottom insulating layer 140 filled in the trench 112. Preferably, the material of the bottom insulating layer 140 is selected from SiO2 and SiN. x One or more of Al2O3, AlN, HfO2, TiO2 or ZrO2.

[0055] In this embodiment, the IC (integrated circuit) backplane 190 is formed beneath the first type semiconductor layer 110 and is electrically connected to the first type semiconductor layer 110 via an interconnect structure 150. For example... Figure 3 As shown, the connecting structure 150 is a connecting support.

[0056] The micro-LED further includes a bottom contact 160. The bottom contact 160 is formed at the bottom of the first type semiconductor layer 110. The upper surface of the connection structure 150 is connected to the bottom contact 160, and the bottom surface of the connection structure 150 is connected to the IC backplane 190. Figure 3 As shown, the bottom contact 160 protrudes from the first type semiconductor layer 110 and serves as the bottom contact of the micro LED.

[0057] In some embodiments, the microLED further includes a top contact 180 and a top conductive layer 170. The top contact 180 is formed on top of the second type semiconductor layer 120. The top conductive layer 170 is formed on top of the second type semiconductor layer 120 and on the top contact 180. The conductivity type of the top contact 180 is the same as that of the second type semiconductor layer 120. For example, in some embodiments, the conductivity type of the second type semiconductor layer 120 is N-type, and the conductivity type of the top contact 180 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 120 is P-type, and the conductivity type of the top contact 180 is P-type. The top contact 180 is made of a metal or metal alloy (such as AuGe, AuGeNi, etc.). The top contact 180 is used to form an ohmic contact between the top conductive layer 170 and the second type semiconductor layer 120 to optimize the electrical properties of the microLED. The top contact 180 has a diameter of approximately 20 nm to 50 nm and a thickness of approximately 10 nm to 20 nm. In some embodiments, a dielectric layer is formed between the top conductive layer and the second type semiconductor layer.

[0058] Figure 4 This is a structural diagram showing a side cross-sectional view of another variant of a first exemplary microLED according to some embodiments of this disclosure. Figure 4As shown, the connection structure 150 is a metal bonding layer used to bond the micro-LED to the IC backplane 190. Additionally, in this variant, the bottom contact 160 is a bottom contact layer.

[0059] Figure 5 The present disclosure illustrates some embodiments for manufacturing a first exemplary microLED (e.g., Figure 3 The flowchart shows a method 500 for manufacturing a microLED. The method 500 for manufacturing a microLED includes steps 501 to 510. Figures 6A to 6J This illustrates some embodiments of the present disclosure in relation to... Figure 5 The diagram shows a structural view of the micro-LED manufacturing process at each step (i.e., steps 501 to 510) corresponding to the method 500 shown.

[0060] refer to Figure 5 and Figures 6A to 6J In step 501, an epitaxial structure is provided. For example... Figure 6A As shown, the epitaxial structure, from top to bottom, includes a first type semiconductor layer 610, a light-emitting layer 630, and a second type semiconductor layer 620. The epitaxial structure is grown on a substrate 600. The substrate 600 can be GaN, GaAs, etc.

[0061] In step 502: Reference Figure 6B The first type semiconductor layer 610 is patterned to form a mesa structure 611, a trench 613, and a fence 613'.

[0062] like Figure 6B As shown, the first type semiconductor layer 610 is etched, and etching stops above the light-emitting layer 630 to prevent the light-emitting layer 630 from being etched during the patterning process. The bottom of the trench 612 does not reach the light-emitting layer 630. The first type semiconductor layer 610 is etched using conventional dry etching processes (such as plasma etching processes), as will be understood by those skilled in the art.

[0063] In step 503: Reference Figure 6C The bottom contact 660 is deposited on the platform structure 611.

[0064] Before depositing the bottom contact 660, a first protective mask (not shown) is used to protect the area where the bottom contact 660 will not form. Then, material for the bottom contact 660 is deposited on the first protective mask and on the first type semiconductor layer 610 using a conventional vapor deposition process (such as physical vapor deposition or chemical vapor deposition). After the deposition process, the first protective mask is removed from the first type semiconductor layer 610, and the material on the first protective mask is also removed along with the first protective mask to form the bottom contact 660 on the mesa structure 611.

[0065] In step 504: Reference Figure 6D An ion implantation process is performed into fence 613'. The arrows indicate the direction of the ion implantation process.

[0066] Combination Figure 6C Ions are implanted into the fence 613' using an ion implantation process (e.g., Figure 6C As shown), to form an ion implantation fence 613 (as shown). Figure 6D As shown), Figure 6D As shown. Prior to the ion implantation process, a second protective mask (not shown) is formed on the region to be implanted with ions. Ions are then implanted into the exposed fence 613'. Subsequently, the second protective mask is removed by a conventional chemical etching process, as will be understood by those skilled in the art. Preferably, the implantation energy is from 0 keV to 500 keV, and the implantation dose is from 1E10 to 9E17.

[0067] In step 505: Reference Figure 6E A bottom isolation layer 640 is deposited over the entire substrate 600. Specifically, the bottom isolation layer 640 is deposited over the first type semiconductor layer 610. The first type semiconductor layer 610 and the bottom contact 660 are covered by the bottom isolation layer 640, and the trench 612 is filled by the bottom isolation layer 640. The bottom isolation layer 640 is deposited using a conventional chemical vapor deposition process.

[0068] In step 506: Reference Figure 6F The bottom isolation layer 640 is patterned to expose the bottom contact 660. The bottom isolation layer 640 is etched using photolithography and dry etching processes.

[0069] In step 507: Reference Figure 6G Metal material 650' is deposited on the entire substrate 600. That is, metal material 650' is deposited on the bottom isolation layer 640 and the bottom contact 660. The metal material is deposited using a conventional physical vapor deposition method.

[0070] In step 508: Reference Figure 6H The top of the metal material is ground down to the top of the bottom insulating layer 640 to form a connection structure 650, such as a connecting pillar. In some embodiments, the metal material is ground using a chemical mechanical polishing (CMP) process.

[0071] In step 509: Reference Figure 6IThe connecting pillar 650 is bonded to the IC backplane 690. First, the epitaxial structure is flipped. Then, the connecting pillar 650 is bonded to the contact pads of the IC backplane 690 using a metal bonding process. Then, the substrate 600 is removed using a conventional separation method (such as laser lift-off) or a chemical etching method. The arrows indicate the removal direction of the substrate 600.

[0072] In step 510: Reference Figure 6J The top contact 680 and the top conductive layer 670 can be sequentially deposited on the second type semiconductor layer 620 using conventional vapor deposition methods.

[0073] Some embodiments of this disclosure further provide a micro LED array panel. The micro LED array panel includes, as described above, and... Figures 1A to 1F , Figure 3 and Figure 4 The image shows multiple micro-LEDs. These micro-LEDs can be arranged in an array within a micro-LED array panel.

[0074] Figure 7 This illustrates some embodiments according to this disclosure. Figure 1A A structural diagram showing a side cross-sectional view of adjacent microLEDs within a microLED. (See diagram below.) Figure 7 As shown, the micro LED array panel includes a first type semiconductor layer 710 continuously formed in the micro LED array panel, a light-emitting layer 730 continuously formed on the first type semiconductor layer 710, and a second type semiconductor layer 720 continuously formed on the light-emitting layer 730.

[0075] The conductivity type of the first type semiconductor layer 710 is different from that of the second type semiconductor layer 720. For example, in some embodiments, the conductivity type of the first type semiconductor layer 710 is P-type, and the conductivity type of the second type semiconductor layer 720 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 720 is P-type, and the conductivity type of the first type semiconductor layer 710 is N-type. The thickness of the first type semiconductor layer 710 is greater than the thickness of the second type semiconductor layer 720. In some embodiments, the material of the first type semiconductor layer 710 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 720 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0076] The first type semiconductor layer 710 includes multiple mesa structures 711, multiple trenches 712, and multiple ion implantation fences 713 separated from the mesa structures 711 by the trenches 712. The top surface of the ion implantation fence 713 is lower than the top surface of the first type semiconductor layer 710. The trenches 712 extend upward but do not penetrate the top of the first type semiconductor layer 710. The top of the trenches 712 is lower than the top surface of the first type semiconductor layer 710. Therefore, the top surface of the trenches 712 does not contact the light-emitting layer 730. The relationship between the top surface of the ion implantation fence 713, the top surface of the first type semiconductor layer 710, and the top surface of the trenches 712 can be referenced. Figures 1B to 1D The micro-LED shown will not be described further here. Additionally, the relationship between the bottom surface of the ion implantation fence 713 and the bottom surface of the first type semiconductor layer 710 can be found in [reference needed]. Figures 1D to 1E The micro-LEDs shown will not be described further here. In another embodiment, the mesa structure may have one or more stepped structures, as shown in [reference needed]. Figure 1F The tabletop structure shown.

[0077] Figure 8 This illustrates some embodiments according to this disclosure. Figure 7 A structural diagram of the bottom view of adjacent micro-LEDs. (See diagram below.) Figure 8 As shown, an ion implantation fence 713 is formed in a trench 712 between adjacent mesa structures 711. Furthermore, in each micro-LED, the ion implantation fence 713 is formed around the trench 712, and the trench 712 is formed around the mesa structure 711. The resistance of the ion implantation fence 713 is higher than the resistance of the mesa structure 711.

[0078] In some embodiments, the space between adjacent sidewalls of adjacent mesa structures of mesa structure 711 can be adjusted. For example, in some embodiments, the space between adjacent sidewalls of mesa structure 711 is no greater than 50% of the diameter of mesa structure 711. In some embodiments, the space between adjacent sidewalls of mesa structure 711 is no greater than 30% of the diameter of mesa structure 711. Preferably, the space between adjacent sidewalls of mesa structure 711 is no greater than 600 nm. Additionally, in some embodiments, the width of ion implantation fence 713 can be adjusted. For example, the width of ion implantation fence 713 may be no greater than 50% of the diameter of mesa structure 711. In some embodiments, the width of ion implantation fence 713 may be no greater than 10% of the diameter of mesa structure 711. Preferably, in a micro-LED array panel, the width of ion implantation fence 713 is no greater than 200 nm.

[0079] Figure 9 This illustrates some embodiments of a micro LED array panel according to this disclosure. Figure 3A structural diagram showing a side cross-sectional view of adjacent microLEDs within a microLED. (See diagram below.) Figure 9 As shown, the micro-LED array panel further includes a bottom isolation layer 940 formed on a first-type semiconductor layer 910 and filled in a trench 912. Preferably, in some embodiments, the material of the bottom isolation layer 940 is SiO2 or SiN. x Alternatively, it may contain one or more of Al2O3, AlN, HfO2, TiO2, or ZrO2. Furthermore, the IC backplane 990 is continuously formed beneath the first type semiconductor layer 910 and electrically connected to the first type semiconductor layer 910 via a connection structure 950. The micro-LED array panel further includes a bottom contact 960 formed at the bottom of the first type semiconductor layer 910. Further details of the bottom isolation layer 940, IC backplane 990, bottom contact 960, and connection structure 950 are provided in [details omitted]. Figure 3 and Figure 4 The micro LED is shown as corresponding to the isolation layer 140, IC backplane 190, bottom contact 160 and connection structure 150, which will not be described further.

[0080] In this embodiment, the micro-LED array panel further includes a top contact 980 and a top conductive layer 970. The top contact 980 is formed on top of the second type semiconductor layer 920. The top conductive layer 970 is formed on top of the second type semiconductor layer 920 and on the top contact 980. The conductivity type of the top contact 980 is the same as that of the second type semiconductor layer 920. For example, in some embodiments, the conductivity type of the second type semiconductor layer 920 is N-type, and the conductivity type of the top contact 980 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 920 is P-type, and the conductivity type of the top contact 980 is P-type. The top contact 980 is made of metal or a metal alloy (such as AuGe, AuGeNi, etc.). The top contact 980 is used to form an ohmic contact between the top conductive layer 970 and the second type semiconductor layer 920 to optimize the electrical properties of the micro-LED. The diameter of the top contact 980 is approximately 20 nm to 50 nm, and the thickness of the top contact 980 is approximately 10 nm to 20 nm.

[0081] Miniature LED array panels can be used as Figure 5 The method shown is 500 manufacturing, which will not be described further.

[0082] In some implementations, a dielectric layer is formed between the top conductive layer and the second type of semiconductor layer.

[0083] Implementation Plan 2

[0084] Figures 10A to 10FThis is a structural diagram showing various different variations of a second exemplary microLED according to some embodiments of this disclosure. (See attached diagram.) Figure 10A As shown, the micro LED includes a first type semiconductor layer 1010, a light-emitting layer 1030, and a second type semiconductor layer 1020. The conductivity type of the first type semiconductor 1010 is different from that of the second type semiconductor layer 1020. For example, the conductivity type of the first type semiconductor 1010 is P-type, and the conductivity type of the second type semiconductor layer 1020 is N-type.

[0085] The second type semiconductor layer 1020 includes a mesa structure 1021, a trench 1022, and an ion implantation fence 1023 separated from the mesa structure 1021. The bottom surface of the ion implantation fence 1023 is higher than the bottom surface of the second type semiconductor layer 1020. Furthermore, the ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021. The resistance of the ion implantation fence 1023 is higher than the resistance of the mesa structure 1021.

[0086] The ion implantation fence 1023 includes a light-absorbing material for absorbing light from the mesa structure 1021. The conductivity type of the light-absorbing material is the same as that of the second type semiconductor layer 1020. Preferably, the light-absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN. Furthermore, the ion implantation fence 1023 is formed at least by implanting ions into the second type semiconductor layer 1020. Preferably, the ion type implanted into the second type semiconductor layer 1020 is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0087] Furthermore, the width of the ion implantation fence 1023 is no greater than 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the ion implantation fence 1023 is no greater than 10% of the diameter of the mesa structure 1021. Preferably, the width of the ion implantation fence 1023 is no greater than 200 nm. The diameter of the mesa structure 1021 is no greater than 2500 nm. The thickness of the second type semiconductor layer 1020 is no greater than 100 nm.

[0088] In some embodiments, the width of the trench 1022 is no greater than 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the trench 1022 is no greater than 10% of the diameter of the mesa structure 1021. Preferably, the width of the trench 1022 is no greater than 200 nm.

[0089] Figure 11 This is a top view structural diagram showing a second exemplary microLED according to some embodiments of this disclosure. Figure 11 A top view of a second type of semiconductor layer 1020 is shown, wherein an ion implantation fence 1023 is separated from the mesa structure 1021 by a trench 1022. Here, the ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021.

[0090] There is no limitation on the depth of trench 1022. In some embodiments, trench 1022 may extend downward through the second type semiconductor layer 1020 but not reach the light-emitting layer 1030. In some embodiments, trench 1022 may extend downward through the second type semiconductor layer 1020 and reach the light-emitting layer 1030. In some embodiments, trench 1022 may extend downward through the second type semiconductor layer 1020 and extend into the interior of the light-emitting layer 1030. In some embodiments, trench 1022 may extend downward through both the second type semiconductor layer 1020 and the light-emitting layer 1030. Furthermore, trench 1022 may extend downward through both the second type semiconductor layer 1020 and the light-emitting layer 1030, and extend downward into the interior of the first type semiconductor layer 1010.

[0091] In some implementation schemes, such as Figure 10A As shown, trench 1022 extends downward but does not penetrate the bottom surface of the second type semiconductor layer 1020. The bottom surface of trench 1022 is higher than the bottom of the second type semiconductor layer 1020. Therefore, the bottom of trench 1022 does not contact the light-emitting layer 1030.

[0092] In some embodiments, the bottom of the ion implantation fence 1023 is lower than or aligned with the bottom of the trench 1022. The bottom of the ion implantation fence 1023 can be formed at any location within the first type semiconductor layer 1010. Preferably, as Figure 10A As shown, the bottom of the ion implantation fence 1023 is lower than the bottom of the trench 1022. In some embodiments, such as Figure 10B As shown, the bottom of the ion implantation fence 1023 is aligned with the bottom of the trench 1022. In some embodiments, such as Figure 10C As shown, the bottom of the ion implantation fence 1023 is higher than the bottom of the trench 1022.

[0093] Additionally, in some embodiments, the top surface of the ion implantation fence 1023 can be formed at any location. Preferably, the top surface of the ion implantation fence 1023 is aligned with the top surface of the second type semiconductor layer 1020. However, in some embodiments, such as Figure 10D As shown, the top surface of the ion implantation fence 1023 is higher than the top surface of the second type semiconductor layer 1020. In some embodiments, such as Figure 10EAs shown, the top surface of the ion implantation fence 1023 is lower than the top surface of the second type semiconductor layer 1020.

[0094] In some implementation schemes, such as Figure 10F As shown, the platform structure 1021 includes a stepped structure 1021a. In some embodiments, the platform structure 1021 may have multiple stepped structures.

[0095] Figure 12 This is a structural diagram showing a side cross-sectional view of another variant of a second exemplary microLED according to some embodiments of this disclosure. Figure 12 As shown, the micro-LED further includes a bottom isolation layer 1040 formed beneath the first type of semiconductor layer 1010. Preferably, the material of the bottom isolation layer 1040 is selected from SiO2 and SiN. x Or one or more of Al2O3.

[0096] In this embodiment, an integrated circuit (IC) backplane 1090 is formed beneath a first type semiconductor layer 1010 and is electrically connected to the first type semiconductor layer 1010 via an interconnect structure 1050. For example... Figure 12 As shown, the connection structure 1050 serves as a connection pillar. The micro-LED further includes a bottom contact 1060 formed at the bottom of the first type semiconductor layer 1010. The upper surface of the connection structure 1050 is connected to the bottom contact 1060, and the bottom of the connection structure 1050 is connected to the IC backplane 1090. In this embodiment, the bottom contact 1060 protrudes from the first type semiconductor layer 1010, serving as the bottom contact of the micro-LED.

[0097] Additionally, in some embodiments, the microLED further includes a top contact 1080 and a top conductive layer 1070. The top contact 1080 is formed on top of the second type semiconductor layer 1020. The top conductive layer 1070 is formed on the top surface of the second type semiconductor layer 1020, covering the top contact 1080 and filling the trench 1022. Therefore, the top conductive layer 1070 is formed on the top surface and sidewalls of the mesa structure 1021, and on the top surface and sidewalls of the ion implantation fence. The conductivity type of the top contact 1080 is the same as that of the second type semiconductor layer 1020. For example, the conductivity type of the second type semiconductor layer 1020 is N-type, and the conductivity type of the top contact 1080 is also N-type. The top contact 1080 is made of metal or a metal alloy (such as AuGe, AuGeNi, etc.). The top contact 1080 is used to form an ohmic contact between the top conductive layer 1070 and the second type semiconductor layer 1020 to optimize the electrical properties of the micro LED. The top contact 1080 has a diameter of about 20 nm to 50 nm and a thickness of about 10 nm to 20 nm.

[0098] Figure 13 This is a structural diagram showing a side cross-sectional view of another variant of a second exemplary microLED according to some embodiments of this disclosure. Figure 13 As shown, the connection structure 1050 can be a metal bonding layer for bonding the micro-LED to the IC backplane 1090. Additionally, in this embodiment, the bottom contact 1060 is a bottom contact layer.

[0099] In some embodiments, the microLED further includes a dielectric layer formed on the surface of a second type semiconductor layer, on the bottom surface of a top conductive layer, and filling trenches. The dielectric layer includes openings for exposing top contacts. Therefore, the top conductive layer can be connected to the top contacts through these openings. Preferably, the material of the dielectric layer is selected from SiO2 and SiN. x Or one or more of Al2O3.

[0100] Figure 14 The following are some embodiments of the fabrication of a second exemplary microLED (e.g., according to this disclosure). Figure 13 The flowchart of method 1400 (shown for miniature LEDs) is shown. Figure 14 As shown, the method for manufacturing micro LEDs includes steps 1401 to 1406. Figures 15A to 15F This illustrates some embodiments according to this disclosure. Figure 14 A structural diagram of a side cross-sectional view of the micro-LED manufacturing process at each step (i.e., steps 1401 to 1406) of the method 1400 shown.

[0101] refer to Figure 14 and Figures 15A to 15F In step 1401: an epitaxial structure is provided. For example... Figure 15A As shown, the epitaxial structure, from top to bottom, includes a first type semiconductor layer 1510, a light-emitting layer 1530, and a second type semiconductor layer 1520. The epitaxial structure is grown on a substrate 1500. The substrate 1500 can be GaN, GaAs, etc.

[0102] Preferably, before flipping the epitaxial structure, a bottom contact layer 1560, serving as a bottom contact, is deposited on the top surface of the first type semiconductor layer 1510. Then, a metal bonding layer, serving as a connection structure 1550, is deposited on the top surface of the bottom contact layer 1560.

[0103] In step 1402: Reference Figure 15BThe epitaxial structure is bonded to the IC backplane 1590. First, the epitaxial structure is flipped. Then, the connection structure 1550 is bonded to the contact pads of the IC backplane 1590 using a metal bonding process. Finally, the substrate 1500 is removed using a conventional separation method (such as laser lift-off) or a chemical etching method. The arrows indicate the removal direction of the substrate 1500.

[0104] In step 1403: Reference Figure 15C The second type semiconductor layer 1520 is patterned to form a mesa structure 1521, a trench 1522, and a fence 1523'. The second type semiconductor layer 1520 is etched, and etching is stopped above the light-emitting layer 1530 to prevent the light-emitting layer 1530 from being etched during the patterning process. The bottom of the trench 1522 is... Figure 15C The light-emitting layer 1530 was not reached. The second type semiconductor layer 1520 was etched using a conventional dry etching process (such as plasma etching), as will be understood by those skilled in the art.

[0105] In step 1404: Reference Figure 15D A top contact 1580 is deposited on the mesa structure 1521. Before depositing the top contact 1580, a first protective mask (not shown) is used to protect areas where the top contact 1580 will not form. Then, material for the top contact 1580 is deposited on the first protective mask and on the second type semiconductor layer 1520 using a conventional vapor deposition process (such as physical vapor deposition or chemical vapor deposition). After the deposition process, the first protective mask is removed from the second type semiconductor layer 1520, and the material on the first protective mask is also removed along with the first protective mask to form the top contact 1580 on the mesa structure 1521.

[0106] In step 1405: Reference Figure 15E An ion implantation process was performed into fence 1523'. See also... Figure 15D Ions are implanted into the fence 1523' using an ion implantation process (e.g., Figure 15D (as shown) to form an ion implantation fence 1523 (as shown) Figure 15E (As shown). The arrows indicate the direction of the ion implantation process. Before the ion implantation process, a second protective mask (not shown) is formed on the area to be implanted with ions. Then, ions are implanted into the exposed enclosure 1523' (as shown). Figure 15D (As shown). Subsequently, the second protective mask is removed by a conventional chemical etching process, as will be understood by those skilled in the art. Preferably, the implantation energy is from 0 keV to 500 keV, and the implantation dose is from 1E10 to 9E17.

[0107] It should be noted that in some implementations, the top contact 1580 can be formed after the ion implantation process.

[0108] In step 1406: Reference Figure 15F A top conductive layer 1570 is deposited on top of the second type semiconductor layer 1520 and on the top contact 1580, and fills the trench 1522. The top conductive layer 1570 is deposited using a conventional physical vapor deposition process.

[0109] Alternatively, a sidewall dielectric layer may be formed in the trench 1522 prior to the deposition of the top conductive layer 1570. Microlenses may further be formed on the top conductive layer 1570, as will be understood by those skilled in the art.

[0110] When the connection structure 1550 is a connection pillar, step 1402 can be replaced by the following steps 1402': depositing a bottom contact on a first type of semiconductor layer; depositing a bottom isolation layer on the entire substrate; patterning the bottom isolation layer to expose the bottom contact; depositing a metal material on the entire substrate; grinding the top of the metal material to the top of the bottom isolation layer to form a connection pillar; and bonding the connection pillar to the IC backplane. First, the epitaxial structure is flipped, and the connection pillar is bonded to the contact pads of the IC backplane using a metal bonding process. Step 1402' can also be described with reference to Embodiment 1. Figure 6C and Figures 6E to 6I To further understand this, we will refer to the description above, but will not describe it in more detail here.

[0111] According to some embodiments of this disclosure, a micro LED array panel is further provided. The micro LED array panel includes a plurality of micro LEDs, as described above and in... Figures 10A to 10F , Figure 12 and Figure 13 As shown in the image. These micro-LEDs can be arranged in an array within a micro-LED array panel.

[0112] Figure 16 This illustrates some embodiments according to this disclosure. Figure 10A A structural diagram showing a side cross-sectional view of adjacent microLEDs within a microLED. (See diagram below.) Figure 16 As shown, the micro LED array panel includes a first type semiconductor layer 1610 continuously formed in the micro LED array panel, a light-emitting layer 1630 continuously formed on the first type semiconductor layer 1610, and a second type semiconductor layer 1620 continuously formed on the light-emitting layer 1630.

[0113] The second type semiconductor layer 1620 includes a plurality of mesa structures 1621, a plurality of trenches 1622, and a plurality of ion implantation fences 1623 separated from the mesa structures 1621 by the trenches 1622. The bottom surface of the ion implantation fences 1623 is higher than the bottom surface of the second type semiconductor layer 1620.

[0114] Figure 17 This illustrates some embodiments according to this disclosure. Figure 16 A top-view structural diagram of adjacent micro-LEDs. Figure 17 A top view of a second type of semiconductor layer 1620 is shown, wherein an ion implantation fence 1623 is formed in a trench 1622 between adjacent mesa structures 1621. The resistance of the ion implantation fence 1623 is higher than that of the mesa structure 1621. The ion implantation fence 1623 is formed around the trench 1622, and the trench 1622 is formed around the mesa structure 1621.

[0115] The trench 1622 extends downward but does not penetrate the bottom of the second type semiconductor layer 1620. The bottom of the trench 1622 is higher than the bottom of the second type semiconductor layer 1620. Therefore, the bottom of the trench 1622 does not contact the light-emitting layer 1630. In some embodiments, the trench 1622 may extend downward through the bottom of the second type semiconductor layer 1620 but not reach the light-emitting layer 1630. In some embodiments, the trench 1622 may extend downward through the second type semiconductor layer 1620 and reach the light-emitting layer 1630. In some embodiments, the trench 1622 may extend downward through the second type semiconductor layer 1620 and extend into the interior of the light-emitting layer 1630. In some embodiments, the trench 1622 may extend downward through both the second type semiconductor layer 1620 and the light-emitting layer 1630. Furthermore, in some embodiments, the second trench 1622 may extend downward through both the second type semiconductor layer 1620 and the light-emitting layer 1630, and extend downward into the interior of the first type semiconductor layer 1610. The variation in the relationship between the bottom surface of the ion implantation fence 1623, the bottom surface of the second type semiconductor layer 1620, and the bottom of the trench 1622 generally corresponds to Figures 10A to 10C The variations shown for micro-LEDs will not be described further here. Additionally, in some embodiments, variations in the relationship between the top surface of the ion-implanted fence 1623 and the top surface of the second type semiconductor layer 1620 generally correspond to... Figures 10C to 10E The variations shown for micro-LEDs will not be described further here. In some embodiments, the mesa structure may have one or more stepped structures, such as... Figure 10F As shown.

[0116] In some embodiments, the space between adjacent sidewalls of adjacent mesa structures of mesa structure 1621 can be adjusted. For example, in some embodiments, the space between adjacent sidewalls of mesa structure 1621 is no greater than 50% of the diameter of mesa structure 1621. In some embodiments, the space between adjacent sidewalls of mesa structure 1621 is no greater than 30% of the diameter of mesa structure 1621. Preferably, the space between adjacent sidewalls of mesa structure 1621 is no greater than 600 nm. Additionally, in some embodiments, the width of ion implantation fence 1623 can be adjusted. For example, the width of ion implantation fence 1623 may be no greater than 50% of the diameter of mesa structure 1621. In some embodiments, the width of ion implantation fence 1623 may be no greater than 10% of the diameter of mesa structure 1621. Preferably, in a micro-LED array panel, the width of ion implantation fence 1623 is no greater than 200 nm.

[0117] Figure 18 This illustrates some embodiments of a micro LED array panel according to this disclosure. Figure 13 A structural diagram showing a side cross-sectional view of adjacent microLEDs within a microLED. (See diagram below.) Figure 18 As shown, the micro LED array panel further includes a top contact 1880 and a top conductive layer 1870. Further details of the top contact 1880 and the top conductive layer 1870 can be found by referring to [reference also provided]. Figures 10A to 10F , Figure 12 and Figure 13 The micro-LEDs shown are used for understanding, and will not be described further here.

[0118] In addition, return to reference Figure 18 An IC backplane 1890 is formed beneath a first-type semiconductor layer 1810 and electrically connected to the first-type semiconductor layer 1810 via a connection structure 1850. The micro-LED array panel further includes a bottom contact 1860 formed at the bottom of the first-type semiconductor layer 1810. The connection structure 1850 may be a metal bonding layer for bonding the micro-LEDs to the IC backplane 1890. Alternatively, in some embodiments, the bottom contact 1860 is a bottom contact layer. Further details of the bottom isolation layer 1840, IC backplane 1890, bottom contact 1860, and connection structure 1850 can be found by referring to [further details omitted]. Figure 13 We will use this to understand it, and will not describe it further here.

[0119] Furthermore, further details regarding the characteristics of ion implantation fences in micro-LEDs and micro-LED array panels can also be found by referring to, for example... Figures 10A to 10F The micro-LEDs shown are used for understanding, and will not be described further here.

[0120] Figure 18 The micro LED array panel shown can be used as follows Figure 14 The method shown for manufacturing the micro LED 1400 will not be described further here.

[0121] Implementation Plan 3

[0122] Figure 19 This is a structural diagram showing a side cross-sectional view of a variant of a third exemplary microLED according to some embodiments of this disclosure. Figure 19 As shown, the micro-LED includes at least a first type semiconductor layer 1910, a light-emitting layer 1930, and a second type semiconductor layer 1920. The conductivity type of the first type semiconductor layer 1910 is different from that of the second type semiconductor layer 1920. For example, in some embodiments, the conductivity type of the first type semiconductor layer 1910 is P-type, and the conductivity type of the second type semiconductor layer 1920 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 1920 is P-type, and the conductivity type of the first type semiconductor layer 1910 is N-type. The thickness of the first type semiconductor layer 1910 is greater than the thickness of the second type semiconductor layer 1920. In some embodiments, the material of the first type semiconductor layer 1910 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer 1920 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0123] The first type semiconductor layer 1910 includes a first mesa structure 1911, a first trench 1912, and a first ion implantation fence 1913. The first trench 1912 extends upward but does not penetrate the top surface of the first type semiconductor layer 1910. The second type semiconductor layer 1920 includes a second mesa structure 1921, a second trench 1922, and a second ion implantation fence 1923 separated from the second mesa structure 1921. The second trench 1922 extends downward but does not penetrate the bottom of the second type semiconductor layer 1920.

[0124] In some embodiments, the center of the first mezzanine structure 1911 is aligned with the center of the second mezzanine structure 1921. The center of the first trench 1912 is aligned with the center of the second trench 1922. The center of the first ion implantation fence 1913 is aligned with the center of the second ion implantation fence 1923.

[0125] Bottom view of the first type semiconductor layer 1910 and Figure 2The bottom view shown is similar. The first ion implantation fence 1913 is separated from the first mesa structure 1911 by a first trench 1912. The first ion implantation fence 1913 is formed around the first trench 1912, and the first trench 1912 is formed around the first mesa structure 1911. The top view of the second type semiconductor layer 1920 is similar. Figure 11 Similar to the top view shown, the second ion implantation fence 1923 is separated from the second mesa structure 1921 by a second trench 1922. The second ion implantation fence 1923 is formed around the second trench 1922, and the second trench 1922 is formed around the second mesa structure 1921.

[0126] The relationship between the top surface of the first ion implantation fence 1913, the top surface of the first trench 1912, and the top surface of the first type semiconductor layer 1910 and Figures 1A to 1C The relationships of the variant of the microLED shown in Embodiment 1 are the same and will not be described further here. The relationships of the bottom of the first ion implantation fence 1913, the bottom of the first trench 1912, and the bottom of the first type semiconductor layer 1910 are the same as in Embodiment 1. Figures 1C to 1E The variations of the microLEDs shown in Embodiment 1 have the same relationship and will not be described further here. Furthermore, in some embodiments, the first mesa structure 1911 may have one or more stepped structures, such as... Figure 1F As shown.

[0127] The relationship between the bottom of the second ion implantation fence 1923, the bottom of the second trench 1922, and the bottom of the second type semiconductor layer 1920 is as follows: Figures 10A to 10C The relationships between the variants of the microLED shown in Embodiment 2 are the same and will not be described further here. The relationships between the top surface of the second ion implantation fence 1923, the top surface of the second trench 1922, and the top surface of the second type semiconductor layer 1920 are as follows: Figures 10C to 10E The variations of the microLEDs shown in embodiment 2 have the same relationship and will not be described further here. Furthermore, in some embodiments, the second mezzanine structure 1921 may have one or more stepped structures, such as... Figure 10F As shown.

[0128] Figure 20 This is a structural diagram showing a side cross-sectional view of another variant of a third exemplary microLED according to some embodiments of this disclosure. Figure 20 As shown, the micro-LED further includes a bottom insulating layer 2030 filled in the first trench 2012. Preferably, the bottom insulating layer 2030 is made of SiO2 or SiN. xOr one or more of Al2O3. An IC backplane 2090 is formed beneath the first type semiconductor layer 2010 and electrically connected to the first type semiconductor layer 2010 via a connection structure 2050. Here, the connection structure 2050 is a connection pillar. The microLED further includes a bottom contact 2060 formed at the bottom of the first type semiconductor layer 2010. Further details of the bottom isolation layer 2040, IC backplane 2090, connection structure 2050, and bottom contact 2060 can be found by referring to the description of embodiment 1, and will not be described further here.

[0129] The microLED further includes a top contact 2080 and a top conductive layer 2070. The top contact 2080 is formed on top of the second type semiconductor layer 2020. The top conductive layer 2070 is formed on top of the second type semiconductor layer 2020 and the top contact 2080 and fills the second trench 2022. Further details regarding the top contact 2080 and the top conductive layer 2070 can be found by referring to the description of embodiment 2, and will not be described further here.

[0130] In some embodiments, the microLED further includes a dielectric layer formed on the surface of a second type of semiconductor layer, on the bottom surface of a top conductive layer, and filling a second trench. The dielectric layer includes openings for exposing top contacts. Therefore, the top conductive layer can be connected to the top contacts through these openings. Preferably, the material of the dielectric layer is selected from SiO2 and SiN. x Or one or more of Al2O3. Further details about the dielectric layer can be found by referring to Embodiment 2, and will not be described further here.

[0131] In addition, regarding Figure 20 Further details of the micro-LEDs shown (including the first ion implantation fence 2013 and the second ion implantation fence 2023) can be found by referring to the descriptions of embodiments 1 and 2, and will not be described further here.

[0132] Figure 21 A flowchart of a method 2100 for manufacturing a third exemplary microLED according to some embodiments of this disclosure is shown. Method 2100 includes at least process I and process II.

[0133] In process I: a first type semiconductor layer is patterned, and then ions are implanted into the first type semiconductor layer to form a first ion implantation fence.

[0134] In process II: a second type semiconductor layer is patterned, and then ions are implanted into the second type semiconductor layer to form a second ion implantation fence.

[0135] refer to Figure 21 Process I includes at least steps 2101 to 2109, and process II includes at least steps 2110 to 2113.

[0136] For process I, steps 2101 to 2109 are as follows: Figure 5 Steps 501 to 509 of method 500 shown are similar. The side cross-sectional view of the microLED fabricated according to steps 2101 to 2109 is similar. Figures 6A to 6I The view shown is similar. (Reference) Figure 21 and Figures 6A to 6I In step 2101: Reference Figure 6A It provides an extensional structure.

[0137] In step 2102: Reference Figure 6B The first type semiconductor layer 610 is patterned to form a mesa structure 611, a trench 612, and a fence 613'.

[0138] In step 2103: Reference Figure 6C The bottom contact 660 is deposited on the platform structure 611.

[0139] In step 2104: Reference Figure 6D An ion implantation process is performed into fence 613'.

[0140] In step 2105: Reference Figure 6E A bottom isolation layer 640 is deposited on the entire substrate 600.

[0141] In step 2106: Reference Figure 6F A patterned bottom isolation layer 640 is used to expose the bottom contact 660.

[0142] In step 2107: Reference Figure 6G Metal material 650' is deposited on the entire substrate 600.

[0143] In step 2108: Reference Figure 6H The top of the metal material 650' is ground to the top of the bottom insulating layer 640 to form the connecting pillar 650.

[0144] In step 2109: Reference Figure 6I The connecting pillar 650 is bonded to the IC backplane 690, and the substrate 600 is removed.

[0145] Figures 22A to 22D This illustrates some embodiments according to this disclosure. Figure 21 A structural diagram of a side cross-sectional view of the micro-LED manufacturing process at steps 2110 to 2113 of method 2100 shown. (Refer to...) Figure 21 and Figures 22A to 22D In step 2110: Reference Figure 22A The second type semiconductor layer 2220 is patterned to form a mesa structure 2221, a trench 2222, and a fence 2223'.

[0146] In step 2111: Reference Figure 22B The top contact 2280 is deposited on the platform structure 2221.

[0147] In step 2112: Reference Figure 22C An ion implantation process is performed into fence 2223'. The arrows indicate the direction of the ion implantation process.

[0148] In step 2113: Reference Figure 22D The top conductive layer 2270 is deposited on top of the second type semiconductor layer 2220, on the top contact 2280, and in the trench 2222.

[0149] Further details of process I can be found by referring to the description of steps 501 to 509 of implementation scheme 1. Further details of process II can be found by referring to the description of steps 1403 to 1406 of implementation scheme 2, which will not be described further here.

[0150] According to some embodiments of this disclosure, a micro LED array panel is further provided. The micro LED array panel includes, as described above, and... Figure 19 and Figure 20 The image shows multiple micro-LEDs. These micro-LEDs can be arranged in an array within a micro-LED array panel.

[0151] Figure 23 This illustrates some embodiments of a micro LED array panel according to this disclosure. Figure 19 A structural diagram showing a side cross-sectional view of adjacent microLEDs within a microLED. (See diagram below.) Figure 23 As shown, the micro LED array panel includes at least a first type semiconductor layer 2310 continuously formed in the micro LED array panel, a light-emitting layer 2330 continuously formed on the first type semiconductor layer 2310, and a second type semiconductor layer 2320 continuously formed on the light-emitting layer 2330.

[0152] The first type semiconductor layer 2310 includes a plurality of first mesa structures 2311, a plurality of first trenches 2312, and a plurality of first ion implantation fences 2313 separated from the first mesa structures via the first trenches 2312. The top surface of the first ion implantation fences 2313 is lower than the top surface of the first type semiconductor layer 2310. (Return to Reference) Figure 8Bottom view of a micro LED array panel without an IC backplane and Figure 8 The bottom view shown is similar. A first ion implantation fence 2313 is formed in a first trench 2312 between adjacent first-type mesa structures. The resistance of the first ion implantation fence 2313 is higher than the resistance of the first mesa structure. Furthermore, the first ion implantation fence 2313 is formed around the first trench 2312, and the first trench 2312 is formed around the first mesa structure.

[0153] The second type semiconductor layer 2320 includes a plurality of second mesa structures 2321, a plurality of second trenches 2322, and a plurality of second ion implantation fences 2323 separated from the second mesa structures 2321 via the second trenches 2322. The bottom surface of the second ion implantation fences 2323 is higher than the bottom surface of the second type semiconductor layer 2320. Top view of the micro-LED array panel and Figure 17 Similar to the top view shown, a second ion implantation fence 2323 is formed in a second trench 2322 between adjacent second mesa structures 2321. The resistance of the second ion implantation fence 2323 is higher than the resistance of the second mesa structure 2321. The second ion implantation fence 2323 is formed around the second trench 2322, and the second trench 2322 is formed around the second mesa structure 2321.

[0154] In some embodiments, the space between adjacent sidewalls of the first mesa structure 2311 can be adjusted. For example, the space between adjacent sidewalls of the first mesa structure 2311 is no greater than 50% of the diameter of the first mesa structure 2311. In some embodiments, the space between adjacent sidewalls of the first mesa structure 2311 is no greater than 30% of the diameter of the first mesa structure 2311. Preferably, the space between adjacent sidewalls of the first mesa structure 2311 is no greater than 600 nm. Additionally, in some embodiments, the width of the first ion implantation fence 2313 can be adjusted. For example, the width of the first ion implantation fence 2313 is no greater than 50% of the diameter of the first mesa structure 2311. In some embodiments, the width of the first ion implantation fence 2313 is no greater than 10% of the diameter of the first mesa structure 2311. Preferably, in some embodiments, in the micro-LED array panel, the width of the first ion implantation fence 2313 is no greater than 200 nm. The space between adjacent sidewalls of the second mesa structure 2321 is no greater than 50% of the diameter of the second mesa structure 2321. In some embodiments, the space between adjacent sidewalls of the second mesa structure 2321 is no greater than 30% of the diameter of the second mesa structure 2321. Preferably, the space between adjacent sidewalls of the second mesa structure 2321 is no greater than 600 nm. Additionally, the width of the second ion implantation fence 2323 is no greater than 50% of the diameter of the second mesa structure 2321. In some embodiments, the width of the second ion implantation fence 2323 is no greater than 10% of the diameter of the second mesa structure 2321. Preferably, in the micro-LED array panel, the width of the second ion implantation fence 2323 is no greater than 200 nm.

[0155] Figure 24 This illustrates some embodiments of a micro LED array panel according to this disclosure. Figure 20 A structural diagram showing a side cross-sectional view of adjacent microLEDs within a microLED. (See diagram below.) Figure 24 As shown, the micro-LED array panel further includes a bottom insulating layer 2440 filled in the first trench 2412. Preferably, the bottom insulating layer 2440 is made of SiO2 or SiN. x One or more of Al2O3, AlN, HfO2, TiO2, or ZrO2 are used. Additionally, the IC backplane 2490 is formed beneath the first type semiconductor layer 2410 and electrically connected to the first type semiconductor layer 2410 via a connection structure 2450. The micro-LED array panel further includes a bottom contact 2460 formed at the bottom of the first type semiconductor layer 2410. The upper surface of the connection structure 2450 is connected to the bottom contact 2460, and the bottom of the connection structure 2450 is connected to the IC backplane 2490. The bottom contact 2460 is a protruding contact. In some embodiments, reference is made to... Figure 4The connection structure 2450 may be a metal bonding layer for bonding the micro-LED to the IC backplane 2490. Additionally, in some embodiments, the bottom contact 2460 is a bottom contact layer.

[0156] Return to reference Figure 24 The micro-LED array panel further includes a top contact 2480 and a top conductive layer 2470. The top contact 2480 is formed on top of the second type semiconductor layer 2420. The top conductive layer 2470 is formed on top of the second type semiconductor layer 2420 and the top contact 2480 and fills a second trench 2422. The conductivity type of the top contact 2480 is the same as that of the second type semiconductor layer 2420. For example, the conductivity type of the second type semiconductor layer 2420 is N-type, and the conductivity type of the top contact 2480 is also N-type. The top contact 2480 is made of metal or a metal alloy (such as AuGe, AuGeNi, etc.). The top contact 2480 is used to form an ohmic contact between the top conductive layer 2470 and the second type semiconductor layer 2420 to optimize the electrical properties of the micro-LED. The diameter of the top contact 2480 is approximately 20 nm to 50 nm, and the thickness of the top contact 2480 is approximately 10 nm to 20 nm.

[0157] Further details regarding the characteristics of the micro-LEDs in the micro-LED array panel can be found by referring to the micro-LEDs described above, and will not be described further here.

[0158] The method for manufacturing a micro-LED array panel includes at least the manufacture of micro-LEDs. Details of the manufacture of micro-LEDs can be found in the descriptions of steps 501 to 509 in Embodiment 1 and steps 1403 to 1406 in Embodiment 2, and will not be described further here.

[0159] In embodiments 1 to 3, microlenses may be further formed on or above the second type of semiconductor layer (such as on the top surface of the top conductive layer), as will be understood by those skilled in the art.

[0160] Micro-LEDs have a very small volume. Micro-LEDs can be organic or inorganic LEDs. Micro-LEDs can be applied in micro-LED array panels. The light-emitting area of ​​a micro-LED array panel is very small, such as 1mm × 1mm or 3mm × 5mm. In some embodiments, the light-emitting area is the area of ​​the micro-LED array within the micro-LED array panel. The micro-LED array panel includes one or more micro-LED arrays forming a pixel array, such as a 1600 × 1200, 680 × 480, or 1920 × 1080 pixel array, where the micro-LED is a pixel. The diameter of the micro-LED is in the range of approximately 200nm to 2μm. An IC backplane is formed on the back surface of the micro-LED array and is electrically connected to the micro-LED array. The IC backplane acquires signals such as image data from the outside via signal lines to control the corresponding micro-LEDs to emit or not emit light.

[0161] It should be noted that relational terms in this document, such as “first” and “second”, are used only to distinguish an entity or operation from another entity or operation, without requiring or implying any actual relationship or order between these entities or operations. Furthermore, the words “comprising,” “having,” “containing,” and “including,” and other similar forms, are intended to be semantically equivalent and are open-ended; one or more items following any of these words do not imply an exhaustive list of such items or that the list is limited to only one or more items.

[0162] As used herein, unless otherwise expressly stated, the term "or" covers all possible combinations unless impractical. For example, if a database is declared to include A or B, then unless otherwise expressly stated or impractical, the database may include A, or B, or A and B. As a second example, if a database is declared to include A, B, or C, then unless otherwise expressly stated or impractical, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0163] In the foregoing description, numerous specific details have been described, which may vary depending on the implementation. Certain modifications and alterations may be made to the described embodiments. Other embodiments will be apparent to those skilled in the art in light of the description and practice of the invention disclosed herein. The description and examples are intended to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims. The order of steps shown in the drawings is also intended for illustrative purposes only and is not intended to limit one to any particular order of steps. Therefore, those skilled in the art will understand that these steps may be performed in different orders while implementing the same method.

[0164] Exemplary embodiments have been disclosed in the accompanying drawings and description. However, many variations and modifications can be made to these embodiments. Therefore, although specific terms are used, they are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A micro-LED, comprising: a first type semiconductor layer; and a light emitting layer formed on the first type semiconductor layer; wherein the first type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure by the trench, wherein the ion implantation fence is formed around the trench, the trench is formed around the mesa structure, the mesa structure comprises one or more step structures; and the electrical resistance of the ion implantation fence is higher than the electrical resistance of the mesa structure; the top surface of the ion implantation fence is lower than the top surface of the first type semiconductor layer.

2. The micro-LED of claim 1, wherein, the bottom surface of the ion implantation fence is aligned with or higher than the bottom surface of the first type semiconductor layer.

3. The micro-LED of claim 1, wherein, the trench extends upward but does not pass through the top surface of the first type semiconductor layer.

4. The micro-LED of claim 3, wherein, the top surface of the ion implantation fence is higher than or aligned with the top surface of the trench.

5. The micro-LED of claim 3, wherein, the top of the ion implantation fence is lower than the top surface of the trench. 6.The micro-LED of claim 1, further comprising a second-type semiconductor layer formed on the light-emitting layer, wherein, the conductivity type of the second type semiconductor layer is different from the conductivity type of the first type semiconductor layer.

7. The micro-LED of claim 6, wherein, the mesa structure, the trench, and the ion implantation fence are a first mesa structure, a first trench, and a first ion implantation fence, respectively; wherein the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure; wherein the bottom surface of the second ion implantation fence is higher than the bottom surface of the second type semiconductor layer, the second ion implantation fence is formed around the second trench, and the second trench is formed around the second mesa structure, and the electrical resistance of the second ion implantation fence is higher than the electrical resistance of the second mesa structure.

8. The micro-LED of claim 7, wherein, the second trench extends downward but does not pass through the bottom surface of the second type semiconductor layer.

9. The micro-LED of claim 8, wherein, the bottom surface of the second ion implantation fence is lower than or aligned with the bottom surface of the second trench.

10. The micro-LED of claim 8, wherein, the bottom surface of the second ion implantation fence is higher than the bottom surface of the second trench.

11. The micro-LED of claim 7, wherein, the top surface of the second ion implantation fence is aligned with or lower than the top surface of the second type semiconductor layer.

12. The micro-LED of claim 7, wherein, the first mesa structure comprises one or more step structures, and the second mesa structure comprises one or more step structures.

13. The micro-LED of claim 7, wherein, the width of the first trench is no more than 50% of the diameter of the first mesa structure, and the width of the second trench is no more than 50% of the diameter of the second mesa structure.

14. The micro-LED of claim 13, wherein, the width of the first trench is no more than 200 nm, and the width of the second trench is no more than 200 nm.

15. The micro-LED of claim 7, wherein, The first ion implantation fence comprises a first light absorbing material and the second ion implantation fence comprises a second light absorbing material; wherein the first light absorbing material is of the same conductivity type as the first type semiconductor and the second light absorbing material is of the same conductivity type as the second type semiconductor, and the first and second light absorbing materials are selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

16. The micro-LED of claim 6, wherein, The first type semiconductor layer has a thickness that is greater than a thickness of the second type semiconductor layer.

17. The micro-LED of claim 1, further comprising a bottom isolation layer that fills in the trench.

18. The micro-LED of claim 17, wherein, The material of the bottom isolation layer is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2.

19. The micro-LED of claim 6, further comprising a top contact and a top conductive layer formed on a top surface of the second type semiconductor layer.

20. The micro-LED of claim 7, further comprising a top conductive layer and a top contact, wherein, The top contact is formed on a top surface of the second mesa structure and the top conductive layer is formed on a top surface and sidewalls of the second mesa structure, on a top surface and sidewalls of the second ion implantation fence, and fills in the second trench.

21. The micro-LED of claim 7, wherein, The ions implanted into the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F; and the ions implanted into the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

22. The micro-LED of claim 7, wherein, The first ion implantation fence is formed by implanting ions into at least the first type semiconductor layer and the second ion implantation fence is formed by implanting ions into at least the second type semiconductor layer.

23. The micro-LED of claim 7, wherein, The first ion implantation fence has a width that is no greater than 50% of a diameter of the first mesa structure and the second ion implantation fence has a width that is no greater than 50% of a diameter of the second mesa structure.

24. The micro-LED of claim 23, wherein, The first ion implantation fence has a width that is no greater than 200 nm, the first mesa structure has a diameter that is no greater than 2500 nm, and the first type semiconductor layer has a thickness that is no greater than 100 nm; and The second ion implantation fence has a width that is no greater than 200 nm, the second mesa structure has a diameter that is no greater than 2500 nm, and the second type semiconductor layer has a thickness that is no greater than 100 nm.

25. The micro-LED of claim 6, wherein, The first type semiconductor layer is of a material selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and the second type semiconductor layer is of a material selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.

26. The micro-LED of claim 1, further comprising an integrated circuit (IC) backplane formed underneath the first-type semiconductor layer; and a connection structure electrically connecting the IC backplane with the first-type semiconductor layer.

27. The micro-LED of claim 26, wherein, The connection structure is a connection pillar or a metal bonding layer.

28. The micro-LED of claim 26, further comprising: A bottom contact formed on a bottom surface of the first-type semiconductor layer, an upper surface of the connection structure is connected with the bottom contact, and a bottom surface of the connection structure is connected with the IC backplane.

29. A micro-LED array panel comprising: A plurality of micro-LEDs according to any one of claims 1-28.

30. A micro-LED array panel, comprising: a first-type semiconductor layer formed in the micro-LED array panel; a light-emitting layer formed on the first-type semiconductor layer; and a second-type semiconductor layer formed on the light-emitting layer; wherein the first-type semiconductor layer is P-type and the second-type semiconductor layer is N-type; the first-type semiconductor layer comprises a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches; a top surface of the ion implantation fence is lower than a top surface of the first-type semiconductor layer; the ion implantation fence is formed in a trench between adjacent mesa structures; the mesa structure comprises one or more stepped structures; and a resistance of the ion implantation fence is higher than a resistance of the mesa structure. The ion implantation fence is formed around the trench, and the trench is formed around the mesa structure.

31. The micro-LED array panel of claim 30, wherein, A bottom surface of the ion implantation fence is aligned with or higher than a bottom surface of the first-type semiconductor layer.

32. The micro-LED array panel of claim 30, wherein, A space between adjacent sidewalls of the mesa structure is no more than 50% of a diameter of the mesa structure.

33. The micro-LED array panel of claim 30, wherein, The space between adjacent sidewalls of the mesa structure is no more than 600 nm.

34. The micro-LED array panel of claim 33, wherein, The ion implantation fence absorbs light from the mesa structure, and the ion implantation fence comprises a light-absorbing material, wherein the light-absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

35. The micro-LED array panel of claim 30, wherein, A thickness of the first-type semiconductor layer is greater than a thickness of the second-type semiconductor layer.

36. The micro-LED array panel of claim 30, wherein, 37. The micro-LED array panel of claim 30, further comprising a bottom isolation layer filled in the trench. The ion implanted into the ion implantation fence is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

38. The micro-LED array panel of claim 37, wherein, The material of the bottom isolation layer is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2.

39. The micro-LED array panel of claim 30, wherein, The ion implantation fence is formed at least by implanting ions into the first-type semiconductor layer.

40. The micro-LED array panel of claim 30, wherein, A width of the ion implantation fence is no more than 50% of a diameter of the mesa structure.

41. The micro-LED array panel of claim 30, wherein, The width of the ion implantation fence is no more than 200 nm, the diameter of the mesa structure is no more than 2500 nm, and a thickness of the first-type semiconductor layer is no more than 300 nm.

42. The micro-LED array panel of claim 41, wherein, ​ 43. The micro-LED array panel of claim 30, wherein, The material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

44. The micro LED array panel of claim 30, further comprising a top contact formed on a top surface of the second type semiconductor layer.

45. The micro LED array panel of claim 30, further comprising an integrated circuit (IC) backplane underneath the first type semiconductor layer; and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.

46. The micro-LED array panel of claim 45, wherein, The connection structure is a connection pillar.

47. The micro-LED array panel of claim 45, further comprising a bottom contact formed under a bottom surface of the first type semiconductor layer, wherein, An upper surface of the connection structure is connected with the bottom contact, and a bottom surface of the connection structure is connected with the IC backplane.

48. The micro-LED array panel of claim 30, wherein, The trench extends upward but does not pass through a top surface of the first type semiconductor layer.

49. The micro-LED array panel of claim 48, wherein, A top surface of the ion implantation fence is higher than or aligned with a top surface of the trench.

50. The micro-LED array panel of claim 48, wherein, A top of the ion implantation fence is lower than a top surface of the trench.

51. A method for manufacturing a micro LED, the method comprising: providing an epitaxial structure, wherein the epitaxial structure comprises, in order from top to bottom, a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer; patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence; depositing a bottom contact on the mesa structure; and performing an ion implantation process into the fence to form an ion implantation fence, the ion implantation fence formed around the trench, the trench formed around the mesa structure, the mesa structure comprising one or more stepped structures, a top surface of the ion implantation fence being lower than a top surface of the first type semiconductor layer.

52. The method of claim 51, wherein, After patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, the method further comprises: depositing a bottom isolation layer on the first type semiconductor layer and the bottom contact; patterning the bottom isolation layer to expose the bottom contact; depositing a metal material on the isolation layer and the bottom contact; polishing the metal material to a top surface of the bottom isolation layer to form a connection structure; and flipping the epitaxial structure and bonding the connection structure with an integrated circuit (IC) backplane.

53. The method of claim 52, wherein, When depositing a metallic material on the isolation layer and the bottom contact, the material of the bottom isolation layer is selected from one or more of SiO2, SiN x , AI2O3, AIN, HfO2, TiO2or ZrO2.

54. The method of claim 52, wherein, When providing the epitaxial structure, the epitaxial structure is grown on a substrate.

55. The method of claim 54, wherein, Flipping the epitaxial structure and bonding the connection structure with an integrated circuit (IC) backplane further comprises: removing the substrate.

56. The method of claim 54, wherein, After flipping the epitaxial structure and bonding the connection structure with the IC backplane, the method further comprises: forming a top contact and a top conductive layer on a top surface of the second type semiconductor layer.

57. The method of claim 51, wherein, The depositing a bottom contact on the mesa structure further comprises: forming a protective mask to protect areas where the bottom contact is not to be deposited; depositing a material of the bottom contact on the protective mask and on the first type semiconductor layer; and removing the protective mask from the first type semiconductor layer and removing the material on the protective mask to form the bottom contact on the mesa structure.

58. The method of claim 51, wherein, the performing the ion implantation process into the fence to form an ion implanted fence further comprises: forming a protective mask on areas not to be ion implanted while exposing the fence; implanting ions into the fence; and removing the protective mask.

59. The method of claim 58, wherein, when performing the ion implantation process into the fence to form an ion implanted fence, implanting at an energy of 0 KeV to 500 KeV.

60. The method of claim 58, wherein, When performing the ion implantation process into the enclosure to form a first ion implanted enclosure, a dose of 1E10 cm -2 to 9E17 cm -2 is implanted.

61. The method of claim 58, wherein, when performing the ion implantation process into the fence to form an ion implanted fence, implanting ions into the ion implanted fence, the ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

62. The method of claim 58, wherein, when performing the ion implantation process into the fence to form the ion implanted fence, a width of the ion implanted fence is no more than 50% of a diameter of the mesa structure.

63. The method of claim 58, wherein, when performing the ion implantation process into the fence to form the ion implanted fence, a width of the ion implanted fence is no more than 200 nm, a diameter of the mesa structure is no more than 2500 nm, and a thickness of the first type semiconductor layer is no more than 300 nm.

64. The method of claim 51, wherein, when patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is no more than 50% of a diameter of the mesa structure.

65. The method of claim 51, wherein, the first type semiconductor layer is of a P-type and the second type semiconductor layer is of an N-type, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

66. The method of claim 65, wherein, the ion implanted fence comprises a light absorbing material.

67. The method of claim 66, wherein, the light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

68. A micro-LED, comprising: a first type semiconductor layer; a light emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light emitting layer; wherein the first type semiconductor layer is of a P-type and the second type semiconductor layer is of an N-type; the second type semiconductor layer comprises a mesa structure, a trench, and an ion implanted fence separated from the mesa structure; wherein a bottom surface of the ion implanted fence is higher than a bottom surface of the second type semiconductor layer; and the ion implanted fence comprises a light absorbing material. The ion implantation fence is formed around the trench, the trench is formed around the mesa structure, the mesa structure includes one or more step structures, wherein the ion implantation fence has a higher electrical resistance than the mesa structure.

69. The micro-LED of claim 68, wherein, The trench extends downward but does not pass through a bottom surface of the second type semiconductor layer.

70. The micro-LED of claim 69, wherein, A bottom surface of the ion implantation fence is lower than or aligned with a bottom surface of the trench.

71. The micro-LED of claim 69, wherein, A bottom of the ion implantation fence is higher than a bottom surface of the trench.

72. The micro-LED of claim 68, wherein, A top surface of the ion implantation fence is aligned with or lower than a top surface of the second type semiconductor layer.

73. The micro-LED of claim 68, wherein, A width of the trench is no more than 50% of a diameter of the mesa structure.

74. The micro-LED of claim 73, wherein, A width of the trench is no more than 200 nm.

75. The micro-LED of claim 68, wherein, The ion implantation fence includes a light absorbing material, and the light absorbing material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

76. The micro-LED of claim 68, wherein, A thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.

77. The micro-LED of claim 68, further comprising a dielectric layer filling in the trench.

78. The micro-LED of claim 77, wherein, The material of the dielectric layer is selected from one or more of SiO2, SiN x , AI2O3, AIN, HfO2, TiO2or ZrO2.

79. The micro-LED of claim 68, further comprising a top conductive layer formed on a top surface and sidewalls of the mesa structure, on a top surface and sidewalls of the ion implantation fence, and filling in the trench.

80. The micro-LED of claim 68, wherein, Ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

81. The micro-LED of claim 68, wherein, The ion implantation fence is formed by implanting ions into at least the second type semiconductor layer.

82. The micro-LED of claim 68, wherein, A width of the ion implantation fence is no more than 50% of a diameter of the mesa structure.

83. The micro-LED of claim 82, wherein, A width of the ion implantation fence is no more than 200 nm, a diameter of the mesa structure is no more than 2500 nm, and a thickness of the second type semiconductor layer is no more than 100 nm.

84. The micro-LED of claim 68, wherein, A material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

85. The micro-LED of claim 68, further comprising: A top contact is formed on a top surface of the second type semiconductor layer.

86. The micro-LED of claim 68, further comprising an integrated circuit (IC) backplane under the first type semiconductor layer; and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.

87. The micro-LED of claim 86, wherein, The connection structure is a connection pillar or a metal bonding layer.

88. The micro-LED of claim 86, further comprising: a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure connected with the bottom contact, and a bottom surface of the connection structure connected with the IC backplane.

89. A micro LED array panel comprising: a first type semiconductor layer formed in the micro LED array panel; a light emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light emitting layer; wherein the first type semiconductor layer is P-type and the second type semiconductor layer is N-type; the second type semiconductor layer comprises a plurality of mesa structures, a plurality of trenches, and a plurality of ion implantation fences separated from the mesa structures by the trenches; wherein a bottom surface of the ion implantation fence is higher than a bottom surface of the second type semiconductor layer; the ion implantation fence is formed in a trench between adjacent mesa structures; the mesa structure comprises one or more step structures; and the ion implantation fence has a higher electrical resistance than the mesa structure.

90. The micro-LED array panel of claim 89, wherein, the ion implantation fence is formed around the trench and the trench is formed around the mesa structure.

91. The micro-LED array panel of claim 89, wherein, a top surface of the ion implantation fence is aligned with or lower than a top surface of the second type semiconductor layer.

92. The micro-LED array panel of claim 89, wherein, a space between adjacent sidewalls of the mesa structure is no more than 50% of a diameter of the mesa structure.

93. The micro-LED array panel of claim 92, wherein, a space between adjacent sidewalls of the mesa structure is no more than 600 nm.

94. The micro-LED array panel of claim 89, wherein, the ion implantation fence absorbs light from the mesa structure, the ion implantation fence comprises a light absorbing material, and the light absorbing material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

95. The micro-LED array panel of claim 89, wherein, a thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.

96. The micro LED array panel of claim 89, further comprising a dielectric layer filling in the trench.

97. The micro-LED array panel of claim 96, wherein, The material of the dielectric layer is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2.

98. The micro LED array panel of claim 89, further comprising a top conductive layer formed on a top surface and sidewalls of the mesa structure, on a top surface and sidewalls of the ion implantation fence, and filling in the trench.

99. The micro-LED array panel of claim 89, wherein, ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

100. The micro-LED array panel of claim 89, wherein, the ion implantation fence is formed by implanting ions into at least the second type semiconductor layer.

101. The micro-LED array panel of claim 89, wherein, a width of the ion implantation fence is no more than 50% of a diameter of the mesa structure.

102. The micro-LED array panel of claim 101, wherein, a width of the ion implantation fence is no more than 200 nm, a diameter of the mesa structure is no more than 2500 nm, and a thickness of the second type semiconductor layer is no more than 100 nm.

103. The micro-LED array panel of claim 89, wherein, The material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

104. The micro-LED array panel of claim 89, further comprising: a top contact formed on a top surface of the second type semiconductor layer.

105. The micro-LED array panel of claim 89, further comprising an integrated circuit (IC) backplane under the first type semiconductor layer; and a connection structure electrically connecting the IC backplane and the first type semiconductor.

106. The micro-LED array panel of claim 105, wherein, The connection structure is a connection pillar or a metal bonding layer.

107. The micro-LED array panel of claim 105, further comprising a bottom contact formed on a bottom of the first type semiconductor layer, an upper surface of the connection structure connected with the bottom contact, and a bottom surface of the connection structure connected with the IC backplane.

108. The micro-LED array panel of claim 89, wherein, The trench extends downward but does not pass through a bottom surface of the second type semiconductor layer.

109. The micro-LED array panel of claim 108, wherein, A bottom of the ion implantation fence is lower than or aligned with a bottom surface of the trench.

110. The micro-LED array panel of claim 108, wherein, A bottom surface of the ion implantation fence is higher than a bottom surface of the trench.

111. A method for manufacturing a micro-LED, the method comprising: providing an epitaxial structure, wherein the epitaxial structure comprises, in order from top to bottom, a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer; bonding the epitaxial structure with an integrated circuit (IC) backplane; patterning the second type semiconductor layer to form a mesa structure, a trench, and a fence; depositing a top contact on the mesa structure; performing an ion implantation process into the fence to form an ion implantation fence, the ion implantation fence formed around the trench, the trench formed around the mesa structure, the mesa structure comprising one or more stepped structures, a bottom surface of the ion implantation fence being higher than a bottom surface of the second type semiconductor layer; depositing a top conductive layer on a top surface of the second type semiconductor layer, on the top contact, and in the trench.

112. The method of claim 111, wherein, providing the epitaxial structure further comprises: depositing a bottom contact layer on a top surface of the first type semiconductor layer; and depositing a metal bonding layer on a top surface of the bottom contact layer.

113. The method of claim 112, wherein, bonding the epitaxial structure with the IC backplane further comprises: flipping the epitaxial structure; and bonding the metal bonding layer with a contact pad of the IC backplane.

114. The method of claim 113, wherein, when providing the epitaxial structure, the epitaxial structure is grown on a substrate.

115. The method of claim 114, wherein, bonding the epitaxial structure with the IC backplane further comprises: removing the substrate.

116. The method of claim 111, wherein, patterning the second type semiconductor layer to form the mesa structure, the trench, and the fence further comprises: etching the second type semiconductor layer to a surface of the light emitting layer.

117. The method of claim 111, wherein, depositing the top contact on the mesa structure further comprises: forming a protection mask; depositing a material of the top contact on the protective mask; removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask to form the top contact on the mesa structure.

118. The method of claim 111, wherein, performing the ion implantation process into the enclosure further comprises: forming a protective mask on areas not to be ion implanted while exposing the enclosure; implanting ions into the enclosure; and removing the protective mask.

119. The method of claim 118, wherein, when performing the ion implantation process into the enclosure, implanting ions at an energy of 0 KeV to 500 KeV.

120. The method of claim 118, wherein, When performing the ion implantation process into the enclosure, a dose of 1E10 cm -2 to 9E17 cm -2 is implanted.

121. The method of claim 118, wherein, when performing the ion implantation process into the enclosure, implanting ions into the ion implantation enclosure, the ions selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

122. The method of claim 118, wherein, when performing the ion implantation process into the enclosure, a width of the ion implantation enclosure is no more than 50% of a diameter of the mesa structure.

123. The method of claim 118, wherein, when performing the ion implantation process into the enclosure, a width of the ion implantation enclosure is no more than 200 nm, a diameter of the mesa structure is no more than 2500 nm, and a thickness of the second type semiconductor layer is no more than 100 nm.

124. The method of claim 111, wherein, the first type semiconductor layer is of a P-type and the second type semiconductor layer is of an N-type; wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

125. The method of claim 124, wherein, the ion implantation enclosure comprises a light absorbing material.

126. The method of claim 125, wherein, the light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

127. A micro-LED comprising: a first type semiconductor layer; a light emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light emitting layer; wherein the first type semiconductor layer is of a P-type and the second type semiconductor layer is of an N-type; the first type semiconductor layer comprises a first mesa structure, a first trench, and a first ion implantation enclosure separated from the first mesa structure; wherein a top surface of the first ion implantation enclosure is lower than a top surface of the first type semiconductor layer; the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation enclosure separated from the second mesa structure; wherein a bottom surface of the second ion implantation enclosure is higher than a bottom surface of the second type semiconductor layer; the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation enclosure separated from the second mesa structure; wherein a bottom surface of the second ion implantation enclosure is higher than a bottom surface of the second type semiconductor layer; The first ion implantation fence is formed around the first trench, and the first trench is formed around the first mesa structure, wherein the electrical resistance of the first ion implantation fence is higher than the electrical resistance of the first mesa structure; and The second ion implantation fence is formed around the second trench, and the second trench is formed around the second mesa structure, wherein the electrical resistance of the second ion implantation fence is higher than the electrical resistance of the second mesa structure.

128. The micro-LED of claim 127, wherein, The center of the first mesa structure is aligned with the center of the second mesa structure, the center of the first trench is aligned with the center of the second trench, and the center of the first ion implantation fence is aligned with the center of the second ion implantation fence.

129. The micro-LED of claim 127, wherein, The bottom surface of the first ion implantation fence is aligned with or higher than the bottom surface of the first type semiconductor layer; And / or, the top surface of the second ion implantation fence is aligned with or lower than the top surface of the second type semiconductor layer.

130. The micro-LED of claim 127, wherein, The first trench extends upwards but does not pass through the top of the first type semiconductor layer; and / or, the second trench extends downwards but does not pass through the bottom of the second type semiconductor layer.

131. The micro-LED of claim 130, wherein, The top surface of the first ion implantation fence is higher than or aligned with the top of the first trench; And / or, the bottom of the second ion implantation fence is lower than or aligned with the bottom of the second trench.

132. The micro-LED of claim 130, wherein, The top of the first ion implantation fence is lower than the top of the first trench; and / or, the bottom of the second ion implantation fence is higher than the bottom of the second trench.

133. The micro-LED of claim 127, wherein, The first mesa structure comprises one or more stepped structures; and / or, the second mesa structure comprises one or more stepped structures.

134. The micro-LED of claim 127, wherein, The width of the first trench is no more than 50% of the diameter of the first mesa structure; and / or, the width of the second trench is no more than 50% of the diameter of the second mesa structure.

135. The micro-LED of claim 134, wherein, The width of the first trench is no more than 200 nm; and / or, the width of the second trench is no more than 200 nm.

136. The micro-LED of claim 127, wherein, The first ion implantation fence comprises a first light-absorbing material; and / or, the second ion implantation fence comprises a second light-absorbing material; the first light-absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN or p-AlGaN; and / or, the second light-absorbing material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN or n-AlGaN.

137. The micro-LED of claim 127, wherein, The thickness of the first type semiconductor layer is greater than the thickness of the second type semiconductor layer.

138. The micro-LED of claim 127, further comprising a bottom isolation layer filling in the first trench; and a dielectric layer filling in the second trench.

139. The micro-LED of claim 138, wherein, The material of the bottom isolation layer is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2; and / or, the material of the dielectric layer is one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2.

140. The micro-LED of claim 127, further comprising a top conductive layer formed on a top surface and sidewalls of the second mesa structure, on a top surface and sidewalls of the second ion implantation fence, and filling in the second trench.

141. The micro-LED of claim 127, wherein, the ions implanted into the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F; and / or, the ions implanted into the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

142. The micro-LED of claim 127, wherein, the first ion implantation fence is formed by implanting ions into at least the first type semiconductor layer; and / or, the second ion implantation fence is formed by implanting ions into at least the second type semiconductor layer.

143. The micro-LED of claim 127, wherein, a width of the first ion implantation fence is no more than 50% of a diameter of the first mesa structure; and / or, a width of the second ion implantation fence is no more than 50% of a diameter of the second mesa structure.

144. The micro-LED of claim 143, wherein, a width of the first ion implantation fence is no more than 200 nm, a diameter of the first mesa structure is no more than 2500 nm, and a thickness of the first type semiconductor layer is no more than 100 nm; and / or, a width of the second ion implantation fence is no more than 200 nm, a diameter of the second mesa structure is no more than 2500 nm, and a thickness of the second type semiconductor layer is no more than 300 nm.

145. The micro-LED of claim 127, wherein, a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and / or, a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

146. The micro-LED of claim 127, further comprising: a top contact formed on a top surface of the second type semiconductor layer.

147. The micro-LED of claim 127, further comprising an integrated circuit (IC) backplane under the first type semiconductor layer; and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.

148. The micro-LED of claim 147, wherein, the connection structure is a connection pillar or a metal bonding layer.

149. The micro-LED of claim 147, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure connected with the bottom contact, and a bottom surface of the connection structure connected with the IC backplane.

150. A micro-LED array panel, comprising, a first type semiconductor layer formed in the micro-LED array panel; a light emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light emitting layer; a first type semiconductor layer formed in the micro-LED array panel; a light emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light emitting layer; wherein the first type semiconductor layer is P-type and the second type semiconductor layer is N-type; the first type semiconductor layer comprises a plurality of first mesa structures, a plurality of first trenches, and a plurality of first ion implantation fences separated from the first mesa structures by the first trenches; wherein a top surface of the first ion implantation fence is lower than a top surface of the first type semiconductor layer; the first ion implantation fence is formed in a first trench between adjacent first type mesa structures, wherein a resistance of the first ion implantation fence is higher than a resistance of the first mesa structure; the second type semiconductor layer comprises a plurality of second mesa structures, a plurality of second trenches, and a plurality of second ion implantation fences separated from the second mesa structures by the second trenches; wherein a bottom surface of the second ion implantation fence is higher than a bottom surface of the second type semiconductor layer; and the second ion implantation fence is formed in a second trench between adjacent second mesa structures, wherein a resistance of the second ion implantation fence is higher than a resistance of the second mesa structure.

151. The micro-LED array panel of claim 150, wherein, a center of the first mesa structure is aligned with a center of the second mesa structure; a center of the first trench is aligned with a center of the second trench; and a center of the first ion implantation fence is aligned with a center of the first ion implantation fence.

152. The micro-LED array panel of claim 150, wherein, the first ion implantation fence is formed around the first trench, the first trench is formed around the first mesa structure, the second ion implantation fence is formed around the second trench, and the second trench is formed around the second mesa structure.

153. The micro-LED array panel of claim 152, wherein, a bottom surface of the first ion implantation fence is aligned with or higher than a bottom surface of the first type semiconductor layer; and a top surface of the second ion implantation fence is aligned with or lower than a top surface of the second type semiconductor layer.

154. The micro-LED array panel of claim 150, wherein, a space between adjacent sidewalls of the first mesa structure is no more than 50% of a diameter of the first mesa structure; and a space between adjacent sidewalls of the second mesa structure is no more than 50% of a diameter of the second mesa structure.

155. The micro-LED array panel of claim 154, wherein, a space between adjacent sidewalls of the first mesa structure is no more than 600 nm, and a space between adjacent sidewalls of the second mesa structure is no more than 600 nm.

156. The micro-LED array panel of claim 150, wherein, the first ion implantation fence absorbs light from the first mesa structure, the second ion implantation fence absorbs light from the second mesa structure; the first ion implantation fence comprises a first light absorbing material, the second ion implantation fence comprises a second light absorbing material; the first light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the second light absorbing material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

157. The micro-LED array panel of claim 150, wherein, a thickness of the first type semiconductor layer is greater than a thickness of the second type semiconductor layer.

158. The micro LED array panel of claim 150, further comprising a bottom isolation layer filling in the first trench; and a dielectric layer filling in the second trench.

159. The micro-LED array panel of claim 158, wherein, The material of the bottom isolation layer is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2; and the material of the dielectric layer is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2.

160. The micro LED array panel of claim 150, further comprising a top conductive layer formed on a top surface and sidewalls of the second mesa structure, on a top and sidewalls of the second ion implantation fence, and filling in the second trench.

161. The micro-LED array panel of claim 150, wherein, The first ion implanted into the first ion implantation fence is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F; and the second ion implanted into the second ion implantation fence is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

162. The micro-LED array panel of claim 150, wherein, The first ion implantation fence is formed by implanting ions into at least the first type semiconductor layer.

163. The micro-LED array panel of claim 150, wherein, A width of the first ion implantation fence is no more than 50% of a diameter of the first mesa structure; and a width of the second ion implantation fence is no more than 50% of a diameter of the second mesa structure.

164. The micro-LED array panel of claim 163, wherein, A width of the ion implantation fence is no more than 200 nm, a diameter of the mesa structure is no more than 2500 nm, and a thickness of the first type semiconductor layer is no more than 300 nm; and A width of the second ion implantation fence is no more than 200 nm, a diameter of the second mesa structure is no more than 2500 nm, and a thickness of the second type semiconductor layer is no more than 100 nm.

165. The micro-LED array panel of claim 150, wherein, A material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and a material of the second type semiconductor layer is n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

166. The micro-LED array panel of claim 150, further comprising: A top contact formed on a top surface of the second type semiconductor layer.

167. The micro LED array panel of claim 150, further comprising an integrated circuit (IC) backplane underneath the first type semiconductor layer; and a connection structure electrically connecting the IC backplane with the first type semiconductor layer.

168. The micro-LED array panel of claim 167, wherein, The connection structure is a connection pillar or a metal bonding layer.

169. The micro-LED array panel of claim 167, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer; wherein, An upper surface of the connection structure is connected with the bottom contact, and a bottom surface of the connection structure is connected with the IC backplane.

170. The micro-LED array panel of claim 150, wherein, The first trench extends upward but does not pass through a top surface of the first type semiconductor layer; and the second trench extends downward but does not pass through a bottom surface of the second type semiconductor layer.

171. The micro-LED array panel of claim 170, wherein, A top surface of the first ion implantation fence is higher than or aligned with a top surface of the first trench; A top surface of the first ion implantation fence is higher than or aligned with a top surface of the first trench; and a bottom surface of the second ion implantation fence is lower than a bottom surface of the first trench or aligned with the bottom surface of the first trench.

172. The micro-LED array panel of claim 170, wherein, a top surface of the first ion implantation fence is lower than a top surface of the first trench; and a bottom surface of the second ion implantation fence is higher than a bottom surface of the second trench.

173. A method for fabricating micro-LEDs, the method comprising: Process I, which comprises patterning a first type semiconductor layer and implanting first ions into the first type semiconductor layer to form a mesa structure, a trench, and an ion implantation fence having a top surface lower than a top surface of the first type semiconductor layer, the ion implantation fence formed around the trench, the trench formed around the mesa structure, the mesa structure comprising one or more stepped structures; and Process II, which comprises patterning a second type semiconductor layer and implanting second ions into the second type semiconductor layer to form a mesa structure, a trench, and an ion implantation fence having a bottom surface higher than a bottom surface of the second type semiconductor layer, the ion implantation fence formed around the trench, the trench formed around the mesa structure, the mesa structure comprising one or more stepped structures.

174. The method of claim 173, wherein, the Process I further comprises: providing an epitaxial structure, wherein the epitaxial structure comprises, in order from top to bottom, a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer; patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence; depositing a bottom contact on the mesa structure; performing an ion implantation process into the fence to form an ion implantation fence; depositing a bottom isolation layer on the first type semiconductor layer and the bottom contact; patterning the bottom isolation layer to expose the bottom contact; depositing a metal material on the isolation layer and the bottom contact; polishing the metal material to a top surface of the bottom isolation layer to form a connection structure; flipping the epitaxial structure and bonding the connection structure with an integrated circuit (IC) backplane.

175. The method of claim 174, wherein, depositing the bottom contact on the mesa structure further comprises: forming a protection mask to protect an area where the bottom contact is not deposited; depositing a material of the bottom contact on the protection mask and on the first type semiconductor layer; and removing the protection mask from the first type semiconductor layer and removing the material on the protection mask to form the bottom contact on the mesa structure.

176. The method of claim 174, wherein, performing the ion implantation process into the fence to form the ion implantation fence further comprises: forming a protection mask on an area not implanted with ions while leaving the fence exposed; implanting ions into the fence; and removing the protection mask.

177. The method of claim 176, wherein, When performing the ion implantation process into the enclosure to form the ion implanted enclosure, implantation is performed at an energy of 0 KeV to 500 KeV, and a dose of 1E10 cm -2 to 9E17 cm -2 .

178. The method of claim 176, wherein, implanting ions into the fence when performing the ion implantation process into the fence to form the ion implantation fence, the ions are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

179. The method of claim 176, wherein, the ion implantation fence has a width no greater than 50% of a diameter of the mesa structure when performing the ion implantation process into the fence to form the ion implantation fence. The ion implantation penalis is not more than 200 nm in width, the mesa structure is not more than 2500 nm in diameter, and the first type semiconductor layer is not more than 300 nm in thickness.

180. The method of claim 174, wherein, In patterning the first type semiconductor layer to form the mesa structure, the trench, and the penalis, the trench is not more than 50% of the diameter of the mesa structure in width.

181. The method of claim 173, wherein, The mesa structure, the trench, and the penalis are a first mesa structure, a first trench, and a first penalis, respectively; wherein the process II further comprises: patterning the second type semiconductor layer to form a second mesa structure, a second trench, and a second penalis; depositing a top contact on the second mesa structure; performing an ion implantation process into the second penalis; depositing a top conductive layer on a top surface of the second type semiconductor layer, on the top contact, and in the second trench.

182. The method of claim 181, wherein, The depositing the top contact on the second mesa structure further comprises: forming a protective mask; depositing a material of the top contact on the protective mask; removing the protective mask from the second type semiconductor layer and removing the material of the top contact on the protective mask to form a top contact on the second mesa structure.

183. The method of claim 181, wherein, The performing the ion implantation process into the second penalis further comprises: forming a protective mask on unimplanted areas while exposing the second penalis; implanting the ions into the second penalis; and removing the protective mask.

184. The method of claim 181, wherein, When performing the ion implantation process into the second fence, implantation is performed at an energy of 0 KeV to 500 KeV, and a dose of 1E10 cm -2 to 9E17 cm -2 .

185. The method of claim 181, wherein, In performing the ion implantation process into the second penalis, ions are implanted into the second penalis, the ions are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

186. The method of claim 181, wherein, In performing the ion implantation process into the second penalis, the second penalis is not more than 50% of the diameter of the second mesa structure in width; the second penalis is not more than 200 nm in width, the second mesa structure is not more than 2500 nm in diameter, and the second type semiconductor layer is not more than 100 nm in thickness.

187. The method of claim 174, wherein, In providing the epitaxial structure, the epitaxial structure is grown on a substrate; the flipping the epitaxial structure and bonding the connection structure with the IC backplane further comprises: removing the substrate.

188. The method of claim 174, wherein, When depositing the bottom isolation layer on the first type semiconductor layer and the bottom contact, the material of the bottom isolation layer is selected from one or more of SiO2, SiN x , AI2O3, AIN, HfO2, TiO2or ZrO2.

189. The method of claim 174, wherein, The ion implantation penalis comprises a light absorbing material.

190. The method of claim 189, wherein, The light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

191. The method of claim 174, wherein, The first type semiconductor layer has a P-type conductivity and the second type semiconductor layer has an N-type conductivity; and the material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN or p-AlGaN; and the material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN or n-AlGaN. The first type semiconductor layer has a P-type conductivity and the second type semiconductor layer has an N-type conductivity; and the material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN or p-AlGaN; and the material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN or n-AlGaN.

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