Methods, systems, devices, and media for impedance optimization of complex single-ended through silicon vias

Abstract

The application provides a method, system, device and medium for impedance optimization of complex single-ended TSV, comprising: performing quasi-static three-dimensional electromagnetic simulation on a target TSV loop to obtain total loop inductance and total capacitance of a TSV structure; constructing a transmission line profile model connected at both ends of the TSV to obtain unit length capacitance and unit length inductance of a transmission line at both ends of the TSV; based on the total loop inductance and the total capacitance of the TSV structure and the unit length capacitance and the unit length inductance of the transmission line at both ends of the TSV, obtaining loop inductance and capacitance of an intermediate TSV part, and calculating characteristic impedance of the target TSV loop based on the loop inductance and the capacitance of the intermediate TSV part; comparing the characteristic impedance of the target TSV loop with target characteristic impedance, and performing impedance matching optimization on an existing structure to obtain a new structure after optimization; the application can greatly reduce the optimization design time of complex single-ended TSV in 2.5D and 3D packaging products, and improve product design efficiency.

Description

Technical Field

[0001] This invention belongs to the field of advanced packaging technology, specifically to a method, system, device, and medium for impedance optimization of complex single-ended through-silicon vias. Background Technology

[0002] With the rapid development of heterogeneous integration technology in the field of advanced packaging, 2.5D / 3D system packaging based on through silicon vias (TSV) has become an important solution to continue Moore's Law in the post-Moore era. TSV enables chip-to-chip communication to achieve shorter signal transmission latency, lower power consumption, and smaller package size.

[0003] However, the presence of TSV makes the signal integrity design of advanced packages more complex. The transition region formed by TSV and transmission line has an impedance discontinuity region, which greatly increases the difficulty of impedance matching design. In the existing related technologies, there is a lack of a method that can accurately analyze and optimize complex single-ended through silicon vias. Summary of the Invention

[0004] To address the problems existing in the prior art, the present invention provides a method, system, device and medium for impedance optimization of complex single-ended through-silicon vias, thereby solving the technical problem that the prior art cannot accurately analyze and optimize complex single-ended through-silicon vias.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for impedance optimization of complex single-ended through-silicon vias includes the following steps:

[0007] Quasi-static three-dimensional electromagnetic simulation of the target TSV circuit was performed to obtain the total loop inductance and total capacitance of the TSV structure.

[0008] Construct a cross-sectional model of the transmission line connecting the two ends of the TSV to obtain the capacitance and inductance per unit length of the transmission line at both ends of the TSV.

[0009] Based on the total loop inductance and total capacitance of the TSV structure, and the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV, the loop inductance and capacitance of the middle TSV section are obtained, and the characteristic impedance of the target TSV loop is calculated based on the loop inductance and capacitance of the middle TSV section.

[0010] The characteristic impedance of the target TSV circuit is compared with the target characteristic impedance, and the impedance matching of the existing structure is optimized to obtain the optimized new structure.

[0011] Furthermore, the quasi-static three-dimensional electromagnetic simulation of the target TSV circuit is performed to obtain the total loop inductance and total capacitance of the TSV structure, including:

[0012] The simulation equipment identifies the signal net and gndnet of the TSV structure based on the target TSV loop;

[0013] Select the current inflow and outflow planes of the signal net and gndnet, and set the current inflow plane as source and the current outflow plane as sink;

[0014] The simulation device outputs simulation results based on the pre-set simulation frequency band, the saved field distribution results, the solution frequency, and the simulation convergence conditions. The unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV are obtained from the simulation results.

[0015] Furthermore, the construction of the transmission line cross-sectional model connecting the two ends of the TSV to obtain the capacitance and inductance per unit length of the transmission line at both ends of the TSV includes:

[0016] In AnsysQ2D software, construct a transmission line profile model connecting the two ends of the TSV. The transmission line structure at both ends is designed by default to the target characteristic impedance.

[0017] The cross-section of the signal line is selected as the signal conductor, and the cross-section of the gnd plane is selected as the reference ground. The simulation bandwidth, solution frequency and simulation convergence conditions are set to obtain the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV.

[0018] Furthermore, the total loop inductance and total capacitance based on the TSV structure, and the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV, to obtain the loop inductance and capacitance of the middle TSV section, include:

[0019] C tsv =C X -C 1pul ×len-C 2pul ×len (1)

[0020] L tsv =L x -L 1pul ×len-L 2pul ×len (2)

[0021] Among them, L tsv C is the loop inductance of the intermediate TSV section. tsv For the loop capacitor of the intermediate TSV section, L X For the total loop inductance of the TSV structure, C X C is the total loop capacitance of the TSV structure. 1pul and L 1pul Transmission line C connected to the upper part of TSV pulWith L pul C 2pul and L 2pul Transmission line C connected to the lower part of TSV pul With L pul .

[0022] Furthermore, the characteristic impedance of the target TSV loop is calculated based on the loop inductance and capacitance of the intermediate TSV section. The characteristic impedance is:

[0023]

[0024] Among them, L tsv C is the loop inductance of the intermediate TSV section. tsv Z is the loop capacitor of the intermediate TSV section. O This is the characteristic impedance.

[0025] Furthermore, the step of comparing the characteristic impedance of the target TSV circuit with the target characteristic impedance, and performing impedance matching optimization on the existing structure to obtain an optimized new structure, includes:

[0026] If the characteristic impedance of the target TSV loop is less than the target characteristic impedance, then the loop capacitance of the intermediate TSV section is reduced, and the loop inductance of the intermediate TSV section is increased.

[0027] If the characteristic impedance of the target TSV circuit is greater than the target characteristic impedance, then the circuit capacitance of the intermediate TSV section is increased, and the circuit inductance of the intermediate TSV section is reduced.

[0028] Furthermore, the process also includes running the optimized new structure in AnsysHFSS and observing whether the return loss in the simulation results is lower than a preset threshold across the entire frequency domain. If it is lower than the preset threshold, the optimization of the structure is successful; otherwise, the optimization is repeated.

[0029] A system for impedance optimization of complex single-ended through-silicon vias, comprising:

[0030] The simulation unit is configured as follows:

[0031] Used for quasi-static three-dimensional electromagnetic simulation of the target TSV circuit to obtain the total loop inductance and total capacitance of the TSV structure;

[0032] The model unit is constructed and configured as follows:

[0033] This is used to construct a cross-sectional model of the transmission line connecting the two ends of the TSV, and to obtain the capacitance and inductance per unit length of the transmission line at both ends of the TSV.

[0034] The computing unit is configured as follows:

[0035] The total loop inductance and total capacitance based on the TSV structure, as well as the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV, are used to obtain the loop inductance and capacitance of the middle TSV section, and the characteristic impedance of the target TSV loop is calculated based on the loop inductance and capacitance of the middle TSV section.

[0036] The optimization unit is configured as follows:

[0037] This is used to compare the characteristic impedance of the target TSV circuit with the target characteristic impedance, and to optimize the impedance matching of the existing structure to obtain an optimized new structure.

[0038] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of a method for impedance optimization of complex single-ended through-silicon vias.

[0039] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of a method for impedance optimization of complex single-ended through-silicon vias.

[0040] Compared with the prior art, the present invention has the following beneficial technical effects:

[0041] This invention provides a method, system, device, and medium for impedance optimization of complex single-ended through-silicon vias (TSVs), comprising the following steps: performing quasi-static three-dimensional electromagnetic simulation on the target TSV loop to obtain the total loop inductance and total capacitance of the TSV structure; constructing a transmission line profile model connecting the two ends of the TSV to obtain the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV; based on the total loop inductance and total capacitance of the TSV structure, and the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV, obtaining the loop inductance and capacitance of the intermediate TSV portion, and calculating the characteristic impedance of the target TSV loop based on the loop inductance and capacitance of the intermediate TSV portion; comparing the characteristic impedance of the target TSV loop with the target characteristic impedance, and... This application optimizes the impedance matching of existing structures to obtain optimized new structures. Utilizing a three-dimensional quasi-static electromagnetic simulation tool, it can accurately determine the frequency domain characteristic impedance of complex single-ended TSVs and obtain the main structural parameters affecting the TSV characteristic impedance. This guides packaging design engineers to optimize the structural design of complex single-ended TSVs, achieving an extremely high accuracy of ±2Ω impedance matching error. It guides packaging design engineers to design complex single-ended TSV structures that meet optimal impedance matching. This application is applicable to various TSV-based interconnect packaging products, offering high design accuracy and wide bandwidth coverage. This invention can significantly reduce the optimization design time of complex single-ended TSVs in 2.5D and 3D packaging products, improving product design efficiency. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating a method for impedance optimization of complex single-ended silicon vias according to an embodiment of this disclosure.

[0043] Figure 2 This is a flowchart illustrating a method for impedance optimization of complex single-ended silicon vias according to an embodiment of this disclosure.

[0044] Figure 3 This is a quasi-static three-dimensional electromagnetic simulation model of the TSV circuit of structure X in the embodiments of this disclosure;

[0045] Figure 4 This is a schematic cross-sectional view of the transmission line of CPWG1 in structure X in an embodiment of this disclosure;

[0046] Figure 5 This is a schematic cross-sectional view of the transmission line of CPWG2 in structure X in an embodiment of this disclosure;

[0047] Figure 6 This is a schematic diagram of the charge distribution of the TSV circuit of structure X in an embodiment of this disclosure;

[0048] Figure 7 The insertion loss of the TSV loop of structure X in the embodiments of this disclosure;

[0049] Figure 8 The return loss of the TSV loop of structure X in the embodiments of this disclosure;

[0050] Figure 9 This is a quasi-static three-dimensional electromagnetic simulation model of the TSV circuit of structure O in the embodiments of this disclosure;

[0051] Figure 10 The insertion loss of the OTSV circuit in the embodiments of this disclosure;

[0052] Figure 11 This refers to the return loss of the OTSV circuit in the embodiments of this disclosure. Detailed Implementation

[0053] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0054] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0056] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0057] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0058] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0059] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0060] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0061] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0062] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0063] Figure 1 An embodiment of this disclosure illustrates a method for impedance optimization of complex single-ended through-silicon vias, comprising the following steps:

[0064] Quasi-static three-dimensional electromagnetic simulation of the target TSV circuit was performed to obtain the total loop inductance and total capacitance of the TSV structure.

[0065] Construct a cross-sectional model of the transmission line connecting the two ends of the TSV to obtain the capacitance and inductance per unit length of the transmission line at both ends of the TSV.

[0066] Based on the total loop inductance and total capacitance of the TSV structure, and the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV, the loop inductance and capacitance of the middle TSV section are obtained, and the characteristic impedance of the target TSV loop is calculated based on the loop inductance and capacitance of the middle TSV section.

[0067] The characteristic impedance of the target TSV circuit is compared with the target characteristic impedance, and the impedance matching of the existing structure is optimized to obtain the optimized new structure.

[0068] In a preferred embodiment of this disclosure, the step of performing a quasi-static three-dimensional electromagnetic simulation on the target TSV circuit to obtain the total loop inductance and total capacitance of the TSV structure includes:

[0069] The simulation equipment identifies the signal net and gndnet of the TSV structure based on the target TSV loop;

[0070] Select the current inflow and outflow planes of the signal net and gndnet, and set the current inflow plane as source and the current outflow plane as sink;

[0071] The simulation device outputs simulation results based on the pre-set simulation frequency band, the saved field distribution results, the solution frequency, and the simulation convergence conditions. The unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV are obtained from the simulation results.

[0072] In a preferred embodiment of this disclosure, the step of constructing a transmission line cross-sectional model connecting the two ends of the TSV to obtain the capacitance and inductance per unit length of the transmission line at both ends of the TSV includes:

[0073] In AnsysQ2D software, construct a transmission line profile model connecting the two ends of the TSV. The transmission line structure at both ends is designed by default to the target characteristic impedance.

[0074] The cross-section of the signal line is selected as the signal conductor, and the cross-section of the gnd plane is selected as the reference ground. The simulation bandwidth, solution frequency and simulation convergence conditions are set to obtain the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV.

[0075] In a preferred embodiment of this disclosure, the process of obtaining the loop inductance and capacitance of the intermediate TSV portion based on the total loop inductance and total capacitance of the TSV structure, and the capacitance and inductance per unit length of the transmission lines at both ends of the TSV, includes:

[0076] C tsv =C X -C 1pul ×len-C 2pul ×len (1)

[0077] L tsv =L X -L 1pul ×len-L 2pul ×len (2)

[0078] Among them, L tsv C is the loop inductance of the intermediate TSV section. tsv For the loop capacitor of the intermediate TSV section, L X For the total loop inductance of the TSV structure, C X C is the total loop capacitance of the TSV structure. 1pul and L 1pul Transmission line C connected to the upper part of TSVpul With L pul C 2pul and L 2pul Transmission line C connected to the lower part of TSV pul With L pul .

[0079] In a preferred embodiment of this disclosure, the characteristic impedance of the target TSV loop is calculated based on the loop inductance and capacitance of the intermediate TSV section. The characteristic impedance is:

[0080]

[0081] Among them, L tsv C is the loop inductance of the intermediate TSV section. tsv Z is the loop capacitor of the intermediate TSV section. O This is the characteristic impedance.

[0082] In a preferred embodiment of this disclosure, comparing the characteristic impedance of the target TSV circuit with the target characteristic impedance and performing impedance matching optimization on the existing structure to obtain an optimized new structure includes:

[0083] If the characteristic impedance of the target TSV loop is less than the target characteristic impedance, then the loop capacitance of the intermediate TSV section is reduced, and the loop inductance of the intermediate TSV section is increased.

[0084] If the characteristic impedance of the target TSV circuit is greater than the target characteristic impedance, then the circuit capacitance of the intermediate TSV section is increased, and the circuit inductance of the intermediate TSV section is reduced.

[0085] In a preferred embodiment of this disclosure, the optimized new structure is run in AnsysHFSS, and the simulation results are observed to see if the return loss is lower than a preset threshold in the full frequency domain. If it is lower than the preset threshold, the structure optimization is successful; otherwise, the optimization is repeated.

[0086] Example 1

[0087] by Figure 3 Taking the complex coaxial TSV structure (structure X) shown as an example, based on the above analysis, Q3D is used to... Figure 3 The equivalent circuit model of the TSV structure is performed. This structure is taken from the actual RF layout. The signal transmission part consists of ground coplanar waveguide (CPWG) transmission lines (CPWG1 and CPWG2), vias (via1 and via2) and dual-signal TSVs. The return current part consists of a ground plane and 34 ground TSVs. There are a total of 4 metal layers (two layers on the front and two layers on the back of silicon). Figure 2 The pink highlighted area represents the signal transmission section. Figure 4 and Figure 5The images show the transmission line cross-sections of CPWG1 and CPWG2, with a metal thickness of 5µm and a silicon thickness of 200µm. Both CPWG1 and CPWG2 are 500µm long. The length of CPWG1 is calculated from the leftmost end of structure X to the leftmost anti-pad of via1, and the length of CPWG2 is calculated from the rightmost end of structure X to the rightmost anti-pad of via2.

[0088] The total capacitance (C) of this structure can be obtained by simulating structure X using Q3D. X ) and total inductance (L X ), C X 320fF, L X The pH is 468.15. Since CPWG1 and CPWG2 are uniform and continuous transmission lines, TSV interconnect modeling should be performed after removing CPWG1 and CPWG2 from structure X. That is, the TSV structure to be optimized should consist of via1, dual-signal TSVs, via2, the corresponding return ground TSV, and the ground plane. However, if only the above portion is removed (without the CPWG transmission lines), and the overall capacitance is solved using Q3D, the calculated capacitance will lose the coupling capacitance between this structure and the CPWG transmission lines, leading to an inaccurate equivalent circuit model. Therefore, the capacitance (C) of the TSV structure to be optimized (without the CPWG transmission lines) is... tsv ) and inductance (L tsv The indirect de-embedding method is used to obtain the result, that is, according to formulas (1) and (2).

[0089] In formulas (1) and (2), len represents the length of the CPWG transmission line, which is 500 μm. C in formulas (1) and (2) 1pul C 2pul L 1pu and L 2pul The four parameters can be determined according to Figure 4 and Figure 5 The cross-sectional structure was obtained from Ansys Q2D, and the required C 1pul and C 2pul Equal, both are 0.124 fF / um, L 1pul and L 2pul The values ​​are equal, both being 0.294 pH / µm. Therefore, C can be obtained from formulas (1) and (2). tsv For 196fF, L tsv The pH value is 174.15.

[0090] From C tsv and L tsv The numerical values ​​also reveal the characteristic impedance of the complex TSV structure. Its characteristic impedance ZO can be obtained from formula (3). OThe impedance is 30Ω. Clearly, this TSV structure is not matched with the CPWG transmission lines at its left and right ends, which have a characteristic impedance of 50Ω. Figure 8 The return loss of structure X is greater than -10dB above 20GHz. Therefore, the ZO of this complex TSV structure needs further optimization. To make Z... O Reaching 50Ω allows for an increase in the area of ​​the anti-solder pad, thereby reducing C. tsv In addition, due to the large capacitance formed between the TSV pad surface and the M2 (M2B) ground plane, Figure 6 The brightest part of the charge distribution indicates that if the ground plane portion overlapping with the TSV pad is cut off, the capacitance of that portion will also decrease, thus reducing C. tsv Further reduction is needed. Based on this analysis, the ground planes of the M2 and M2B layers overlapping with the TSV pads can be removed first. Then, a circular anti-pad region with a parameterizable diameter can be created in the TSV pad area of ​​structure X. The anti-pad region can be parametrically scanned using Ansys Q3D, and the L obtained after each scan can be used to further reduce the size. tsv With C tsv Calculate the new Z O When the obtained Z O When the resistance approaches 50Ω, the parametric scan can be stopped. Based on this, the optimization steps are as follows: Figure 9 The optimized complex TSV structure (structure O) is shown in the figure. The diameter of the anti-pad region is 280 μm. The ground planes of the M2 and M2B layers that overlap with the TSV pads have been removed. The resulting Ltsv and Ctsv are 250.5 pH and 100 fF, respectively. O The S-parameter amplitude obtained from the full-wave electromagnetic field simulation of structure O is 50Ω. Figure 10 and Figure 11 As shown.

[0091] Compare Figure 7 , Figure 8 , Figure 10 and Figure 11 It can be seen that the maximum insertion loss of structure O is 0.48dB, and the return loss is less than -30dB across the entire frequency domain; the maximum insertion loss of structure X is 1.16dB, and the return loss is greater than -10dB above 20GHz. Clearly, both the insertion loss and return loss of structure O are smaller than those of structure X, demonstrating the correctness and guiding significance of the optimization design method proposed in this invention.

[0092] This embodiment also provides a system for impedance optimization of complex single-ended through-silicon vias, including:

[0093] The simulation unit is configured as follows:

[0094] Used for quasi-static three-dimensional electromagnetic simulation of the target TSV circuit to obtain the total loop inductance and total capacitance of the TSV structure;

[0095] The model unit is constructed and configured as follows:

[0096] This is used to construct a cross-sectional model of the transmission line connecting the two ends of the TSV, and to obtain the capacitance and inductance per unit length of the transmission line at both ends of the TSV.

[0097] The computing unit is configured as follows:

[0098] The total loop inductance and total capacitance based on the TSV structure, as well as the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV, are used to obtain the loop inductance and capacitance of the middle TSV section, and the characteristic impedance of the target TSV loop is calculated based on the loop inductance and capacitance of the middle TSV section.

[0099] The optimization unit is configured as follows:

[0100] This is used to compare the characteristic impedance of the target TSV circuit with the target characteristic impedance, and to optimize the impedance matching of the existing structure to obtain an optimized new structure.

[0101] In another embodiment of the present invention, a computer device is provided, comprising a processor and a memory. The memory stores a computer program, which includes program instructions. The processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions in the computer storage medium to achieve a corresponding method flow or corresponding function. The processor described in this embodiment of the present invention can be used to operate a method for impedance optimization of complex single-ended through-silicon vias.

[0102] In another embodiment of the present invention, a storage medium is provided, specifically a computer-readable storage medium (Memory), which is a memory device in a computer device used to store programs and data. It is understood that the computer-readable storage medium here can include both the built-in storage medium in the computer device and extended storage media supported by the computer device. The computer-readable storage medium provides storage space that stores the operating system of the terminal. Furthermore, the storage space also stores one or more instructions suitable for loading and execution by a processor, which can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk storage device. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the method for impedance optimization of complex single-ended through-silicon vias in the above embodiments.

[0103] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0104] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0105] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0106] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0107] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the scope of the invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0108] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A method for impedance optimization of complex single-ended silicon vias, characterized in that, Includes the following steps: Quasi-static three-dimensional electromagnetic simulation of the target TSV circuit was performed to obtain the total loop inductance and total capacitance of the TSV structure. Construct a cross-sectional model of the transmission line connecting the two ends of the TSV to obtain the capacitance and inductance per unit length of the transmission line at both ends of the TSV. Based on the total loop inductance and total capacitance of the TSV structure, and the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV, the loop inductance and capacitance of the middle TSV section are obtained, and the characteristic impedance of the target TSV loop is calculated based on the loop inductance and capacitance of the middle TSV section. The characteristic impedance of the target TSV circuit is compared with the target characteristic impedance, and the impedance matching of the existing structure is optimized to obtain the optimized new structure. The total loop inductance and total capacitance based on the TSV structure, and the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV, are used to obtain the loop inductance and capacitance of the middle TSV section, including: （1） （2） in, L tsv The loop inductance for the intermediate TSV section. C tsv This refers to the loop capacitor of the intermediate TSV section. L X The total loop inductance of the TSV structure, C X The total loop capacitance of the TSV structure; C 1pul and L 1pul Transmission lines for TSV top-end connections C pul and L pul ; C 2pul and L 2pul Transmission lines connected to the lower part of TSV C pul and L pul ; The characteristic impedance of the target TSV loop is calculated based on the loop inductance and capacitance of the intermediate TSV section. The characteristic impedance is: (3) in, L tsv The loop inductance for the intermediate TSV section. C tsv This refers to the loop capacitor of the intermediate TSV section. Z O This is the characteristic impedance.

2. The method for impedance optimization of complex single-ended silicon vias according to claim 1, characterized in that, The quasi-static three-dimensional electromagnetic simulation of the target TSV circuit yields the total loop inductance and total capacitance of the TSV structure, including: The simulation equipment identifies the signal net and gndnet of the TSV structure based on the target TSV loop; Select the current inflow and outflow planes of the signal net and gndnet, and set the current inflow plane as source and the current outflow plane as sink; The simulation device outputs simulation results based on the pre-set simulation frequency band, the saved field distribution results, the solution frequency, and the simulation convergence conditions. The unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV are obtained from the simulation results.

3. The method for impedance optimization of complex single-ended silicon vias according to claim 1, characterized in that, The construction of the transmission line cross-sectional model connecting the two ends of the TSV yields the capacitance and inductance per unit length of the transmission line at both ends of the TSV, including: In AnsysQ2D software, construct a transmission line profile model connecting the two ends of the TSV. The transmission line structure at both ends is designed by default to the target characteristic impedance. The cross-section of the signal line is selected as the signal conductor, and the cross-section of the gnd plane is selected as the reference ground. The simulation bandwidth, solution frequency and simulation convergence conditions are set to obtain the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV.

4. The method for impedance optimization of complex single-ended silicon vias according to claim 1, characterized in that, The process of comparing the characteristic impedance of the target TSV circuit with the target characteristic impedance and performing impedance matching optimization on the existing structure to obtain an optimized new structure includes: If the characteristic impedance of the target TSV loop is less than the target characteristic impedance, then the loop capacitance of the intermediate TSV section is reduced, and the loop inductance of the intermediate TSV section is increased. If the characteristic impedance of the target TSV circuit is greater than the target characteristic impedance, then the circuit capacitance of the intermediate TSV section is increased, and the circuit inductance of the intermediate TSV section is reduced.

5. The method for impedance optimization of complex single-ended silicon vias according to claim 1, characterized in that, The process also includes running the optimized new structure in AnsysHFSS and observing whether the return loss in the simulation results is lower than a preset threshold across the entire frequency domain. If it is lower than the preset threshold, the optimization of the structure is successful; otherwise, the optimization is repeated.

6. A system for impedance optimization of complex single-ended through-silicon vias, characterized in that, A method for impedance optimization of complex single-ended silicon vias according to any one of claims 1-5 includes: The simulation unit is configured as follows: Used for quasi-static three-dimensional electromagnetic simulation of the target TSV circuit to obtain the total loop inductance and total capacitance of the TSV structure; The model unit is constructed and configured as follows: This is used to construct a cross-sectional model of the transmission line connecting the two ends of the TSV, and to obtain the capacitance and inductance per unit length of the transmission line at both ends of the TSV. The computing unit is configured as follows: The total loop inductance and total capacitance based on the TSV structure, as well as the unit length capacitance and unit length inductance of the transmission lines at both ends of the TSV, are used to obtain the loop inductance and capacitance of the middle TSV section, and the characteristic impedance of the target TSV loop is calculated based on the loop inductance and capacitance of the middle TSV section. The optimization unit is configured as follows: This is used to compare the characteristic impedance of the target TSV circuit with the target characteristic impedance, and to optimize the impedance matching of the existing structure to obtain an optimized new structure.

7. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method for impedance optimization of complex single-ended through-silicon vias as described in any one of claims 1-5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for impedance optimization of complex single-ended through-silicon vias as described in any one of claims 1-5.

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