Display panel and display device

Abstract

The application provides a display panel and a display device. A voltage division control module is arranged, so that the voltage division control module transmits a received pixel voltage signal to a main pixel electrode and an auxiliary pixel electrode of a corresponding sub-pixel according to a voltage division control signal, so that the pixel voltage corresponding to the auxiliary pixel electrode is different from the pixel voltage corresponding to the main pixel electrode. Thus, while improving the viewing angle, the pixel voltage corresponding to the main pixel electrode and the auxiliary pixel electrode of at least one sub-pixel can be provided by one pixel voltage signal, and the pixel voltage signal needs to be formed for the main pixel electrode and the auxiliary pixel electrode of the corresponding sub-pixel respectively, so that the number of driving chips required for matching the supply pixel voltage signal of the display panel is reduced, and the cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] The use of 8-domain technology in a display panel can improve the display color cast problem. Common 8-domain technology implementation methods include capacitive coupling (CC) technology, 1G2D (1 Gate 2 Data) technology, 2G1D (2 Gate 1 Data) technology, capacitive share (CS) technology, common voltage modulation technology, etc. Among them, compared with the design of setting one data line for one sub-pixel, the 1G2D technology needs to set two data lines for one sub-pixel, so the number of data lines is doubled, and double chip-on-film needs to be set to transmit data signals to multiple data lines, and a timing controller is also needed to process the data signals corresponding to the main domain area and the sub-domain area, which is not conducive to cost reduction. SUMMARY

[0003] The embodiments of the present application provide a display panel and a display device, which can improve the color cast problem and reduce the cost.

[0004] The embodiments of the present application provide a display panel, which includes a plurality of sub-pixels and a plurality of voltage division control modules. Each of the sub-pixels includes a main pixel electrode and an auxiliary pixel electrode, and each of the voltage division control modules is electrically connected to the main pixel electrode and the auxiliary pixel electrode of at least one of the sub-pixels. Each of the voltage division control modules is configured to transmit a received pixel voltage signal to the main pixel electrode and the auxiliary pixel electrode of the corresponding sub-pixel according to a voltage division control signal, so that the pixel voltage corresponding to the auxiliary pixel electrode is different from the pixel voltage corresponding to the main pixel electrode.

[0005] The present application also provides a display device, which includes any of the above display panels.

[0006] The application provides a display panel and a display device, by arranging a voltage division control module, the voltage division control module transmits a received pixel voltage signal to a main pixel electrode and an auxiliary pixel electrode of a corresponding sub-pixel according to a voltage division control signal, so that the pixel voltage corresponding to the auxiliary pixel electrode is different from the pixel voltage corresponding to the main pixel electrode, thereby improving the viewing angle, and the pixel voltage corresponding to the main pixel electrode and the auxiliary pixel electrode of at least one sub-pixel can be provided by a pixel voltage signal, without forming a pixel voltage signal for the main pixel electrode and the auxiliary pixel electrode of the corresponding sub-pixel respectively, so that the number of driving chips required for matching the supply pixel voltage signal of the display panel is reduced, and the cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0008] Figures 1A-1B is a structural schematic diagram of a display panel provided by the embodiment of the application;

[0009] Figure 2 is a structural schematic diagram of a voltage division control module provided by the embodiment of the application;

[0010] Figure 3 is a timing diagram of a voltage division control signal provided by the embodiment of the application;

[0011] Figure 4 is another timing diagram of a voltage division control signal provided by the embodiment of the application;

[0012] Figure 5 is another structural schematic diagram of a voltage division control module provided by the embodiment of the application;

[0013] Figure 6 is a structural schematic diagram of a sub-pixel provided by the embodiment of the application;

[0014] Figures 7A-7B is a pixel voltage polarity schematic diagram provided by the embodiment of the application;

[0015] Figure 8 is a structural schematic diagram of a display device provided by the embodiment of the application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application. In addition, it should be understood that the specific implementation described herein is only used to illustrate and explain the present application, and is not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the contour of the device.

[0017] Specifically, Figures 1A-1B FIG. 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application. The present embodiment provides a display panel DP, which includes a plurality of sub-pixels Spi and a plurality of voltage division control modules DVU.

[0018] Optionally, the display panel DP includes a liquid crystal display panel.

[0019] Each of the sub-pixels Spi includes a main pixel electrode Sm and a sub-pixel electrode Ss.

[0020] Each of the voltage division control modules DVU is electrically connected with the main pixel electrode Sm and the sub-pixel electrode Ss of at least one of the sub-pixels Spi. Each of the voltage division control modules DVU is configured to transmit a received pixel voltage signal Dat to the main pixel electrode Sm and the sub-pixel electrode Ss of the corresponding sub-pixel Spi according to a voltage division control signal Dvc, so that the pixel voltage corresponding to the sub-pixel electrode Ss is different from the pixel voltage corresponding to the main pixel electrode Sm. Wherein, a voltage division control line DVL transmits the voltage division control signal Dvc, and a pixel voltage line PVL transmits the pixel voltage signal Dat.

[0021] It can be understood that the pixel voltage corresponding to the sub-pixel electrode Ss is different from the pixel voltage corresponding to the main pixel electrode Sm, that is, the pixel voltage corresponding to the sub-pixel electrode Ss is greater than or less than the pixel voltage corresponding to the main pixel electrode Sm.

[0022] The voltage dividing control module DVU is arranged in the display panel DP, and the voltage dividing control module DVU transmits the received pixel voltage signal Dat to the main pixel electrode Sm and the auxiliary pixel electrode Ss of the corresponding sub-pixel Spi according to the voltage dividing control signal Dvc, so that the pixel voltage corresponding to the auxiliary pixel electrode Ss is different from the pixel voltage corresponding to the main pixel electrode Sm, thereby improving the viewing angle, and the pixel voltage corresponding to the main pixel electrode Sm and the auxiliary pixel electrode Ss of at least one sub-pixel Spi can be provided by one pixel voltage signal Dat without forming a pixel voltage signal Dat for the main pixel electrode Sm and the auxiliary pixel electrode Ss of the corresponding sub-pixel Spi respectively, so that the number of driving chips required to match the supply pixel voltage signal Dat of the display panel DP is reduced, and the cost is reduced.

[0023] Please continue to refer to Figures 1A-1B The display panel DP includes a plurality of data lines DL, and the plurality of data lines DL are electrically connected between the plurality of sub-pixels Spi and the plurality of voltage dividing control modules DVU. Each data line DL is configured to electrically connect the voltage dividing control module DVU and the corresponding sub-pixel Spi.

[0024] Optionally, each sub-pixel Spi is electrically connected to two data lines DL, so that the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi receive different pixel voltages.

[0025] Optionally, the plurality of data lines DL includes a plurality of first data lines DL1 and a plurality of second data lines DL2. In the same sub-pixel Spi, the main pixel electrode Sm is electrically connected to a first data line DL1, and the auxiliary pixel electrode Ss is electrically connected to a second data line DL2, so that the first data line DL1 and the second data line DL2 are used to transmit the required pixel voltage to the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi.

[0026] Optionally, in order to reduce the number of data lines DL and control complexity and improve the aperture ratio, each first data line DL1 is electrically connected to the main pixel electrode Sm of a plurality of sub-pixels Spi located in the same column, and each second data line DL2 is electrically connected to the auxiliary pixel electrode Ss of a plurality of sub-pixels Spi located in the same column.

[0027] Optionally, to reduce the coupling effect caused by the fluctuation of the pixel voltage signal Dat transmitted by the data line DL and to reduce the impact on the display panel DP, the first data line DL1 and the second data line DL2 electrically connected to the same sub-pixel Spi are located on opposite sides of the sub-pixel Spi; or the first data line DL1 and the second data line DL2 electrically connected to the plurality of sub-pixels Spi in the same column are located on opposite sides of the plurality of sub-pixels Spi in the same column, so that each sub-pixel Spi is only affected by the fluctuation of the pixel voltage signal Dat transmitted by the first data line DL1 and the second data line DL2 electrically connected thereto, and the impact of the remaining data lines DL is reduced.

[0028] Optionally, one voltage division control module DVU can be provided for each sub-pixel Spi, or one voltage division control module DVU can be provided for a plurality of sub-pixels Spi.

[0029] Optionally, one voltage division control module DVU can be provided for a plurality of sub-pixels Spi, so as to reduce the number of voltage division control modules DVU included in the display panel DP and facilitate the realization of high-resolution design of the display panel DP.

[0030] Optionally, the display panel DP includes a plurality of groups of data lines DL, and each voltage division control module DVU is connected to each group of data lines DL. Each group of data lines DL includes the first data line DL1 and the second data line DL2. The first data line DL1 is electrically connected to the main pixel electrode Sm of the plurality of sub-pixels Spi in the same column, and the second data line DL2 is electrically connected to the auxiliary pixel electrode Ss of the plurality of sub-pixels Spi in the same column. By electrically connecting each voltage division control module DVU to the first data line DL1 and the second data line DL2 corresponding to the plurality of sub-pixels Spi in the same column, the plurality of sub-pixels Spi in the same column share the same voltage division control module DVU, thereby reducing the number of voltage division control modules DVU included in the display panel DP and facilitating the realization of high-resolution design of the display panel DP.

[0031] Optionally, to reduce the impact of the voltage division control module DVU on the resolution of the display panel DP, the voltage division control module DVU can be arranged in the frame area of the display panel DP.

[0032] It can be understood that one of the voltage division control modules DVU is arranged for each of the sub-pixels Spi, and the voltage division control modules DVU are arranged in the frame area of the display panel DP, so that the number of the voltage division control modules DVU included in the display panel DP is reduced, and the display panel DP is facilitated to realize the narrow frame design.

[0033] Figure 2 is a structural schematic diagram of a voltage division control module provided by an embodiment of the present application, Figure 3 is a timing diagram of a voltage division control signal provided by an embodiment of the present application, Figure 4 is another timing diagram of a voltage division control signal provided by an embodiment of the present application.

[0034] Each of the voltage division control modules DVU includes a first transistor T1 and a second transistor T2.

[0035] The input end of the first transistor T1 is configured to receive the pixel voltage signal Dat, and the output end of the first transistor T1 is electrically connected with the main pixel electrode Sm of the corresponding sub-pixel Spi.

[0036] The input end of the second transistor T2 is electrically connected with the input end of the first transistor T1, and the output end of the second transistor T2 is electrically connected with the auxiliary pixel electrode Ss of the corresponding sub-pixel Spi.

[0037] Optionally, the input end of the first transistor T1 is electrically connected with a pixel voltage line PVL, the output end of the first transistor T1 is electrically connected with a first data line DL1, and the output end of the second transistor T2 is electrically connected with a second data line DL2.

[0038] Since the main pixel electrode Sm and the auxiliary pixel electrode Ss of the same sub-pixel Spi correspond to the pixel voltage provided by the pixel voltage signal Dat, in order to enable the main pixel electrode Sm and the auxiliary pixel electrode Ss of the same sub-pixel Spi to have the corresponding pixel voltage based on the same pixel voltage signal Dat, the conduction period of the first transistor T1 and the conduction period of the second transistor T2 can at least partially coincide.

[0039] Optionally, at least one of the conduction time length and the conduction degree of the first transistor T1 and the second transistor T2 can be controlled to make the pixel voltage corresponding to the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi different.

[0040] When the pixel voltage corresponding to the auxiliary pixel electrode Ss is less than the pixel voltage corresponding to the main pixel electrode Sm, the first transistor T1 can have a longer on duration than the second transistor T2, and / or the first transistor T1 can have a higher on degree than the second transistor T2. Similarly, when the pixel voltage corresponding to the auxiliary pixel electrode Ss is greater than the pixel voltage corresponding to the main pixel electrode Sm, the first transistor T1 can have a shorter on duration than the second transistor T2, and / or the first transistor T1 can have a lower on degree than the second transistor T2.

[0041] Optionally, the first transistor T1 and the second transistor T2 can be controlled by different voltage division control signals Dvc, so that the first transistor T1 and the second transistor T2 can be independently controlled, thereby making the on duration and / or on degree of the first transistor T1 and the second transistor T2 different.

[0042] As shown in Figures 2-4 The voltage division control signal Dvc includes a first voltage division control signal Dvc1 and a second voltage division control signal Dvc2, and the voltage division control line DVL includes a first voltage division control line DVL1 for transmitting the first voltage division control signal Dvc1 and a second voltage division control line DVL2 for transmitting the second voltage division control signal Dvc2. The control end of the first transistor T1 is electrically connected to the first voltage division control line DVL1, and the control end of the first transistor T1 is configured to receive the first voltage division control signal Dvc1. The control end of the second transistor T2 is electrically connected to the second voltage division control line DVL2, and the control end of the second transistor T2 is configured to receive the second voltage division control signal Dvc2, so that the first transistor T1 is controlled by the first voltage division control signal Dvc1, and the second transistor T2 is controlled by the second voltage division control signal Dvc2.

[0043] The effective pulse of the first voltage division control signal Dvc1 at least partially overlaps with the effective pulse of the second voltage division control signal Dvc2, as shown in Figures 3-4 so that the on duration of the first transistor T1 at least partially overlaps with the on duration of the second transistor T2.

[0044] Optionally, the pulse width of the effective pulse of the first voltage division control signal Dvc1 is greater than the pulse width of the effective pulse of the second voltage division control signal Dvc2, as shown in Figure 3The first transistor T1 is turned on for a longer time than the second transistor T2 is turned on, so that the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi correspondingly receive the pixel voltage signal Dat for different lengths of time, and then the pixel voltage corresponding to the main pixel electrode Sm is greater than the pixel voltage corresponding to the auxiliary pixel electrode Ss in the same sub-pixel Spi. Similarly, the pulse width of the effective pulse of the first voltage division control signal Dvc1 is smaller than the pulse width of the effective pulse of the second voltage division control signal Dvc2, so that the pixel voltage corresponding to the main pixel electrode Sm is smaller than the pixel voltage corresponding to the auxiliary pixel electrode Ss in the same sub-pixel Spi.

[0045] Alternatively, the pulse width of the effective pulse of the first voltage division control signal Dvc1 corresponding to the same voltage division control module DVU can be equal to the pulse width of the effective level of the pixel voltage signal Dat corresponding to the same voltage division control module DVU, as shown in Figures 3-4 The pulse width of the effective pulse of the first voltage division control signal Dvc1 corresponding to the same voltage division control module DVU can also be smaller than the pulse width of the effective level of the pixel voltage signal Dat corresponding to the same voltage division control module DVU.

[0046] Alternatively, when the difference in the degree of conduction of the first transistor T1 and the second transistor T2 is used to achieve different pixel voltages corresponding to the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi, the difference in the degree of conduction of the first transistor T1 and the second transistor T2 can be achieved by controlling the channel resistance of the first transistor T1 and the second transistor T2 when they are turned on.

[0047] Specifically, the channel resistance corresponding to the first transistor T1 when it is turned on is smaller than the channel resistance corresponding to the second transistor T2 when it is turned on, so that the degree of conduction of the first transistor T1 is greater than the degree of conduction of the second transistor T2, thereby making the degree of charging corresponding to the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi according to the pixel voltage signal Dat different, and then making the pixel voltage corresponding to the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi different.

[0048] Correspondingly, please continue to refer to Figures 2-4, when the first transistor T1 is controlled by the first voltage division control signal Dvc1 and the second transistor T2 is controlled by the second voltage division control signal Dvc2, the channel resistance corresponding to the on state of the first transistor T1 is less than the channel resistance corresponding to the on state of the second transistor T2.

[0049] Similarly, the channel resistance corresponding to the on state of the first transistor T1 can be made greater than the channel resistance corresponding to the on state of the second transistor T2, so that the on state of the first transistor T1 is less than the on state of the second transistor T2.

[0050] Alternatively, the channel resistance corresponding to the on state of the first transistor T1 and the second transistor T2 can be made different by controlling the voltage difference of the voltage division control signal Dvc corresponding to the first transistor T1 and the second transistor T2, and / or controlling the threshold voltage difference of the first transistor T1 and the second transistor T2.

[0051] As a specific example, referring to Figure 2 and Figure 4 , when the first transistor T1 is controlled by the first voltage division control signal Dvc1 and the second transistor T2 is controlled by the second voltage division control signal Dvc2, the first voltage division control signal Dvc1 has a first voltage corresponding to the effective level, and the second voltage division control signal Dvc2 has a second voltage corresponding to the effective level. The absolute value of the first voltage can be made different from the absolute value of the second voltage, so that the on state of the first transistor T1 and the second transistor T2 is different.

[0052] Alternatively, the threshold voltage of the first transistor T1 and the second transistor T2 is equal. The first transistor T1 and the second transistor T2 are both N-type transistors, and the first voltage is greater than the second voltage; or, the first transistor T1 and the second transistor T2 are both P-type transistors, and the absolute value of the first voltage is greater than the absolute value of the second voltage, so that the on state of the first transistor T1 is greater than the on state of the second transistor T2, so that the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi correspond to different degrees of charging according to the pixel voltage signal Dat.

[0053] Similarly, the threshold voltages of the first transistor T1 and the second transistor T2 are equal. The first transistor T1 and the second transistor T2 are both N-type transistors, and the first voltage is less than the second voltage; or, the first transistor T1 and the second transistor T2 are both P-type transistors, and the absolute value of the first voltage is less than the absolute value of the second voltage, so that the on degree of the first transistor T1 is less than the on degree of the second transistor T2, thereby making the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi correspond to different degrees of charging according to the pixel voltage signal Dat.

[0054] For example, as shown in FIG. 1, the threshold voltages of the first transistor T1 and the second transistor T2 are equal, and the first transistor T1 and the second transistor T2 are both N-type transistors, and the first voltage is less than the second voltage. Figures 2-3 For example, as shown in FIG. 1, the threshold voltages of the first transistor T1 and the second transistor T2 are equal, and the first transistor T1 and the second transistor T2 are both N-type transistors, and the first voltage is less than the second voltage.

[0055] Alternatively, the first transistor T1 and the second transistor T2 have the same voltage when the voltage of the voltage division control signal Dvc is at an effective level, the first transistor T1 and the second transistor T2 are N-type transistors, and the threshold voltage of the first transistor T1 is less than the threshold voltage of the second transistor T2; or, the first transistor T1 and the second transistor T2 are P-type transistors, and the threshold voltage of the first transistor T1 is greater than the threshold voltage of the second transistor T2, so that the on degree of the first transistor T1 is greater than the on degree of the second transistor T2, thereby making the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi correspond to different degrees of charging according to the pixel voltage signal Dat.

[0056] Similarly, the first transistor T1 and the second transistor T2 have the same voltage when the voltage of the voltage division control signal Dvc is at an effective level, the first transistor T1 and the second transistor T2 are N-type transistors, and the threshold voltage of the first transistor T1 is greater than the threshold voltage of the second transistor T2; or, the first transistor T1 and the second transistor T2 are P-type transistors, and the threshold voltage of the first transistor T1 is less than the threshold voltage of the second transistor T2, so that the on degree of the first transistor T1 is less than the on degree of the second transistor T2, thereby making the main pixel electrode Sm and the auxiliary pixel electrode Ss in the same sub-pixel Spi correspond to different degrees of charging according to the pixel voltage signal Dat.

[0057] It should be noted that when the threshold voltages of the first transistor T1 and the second transistor T2 are controlled to be different, the first transistor T1 can still be controlled by the first voltage division control signal Dvc1, and the second transistor T2 can still be controlled by the second voltage division control signal Dvc2. The first voltage and the second voltage can be the same.

[0058] Alternatively, when the threshold voltages of the first transistor T1 and the second transistor T2 are controlled to be different, the first transistor T1 and the second transistor T2 can be controlled by the same voltage division control signal Dvc (that is, the control end of the first transistor T1 and the control end of the second transistor T2 are configured to receive the voltage division control signal Dvc), so as to reduce the number of control signals required by the display panel DP.

[0059] It should be noted that when the conduction degrees of the first transistor T1 and the second transistor T2 are different, the conduction time of the first transistor T1 can also be different from the conduction time of the second transistor T2. When the conduction degrees of the first transistor T1 and the second transistor T2 are different, the conduction time of the first transistor T1 can also be equal to the conduction time of the second transistor T2.

[0060] It can be understood that when the conduction time and the conduction degree of the first transistor T1 and the second transistor T2 are adjusted at the same time, the difference between the main pixel electrode Sm and the auxiliary pixel electrode Ss corresponding to the pixel in the same sub-pixel Spi will be greater, and the adjustable viewing angle range will be wider.

[0061] Please continue to refer to Figures 1A-1B When the plurality of sub-pixels Spi in the same column share one voltage division control module DVU, the plurality of first transistors T1 can share the first voltage division control signal Dvc1, and the plurality of second transistors T2 can share the second voltage division control signal Dvc2, so as to reduce the number of voltage division control signals Dvc required by the display panel DP.

[0062] When the plurality of sub-pixels Spi in the same column share one voltage division control module DVU, and the first transistor T1 and the second transistor T2 share one voltage division control signal Dvc, the plurality of first transistors T1 and the plurality of second transistors T2 can share one voltage division control signal Dvc, so as to reduce the number of voltage division control signals Dvc required by the display panel DP.

[0063] Figure 5is another structural schematic view of the voltage division control module provided by the embodiment of the present application. In order to reduce the time delay of the voltage division control signal Dvc and reduce the loss of the pixel voltage signal Dat, at least one voltage division control module DVU further comprises a third transistor T3 and a fourth transistor T4. The input end of the third transistor T3 is electrically connected with the input end of the first transistor T1, and the output end of the third transistor T3 is electrically connected with the output end of the first transistor T1. The input end of the fourth transistor T4 is electrically connected with the input end of the second transistor T2, and the output end of the fourth transistor T4 is electrically connected with the output end of the second transistor T2. The voltage division control signal Dvc comprises a third voltage division control signal and a fourth voltage division control signal. The voltage division control line DVL comprises a third voltage division control line DVL3 for transmitting the third voltage division control signal and a fourth voltage division control line DVL4 for transmitting the fourth voltage division control signal. The control end of the third transistor T3 is electrically connected with the third voltage division control line DVL3, and the control end of the third transistor T3 is configured to receive the third voltage division control signal. The control end of the fourth transistor T4 is electrically connected with the third voltage division control line DVL3, and the control end of the fourth transistor T4 is configured to receive the fourth voltage division control signal. In this way, the path for the main pixel electrode Sm and the auxiliary pixel electrode Ss to receive the corresponding pixel voltage can be increased, so that the pixel voltage received by the main pixel electrode Sm and the auxiliary pixel electrode Ss is more consistent with the expectation.

[0064] Optionally, the first voltage division control signal Dvc1 and the third voltage division control signal are the same, and the second voltage division control signal Dvc2 and the fourth voltage division control signal are the same, so that the conduction and cutoff of the first transistor T1 and the third transistor T3 tend to be consistent, and the conduction and cutoff of the second transistor T2 and the fourth transistor T4 tend to be consistent, so as to make the main pixel electrode Sm and the auxiliary pixel electrode Ss receive the corresponding pixel voltage in a shorter time when they need to receive the pixel voltage.

[0065] Due to the loss in the signal transmission process, the first voltage division control signal Dvc1 and the third voltage division control signal can have certain differences due to signal loss, and the second voltage division control signal Dvc2 and the fourth voltage division control signal can have certain differences due to signal loss, so that the conduction and cutoff of the first transistor T1 and the third transistor T3 can not be completely synchronized; the conduction and cutoff of the second transistor T2 and the fourth transistor T4 can not be completely synchronized. That is, one of the first transistor T1 and the third transistor T3 can be turned on or off first, and the other can be turned on or off later. One of the second transistor T2 and the fourth transistor T4 can be turned on or off first, and the other can be turned on or off later.

[0066] Optionally, when multiple sub-pixels Spi in the same column share one voltage division control module DVU, multiple third transistors T3 can share the third voltage division control signal, and multiple fourth transistors T4 can share the fourth voltage division control signal, so as to reduce the number of voltage division control signals Dvc required by the display panel DP.

[0067] Optionally, the first transistor T1 has the same parameters (such as channel length, channel width, threshold voltage, etc.) as the third transistor T3, and the second transistor T2 has the same parameters as the fourth transistor T4.

[0068] Optionally, the first voltage division control signal Dvc1 to the fourth voltage division control signal can be generated by a timing controller or the like.

[0069] Optionally, the on duration and threshold voltage of the first transistor T1 to the fourth transistor T4, and the first voltage and the second voltage can be determined according to actual requirements, so that the ratio of the pixel voltage corresponding to the auxiliary pixel electrode Ss to the pixel voltage corresponding to the main pixel electrode Sm in the same sub-pixel Spi meets the design, so as to achieve better transmittance and viewing angle. Optionally, according to the required viewing angle range of the display panel DP, the ratio of the pixel voltage corresponding to the auxiliary pixel electrode Ss to the pixel voltage corresponding to the main pixel electrode Sm changes in the range of 0-1.

[0070] It can be understood that the third transistor T3 and the fourth transistor T4 can be arranged in the same way as the first transistor T1 and the second transistor T2. For example, the third transistor T3 and the fourth transistor T4 can also share one voltage division control signal Dvc, and the pixel voltage corresponding to the auxiliary pixel electrode Ss is different from the pixel voltage corresponding to the main pixel electrode Sm by controlling the different conduction degrees of the third transistor T3 and the fourth transistor T4. In this case, the third transistor T3 and the fourth transistor T4 share one voltage division control signal, the first transistor T1 and the second transistor T2 can share another voltage division control signal, and the voltage division control signal corresponding to the third transistor T3 and the fourth transistor T4 can be the same as the voltage division control signal corresponding to the first transistor T1 and the second transistor T2. In another example, the third transistor T3 and the fourth transistor T4 are controlled by different voltage division control signals Dvc, and the pixel voltage corresponding to the auxiliary pixel electrode Ss is different from the pixel voltage corresponding to the main pixel electrode Sm by controlling the different conduction degrees and / or on durations of the third transistor T3 and the fourth transistor T4.

[0071] Please continue to refer to Figures 1A-1BThe display panel DP can further include a plurality of scan lines SL configured to transmit a plurality of gate control signals Scan. Each of the sub-pixels Spi receives a corresponding pixel voltage signal Dat according to the gate control signal Scan transmitted by the corresponding electrically connected scan line SL.

[0072] Optionally, each of the sub-pixels Spi is electrically connected with a scan line SL. Accordingly, the main pixel electrode Sm and the auxiliary pixel electrode Ss of the same sub-pixel Spi are configured to achieve electrical connection with the corresponding data line DL according to the gate control signal Scan transmitted by the same scan line SL.

[0073] Optionally, each scan line SL is electrically connected with the main pixel electrode Sm and the auxiliary pixel electrode Ss of a plurality of sub-pixels Spi located in the same row. The main pixel electrode Sm and the auxiliary pixel electrode Ss of each sub-pixel Spi are located on opposite sides of the scan line SL to which it is electrically connected, so as to reduce the winding distance of the scan line SL and the occupied layout space.

[0074] Figure 6 is a structural schematic diagram of a sub-pixel provided by an embodiment of the present application. Optionally, each of the sub-pixels Spi includes a first switch transistor Ts1, a second switch transistor Ts2, a first storage capacitor Cst1, a second storage capacitor Cst2, a first liquid crystal capacitor Clc1, a second liquid crystal capacitor Clc2, a common electrode Com, and liquid crystal molecules.

[0075] The control end of the first switch transistor Ts1 and the control end of the second switch transistor Ts2 are electrically connected with a corresponding scan line SL. The input end of the first switch transistor Ts1 is electrically connected with a corresponding first data line DL1. The output end of the first switch transistor Ts1 is electrically connected with a corresponding main pixel electrode Sm. The input end of the second switch transistor Ts2 is electrically connected with a corresponding second data line DL2. The output end of the second switch transistor Ts2 is electrically connected with a corresponding auxiliary pixel electrode Ss.

[0076] The first liquid crystal capacitor Clc1 and the first storage capacitor Cst1 are electrically connected with the main pixel electrode Sm. The second liquid crystal capacitor Clc2 and the second storage capacitor Cst2 are electrically connected with the auxiliary pixel electrode Ss.

[0077] Optionally, the first storage capacitor Cst1, the second storage capacitor Cst2, the first liquid crystal capacitor Clc1, and the second liquid crystal capacitor Clc2 can be electrically connected with the common electrode Com.

[0078] The liquid crystal molecules are arranged between the main pixel electrode Sm and the common electrode Com, and the liquid crystal molecules are arranged between the auxiliary pixel electrode Ss and the common electrode Com.

[0079] The display panel DP is provided with the voltage division control module DVU, so that the pixel voltage corresponding to the auxiliary pixel electrode Ss is different from the pixel voltage corresponding to the main pixel electrode Sm, the deflection angles of the liquid crystal molecules corresponding to the auxiliary pixel electrode Ss and the main pixel electrode Sm are different, and then the viewing angle ranges corresponding to the main domain region including the main pixel electrode Sm and the sub-domain region including the auxiliary pixel electrode Ss in the same sub-pixel Spi are different, thereby improving the viewing angle adjustment. Thus, the display panel DP provided by the application can realize the effect of improving the viewing angle in the 8-domain design, and is also conducive to reducing the cost.

[0080] Please continue to refer to Figures 1A-1B Since the pixel voltages corresponding to the main pixel electrode Sm and the auxiliary pixel electrode Ss of the same sub-pixel Spi are generated based on the same pixel voltage signal Dat, the polarities of the pixel voltages corresponding to the main pixel electrode Sm and the auxiliary pixel electrode Ss of the same sub-pixel Spi are the same. The polarities of the pixel voltages corresponding to two adjacent sub-pixels Spi in the row direction can be the same or different, and the polarities of the pixel voltages corresponding to two adjacent sub-pixels Spi in the column direction can be the same or different.

[0081] Figures 7A-7B It is a pixel voltage polarity diagram provided by the embodiment of the application. Wherein, + represents positive polarity, and - represents negative polarity.

[0082] Alternatively, the polarities of the pixel voltages corresponding to the main pixel electrode Sm and the auxiliary pixel electrode Ss of the same sub-pixel Spi are the same, the polarities of the pixel voltages corresponding to the main pixel electrodes Sm of two adjacent sub-pixels Spi in the row direction are different, and the polarities of the pixel voltages corresponding to the auxiliary pixel electrodes Ss of two adjacent sub-pixels Spi in the row direction are different.

[0083] Please continue to refer to Figure 7A The polarities of the pixel voltages corresponding to the main pixel electrodes Sm of two adjacent sub-pixels Spi in the column direction are the same, and the polarities of the pixel voltages corresponding to the auxiliary pixel electrodes Ss of two adjacent sub-pixels Spi in the row direction are the same, so that the display panel DP realizes column inversion design.

[0084] Please continue to refer to Figure 7BThe polarities of the pixel voltages corresponding to the main pixel electrodes Sm of two adjacent sub-pixels Spi in the column direction are different, and the polarities of the pixel voltages corresponding to the auxiliary pixel electrodes Ss of two adjacent sub-pixels Spi in the column direction are different, so that the display panel DP implements a dot inversion design.

[0085] Taking the first transistor T1 to the fourth transistor T4, the first switch transistor Ts1 and the second switch transistor Ts2 as N-type transistors as an example, the working principle of the voltage division control module DVU acting on a sub-pixel Spi to make the pixel voltage corresponding to the auxiliary pixel electrode smaller than the pixel voltage corresponding to the main pixel electrode is described in combination with Figures 1A-1B , Figures 2-6

[0086] In the first stage t1, the gate control signal Scan corresponding to the sub-pixel Spi has a high level, the pixel voltage signal Dat is low, and the first voltage division control signal Dvc1 and the second voltage division control signal Dvc2 are low. In the sub-pixel Spi, the first switch transistor Ts1 and the second switch transistor Ts2 are turned on, and the first transistor T1 and the second transistor T2 are turned off. In the voltage division control module DVU shown in Figure 5 , the third transistor T3 and the fourth transistor T4 are turned off.

[0087] Please continue to refer to Figures 2-3 and Figures 5-6 In the second stage t2, the gate control signal Scan corresponding to the sub-pixel Spi has a high level, the pixel voltage signal Dat is high, the first voltage division control signal Dvc1 is high, and the second voltage division control signal Dvc2 is low. In the sub-pixel Spi, the first switch transistor Ts1 and the second switch transistor Ts2 are turned on, the first transistor T1 is turned on, the pixel voltage signal Dat is transmitted to the main pixel electrode Sm, and the second transistor T2 is turned off. In the voltage division control module DVU shown in Figure 5 , the third transistor T3 is turned on, and the fourth transistor T4 is turned off.

[0088] Please continue to refer to Figure 2 , Figure 4 and Figures 5-6 ​In the second stage t2, the sub-pixel Spi corresponds to the gate control signal Scan with a high level, the pixel voltage signal Dat is high, the first voltage dividing control signal Dvc1 is high, the second voltage dividing control signal Dvc2 is high, and the first voltage corresponding to the high level of the first voltage dividing control signal Dvc1 is greater than the second voltage corresponding to the high level of the second voltage dividing control signal Dvc2. In the sub-pixel Spi, the first switch transistor Ts1 and the second switch transistor Ts2 are turned on, the first transistor T1 and the second transistor T2 are turned on, and the pixel voltage signal Dat is transmitted to the main pixel electrode Sm and the auxiliary pixel electrode Ss, but the on degree of the second transistor T2 is less than the on degree of the first transistor T1, so that the charging rates of the main pixel electrode Sm and the auxiliary pixel electrode Ss are different. Figure 5 In the voltage dividing control module DVU shown in the figure, the third transistor T3 and the fourth transistor T4 are turned on, and the on degree of the fourth transistor T4 is less than the on degree of the third transistor T3.

[0089] Please continue to refer to Figures 2-6 In the third stage t3, the sub-pixel Spi corresponds to the gate control signal Scan with a low level. In the sub-pixel Spi, the first switch transistor Ts1 and the second switch transistor Ts2 are turned off, and the pixel voltage signal Dat is not transmitted to the main pixel electrode Sm and the auxiliary pixel electrode Ss.

[0090] Figure 8 It is the structural schematic diagram of the display device provided by the embodiment of the application, and the application further provides a display device comprising any of the above display panels DP.

[0091] Optionally, the display device further comprises a source driving chip SIC. The source driving chip SIC is electrically connected with the plurality of voltage dividing control modules DVU, and the source driving chip SIC is configured to generate a plurality of pixel voltage signals Dat to output to the plurality of voltage dividing control modules DVU.

[0092] Optionally, the display device further comprises a gate driving chip GIC, and the gate driving chip GIC is electrically connected with the plurality of scan lines SL, and the gate driving chip GIC is configured to generate a plurality of gate control signals Scan to output to the plurality of scan lines SL.

[0093] Optionally, the display device further comprises a control module Ctr, and the control module Ctr is configured to provide the required voltage dividing control signals Dvc to the plurality of voltage dividing control modules DVU.

[0094] Optionally, the control module Ctr comprises at least one of a time controller, a central processor, etc.

[0095] The principles and implementation modes of the present application are described herein by using specific examples, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation modes and application ranges will have changes, and the above description should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a plurality of sub-pixels, each of the sub-pixels comprising a main pixel electrode and an auxiliary pixel electrode; a plurality of voltage division control modules, each of the voltage division control modules being electrically connected to the main pixel electrode and the auxiliary pixel electrode of at least one of the sub-pixels, and each of the voltage division control modules being configured to transmit a pixel voltage signal received to the main pixel electrode and the auxiliary pixel electrode of the corresponding sub-pixel according to a voltage division control signal, so that the pixel voltage corresponding to the auxiliary pixel electrode is different from the pixel voltage corresponding to the main pixel electrode; each of the voltage division control modules comprises: a first transistor, an input end of the first transistor being configured to receive the pixel voltage signal, and an output end of the first transistor being electrically connected to the main pixel electrode of the corresponding sub-pixel; and a second transistor, an input end of the second transistor being electrically connected to the input end of the first transistor, and an output end of the second transistor being electrically connected to the auxiliary pixel electrode of the corresponding sub-pixel; a conduction period of the first transistor at least partially overlaps with a conduction period of the second transistor. The voltage division control signal comprises a first voltage division control signal and a second voltage division control signal; 2. The display panel of claim 1, wherein, an control end of the first transistor is configured to receive the first voltage division control signal, and a control end of the second transistor is configured to receive the second voltage division control signal. An effective pulse of the first voltage division control signal at least partially overlaps with an effective pulse of the second voltage division control signal, and a pulse width of the effective pulse of the first voltage division control signal is greater than a pulse width of the effective pulse of the second voltage division control signal.

3. The display panel of claim 2, wherein, A channel resistance corresponding to a conduction period of the first transistor according to the effective pulse of the first voltage division control signal is less than a channel resistance corresponding to a conduction period of the second transistor according to the effective pulse of the second voltage division control signal.

4. The display panel of claim 2 or 3, wherein, The voltage division control signal comprises a third voltage division control signal and a fourth voltage division control signal; and at least one of the voltage division control modules further comprises:

5. The display panel of claim 2, wherein, a third transistor, a control end of the third transistor being configured to receive the third voltage division control signal, an input end of the third transistor being electrically connected to the input end of the first transistor, and an output end of the third transistor being electrically connected to the output end of the first transistor; and a fourth transistor, a control end of the fourth transistor being configured to receive the fourth voltage division control signal, an input end of the fourth transistor being electrically connected to the input end of the second transistor, and an output end of the fourth transistor being electrically connected to the output end of the second transistor.

6. The display panel according to claim 5, wherein: the first voltage division control signal and the third voltage division control signal are the same, and the second voltage division control signal and the fourth voltage division control signal are the same. the control end of the first transistor and the control end of the second transistor are configured to receive the voltage division control signal.

7. The display panel of claim 1, wherein, ​ The first transistor and the second transistor are N-type transistors, and a threshold voltage of the first transistor is less than a threshold voltage of the second transistor; or the first transistor and the second transistor are P-type transistors, and a threshold voltage of the first transistor is greater than a threshold voltage of the second transistor.

8. The display panel of claim 1, wherein, The display panel comprises: a plurality of groups of data lines, each of the voltage division control modules being connected to each group of the data lines, wherein each group of the data lines comprises a first data line and a second data line, the first data line being electrically connected to the main pixel electrodes of the plurality of sub-pixels in the same column, and the second data line being electrically connected to the auxiliary pixel electrodes of the plurality of sub-pixels in the same column.

9. A display device, characterized by comprising: The display panel comprises any one of claims 1-8.

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