A Pulse Width Modulation Circuit and an ANPC Three-Level Conversion System

Abstract

A pulse width modulation circuit and an ANPC three-level conversion system of the present application relate to the field of power electronics technology. Since the two first output terminals of the pulse width modulation module are respectively connected to the input terminals of the two turn-off delay modules, and the output terminals of the two turn-off delay modules are respectively used to output the control signals of the two switching tubes for the power frequency switching action in the ANPC three-level topology, the switching tubes for the power frequency switching action can be turned off with a delay. Therefore, when the on-off states of the two switching tubes for the power frequency switching action are switched, that is, when switching at the zero crossing point, one switching tube for the power frequency switching action may be turned off after the other switching tube for the power frequency switching action is turned on; and since the switching tubes for the power frequency switching action are the inner tubes in the ANPC three-level topology, it may cause a commutation path in the ANPC three-level topology to form an open circuit after another commutation path forms a closed circuit at this time, thereby reducing the possibility of non-zero level switching when switching at the zero crossing point.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and particularly to a pulse width modulation circuit and an ANPC three-level conversion system. Background Art

[0002] Compared with the neutral point clamped (NPC) three-level topology, the active neutral point clamped (ANPC) three-level topology has more switching states and current conduction paths. By selecting different current paths, the on-state loss and switching loss can be dispersed among different switching devices.

[0003] In practice, due to parameter differences among the switching devices in the ANPC three-level topology, the on-off coordination between the two switching devices for the power frequency switching action may not be very precise, which may lead to non-zero level switching during zero-crossing switching, and further may cause the corresponding switching device to be damaged due to excessive turn-off stress.

[0004] Therefore, how to reduce the possibility of non-zero level switching during zero-crossing switching is a technical problem to be solved urgently. Summary of the Invention

[0005] In view of this, the present invention provides a pulse width modulation circuit and an ANPC three-level conversion system to reduce the possibility of non-zero level switching during zero-crossing switching, which is a technical problem to be solved urgently.

[0006] To achieve the above object, the embodiments of the present invention provide the following technical solutions:

[0007] On the one hand, the present application provides a pulse width modulation circuit, including: a pulse width modulation module and two turn-off delay modules; wherein:

[0008] The input end of the pulse width modulation module is connected to the output end of the controller of the ANPC three-level topology;

[0009] The two first output ends of the pulse width modulation module are respectively connected to the input ends of the two turn-off delay modules, and the output ends of the two turn-off delay modules are respectively used to output the control signals of the two inner tubes for the power frequency switching action in the ANPC three-level topology.

[0010] Optionally, the two second output ends of the pulse width modulation module are respectively used to output the control signals of the two outer tubes for the half-wave switching frequency action in the ANPC three-level topology;

[0011] The two third output terminals of the pulse width modulation module are respectively used to output the control signals of the two clamping tubes that operate at the full-wave switching frequency in the ANPC three-level topology.

[0012] Optionally, it further includes: two first turn-on delay modules and two second turn-on delay modules; where:

[0013] The two second output terminals of the pulse width modulation module are respectively connected to the input terminals of the two first turn-on delay modules, and the output terminals of the two first turn-on delay modules are respectively used to output the control signals of the two outer tubes that operate at the half-wave switching frequency in the ANPC three-level topology;

[0014] The two third output terminals of the pulse width modulation module are respectively connected to the input terminals of the two second turn-on delay modules, and the output terminals of the two second turn-on delay modules are respectively used to output the control signals of the two inner tubes that operate at the full-wave switching frequency in the ANPC three-level topology;

[0015] The delay time of each first turn-on delay module is greater than the delay time of each second turn-on delay module.

[0016] Optionally, the first turn-on delay module includes: a first diode, a first capacitor, and two resistors; where:

[0017] The cathode of the first diode is connected to one end of the first resistor, and the connection point serves as the input terminal of the first turn-on delay module;

[0018] The other end of the first resistor is connected to one end of the second resistor;

[0019] The other end of the second resistor, the anode of the first diode, and one end of the first capacitor are all connected, and the connection point serves as the output terminal of the first turn-on delay module;

[0020] The other end of the first capacitor is grounded.

[0021] Optionally, the second turn-on delay module includes: a second diode, a second capacitor, and a third resistor; where:

[0022] The cathode of the second diode is connected to one end of the third resistor, and the connection point serves as the input terminal of the second turn-on delay module;

[0023] The other end of the third resistor, the anode of the second diode, and one end of the second capacitor are all connected, and the connection point serves as the input terminal of the second turn-on delay module;

[0024] The other end of the second capacitor is grounded.

[0025] Optionally, the pulse width modulation module includes: three comparators, three NOT gates, three selectors, and two AND gates; where:

[0026] The non-inverting input terminal of the first comparator is connected to the input terminal of the pulse width modulation module. The inverting input terminal of the first comparator is used to receive the carrier signal in the positive half cycle, and the output terminal of the first comparator is connected to the first input terminal of the first selector;

[0027] The non-inverting input terminal of the second comparator serves as the carrier signal receiving the negative half cycle. The inverting input terminal of the second comparator is connected to the input terminal of the pulse width modulation module, and the output terminal of the second comparator is connected to the second input terminal of the first selector;

[0028] The output terminal of the first selector is respectively connected to one input terminal of the first AND gate and one input terminal of the second AND gate;

[0029] The output terminal of the first AND gate is connected to the first input terminal of the second selector through the first NOT gate, and the output terminal of the second AND gate is connected to the first input terminal of the third selector through the second NOT gate;

[0030] The second input terminal of the second selector is connected to the output terminal of the second AND gate, and the second input terminal of the third selector is connected to the output terminal of the first AND gate;

[0031] The control terminal of the third selector is connected to the other input terminal of the second AND gate, and the connection point is connected to the output terminal of the third NOT gate. The input terminal of the third NOT gate is connected to the output terminal of the third comparator;

[0032] The non-inverting input terminal of the third comparator is connected to the input terminal of the pulse width modulation module, and the inverting input terminal of the third comparator is grounded;

[0033] The control terminal of the first selector, the control terminal of the second selector, and the other input terminal of the first AND gate are all connected to the output terminal of the third comparator;

[0034] The potential of the output terminal of each selector is equal to its first input terminal when its control terminal is at a high level, and the potential of the output terminal of each selector is equal to its second input terminal when its control terminal is at a low level;

[0035] The output terminal of the third comparator and the output terminal of the third NOT gate respectively serve as the two first output terminals of the pulse width modulation module;

[0036] The output terminal of the first AND gate and the output terminal of the second AND gate respectively serve as the two second output terminals of the pulse width modulation module;

[0037] The output terminals of the second selector and the third selector respectively serve as two third output terminals of the pulse width modulation module.

[0038] Optionally, the pulse width modulation module further includes: an adder; where:

[0039] The inverting input terminal of the first comparator is used to receive a triangular wave signal;

[0040] The non-inverting input terminal of the second comparator is connected to the output terminal of the adder. One input terminal of the adder receives the triangular wave signal, and the other input terminal of the adder receives a preset negative voltage; the absolute value of the preset negative voltage is equal to twice the amplitude of the triangular wave signal.

[0041] Optionally, the turn-off delay module includes: a third diode, a third capacitor, and a fourth resistor; where:

[0042] The anode of the third diode is connected to one end of the fourth resistor, and the connection point serves as the input terminal of the turn-off delay module;

[0043] The other end of the fourth resistor, the cathode of the third diode, and one end of the third capacitor are all connected, and the connection point serves as the output terminal of the turn-off delay module;

[0044] The other end of the third capacitor is grounded.

[0045] On the other hand, the present application provides an ANPC three-level conversion system, including: a controller, an inductor unit, a capacitor unit, a sampling unit, a grid-connected switch, a power unit, at least one driving circuit, and at least one pulse width modulation circuit as described in any one of the aspects of the present application;

[0046] The power unit includes at least one ANPC three-level topology, and the DC side of each ANPC three-level topology is connected to a DC source;

[0047] The AC sides of all the ANPC three-level topologies serve as the AC side of the power unit and are connected to one end of the inductor unit;

[0048] The other end of the inductor unit is connected to one end of the grid-connected switch, and the other end of the grid-connected switch is used to connect to the power grid;

[0049] The output terminal of the sampling unit is connected to the input terminal of the controller, and the sampling unit is used to sample the AC side current and AC side voltage of the power unit;

[0050] The output terminal of the controller is connected to the input terminal of each pulse width modulation circuit;

[0051] Each output terminal of each of the pulse width modulation circuits is respectively connected to each control terminal of the ANPC three-level topology corresponding to each of the pulse width modulation circuits through the driving circuit corresponding to each of the pulse width modulation circuits;

[0052] The capacitor unit is used to arrange a capacitor between every two interfaces on the AC side of the power unit.

[0053] Optionally, if the number of the driving circuits is greater than 1, all the driving circuits are integrated on the same driving board;

[0054] If the number of the pulse width modulation circuits is greater than 1, all the pulse width modulation circuits are integrated on the same circuit board.

[0055] As can be seen from the above technical solutions, the present invention provides a pulse width modulation circuit, which specifically includes: a pulse width modulation module and two turn-off delay modules. In this pulse width modulation circuit, since the two first output terminals of the pulse width modulation module are respectively connected to the input terminals of the two turn-off delay modules, and the output terminals of the two turn-off delay modules are respectively used to output the control signals of the two switching tubes for the power frequency switching operation in the ANPC three-level topology, the switching tube for the power frequency switching operation can receive its own turn-off signal with a delay, that is, the switching tube for the power frequency switching operation can be turned off with a delay. Therefore, when the on-off states of the two switching tubes for the power frequency switching operation are switched, that is, when switching at the zero crossing point, one switching tube for the power frequency switching operation may be turned off after the other switching tube for the power frequency switching operation is turned on; and since the switching tube for the power frequency switching operation is the inner tube in the ANPC three-level topology, when the switching tube for the power frequency switching operation is turned on, a current-carrying path where it is located is formed, so at this time, it is possible that a current-carrying path in the ANPC three-level topology forms an open circuit after another current-carrying path is formed, that is, there is always a current-carrying path as a conducting path at this time, thereby reducing the possibility of non-zero level switching when switching at the zero crossing point. Description of the Drawings

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0057] Figure 1 It is a schematic structural diagram of an implementation manner of the pulse width modulation circuit provided by the embodiment of the present application;

[0058] Figure 2 It is a schematic structural diagram of the ANPC three-level topology;

[0059] Figure 3 Schematic diagram of the principle of the pulse width modulation method for the ANPC three-level topology;

[0060] Figure 4 Schematic diagram of another implementation of the pulse width modulation circuit provided by the embodiment of the present application;

[0061] Figure 5 Schematic diagram of an implementation of the first turn-on delay module provided by the embodiment of the present application;

[0062] Figure 6 Schematic diagram of an implementation of the second turn-on delay module provided by the embodiment of the present application;

[0063] Figure 7 and Figure 8 Schematic diagrams of two implementations of the pulse width modulation module provided by the embodiment of the present application respectively;

[0064] Figure 9 Schematic diagram of an implementation of the turn-off delay module provided by the embodiment of the present application;

[0065] Figure 10 Schematic diagram of the ANPC three-level conversion system provided by the embodiment of the present application. Detailed implementation manners

[0066] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0067] In the present application, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0068] To reduce the possibility of non - zero - level switching during zero - crossing switching, an embodiment of the present application provides a pulse - width modulation circuit, and its specific structure is as follows Figure 1 shown, specifically including: a pulse - width modulation module 10 and two turn - off delay modules 20; the connection relationships between the modules are specifically described as follows:

[0069] The input end of the pulse - width modulation module 10 is connected to the output end of the controller 110 of the ANPC three - level topology, and receives the modulation wave signal Us sent by the controller 110. The pulse - width modulation module 10 is used to perform pulse - width modulation according to the received modulation wave signal Us, and respectively generate control signals for the six switching tubes in the ANPC three - level topology.

[0070] Specifically, the control signals of the switching tubes include: a turn - on signal for turning on the switching tube, and a turn - off signal for turning off the switching tube.

[0071] Two first output ends of the pulse - width modulation module 10 are respectively connected to the input ends of the two turn - off delay modules 20; the output ends of the two turn - off delay modules 20 are respectively used as the two first output ends of the pulse - width modulation circuit, and are respectively used to output the control signals of the two switching tubes for the power - frequency switching operation in the ANPC three - level topology, and the two switching tubes for the power - frequency switching operation are the two inner tubes in the ANPC three - level topology.

[0072] The turn - off delay module 20 is used to delay the output of the turn - off signal of the switching tube for the power - frequency switching operation, and does not delay the output of the turn - on signal of the switching tube for the power - frequency switching operation, that is: the switching tube for the power - frequency switching operation receives its own turn - off signal with a delay, and does not receive its own turn - on signal with a delay.

[0073] Two second output ends of the pulse - width modulation module 10 are respectively used as the two second output ends of the pulse - width modulation circuit, and are respectively used to output the control signals of the two outer tubes in the ANPC three - level topology.

[0074] Two third output ends of the pulse - width modulation module 10 are respectively used as the two third output ends of the pulse - width modulation circuit, and are respectively used to output the control signals of the two clamping tubes in the ANPC three - level topology.

[0075] Among them, Figure 2 For the ANPC three - level topology, the two inner tubes specifically refer to Figure 2 the switching tubes T2 and T3 in Figure 2 the two outer tubes specifically refer to Figure 2 the switching tubes T1 and T4 in

[0076] Taking the control signals of the two outer tubes, the control signals of the two clamping tubes, and the control signals of the two inner tubes as an example, as shown in Figure 3 the following, the differences between not setting the turn-off delay module 20 and setting the turn-off delay module 20 are compared as follows:

[0077] If the turn-off delay module 20 is not set, then in the negative half-cycle of the modulation wave signal Us, when the switching tubes T3 and T6 are conducting, the current flow path is as shown in Figure 2 2 in; during the process of the modulation wave signal Us switching from the negative half-cycle to the positive half-cycle, when the switching tube T3 is turned off and the switching tube T2 is not turned on, the current flow path is as shown in Figure 2 3 in; in the positive half-cycle of the modulation wave signal Us, when the switching tubes T2 and T5 are conducting, the current flow path is as shown in Figure 2 1 in; therefore, the zero-crossing switching switches from path 2 to path 3 and then to path 1, so during the zero-crossing switching process, a direct switching from a negative level to a zero level will occur, and thus zero-level switching at the zero crossing cannot be achieved.

[0078] If the turn-off delay module 20 is set, then during the process of the modulation wave signal Us switching from the negative half-cycle to the positive half-cycle, the switching tube T3 is turned off with a delay, so the switching tube T3 may be turned off after the switching tube T2 is turned on, and then there is a part where the switching tubes T2 and T3 are conducting simultaneously. Therefore, the zero-crossing switching switches from path 2 to path 1, that is, zero-level switching at the zero crossing can be achieved.

[0079] Since the two first output terminals of the pulse width modulation module 10 are respectively connected to the input terminals of the two turn-off delay modules 20, and the output terminals of the two turn-off delay modules 20 are respectively used to output the control signals of the two switching tubes for the power frequency switching action in the ANPC three-level topology, the switching tubes for the power frequency switching action can receive their own turn-off signals with a delay, that is, the switching tubes for the power frequency switching action can be turned off with a delay. Therefore, when the on-off states of the two switching tubes for the power frequency switching action are switched, that is, during the zero-crossing switching, one switching tube for the power frequency switching action may be turned off after the other switching tube for the power frequency switching action is turned on; and since the switching tubes for the power frequency switching action are the inner tubes in the ANPC three-level topology, when the switching tubes for the power frequency switching action are turned on, a conduction path is formed in the commutation path where they are located, so at this time, it is possible that a commutation path in the ANPC three-level topology forms an open circuit after another commutation path forms a conduction path, that is, there is always a commutation path that is in a conduction state at this time, thereby reducing the possibility of non-zero-level switching during the zero-crossing switching.

[0080] Another embodiment of the present application provides another implementation manner of the pulse width modulation circuit. Its specific structure is the same as that of the previous implementation manner. The difference between the two is that in this embodiment, two outer tubes in the ANPC three-level topology operate at half-wave switching frequency, and two clamping tubes in the ANPC three-level topology operate at full-wave switching frequency.

[0081] In this case, in the positive half-cycle of the modulation wave signal, the control signal of the clamping tube located in the lower half-bridge is the same as the control signal of the outer tube located in the upper half-bridge, and the control signal of the clamping tube located in the upper half-bridge is complementary to the control signal of the outer tube located in the upper half-bridge.

[0082] In this case, in the negative half-cycle of the modulation wave signal, the control signal of the clamping tube located in the upper half-bridge is the same as the control signal of the outer tube located in the lower half-bridge, and the control signal of the clamping tube located in the lower half-bridge is complementary to the control signal of the outer tube located in the lower half-bridge.

[0083] Among them, the outer tube located in the upper half-bridge specifically refers to Figure 2 the switching tube T1 in Figure 2 the switching tube T2 in the lower half-bridge specifically refers to Figure 2 the switching tube T5 in the upper half-bridge specifically refers to Figure 2 the switching tube T6 in the lower half-bridge.

[0084] Taking the control signals of the two outer tubes, the control signals of the two clamping tubes, and the control signals of the two inner tubes as shown in Figure 3 as an example, the current flow path of the ANPC three-level topology is described as follows:

[0085] In the positive half-cycle of the modulation wave signal Us, the switching tube T2 is always on, and the switching tubes T3 and T4 are always off. At this time, the current flow paths in different situations are specifically described as follows:

[0086] When Us > Ut, the switching tubes T1 and T6 are both on, and the switching tube T5 is off. At this time, the current flow path is as shown in Figure 2 4 in. At this time, since the switching tube T6 is conducting, the voltage borne by the switching tube T3 is the same as the voltage borne by the switching tube T4; when Us < Ut, the switching tube T5 is on, and the switching tubes T1 and T6 are both off. At this time, the current flow path is as shown in Figure 2 1 in.

[0087] In the negative half-cycle of the modulation wave signal Us, the switching tube T3 is always on, and the switching tubes T1 and T2 are both always off. At this time, the current flow paths in different situations are specifically described as follows:

[0088] When Us > Ut, switch tube T6 turns on, and switch tubes T4 and T5 both turn off. At this time, the current flow path is as shown in Figure 2 Figure 2; when Us < Ut, switch tubes T4 and T5 both turn on, and switch tube T6 turns off. At this time, the current flow path is as shown in Figure 2 Figure 3. At this time, since switch tube T5 is conducting, the voltage borne by switch tube T1 is the same as the voltage borne by switch tube T2.

[0089] As can be seen from the above, in this embodiment, the inner and outer tubes located in the lower half-bridge can bear the same voltage during the positive half-cycle of the modulation wave signal Us, and the inner and outer tubes located in the upper half-bridge can bear the same voltage during the negative half-cycle of the modulation wave signal Us.

[0090] Another embodiment of the present application provides another implementation manner of the pulse width modulation circuit, and its specific structure is as shown in Figure 4 Figure 12. On the basis of the previous embodiment, this implementation manner further includes: two first turn-on delay modules 30 and two second turn-on delay modules 40; the connection relationships between the modules are specifically as described below:

[0091] The two second output terminals of the pulse width modulation module 10 are respectively connected to the input terminals of the two first turn-on delay modules 30, and the output terminals of the two first turn-on delay modules 30 respectively serve as the two second output terminals of this pulse width modulation circuit.

[0092] The first turn-on delay module 30 is used to delay the output of the turn-on signal of the outer tube and does not delay the output of the turn-off signal of the outer tube, that is: the outer tube receives its own turn-on signal with a delay and does not receive its own turn-off signal with a delay.

[0093] The two third output terminals of the pulse width modulation module 10 are respectively connected to the input terminals of the two second turn-on delay modules 40, and the output terminals of the two second turn-on delay modules 40 respectively serve as the two third output terminals of this pulse width modulation circuit.

[0094] The second turn-on delay module 40 is used to delay the output of the turn-on signal of the clamping tube and does not delay the output of the turn-off signal of the clamping tube, that is: the clamping tube receives its own turn-on signal with a delay and does not receive its own turn-off signal with a delay.

[0095] Wherein, the delay time of each first turn-on delay module 30 is greater than the delay time of each second turn-on delay module 40, that is: the time for each outer tube to receive its own turn-on signal with a delay is greater than the time for each clamping tube to receive its own turn-on signal with a delay.

[0096] Taking the control signals of the two outer tubes, the control signals of the two clamping tubes, and the control signals of the two inner tubes as shown in Figure 3Taking the example shown below, compare the difference in the voltages borne by switching transistors T3 and T4 when the delay time of each first turn-on delay module 30 is equal to the delay time of each second turn-on delay module 40, and when the delay time of each first turn-on delay module 30 is greater than the delay time of each second turn-on delay module 40, as described in detail below:

[0097] In the positive half-cycle of the modulation wave signal Us, when Us > Ut, switching transistors T1 and T6 turn on, switching transistor T4 turns off, switching transistor T2 is always on. After switching transistors T1 and T2 turn on, the DC voltage is applied across switching transistors T3 and T4. When switching transistor T6 turns on, the voltages borne by switching transistors T3 and T4 are equal.

[0098] If at this time the delay time of each first turn-on delay module 30 is equal to the delay time of each second turn-on delay module 40, that is, the time when switching transistor T1 receives its own turn-on signal with delay is equal to the time when switching transistor T6 receives its own turn-on signal with delay, it may cause switching transistor T1 to turn on before switching transistor T6, resulting in switching transistors T3 and T4 possibly bearing different voltage divisions due to hardware differences for a period of time.

[0099] If at this time the delay time of each first turn-on delay module 30 is greater than the delay time of each second turn-on delay module 40, that is, the time when switching transistor T1 receives its own turn-on signal with delay is greater than the time when switching transistor T6 receives its own turn-on signal with delay, it causes switching transistor T1 to turn on after switching transistor T6, thus avoiding different voltage divisions borne by switching transistors T3 and T4.

[0100] In the negative half-cycle of the modulation wave signal Us, when the delay time of each first turn-on delay module 30 is equal to the delay time of each second turn-on delay module 40, and when the delay time of each first turn-on delay module 30 is greater than the delay time of each second turn-on delay module 40, the difference in the voltages borne by switching transistors T1 and T2 is the same as described above, and will not be elaborated here.

[0101] As can be seen from the above, in this embodiment, by setting the first turn-on delay module and the second turn-on delay module 40, in the positive half-cycle of the modulation wave signal Us, the outer transistor in the upper half-bridge is made to turn on before the clamping transistor in the lower half-bridge, and in the negative half-cycle of the modulation wave signal Us, the outer transistor in the lower half-bridge is made to turn on before the clamping transistor in the upper half-bridge, thus avoiding different voltage divisions borne by the inner and outer transistors in the lower half-bridge in the positive half-cycle of the modulation wave signal Us, and avoiding different voltage divisions borne by the inner and outer transistors in the upper half-bridge in the negative half-cycle of the modulation wave signal Us.

[0102] Another embodiment of the present application provides a specific implementation manner of the first turn-on delay module 30, and its specific structure is as Figure 5 shown, and specifically includes: a first diode D1, a first capacitor C1, and two resistors R1, R2; the connection relationships between the components are specifically described as follows:

[0103] The cathode of the first diode D1 is connected to one end of the first resistor R1, and the connection point serves as the input end of the first turn-on delay module 30; the other end of the first resistor R1 is connected to one end of the second resistor R2.

[0104] The other end of the second resistor R2, the anode of the first diode D1, and one end of the first capacitor C1 are all connected, and the connection point serves as the output end of the first turn-on delay module 30; the other end of the first capacitor C1 is grounded.

[0105] Taking the outer tube in the upper half-bridge as an example, that is, taking Figure 2 the switch tube T1 in it as an example, if the control signal of the switch tube T1 is high level, then the current passes through the first resistor R1 and the second resistor R2 and then charges the first capacitor C1C1. The charging time constant determines the charging speed of the first capacitor C1C1, that is, the charging time constant determines the delay time of the first turn-on delay module 30; if the control signal of the switch tube T1 is low level, then the first capacitor C1 directly discharges through the first diode D1D1, and the discharge time can be ignored. Therefore, there is no delay in turning off; in summary, there is a delay in turning on the switch tube T1, and there is no delay in turning off.

[0106] It should be noted that the process of the outer tube in the lower half-bridge, that is, Figure 2 the switch tube T5 in it, is the same as the above, and will not be elaborated here; in addition, the high level and the low level are set according to the circuit situation, and no specific limitation is made here.

[0107] The implementation manner of the first turn-on delay module 30 provided in this embodiment only needs capacitors, resistors, and diodes to achieve turn-on delay. Therefore, the structure of the first turn-on delay module 30 is simplified, thereby reducing the cost of the first turn-on delay module 30.

[0108] The above is only one implementation manner of the first turn-on delay module 30. In practical applications, it includes but is not limited to this. No specific limitation is made here, and it can be determined according to specific situations, and all are within the protection scope of the present application.

[0109] Another embodiment of the present application provides a specific implementation manner of the second turn-on delay module 40, and its specific structure is as Figure 6 shown, and specifically includes: a second diode D2, a second capacitor C2, and a third resistor R3; the connection relationships between the components are specifically described as follows:

[0110] The cathode of the second diode D2 is connected to one end of the third resistor R3, and the connection point serves as the input terminal of the second turn-on delay module 40.

[0111] The other end of the third resistor R3, the anode of the second diode D2, and one end of the second capacitor C2 are all connected, and the connection point serves as the input terminal of the second turn-on delay module 40; the other end of the second capacitor C2 is grounded.

[0112] Taking the clamping tube located in the upper half-bridge as an example, that is, Figure 2 taking the switching tube T5 in it as an example, if the control signal of the switching tube T5 is high level, then after the current passes through the third resistor R3, the second capacitor C2 is charged, and the charging time constant RC determines the charging speed of the second capacitor C2, that is, the RC time constant determines the delay time of the second turn-on delay module 40; if the control signal of the switching tube T5 is low level, then the second capacitor C2 directly discharges through the second diode D2, and the discharge time can be ignored, so there is no delay in turn-off; in summary, there is a delay in turn-on of the switching tube T5 and no delay in turn-off.

[0113] It should be noted that the process of the clamping tube located in the lower half-bridge, that is, Figure 2 the switching tube T6 in it, is the same as the above, and will not be elaborated here; in addition, the high level and the low level are set according to the circuit conditions, and no specific limitation is made here.

[0114] The implementation manner of the second turn-on delay module 40 provided in this embodiment only needs a capacitor, a resistor, and a diode to achieve turn-on delay, so the structure of the second turn-on delay module 40 is simplified, thereby reducing the cost of the second turn-on delay module 40.

[0115] The above is only one implementation manner of the second turn-on delay module 40. In practical applications, including but not limited to this, no specific limitation is made here, and it can be determined according to specific situations, and all are within the protection scope of this application.

[0116] Another embodiment of the present application provides an implementation manner of the pulse width modulation module 10, which is applicable to the situation where two outer tube half-wave switching frequencies act in the ANPC three-level topology and two clamping tube full-wave switching frequencies act in the ANPC three-level topology; the specific structure of this implementation manner is as Figure 7 shown, and specifically includes: three comparators 101 to 103, three selectors 104 to 106, two AND gates 107, 108, and three NOT gates 109 to 111; the connection relationships between the components are specifically described as follows:

[0117] The non-inverting input terminal of the first comparator 101 is connected to the input terminal of the pulse width modulation module 10. The inverting input terminal of the first comparator 101 is used to receive the positive half-cycle of the carrier signal. The output terminal of the first comparator 101 is connected to the first input terminal of the first selector 104.

[0118] The non-inverting input terminal of the second comparator 102 serves as the input for receiving the negative half-cycle of the carrier signal. The inverting input terminal of the second comparator 102 is connected to the input terminal of the pulse width modulation module 10. The output terminal of the second comparator 102 is connected to the second input terminal of the first selector 104.

[0119] The output terminal of the first selector 104 is respectively connected to one input terminal of the first AND gate 107 and one input terminal of the second AND gate 108.

[0120] The output terminal of the first AND gate 107 is connected to the first input terminal of the second selector 105 through the first NOT gate 109. The output terminal of the second AND gate 108 is connected to the first input terminal of the third selector 106 through the second NOT gate 110.

[0121] The second input terminal of the second selector 105 is connected to the output terminal of the second AND gate 108. The second input terminal of the third selector 106 is connected to the output terminal of the first AND gate 107.

[0122] The control terminal of the third selector 106 is connected to the other input terminal of the second AND gate 108. The connection point is connected to the output terminal of the third NOT gate 111. The input terminal of the third NOT gate 111 is connected to the output terminal of the third comparator 103.

[0123] The non-inverting input terminal of the third comparator 103 is connected to the input terminal of the pulse width modulation module 10. The inverting input terminal of the third comparator 103 is grounded.

[0124] The control terminal of the first selector 104, the control terminal of the second selector 105, and the other input terminal of the first AND gate 107 are all connected to the output terminal of the third comparator 103.

[0125] The potential of the output terminal of each selector is equal to its first input terminal when its control terminal is at a high level, and the potential of the output terminal of each selector is equal to its second input terminal when its control terminal is at a low level.

[0126] Specifically, the control signal G2 of the switching transistor T2 is connected to the control terminals of the first selector 104 and the second selector 105. If the control signal G2 of the switching transistor T2 is at a high level, both the first selector 104 and the second selector 105 select their respective first input ports as outputs; the control signal G3 of the switching transistor T3 is connected to the control terminal of the third selector 106. If the control signal G3 of the switching transistor T3 is at a high level, the third selector 106 selects its own first input port as the output.

[0127] The output terminals of the third comparator 103 and the third NOT gate 111 respectively serve as two first output terminals; the output terminals of the first AND gate 107 and the second AND gate 108 respectively serve as two second output terminals of the pulse width modulation module 10; the output terminals of the second selector 105 and the third selector 106 respectively serve as two third output terminals of the pulse width modulation module 10.

[0128] The working process of this embodiment of the pulse width modulation module 10 is specifically as follows:

[0129] The modulation wave signal Us and the zero level pass through the third comparator 103 to obtain the control signal G2 of the switching transistor T2, and the control signal G2 of the switching transistor T2 passes through the third NOT gate 111 to obtain the control signal G3 of the switching transistor T3. If the modulation wave signal Us is in the positive half cycle, the obtained control signal G2 of the switching transistor T2 is at a high level and the control signal G3 of the switching transistor T3 is at a low level. If the modulation wave signal Us is in the negative half cycle, the obtained control signal G2 of the switching transistor T2 is at a low level and the control signal G3 of the switching transistor T3 is at a high level.

[0130] If the modulation wave signal Us is in the positive half cycle, except for the control signals G2 of the switching transistor T2 and G3 of the switching transistor T3, the generation process of the control signals of other switching transistors is specifically as follows:

[0131] When the modulation wave signal Us > the positive half cycle of the carrier signal, the first comparator 101 outputs a high level. Since the control signal G2 of the switching transistor T2 is at a high level at this time, the output M of the first selector 104 is at a high level.

[0132] When the output M of the first selector 104 is at a high level, the control signal G1 of the switching transistor T1 output by the first AND gate 107 is at a high level, and the first NOT gate 109 outputs a low level. Since the control signal G2 of the switching transistor T2 is at a high level at this time, the control signal G5 of the switching transistor T5 output by the second selector 105 is at a low level.

[0133] When the output M of the first selector 104 is at a high level, the control signal G4 of the switching transistor T4 output by the second AND gate 108 is at a low level. Since the control signal G3 of the switching transistor T3 is at a low level, the control signal G6 of the switching transistor T6 output by the third selector 106 is the same as the control signal G1 of the switching transistor T1, that is, the control signal G6 of the switching transistor T6 is at a high level.

[0134] When the modulation wave signal Us < the positive half-cycle of the carrier signal, the first comparator 101 outputs a low level. Since the control signal G2 of the switching transistor T2 is at a high level at this time, the output M of the first selector 104 is at a low level.

[0135] When the output M of the first selector 104 is at a low level, the control signal G1 of the switching transistor T1 output by the first AND gate 107 is at a low level, and the first NOT gate 109 outputs a high level. Since the control signal G2 of the switching transistor T2 is at a high level at this time, the control signal G5 of the switching transistor T5 output by the second selector 105 outputs a high level.

[0136] When the output M of the first selector 104 is at a low level, the control signal G4 of the switching transistor T4 output by the second AND gate 108 is at a low level. Since the control signal G3 of the switching transistor T3 is at a low level, the control signal G6 of the switching transistor T6 output by the third selector 106 is the same as the control signal G1 of the switching transistor T1, that is, the control signal G6 of the switching transistor T6 is at a low level.

[0137] If the modulation wave signal Us is in the negative half-cycle, except for the control signal G2 of the switching transistor T2 and the control signal G3 of the switching transistor T3, the generation process of the control signals of other switching transistors is specifically as described below:

[0138] When the modulation wave signal Us > the negative half-cycle of the carrier signal, the second comparator 102 outputs a low level. Since the control signal G2 of the switching transistor T2 is at a low level at this time, the output M of the first selector 104 is at a low level.

[0139] When the output M of the first selector 104 is at a low level, the control signal G4 of the switching transistor T4 output by the second AND gate 108 is at a low level, and the second NOT gate 110 outputs a high level. Since the control signal G3 of the switching transistor T3 is at a high level, the control signal G6 of the switching transistor T6 output by the third selector 106 is at a high level.

[0140] When the output M of the first selector 104 is at a low level, the control signal G1 of the switching transistor T1 output by the first over-AND gate is at a low level. Since the control signal G2 of the switching transistor T2 is at a low level, the control signal of the switching transistor T5 output by the second selector 105 is the same as the control signal G4 of the switching transistor T4, that is, the control signal of the switching transistor T5 output by the second selector 105 is at a low level.

[0141] When the modulation wave signal Us < the negative half - cycle of the carrier signal, the second comparator 102 outputs a high level. Since the control signal G2 of the switching transistor T2 is at a low level at this time, the output M of the first selector 104 is at a high level.

[0142] When the output M of the first selector 104 is at a high level, the control signal G4 of the switching transistor T4 output by the second AND gate 108 is at a high level, and the second NOT gate 110 outputs a low level. Since the control signal G3 of the switching transistor T3 is at a high level, the control signal G6 of the switching transistor T6 output by the third selector 106 is at a low level.

[0143] When the output M of the first selector 104 is at a high level, the control signal G1 of the switching transistor T1 output by the first AND gate 107 is at a low level. Since the control signal G2 of the switching transistor T2 is at a low level, the control signal G5 of the switching transistor T5 output by the second selector 105 is the same as the control signal G4 of the switching transistor T4, that is, the control signal G5 of the switching transistor T5 output by the second selector 105 is at a high level.

[0144] The above is only one implementation manner of the pulse - width modulation module 10. In practical applications, it includes but is not limited to this. No specific limitation is made here, and it can be determined according to specific situations, and all are within the protection scope of this application.

[0145] Another embodiment of this application also provides another implementation manner of the pulse - width modulation module 10. This implementation manner is applicable to the case where both the positive half - cycle and the negative half - cycle of the carrier signal are triangular wave signals; the specific structure of this implementation manner is as Figure 8 shown. On the basis of the previous implementation manner, this implementation manner further includes: an adder 112.

[0146] The inverting input terminal of the first comparator 101 is used to receive the triangular wave signal; the non - inverting input terminal of the second comparator 102 is connected to the output terminal of the adder 112. One input terminal of the adder 112 receives the triangular wave signal, and the other input terminal of the adder 112 receives a preset negative voltage; the absolute value of the preset negative voltage is equal to twice the amplitude of the triangular wave signal.

[0147] Since the absolute value of the preset negative voltage is equal to twice the amplitude of the triangular wave signal, the triangular wave signal Ut and the preset negative voltage V can adjust the triangular wave signal to a negative value through the adder 112. At this time, the output of the adder 112 is the negative half - cycle of the carrier signal.

[0148] In this implementation manner, the triangular wave signal can be adjusted to a negative value through the adder 112 and the preset negative voltage. Therefore, the process of obtaining a negative triangular wave signal is simplified, thereby reducing the cost of the pulse - width modulation module 10.

[0149] The above is only one implementation manner of the pulse width modulation module 10. In practical applications, it includes but is not limited to this. Specific limitations are not made here and can be determined according to specific situations, and all are within the protection scope of this application.

[0150] Another embodiment of this application provides a specific implementation manner of the turn-off delay module 20, and its specific structure is as Figure 9 shown, specifically including: a third diode D3, a third capacitor C3, and a fourth resistor R4; the connection relationships between the components are specifically described as follows:

[0151] The anode of the third diode D3 is connected to one end of the fourth resistor R4, and the connection point serves as the input end of the turn-off delay module 20.

[0152] The other end of the fourth resistor R4, the cathode of the third diode D3, and one end of the third capacitor C3 are all connected, and the connection point serves as the output end of the turn-off delay module 20; the other end of the third capacitor C3 is grounded.

[0153] Taking the inner tube in the upper half-bridge as an example, that is, taking Figure 2 the switching tube T2 in it as an example, if the control signal of the switching tube T2 is high level, the current directly charges the third capacitor C3 through the third diode D3, and the charging time can be ignored, so there is no delay in turning on; if the control signal of the switching tube T2 is low level, the current discharges the third capacitor C3 through the fourth resistor R4, and the discharge time constant determines the discharge speed of the third capacitor C3, that is, the charging time constant determines the delay time of the turn-off delay module 20; in summary, the switching tube T2 has no delay in turning on and has a delay in turning off.

[0154] It should be noted that the process of the inner tube in the lower half-bridge, that is, Figure 2 the switching tube T3 in it, is the same as the above, and details are not described here again; in addition, the high level and the low level are set according to the circuit conditions, and specific limitations are not made here.

[0155] The implementation manner of the turn-off delay module 20 provided in this embodiment only needs a capacitor, a resistor, and a diode to achieve turn-off delay. Therefore, the structure of the turn-off delay module 20 is simplified, thereby reducing the cost of the turn-off delay module 20.

[0156] The above is only one implementation manner of the turn-off delay module 20. In practical applications, it includes but is not limited to this. Specific limitations are not made here and can be determined according to specific situations, and all are within the protection scope of this application.

[0157] Another embodiment of this application further provides an ANPC three-level conversion system, and its specific structure is as Figure 10As shown, specifically including: a controller 110, an inductor unit 120, a capacitor unit 130, a sampling unit 140, a grid-connected switch 150, a power unit 160, at least one driving circuit 170, and at least one pulse width modulation circuit 180 provided in the above embodiments; the connection relationships between the components are specifically as follows:

[0158] The power unit 160 includes at least one ANPC three-level topology, and the DC side of each ANPC three-level topology is connected to a DC source. For example, as Figure 10 shown, Figure 10 the power unit 160 in [reference] includes three ANPC three-level topologies, and the three ANPC three-level topologies are connected in parallel.

[0159] The AC sides of all the ANPC three-level topologies serve as the AC side of the power unit 160 and are connected to one end of the inductor unit 120.

[0160] The other end of the inductor unit 120 is connected to one end of the grid-connected switch 150, and the other end of the grid-connected switch 150 is used to connect to the grid. When the power unit 160 includes three parallel-connected ANPC three-level topologies, the specific structure of the inductor unit 120 is as shown by 120 in Figure 10 [reference]. When the power unit 160 includes three parallel-connected ANPC three-level topologies, the specific structure of the grid-connected switch 150 is as shown by 150 in Figure 10 [reference].

[0161] The output end of the sampling unit 140 is connected to the input end of the controller 110. The sampling unit 140 is used to sample the AC side current and AC side voltage of the power unit 160; usually, the current sampling position is on the load side of the grid-connected switch 150, that is, Figure 10 on the left side of the grid-connected switch 150 in [reference], and the voltage sampling position is on the grid side of the grid-connected switch 150, that is, Figure 10 on the right side of the grid-connected switch 150 in [reference].

[0162] The output end of the controller 110 is connected to the input end of each pulse width modulation circuit.

[0163] The respective output ends of each pulse width modulation circuit are respectively connected to the respective control ends of the ANPC three-level topology corresponding to each pulse width modulation circuit through the driving circuit 170 corresponding to each pulse width modulation circuit. For example, as Figure 10 shown, it includes three pulse width modulation circuits and three driving circuits 170.

[0164] The capacitor unit 130 is used to provide a capacitor between every two interfaces on the AC side of the power unit 160. When the power unit 160 includes three parallel-connected ANPC three-level topologies, the specific structure of the capacitor unit 130 is as shown by 130 in Figure 10 [reference].

[0165] If the number of drive circuits 170 is greater than 1, all the drive circuits 170 are integrated on the same drive board; if the number of pulse width modulation circuits is greater than 1, all the pulse width modulation circuits are integrated on the same circuit board.

[0166] In this embodiment, since the pulse width modulation circuit 180 provided in the above embodiment is adopted, the ANPC three-level conversion system can reduce the possibility of non-zero level switching during zero-crossing switching.

[0167] Regarding the above description of the disclosed embodiments, the features described in each embodiment in this specification can be replaced or combined with each other, enabling those skilled in the art to implement or use this application. The above are only preferred embodiments of the present invention, and are not intended to limit the present invention in any form. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above, or modify it into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A pulse width modulation circuit, characterized in that, Comprising: A pulse width modulation module and two turn-off delay modules; wherein: The input end of the pulse width modulation module is connected to the output end of the controller of the ANPC three-level topology; Two first output ends of the pulse width modulation module are respectively connected to the input ends of the two turn-off delay modules, and the output ends of the two turn-off delay modules are respectively used for outputting the control signals of the two inner tubes for the power frequency switch action in the ANPC three-level topology; Two second output ends of the pulse width modulation module are respectively used for outputting the control signals of the two outer tubes for the half-wave switch frequency action in the ANPC three-level topology; Two third output ends of the pulse width modulation module are respectively used for outputting the control signals of the two clamping tubes for the full-wave switch frequency action in the ANPC three-level topology; The pulse width modulation module includes: three comparators, three NOT gates, three selectors and two AND gates; wherein: The non-inverting input end of the first comparator is connected to the input end of the pulse width modulation module, the inverting input end of the first comparator is used for receiving the carrier signal in the positive half cycle, and the output end of the first comparator is connected to the first input end of the first selector; The non-inverting input end of the second comparator is used for receiving the carrier signal in the negative half cycle, the inverting input end of the second comparator is connected to the input end of the pulse width modulation module, and the output end of the second comparator is connected to the second input end of the first selector; The output end of the first selector is respectively connected to one input end of the first AND gate and one input end of the second AND gate; The output end of the first AND gate is connected to the first input end of the second selector through the first NOT gate, and the output end of the second AND gate is connected to the first input end of the third selector through the second NOT gate; The second input end of the second selector is connected to the output end of the second AND gate, and the second input end of the third selector is connected to the output end of the first AND gate; The control end of the third selector is connected to the other input end of the second AND gate, the connection point is connected to the output end of the third NOT gate, and the input end of the third NOT gate is connected to the output end of the third comparator; The non-inverting input end of the third comparator is connected to the input end of the pulse width modulation module, and the inverting input end of the third comparator is grounded; The control end of the first selector, the control end of the second selector, and the other input end of the first AND gate are all connected to the output end of the third comparator; The potential of the output end of each selector is equal to its first input end when its control end is at a high level, and the potential of the output end of each selector is equal to its second input end when its control end is at a low level; The output end of the third comparator and the output end of the third NOT gate are respectively used as the two first output ends of the pulse width modulation module; The output end of the first AND gate and the output end of the second AND gate are respectively used as the two second output ends of the pulse width modulation module; The output end of the second selector and the output end of the third selector are respectively used as the two third output ends of the pulse width modulation module.

2. The pulse width modulation circuit according to claim 1, characterized in that, Further comprising: Two first turn-on delay modules and two second turn-on delay modules; wherein: The two second output terminals of the pulse width modulation module are respectively connected to the input terminals of the two first turn-on delay modules, and the output terminals of the two first turn-on delay modules are respectively used to output the control signals of the two outer tubes that act at the half-wave switching frequency in the ANPC three-level topology; The two third output terminals of the pulse width modulation module are respectively connected to the input terminals of the two second turn-on delay modules, and the output terminals of the two second turn-on delay modules are respectively used to output the control signals of the two inner tubes that act at the full-wave switching frequency in the ANPC three-level topology; The delay time of each first turn-on delay module is greater than the delay time of each second turn-on delay module.

3. The pulse width modulation circuit according to claim 2, wherein The first turn-on delay module includes: a first diode, a first capacitor and two resistors; wherein: The cathode of the first diode is connected to one end of the first resistor, and the connection point serves as the input terminal of the first turn-on delay module; The other end of the first resistor is connected to one end of the second resistor; The other end of the second resistor, the anode of the first diode and one end of the first capacitor are all connected, and the connection point serves as the output terminal of the first turn-on delay module; The other end of the first capacitor is grounded.

4. The pulse width modulation circuit according to claim 2, wherein The second turn-on delay module includes: a second diode, a second capacitor and a third resistor; wherein: The cathode of the second diode is connected to one end of the third resistor, and the connection point serves as the input terminal of the second turn-on delay module; The other end of the third resistor, the anode of the second diode and one end of the second capacitor are all connected, and the connection point serves as the input terminal of the second turn-on delay module; The other end of the second capacitor is grounded.

5. The pulse width modulation circuit according to claim 1, characterized in that The pulse width modulation module further includes: an adder; wherein: The inverting input terminal of the first comparator is used to receive a triangular wave signal; The non-inverting input terminal of the second comparator is connected to the output terminal of the adder. One input terminal of the adder receives the triangular wave signal, and the other input terminal of the adder receives a preset negative voltage; the absolute value of the preset negative voltage is equal to twice the amplitude of the triangular wave signal.

6. The pulse width modulation circuit according to any one of claims 1 to 5, characterized in that, The turn-off delay module includes: a third diode, a third capacitor and a fourth resistor; wherein: The anode of the third diode is connected to one end of the fourth resistor, and the connection point serves as the input terminal of the turn-off delay module; The other end of the fourth resistor, the cathode of the third diode and one end of the third capacitor are all connected, and the connection point serves as the output terminal of the turn-off delay module; The other end of the third capacitor is grounded.

7. An ANPC three-level conversion system, characterized in that, Including: A controller, an inductor unit, a capacitor unit, a sampling unit, a grid-connected switch, a power unit, at least one drive circuit and at least one pulse width modulation circuit according to any one of claims 1 to 6; The power unit includes at least one ANPC three-level topology, and the DC side of each ANPC three-level topology is connected to a DC source; The AC sides of all the ANPC three-level topologies serve as the AC side of the power unit and are connected to one end of the inductor unit; The other end of the inductor unit is connected to one end of the grid-connected switch, and the other end of the grid-connected switch is used to connect to the power grid; The output end of the sampling unit is connected to the input end of the controller, and the sampling unit is used to sample the AC side current and AC side voltage of the power unit; The output end of the controller is connected to the input end of each of the pulse width modulation circuits; Each output end of each pulse width modulation circuit is respectively connected to each control end of the ANPC three-level topology corresponding to each pulse width modulation circuit through the driving circuit corresponding to each pulse width modulation circuit; The capacitor unit is used to arrange a capacitor between every two interfaces on the AC side of the power unit.

8. The ANPC three-level conversion system according to claim 7, wherein If the number of driving circuits is greater than 1, all the driving circuits are integrated on the same driving board; If the number of pulse width modulation circuits is greater than 1, all the pulse width modulation circuits are integrated on the same circuit board.

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