Micro LED structure and micro display panel

Abstract

A micro light emitting diode (LED) structure includes a mesa structure. The mesa structure further includes a first semiconductor layer, a light emitting layer formed on the first semiconductor layer, a second semiconductor layer formed on the light emitting layer, a sidewall protection layer formed on a sidewall of the mesa structure, and a sidewall reflection layer formed on a surface of the sidewall protection layer. A top surface area of the second semiconductor layer is greater than each of a bottom surface area of the first semiconductor layer, a top surface area of the first semiconductor layer, and a bottom surface area of the second semiconductor layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of light emitting diode technology, and more particularly to a micro light emitting diode (LED) structure and a micro display panel including the same. BACKGROUND

[0002] Inorganic micro light emitting diodes (also referred to as “micro-LEDs” or “p-LEDs”) are increasingly important due to their use in various applications including, for example, self-emissive micro-displays, visible light communications, and optogenetics. p-LEDs have better output performance than traditional LEDs due to better strain relaxation, improved light extraction efficiency, uniform current spreading, etc. p-LEDs are characterized by improved thermal effects, improved operation at higher current densities, better response rates, larger operating temperature ranges, higher resolutions, wider color gamut, higher contrast, and lower power consumption, etc. as compared to traditional LEDs.

[0003] p-LEDs include III-V epitaxial layers for forming a plurality of mesas. In certain p-LED designs, a space is needed to be formed between adjacent p-LEDs to avoid the diffusion of carriers in the epitaxial layer from one mesa to an adjacent mesa. The space formed between adjacent p-LEDs can reduce the effective light emitting area and lower the light extraction efficiency. Eliminating the space can increase the effective light emitting area, but this will cause the carriers in the epitaxial layer to laterally diffuse onto adjacent mesas and thus reduce the light emitting efficiency. Moreover, without the space between adjacent mesas, cross-talk between adjacent p-LEDs will occur, which will cause the p-LEDs to be less reliable or less accurate.

[0004] Furthermore, in some p-LED structures, small LED pixels with high current density will be more likely to experience red-shift, lower maximum efficiency, and non-uniform emission, which is typically caused by deteriorated electrical injection during fabrication. Moreover, the peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) of micro-LEDs greatly decrease as the chip size decreases. The decrease in EQE and IQE is caused by non-radiative recombination at the quantum well sidewall that is not properly etched. The decrease in IQE is caused by poor current injection and electron leakage current of the p-LED. Improving the EQE and IQE requires optimizing the quantum well sidewall region to reduce the current density. SUMMARY

[0005] According to the present disclosure, a micro-LED structure is provided. The structure includes a mesa structure. The mesa structure further includes a first semiconductor layer, a light emitting layer formed on the first semiconductor layer, a second semiconductor layer formed on the light emitting layer, a sidewall protection layer formed on a sidewall of the mesa structure, and a sidewall reflective layer formed on a surface of the sidewall protection layer. A top surface area of the second semiconductor layer is greater than each of a bottom surface area of the first semiconductor layer, a top surface area of the first semiconductor layer, and a bottom surface area of the second semiconductor layer.

[0006] Further, according to the present disclosure, a micro-display panel is provided. The micro-display panel includes a micro-LED array. The micro-LED array includes a first micro-LED structure and an integrated circuit (IC) backplane formed underneath the first micro-LED structure. The first micro-LED structure is electrically coupled to the IC backplane. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a micro-LED structure according to an example embodiment of the present disclosure; and

[0008] Figure 2 is a schematic cross-sectional view of at least a portion of an example micro-display panel according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0009] Hereinafter, embodiments consistent with the present disclosure will be described with reference to the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0010] As discussed above, micro-LEDs of the prior art can experience problems such as red-shift, low maximum efficiency, non-uniform emission, etc. To address these problems, a micro-LED structure is provided in embodiments of the present invention. In embodiments consistent with the present disclosure, Figure 1 In some embodiments consistent with the present disclosure, the micro-LED structure includes a mesa structure 01, a top contact 02, a bottom contact 03, a top conductive layer 04, a sidewall protection layer 104, and a sidewall reflective layer 105. The mesa structure 01 further includes a first type semiconductor layer 101, a light emitting layer 102, and a second type semiconductor layer 103. The light emitting layer 102 is formed on top of the first type semiconductor layer 101. The second type semiconductor layer 103 is on top of the light emitting layer 102. In some embodiments, the first type and the second type refer to different conductive types. For example, the first type is P-type, while the second type is N-type. In another example, the first type is N-type, while the second type is P-type.

[0011] Still referring to Figure 1A sidewall protective layer 104 is formed on the sidewall of the mesa structure 01 and a sidewall reflective layer 105 is formed on the surface of the sidewall protective layer 104. In some further embodiments, the sidewall protective layer 104 comprises the same material as the first semiconductor layer 101 or the second semiconductor layer 103. The sidewall protective layer 104 comprises a material that does not have conductive properties. In some embodiments, the sidewall protective layer 104 comprises InP or GaAs. The sidewall protective layer 104 is bonded to the sidewall of the mesa structure 01 via atomic bonds. In some embodiments, the sidewall reflective layer 104 comprises gold and silver. In some embodiments, the sidewall reflective layer 105 comprises a dielectric material combined with gold and silver.

[0012] Still referring to Figure 1 The top surface area of the second semiconductor layer 103 is made larger than the top surface area of the first semiconductor layer 101. In some embodiments, the top surface area of the second semiconductor layer 103 is made larger than the bottom surface area of the second semiconductor layer 103. The top surface area of the first semiconductor layer 101 is made larger than the bottom surface area of the first semiconductor layer 101. In some embodiments, the sidewalls of the first semiconductor layer 101, the light emitting layer 102 and the second semiconductor layer 103 are in the same plane in this embodiment, such that the sidewalls are flat. In some embodiments, the light emitting layer 102 and the second semiconductor layer 103 are not in the same plane and the sidewalls are not flat. In some embodiments, the diameter of the second semiconductor layer 103 is smaller than the diameter of the light emitting layer 102. In some embodiments, the diameter of the first semiconductor layer 101 is smaller than the diameter of the light emitting layer 102. In some embodiments, the material of the first type semiconductor layer 101 comprises at least one of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, p-AlGaN, etc. The material of the second type semiconductor layer 103 comprises at least one of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-InGaN, n-AlGaN, etc. The light emitting layer 102 is formed of a quantum well layer. The material of the quantum well layer comprises at least one of GaAs, InGaN, AlGaN, AlInP, GaInP, AlGaInP, etc. In some further embodiments, the thickness of the first type semiconductor layer 101 is larger than the thickness of the second type semiconductor layer 103 and the thickness of the light emitting layer 102 is smaller than the thickness of the first type semiconductor layer 101. In some embodiments, the thickness of the first type semiconductor layer 101 ranges from 700 nm to 2 pm and the thickness of the second type semiconductor layer 103 ranges from 100 nm to 200 nm. In some embodiments, the thickness of the quantum well layer is less than or equal to 30 nm. In some embodiments, the quantum well layer comprises no more than three pairs of quantum wells.

[0013] In some embodiments, the first-type semiconductor layer 101 includes one or more mirrors 1011. In some embodiments, the mirror 1011 is formed at a bottom surface of the first-type semiconductor layer 101. In some embodiments, the mirror 1011 is formed inside the first-type semiconductor layer 101. In some embodiments, the material of the mirror 1011 is a mixture of a dielectric material and a metal material. In some further embodiments, the dielectric material includes SiO2or SiN x wherein “x” is a positive integer. In some embodiments, the metal material includes Au or Ag. In some embodiments, the plurality of mirrors 1011 is formed in the first-type semiconductor layer 101 one after another in different horizontal planes, horizontally, thereby dividing the first-type semiconductor layer 101 into multiple layers. In some embodiments, a top contact 02 is formed at a top surface of the second-type semiconductor layer 103. The conductive type of the top contact 02 is the same as that of the second-type semiconductor layer 103. For example, if the second type is N-type, the top contact 02 is an N-type contact; or if the second type is P-type, the top contact 02 is a P-type contact. In some embodiments, the top contact 02 is made of a metal or a metal alloy including at least one of AuGe, AuGeNi, etc. The top contact 02 is used to form an ohmic contact between a top conductor layer 04 and the second-type semiconductor layer 103, thereby optimizing the electrical properties of the micro-LED. In some embodiments, the diameter of the top contact 02 ranges from 20 nm to 50 nm, and the thickness of the top contact 02 ranges from 10 nm to 20 nm.

[0014] Still referring to Figure 1 In some embodiments, the micro-LED structure further includes a top conductor layer 04 covering a top surface of the second-type semiconductor layer 103, and the top contact 02. The top conductor layer 04 is transparent and conductive. In some embodiments, the top conductor layer 04 includes at least one of indium tin oxide (ITO) and fluorine-doped tin oxide (FTO).

[0015] In some embodiments, the bottom contact 03 is formed at a bottom surface of the first type semiconductor layer 101. The conductive type of the bottom contact 03 is the same as the conductive type of the first type semiconductor layer 101. For example, if the first type semiconductor layer 101 is P-type, then the bottom contact 03 is also P-type. Similarly, if the first type semiconductor layer 101 is N-type, then the bottom contact 03 is also N-type. In some embodiments, light is emitted from a top surface of the mesa structure 01. To this end, the diameter of the bottom contact 03 is made larger than the diameter of the top contact 02, and the diameter of the top contact 02 is made as small as possible so that the top contact 02 appears like a point on the top surface of the second type semiconductor layer 103. In some embodiments, the diameter of the bottom contact 03 is equal to or smaller than the diameter of the top contact 02. In some embodiments, the bottom contact 03 is configured to be connected to a bottom electrode, such as a contact pad in an IC backplane. In some embodiments, the diameter of the bottom contact 03 ranges from 20 nm to 1 pm. In some embodiments, the diameter of the bottom contact 03 ranges from 800 nm to 1 pm. In some embodiments, the center of the bottom contact 03 is aligned with the center of the top contact 02 along an axis perpendicular to the upper surface of the first type semiconductor region. In some embodiments, the center of the bottom contact 03, the center of the top contact 02, and the center of the first type semiconductor region are all aligned along an axis perpendicular to the upper surface of the first type semiconductor region. In some embodiments, the material of the bottom contact 03 comprises a transparent conductive material. In some further embodiments, the material of the bottom contact 03 comprises ITO or FTO. In some embodiments, the bottom contact 03 is opaque, and the material of the bottom contact is a conductive metal. In some embodiments, the material of the bottom contact comprises at least one of the following elements: Au, Zn, Be, Cr, Ni, Ti, Ag, and Pt.

[0016] In some embodiments consistent with Figure 2 A micro display panel is provided. The micro display panel includes a micro LED array and an IC backplane 06 formed underneath the micro LED array. The micro LED array includes a plurality of the aforementioned micro LED structures. The micro LED structures are electrically coupled or connected to the IC backplane 06. In some embodiments, the length of the entire micro LED array is no more than 5 cm. The length of the backplane 06 is larger than the length of the micro LED array. In some embodiments, the length of the backplane 06 is no more than 6 cm. The area of the micro LED array is the effective display area.

[0017] In some embodiments, the micro LED structure further includes a metal bonding structure. More specifically, the metal bonding structure includes a metal bonding layer or a connection hole. For example, as Figure 2As shown, the metal bonding structure is the connection hole 05, and the connection hole 05 is filled with bonding metal. The top side of the connection hole 05 is connected with the top contact 03, and the bottom side of the connection hole 05 is connected with the contact pad on the surface of the IC backboard 06. In some embodiments, the top conductive layer 04 in the micro display panel covers the entire display panel.

[0018] Still referring to Figure 2 , the micro display panel further includes a dielectric layer 08. The dielectric layer 08 is formed between adjacent mesa structures 01. The material of the dielectric layer 08 is non-conductive, so that adjacent micro-LEDs are electrically isolated. In some embodiments, the material of the dielectric layer includes at least one of SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2. In some further embodiments, a reflective structure 07 is formed in the dielectric layer 08 between adjacent mesa structures 01 to avoid crosstalk. In some embodiments, the reflective structure 07 does not contact the mesa structure 01. In some embodiments, the top surface of the reflective structure 07 is aligned with the top surface of the mesa structure 01, and the bottom surface of the reflective structure 07 is aligned with the bottom surface of the mesa structure 01. The cross-sectional structure of the reflective structure 07 can be a triangular, rectangular, trapezoidal or any other shaped structure. In some embodiments, a sidewall reflective layer 105 is formed at the sidewall of the mesa structure 01, and the space between adjacent mesa structures 01 can be formed as small as possible. In some embodiments, the bottom of the reflective structure 07 extends downward, below the bottom of the mesa structure 01.

[0019] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The specification and examples are intended to be exemplary only and the true scope and spirit of the application is indicated by the following claims.

Claims

1. A micro light emitting diode (LED) structure, comprising: a mesa structure, comprising: a first semiconductor layer; a light emitting layer formed on the first semiconductor layer; a second semiconductor layer formed on the light emitting layer; a sidewall protection layer formed on a sidewall of the mesa structure; and, a sidewall reflective layer formed on a surface of the sidewall protection layer; wherein a top surface area of the second semiconductor layer is greater than each of a bottom surface area of the first semiconductor layer, a top surface area of the first semiconductor layer, and a bottom surface area of the second semiconductor layer; the sidewall protection layer comprises a same material as the first semiconductor layer or the second semiconductor layer, and does not have an electrically conductive property.

2. The micro-LED structure of claim 1, wherein, the sidewall is flat.

3. The micro-LED structure of claim 1, wherein, the sidewall is not flat.

4. The micro-LED structure of claim 1, wherein, a material of the sidewall protection layer comprises InP or GaAs.

5. The micro-LED structure of claim 1, wherein, the sidewall protection layer is bonded to the sidewall of the mesa structure via atomic bonds.

6. The micro-LED structure of claim 1, wherein, a material of the sidewall reflective layer comprises Au and Ag, or comprises a dielectric material combined with Au and Ag.

7. The micro-LED structure of claim 1, further comprising: a first mirror formed on a bottom surface of the first semiconductor layer.

8. The micro-LED structure of claim 7, further comprising: a second mirror formed inside the first semiconductor layer.

9. The micro-LED structure of claim 1, wherein, a thickness of the first semiconductor layer is greater than a thickness of the second semiconductor layer.

10. The micro-LED structure of claim 9, wherein, the thickness of the first semiconductor layer ranges from 700 nm to 2 pm, and the thickness of the second semiconductor layer ranges from 100 nm to 200 nm.

11. The micro-LED structure of claim 1, wherein, a thickness of the light emitting layer is less than the thickness of the first semiconductor layer.

12. The micro-LED structure of claim 1, wherein, the light emitting layer is formed by a quantum well layer located between the first semiconductor layer and the second semiconductor layer.

13. The micro-LED structure of claim 12, wherein, a thickness of the quantum well layer is less than or equal to 30 nm.

14. The micro-LED structure of claim 13, wherein, the quantum well layer comprises three or less than three pairs of quantum wells.

15. The micro LED structure of claim 1, further comprising a top contact formed on a top surface of the second semiconductor layer, and a top conductive layer formed on the second semiconductor layer and the top contact.

16. A micro display panel, comprising: a micro light emitting diode (LED) array, comprising: a first said micro LED structure according to claim 1, the first said micro LED structure comprising a first mesa structure; and an integrated circuit (IC) backplane formed under the first micro LED structure, wherein the first micro LED structure is electrically coupled to the IC backplane.

17. The microdisplay panel of claim 16, wherein, the first micro LED structure further comprises: a bottom contact, a top contact, a top conductive layer, and a connection hole, wherein a top side of the connection hole is connected with the bottom contact, and a bottom side of the connection hole is bonded with the IC backplane; and wherein the top conductive layer is formed on the display panel and electrically coupled to the top contact.

18. The microdisplay panel of claim 16, wherein, the micro light emitting diode (LED) array further comprises: a second said micro LED structure according to claim 1, the second said micro LED structure comprising a second mesa structure located adjacent to the first mesa structure; and a dielectric layer, wherein the dielectric layer is electrically non-conductive and formed between the first mesa structure and the second mesa structure.

19. The microdisplay panel of claim 18, wherein, The material of the dielectric layer is at least one of SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2.

20. The microdisplay panel of claim 19, wherein, The sidewall reflective layer of the first mesa structure and the second mesa structure is connected at the top surface of the first mesa structure and the second mesa structure.

21. The microdisplay panel of claim 20, wherein, The top surface of the first mesa structure and the second mesa structure are connected, and the micro display panel further comprises a reflective structure in the dielectric layer between the first mesa structure and the second mesa structure, wherein the top surface of the reflective structure is below the connected top surface of the first mesa structure and the second mesa structure.

22. The microdisplay panel of claim 21, wherein, The reflective structure is triangular.

23. The microdisplay panel of claim 22, wherein, The reflective structure comprises a first sidewall parallel to the sidewall reflective layer of the first mesa structure and a second sidewall parallel to the sidewall reflective layer of the second mesa structure. The reflective structure comprises a first sidewall parallel to the sidewall reflective layer of the first mesa structure and a second sidewall parallel to the sidewall reflective layer of the second mesa structure.

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