A planar gate MOSFET with multiple conductive channels and a method of fabrication
By precisely controlling the N+ region thickness in planar gate MOSFETs through etching and backfill processes, the problem of reducing on-resistance was solved, resulting in further reduction of on-resistance and improvement of yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGZHOU YANGJIE ELECTRONIC TECH CO LTD
- Filing Date
- 2024-07-15
- Publication Date
- 2026-07-21
AI Technical Summary
The reduction of on-resistance of existing planar gate MOSFETs has reached a theoretical limit. Traditional diffusion or ion implantation processes have insufficient precision in controlling the thickness of the N+ region sandwiched between the P+ channel region and the P-body region, resulting in low yield.
By using etching and backfilling processes instead of diffusion or ion implantation, the thickness of the N+ region sandwiched between the P+ channel region and the P-body region can be precisely controlled within 3-5 nm by controlling the etching rate, thus expanding the design range of the N+ region thickness.
It achieves adaptability to different application scenarios, reduces the on-resistance of planar gate MOSFETs, and improves device yield and process flexibility.
Smart Images
Figure CN118658786B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a planar gate MOSFET with multiple conductive channels and its fabrication method. Background Technology
[0002] In the field of power electronic device technology, MOSFET, as a commonly used power semiconductor, has replaced transistor as one of the most commonly used switching devices in the power semiconductor field.
[0003] Over the decades of iteration, increasing power density has always been one of the main directions of MOSFET development. Reducing the on-resistance per unit area is the most effective way to improve the power density of the device, and it is also one of the most important research and development directions for MOSFETs.
[0004] The industry's measures to reduce the on-resistance of planar gate MOSFETs mainly involve reducing the cell pitch and adopting superjunction structures. With the improvement of process precision, the cell pitch of planar gate MOSFETs has been reduced to its theoretical limit in recent years. After 20 years of development, superjunction structures have also reached their theoretical limit. Therefore, to further reduce the on-resistance of planar gate MOSFETs, new technologies and structures must be adopted.
[0005] Integrating an additional gate-controlled conductive channel into a MOSFET through structural design is a novel approach. On the same day, the inventors filed a patent application for a planar gate MOSFET with reduced on-resistance and its fabrication method. This invention provides a structure and fabrication method for integrating an additional gate-controlled conductive channel into a MOSFET. The P+ channel region is fabricated using diffusion or ion implantation processes. When the thickness of the N+ region sandwiched between the P+ channel region and the P-body region is large (greater than 100 nm), this method has the advantages of simple process and low cost. When the thickness of the N+ region sandwiched between the P+ channel region and the P-body region is less than 100 nm, the thickness of the P+ channel region needs to be precisely controlled to ensure that the P+ channel region and the P-body region are not connected, which can lead to low yield in actual operation. Summary of the Invention
[0006] To address the above problem, this invention uses an etching process combined with a backfilling process instead of a diffusion process (ion implantation process). By controlling the etching rate, the thickness of the N+ region sandwiched between the P+ channel region and the P-body region is precisely controlled within 3-5 nm, expanding the design range of the N+ region thickness in this structure. This enables a planar gate MOSFET with multiple conductive channels and its fabrication method to meet different application scenarios.
[0007] The technical solution of this invention is:
[0008] A method for fabricating a multi-channel planar gate MOSFET includes the following steps:
[0009] Step S100: Prepare several spaced P-body regions within the epitaxial wafer;
[0010] Step S200: Prepare several N+ regions spaced apart within the P-body region;
[0011] Step S300: A gate trench is prepared in the N+ region, and a P+ channel region is prepared in the gate trench;
[0012] Step S310: Using photolithography, a mask is used to protect the outer area of the gate trench, and the gate trench is prepared by etching (4).
[0013] Step S320: A P+ channel region is formed in the gate trench by chemical vapor deposition;
[0014] Step S400: A gate dielectric is prepared on the epitaxial wafer, and a plurality of spaced polysilicon is prepared on the gate dielectric above the P+ channel region.
[0015] In step S500, an isolation layer is deposited on the gate dielectric and polysilicon, and windows are opened in the N+ region and polysilicon to prepare the S electrode and G electrode, respectively.
[0016] Step S600: The D electrode is fabricated on the bottom of the epitaxial wafer, and the entire device fabrication is completed.
[0017] Specifically, step S100 includes:
[0018] Step S110: Using photolithography, a mask is used to protect the outer region of the P-body region; through diffusion or ion implantation, several spaced P-body regions are formed.
[0019] Specifically, the thickness of the P-body region is 1-20 μm, and the spacing is 1-10 μm.
[0020] Specifically, step S200 includes:
[0021] In step S210, a photolithography process is used to protect the outer region of the N+ region using a mask; and several N+ regions are formed at intervals by a diffusion process or an ion implantation process.
[0022] Specifically, the thickness of the N+ region is 0.5-10 μm.
[0023] Specifically, step S400 includes:
[0024] Step S410: The gate dielectric is fabricated on the epitaxial wafer using a thermal oxidation technique;
[0025] In step S420, the area outside the P+ channel region is protected by a photolithography process using a mask, and polycrystalline silicon is prepared on the gate dielectric above the P+ channel region by chemical vapor deposition.
[0026] Specifically, step S500 includes:
[0027] Step S510: Prepare an isolation layer using chemical vapor deposition; use a photolithography process to protect the N+ region and the external region of the polysilicon using a mask; and use an etching process to open windows in the N+ region and the polysilicon.
[0028] Step S520: The corresponding S electrode and G electrode are prepared in the N+ region and the polysilicon window by a stripping process or an etching process.
[0029] A planar gate MOSFET with multiple conductive channels includes a drain electrode, an epitaxial wafer, polysilicon, and an isolation layer arranged sequentially from bottom to top.
[0030] The top of the epitaxial wafer is provided with:
[0031] The P-body region is provided with several spaced apart from each other, each extending downward from the top surface of the epitaxial sheet;
[0032] The N+ region is provided in several parts, which are located in the P-body region and extend downward from the top surface of the epitaxial wafer, with their bottom surface being higher than the bottom surface of the P-body region.
[0033] The P+ channel region is provided with several channels, each extending downward from the top surface of the N+ region along one side, with its bottom surface higher than the bottom surface of the N+ region. One side of the N+ region and the P+ channel region is aligned with one side of the P body region in the vertical direction.
[0034] The gate dielectric is located on the top surface of the epitaxial wafer;
[0035] The polycrystalline silicon is provided with several spaced apart from each other, each located on the top surface of the gate dielectric above the P+ channel region;
[0036] The isolation layers are respectively disposed on the top surface of the gate dielectric and the top surface of the polysilicon; the isolation layer on the top surface of the gate dielectric is located between adjacent polysilicon cells;
[0037] The isolation layer contains:
[0038] The S electrode extends downward from the top surface of the isolation layer into the P-body region and connects with the N+ region and the P-body region to form an ohmic contact.
[0039] The G electrode extends downward from the top surface of the isolation layer into the polycrystalline silicon and forms an ohmic contact with the polycrystalline silicon.
[0040] Specifically, the epitaxial wafer includes an N+ substrate layer and an N- withstand voltage layer connected from bottom to top.
[0041] Specifically, the bottom of the substrate layer is provided with a D electrode, which forms an ohmic contact with the N+ substrate layer.
[0042] Beneficial effects of this invention:
[0043] The invention proposes a new fabrication scheme that uses an etching process plus a backfilling process instead of a diffusion process (ion implantation process). By controlling the etching rate, the thickness of the N+ region sandwiched between the P+ channel region and the P-body region can be precisely controlled within 3-5 nm, expanding the design range of the N+ region thickness of the structure to cope with different application scenarios.
[0044] Compared to traditional planar gate vertical conductive MOSFETs, this innovative design forms a thin N+ layer between the P-body region and the P+ channel region. In the off-state, when no voltage is applied to the gate electrode, the N+ layer is completely depleted and non-conductive due to the clamping effect between the P-body region and the P+ channel region. In the on-state, when a positive voltage is applied to the gate electrode, an inversion layer conductive channel is formed in the P+ channel region on the gate oxide side. Simultaneously, due to the positive voltage applied to the gate electrode, the N+ layer clamped between the P-body region and the P+ channel region changes from a completely depleted state to a normally conductive state. The N+ layer and the inversion layer conductive channel are connected in parallel and share the current carrying capacity of the device, reducing the on-resistance of the planar gate vertical conductive MOSFET. Attached Figure Description
[0045] Figure 1 This is a process flow diagram of the present invention;
[0046] Figure 2 This is a schematic diagram of the cross-sectional structure of the device in step S100;
[0047] Figure 3 This is a schematic diagram of the cross-sectional structure of the device in step S200;
[0048] Figure 4 This is a schematic diagram of the cross-sectional structure of the gate trench 4 fabricated within the N+ region 3;
[0049] Figure 5 This is a schematic diagram of the cross-sectional structure of the P+ channel region 5 fabricated within the gate trench 4;
[0050] Figure 6 This is a schematic diagram of the cross-sectional structure of the gate dielectric.
[0051] Figure 7 This is a schematic diagram of the cross-sectional structure of polycrystalline silicon.
[0052] Figure 8 This is a schematic diagram of the cross-sectional structure of the isolation layer.
[0053] Figure 9 This is a schematic diagram of the cross-sectional structure of a window opening on the isolation layer;
[0054] Figure 10 This is a schematic diagram of the cross-sectional structure of the S-electrode and G-electrode;
[0055] Figure 11 This is a schematic diagram of the cross-sectional structure of the D electrode.
[0056] In the figure, 1 is the epitaxial wafer, 2 is the P-body region, 3 is the N+ region, 4 is the gate trench, 5 is the P+ channel region, 6 is the gate dielectric, 7 is polysilicon, 8 is the isolation layer, 9 is the S electrode, 10 is the G electrode, 11 is the D electrode, 12 is the N+ substrate layer, and 13 is the N- breakdown layer. Detailed Implementation
[0057] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0058] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0059] The present invention will now be described with reference to Figures 1-11;
[0060] A method for fabricating a multi-channel planar gate MOSFET includes the following steps:
[0061] Step S100: A plurality of spaced P-body regions 2 are prepared within the epitaxial wafer 1, such as... Figure 2 As shown;
[0062] Step S110: Using photolithography, a mask is used to protect the outer region of the P-body region 2; through diffusion or ion implantation, several spaced P-body regions 2 are formed.
[0063] Accordingly, epitaxial wafer 1 is an N-type epitaxial wafer, consisting of an N+ substrate layer 12 and an N- withstand voltage layer 13 from bottom to top. The thickness of epitaxial wafer 1 is 100-2000 μm, the thickness of N+ substrate layer 12 is 90-1500 μm, the thickness of N- withstand voltage layer 13 is 10-500 μm, the thickness of P-body region 2 is 1-20 μm, and the spacing between them is 1-10 μm. The N-type doping concentration range is 1e. 14 .cm-3 -1e 20 .cm -3 The doping concentration range for P-type doping is 1e. 15 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device;
[0064] In this embodiment, the thickness of the epitaxial wafer 1 is 350 μm, the thickness of the N+ substrate layer 13 is 300 μm, and the doping concentration is 2e. 19 .cm -3 The N-terminal withstand layer 14 has a thickness of 50 μm and a doping concentration of 1e. 16 .cm -3 The thickness of the P-body region 2 is 5 μm, the spacing is 2 μm, and the doping concentration is 1e. 18 .cm -3 The P-body region 2 was prepared using an ion implantation process.
[0065] Step S200: Prepare several N+ regions 3 spaced apart within the P-body region 2, such as... Figure 3 As shown;
[0066] Step S210: Using photolithography, a mask is used to protect the outer region of N+ region 3; through diffusion or ion implantation, several N+ regions 3 are formed at intervals.
[0067] Correspondingly, N+ region 3 extends downward from the top surface of epitaxial wafer 1, with its bottom surface higher than the bottom surface of P-body region 2, a thickness of 0.5-10 μm, and a doping concentration range of 1e. 18 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device;
[0068] In this embodiment, the thickness of the N+ region 3 is 3 μm, and the doping concentration is 2e⁻¹. 19. cm -3 The N+ region 3 was prepared using ion implantation.
[0069] Step S300: A gate trench 4 is formed within the N+ region 3, and a P+ channel region 5 is formed within the gate trench 4; as shown... Figure 4 , 5 As shown;
[0070] Step S310: Using photolithography, a mask is used to protect the external area of the gate trench 4, and the gate trench 4 is prepared by etching.
[0071] In step S320, a P+ channel region 5 is formed in the gate trench 4 by chemical vapor deposition;
[0072] Accordingly, the gate trench 4 extends downward from the top surface of the epitaxial wafer 1, with its bottom surface higher than the bottom surface of the N+ region 3, and its depth is set to 0.5-10 μm. The P+ channel region 5 fills the gate trench 4, and the doping concentration ranges from 1e. 18 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device;
[0073] In this embodiment, gate trench 4 is fabricated by etching, with a depth of 2.99 μm. P+ channel region 5 is fabricated by chemical vapor deposition, with a doping concentration of 3e. 18. cm -3 The thickness of the N+ region 3 below the P+ channel region 5 is 10 nm.
[0074] In step S400, a gate dielectric 6 is fabricated on the epitaxial wafer 1, and a plurality of spaced polysilicon 7s are fabricated on the gate dielectric 6 above the P+ channel region 5, such as... Figure 6 , 7 As shown;
[0075] Step S410: The gate dielectric 6 is prepared on the epitaxial wafer 1 using a thermal oxidation technique;
[0076] In step S420, the external region of the P+ channel region 5 is protected by a mask using a photolithography process, and polysilicon 7 is prepared on the gate dielectric 6 above the P+ channel region 5 by chemical vapor deposition.
[0077] Correspondingly, the gate dielectric 6 is made of SiO2 with a thickness of 40-500nm, and the polysilicon 7 has a thickness of 100nm-5um.
[0078] In this embodiment, 80nm SiO2 is prepared using thermal oxidation technology as the gate dielectric 6, and 500nm polycrystalline silicon 7 is prepared using chemical vapor deposition.
[0079] Step S500: An isolation layer 8 is deposited on the gate dielectric 6 and the polysilicon 7, such as... Figure 8 As shown;
[0080] Windowing is performed at N+ region 3 and polysilicon region 7, such as Figure 9 As shown, S electrode 9 and G electrode 10 are prepared respectively. Figure 10 As shown;
[0081] In step S510, an isolation layer 8 is prepared by chemical vapor deposition. The N+ region 3 and the external area of the polysilicon 7 are protected by a mask through photolithography. Windows are opened in the N+ region 3 and the polysilicon 7 by etching.
[0082] Step S520: Prepare the corresponding S electrode 9 and G electrode 10 in the N+ region and the opening of the polysilicon 7 by stripping or etching process.
[0083] Correspondingly, the isolation layer 8 serves a protective function. It is made of SiO2 or Si3N4 and has a thickness of 10-5000nm. It is etched using ICP dry etching to create a window. The window depth is greater than the sum of the thicknesses of the isolation layer 8 and the gate dielectric 6. The S electrode 9 extends downward from the top surface of the isolation layer 8 and connects with the N+ region 3 and the P-body region 2 to form an ohmic contact. The G electrode 10 extends downward from the top surface of the isolation layer 8 and connects with the polysilicon 7 to form an ohmic contact.
[0084] In this embodiment, Si3N4 is used as the isolation layer 8 with a thickness of 200nm. ICP dry etching is used to create a window with a depth of 300nm. The S electrode 9 and G electrode 10 are fabricated using two Al / Ti metal layers.
[0085] In step S600, the D electrode 11 is fabricated on the bottom of the epitaxial wafer, completing the fabrication of the entire device; as shown below. Figure 11 As shown;
[0086] In step S610, the D electrode 11 is fabricated on the bottom of the epitaxial wafer 1 through a thinning process and a back gold process, and the entire device is fabricated.
[0087] Accordingly, the epitaxial wafer 1 is thinned using a thinning process, and the D electrode 11 is fabricated using a back-gold process. The D electrode 11 and the N+ substrate layer 12 are connected to form an ohmic contact.
[0088] In this embodiment, a thinning process is used to reduce the thickness of the 350µm epitaxial wafer 1 to 180µm, and the D electrode 11 is fabricated using two Al / Ti metal layers, thus completing the fabrication of the entire device.
[0089] A planar gate MOSFET with multiple conductive channels includes a D electrode 11, an epitaxial wafer 1, a polysilicon 7, and an isolation layer 8 arranged sequentially from bottom to top;
[0090] The top of the epitaxial wafer 1 is provided with:
[0091] P-body region 2 is provided with several spaced apart from each other, located in the N-pressure resistant layer 13, extending downward from the top surface of the epitaxial wafer 1, and its bottom surface is higher than the bottom surface of the N-pressure resistant layer 13;
[0092] N+ regions 3 are provided in several places, which are located in the P-body region 2 and extend downward from the top surface of the epitaxial sheet 1, with their bottom surfaces being higher than the bottom surface of the P-body region 2.
[0093] Gate trench 4 is provided in several ways, each extending downward from the top surface of the corresponding N+ region 3, and its bottom surface is higher than the bottom surface of the N+ region 3;
[0094] P+ channel region 5, filling the gate trench 4, and one side of N+ region 3 and P+ channel region 5 respectively aligns with one side of P body region 2 in the vertical direction.
[0095] Within the P-body region 2, a structure consisting of P+ channel region 5, N+ region 3, and P-body region 2 is formed from top to bottom along the vertical direction of the region where P+ channel region 5 is located. In this structure, N+ region 3 is completely consumed by P+ channel region 5 and P-body region 2 above and below it.
[0096] Gate dielectric 6 is located on the top surface of the epitaxial wafer 1;
[0097] The polycrystalline silicon 7 is provided with several spaced apart from each other, and is located on the top surface of the gate dielectric 6;
[0098] The isolation layer 8 is disposed on the top surface of the gate dielectric 6 and the top surface of the polysilicon 7 respectively; the isolation layer 8 on the top surface of the gate dielectric 6 is located between adjacent polysilicon 7.
[0099] The isolation layer 8 is provided with:
[0100] The S electrode 9 extends downward from the top surface of the isolation layer 8 into the P-body region 2 and connects with the N+ region 3 and the P-body region 2 to form an ohmic contact.
[0101] The G electrode 10 extends downward from the top surface of the isolation layer 8 into the polysilicon 7 and forms an ohmic contact with the polysilicon 7;
[0102] Further defined, the epitaxial wafer 1 includes an N+ substrate layer 12 and an N- withstand layer 13 connected from bottom to top; the D electrode 11 is connected to the N+ substrate layer 12 to form an ohmic contact.
[0103] The present invention has the following advantages:
[0104] Integrating an additional gate-controlled conductive channel into a MOSFET through structural design is a novel approach. On the same day, the inventors filed a patent application for a planar gate MOSFET with reduced on-resistance and its fabrication method. This invention provides a structure and fabrication method for integrating an additional gate-controlled conductive channel into a MOSFET. The P+ channel region 5 is fabricated using diffusion or ion implantation processes. When the thickness of the N+ region 3 sandwiched between the P+ channel region 5 and the P-body region 2 is large (greater than 100 nm), this method has the advantages of simple process and low cost. When the thickness of the N+ region 3 sandwiched between the P+ channel region 5 and the P-body region 2 is less than 100 nm, the thickness of the P+ channel region 5 needs to be precisely controlled to ensure that the P+ channel region 5 and the P-body region 2 are not connected, which can lead to low yield in actual operation. To address this problem, this invention proposes a novel fabrication scheme that replaces the diffusion process (ion implantation) with an etching process combined with a backfill process. By controlling the etching rate, the thickness of the N+ region 3 sandwiched between the P+ channel region 5 and the P-body region 2 can be precisely controlled within 3-5 nm, thus expanding the design range of the N+ region 3 thickness in this structure to accommodate different application scenarios.
[0105] Compared to traditional planar gate vertical conductive MOSFETs, this invention innovatively forms a thin N+ layer between the P-body region and the P+ channel region of the device. In the off-state, when no voltage is applied to the gate electrode, the N+ layer is completely depleted and non-conductive under the clamping of the P-body region and the P+ channel region. In the on-state, when a positive voltage is applied to the gate electrode, an inversion layer conductive channel is formed in the P+ channel region on the gate oxide side. At the same time, due to the positive voltage applied to the gate electrode, the N+ layer clamped between the P-body region and the P+ channel region changes from a completely depleted state to a normal conductive state. The N+ layer and the inversion layer conductive channel are connected in parallel and jointly bear the current of the device, reducing the on-resistance of the planar gate vertical conductive MOSFET.
[0106] Regarding the information disclosed in this case, the following points need to be clarified:
[0107] The accompanying drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case; other structures can be referred to with ordinary designs.
[0108] Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;
[0109] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.
Claims
1. A method for fabricating a multi-channel planar gate MOSFET, characterized in that, Includes the following steps: Step S100: Prepare a plurality of spaced P-body regions (2) within the epitaxial wafer (1); Step S200: Prepare several N+ regions (3) spaced apart within the P-body region (2); In step S300, using photolithography, a mask is used to protect the outer region of the gate trench (4), and the gate trench (4) is prepared in the N+ region (3) by etching; and the P+ channel region (5) is prepared in the gate trench (4) by chemical vapor deposition. Step S400: A gate dielectric (6) is prepared on the epitaxial wafer (1), and a plurality of spaced polysilicon (7) is prepared on the gate dielectric (6) above the P+ channel region (5). In step S500, an isolation layer (8) is deposited on the gate dielectric (6) and polysilicon (7), and windows are opened at the N+ region (3) and polysilicon (7) to prepare the S electrode (9) and G electrode (10) respectively. Step S600: D electrode (11) is fabricated on the bottom of the epitaxial wafer, and the entire device is fabricated. The thickness of the N+ region (3) sandwiched between the P+ channel region (5) and the P body region (2) is 3-5nm. In the off state, no voltage is applied to the G electrode, and the N+ region (3) is completely depleted under the sandwiching of the P body region (2) and the P+ channel region (5), and does not conduct electricity. In the on state, a positive voltage is applied to the G electrode, and the P+ channel region (5) on the gate oxide side forms an inversion layer conductive channel. At the same time, due to the positive voltage applied to the G electrode, the N+ region (3) sandwiched between the P body region (2) and the P+ channel region (5) changes from a completely depleted state to a normal conductive state. The N+ region (3) and the inversion layer conductive channel are connected in parallel and jointly bear the current of the device, reducing the on-resistance of the planar gate vertical conductive MOSFET.
2. The method for fabricating a multi-channel planar gate MOSFET according to claim 1, characterized in that, Step S100 includes: Step S110: Using photolithography, a mask is used to protect the outer region of the P-body region (2); through diffusion or ion implantation, several spaced P-body regions (2) are formed.
3. A method for fabricating a multi-channel planar gate MOSFET according to claim 1 or 2, characterized in that, The thickness of the P-body region (2) is 1-20 μm, and the spacing is 1-10 μm.
4. The method for fabricating a multi-channel planar gate MOSFET according to claim 1, characterized in that, Step S200 includes: Step S210: Using photolithography, a mask is used to protect the outer region of the N+ region (3); through diffusion or ion implantation, several N+ regions (3) are formed at intervals.
5. A method for fabricating a multi-channel planar gate MOSFET according to claim 1 or 4, characterized in that, The thickness of the N+ region (3) is 0.5-10 μm.
6. The method for fabricating a multi-channel planar gate MOSFET according to claim 1, characterized in that, Step S400 includes: Step S410: The gate dielectric (6) is prepared on the epitaxial wafer (1) using the thermal oxidation technique. In step S420, the external region of the P+ channel region (5) is protected by a photolithography process using a mask, and polysilicon (7) is prepared on the gate dielectric (6) above the P+ channel region (5) by chemical vapor deposition.
7. The method for fabricating a multi-channel planar gate MOSFET according to claim 1, characterized in that, Step S500 includes: Step S510: Prepare an isolation layer (8) using chemical vapor deposition. Protect the N+ region (3) and the external region of polysilicon (7) using a photolithography process and an etching process to open windows in the N+ region (3) and polysilicon (7). Step S520: Prepare the corresponding S electrode (9) and G electrode (10) at the opening in the N+ region and polysilicon (7) by stripping or etching process.
8. A planar gate MOSFET with reduced on-resistance fabricated by the method for fabricating a multi-channel planar gate MOSFET according to claim 1, characterized in that, It includes a D electrode (11), an epitaxial wafer (1), a polysilicon (7) and an isolation layer (8) arranged sequentially from bottom to top; The top of the epitaxial wafer (1) is provided with: The P-body region (2) is provided with several spaced apart from each other, each extending downward from the top surface of the epitaxial sheet (1); The N+ region (3) is provided in several places, which are located in the P body region (2) and extend downward from the top surface of the epitaxial sheet (1), with its bottom surface being higher than the bottom surface of the P body region (2); The P+ channel region (5) is provided with several channels, which extend downward from the top surface of the N+ region (3) along one side, and their bottom surface is higher than the bottom surface of the N+ region (3); The gate dielectric (6) is located on the top surface of the epitaxial wafer (1); The polysilicon (7) is provided with several spaced apart from each other, and is located on the top surface of the gate dielectric (6) above the P+ channel region (5); The isolation layer (8) is disposed on the top surface of the gate dielectric (6) and the top surface of the polysilicon (7); the isolation layer (8) on the top surface of the gate dielectric (6) is located between adjacent polysilicon (7); The isolation layer (8) contains: The S electrode (9) extends downward from the top surface of the isolation layer (8) into the P-body region (2) and connects with the N+ region (3) and the P-body region (2) to form an ohmic contact; The G electrode (10) extends downward from the top surface of the isolation layer (8) into the polysilicon (7) and forms an ohmic contact with the polysilicon (7).
9. A planar gate MOSFET with reduced on-resistance according to claim 8, characterized in that, The epitaxial wafer (1) includes an N+ substrate layer (12) and an N- withstand layer (13) connected from bottom to top.
10. A planar gate MOSFET with reduced on-resistance according to claim 9, characterized in that, The bottom of the N+ substrate (12) is provided with a D electrode (11) and forms an ohmic contact with the N+ substrate (12).