A method for monitoring chip temperature
By setting up multiple monitoring points and temperature sensing circuits in the power management chip, combining historical and external temperature data to reconstruct the internal temperature distribution, the problem of temperature monitoring error in the existing technology is solved, and more accurate temperature monitoring and more Small chip size.
Patent Information
- Application Number
- CN202411098186.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-12
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2044-08-12
AI Technical Summary
The prior art cannot accurately monitor the internal temperature of the power management chip, resulting in errors in the acquired temperature and cannot effectively reflect the actual working status of the chip.
By setting multiple monitoring points in the power management chip, using the temperature sensing circuit to obtain temperature data, and combining historical temperature distribution and off-chip temperature distribution, the internal temperature distribution of the chip is reconstructed to achieve accurate monitoring of the internal temperature of the power management chip.
Improves the accuracy of temperature monitoring, reduces the number of components, reduces the chip volume, and avoids temperature prediction errors caused by failure or excessive service life.
Smart Images
Figure CN118658838B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip temperature monitoring, and in particular to a method for monitoring chip temperature. Background Art
[0002] The power management chip is used to change, distribute and detect the power of electronic equipment. It is responsible for identifying the CPU power supply amplitude, generating corresponding short-moment waves, and converting the input voltage and power into power that can be used by electronic components on circuits such as microprocessors and sensors. When there is a problem with the power management chip, it will cause problems that seriously affect the use of the device, such as the inability to start the device normally and abnormal charging. Therefore, it is necessary to monitor the working status of the power management chip to avoid equipment problems. As an important parameter when the power management chip is working, the operating temperature can reflect to a certain extent whether the power management chip is in a normal working state. By monitoring the chip working temperature, it is possible to detect whether the chip is faulty in time. The prior art calculates the operating temperature of the chip by the temperature of the surrounding environment of the current power management chip and / or the temperature of the adjacent chip. However, since the measured temperature is not the temperature inside the power management chip, there is a certain error between the obtained temperature and the actual temperature, and it cannot accurately reflect the actual internal temperature of the power management chip.
[0003] In view of this, the present invention proposes a method for monitoring chip temperature, by setting a small number of monitoring points in the power management chip, and reconstructing the temperature distribution inside the power management chip through the internal monitoring temperature and the external monitoring temperature, so as to realize accurate monitoring of the internal temperature of the power management chip. Summary of the invention
[0004] The object of the present invention is to provide a method for monitoring chip temperature, comprising: obtaining monitoring temperatures of multiple points in a power management chip; based on the current working state of the power management chip, comparing the distribution of multiple monitoring temperatures to the historical temperature distribution to obtain a predicted temperature distribution within the chip; obtaining an off-chip temperature distribution, and based on the off-chip temperature distribution, correcting the predicted temperature distribution within the chip to obtain a current temperature distribution; obtaining a maximum temperature in the current temperature distribution, and using the maximum temperature as the current monitoring temperature of the power management chip.
[0005] Furthermore, obtaining the monitoring temperature at each point includes: setting a temperature sensing circuit at the corresponding point; obtaining a first current and a second current through the temperature sensing circuit; processing the first current and the second current respectively based on the temperature characteristic curve of the current to obtain a first temperature and a second temperature; processing the first temperature and the second temperature to obtain the monitoring temperature of the corresponding point.
[0006] Further, the temperature sensing circuit includes a first temperature sensing circuit and a second temperature sensing circuit; the first temperature sensing circuit is used to obtain the first temperature; the first temperature sensing circuit includes transistors Q1, Q2, Q3 and Q4, MOS tubes M1, M2 and M3, resistors R1 and R2 and an amplifier OP; the collector of the transistor Q1 is connected to the power supply Vb1; the emitter is connected to the resistors R1 and R2, the emitters of the transistors Q2, Q3 and Q4, the positive output end of the amplifier OP and the second temperature sensing circuit; the base is connected to the drain of the MOS tube M1 and the other end of the resistor R1; the source of the MOS tube M1 is connected to the power supply Vb1; The gate is connected to the input end of the amplifier OP; the source of the MOS tube M2 is connected to the power supply Vb1; the drain is connected to the other end of the resistor R2 and the negative output end of the amplifier OP; the gate is connected to the input end of the amplifier OP and the gate of the MOS tube M3; the source of the MOS tube M3 is connected to the power supply Vb1 and the second temperature sensing circuit; the drain is connected to the positive output end of the amplifier OP; the base and collector of the transistors Q2, Q3 and Q4 are grounded; the second temperature sensing circuit is used to obtain the second temperature; the second temperature sensing circuit includes transistors Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12 and Q13, resistors R3, R4, R5, R6, R7, R8, R9 and R10 and capacitor C; the collector of transistor Q5 is connected to the power supply Vb1; the base is connected to the power supply Vb2; the emitter is connected to the collector of transistor Q6, the grounding resistor R3 and the first temperature sensing circuit; the emitter of transistor Q6 is connected to the power supply VIN; the base is connected to the power supply Vb1; the emitter of transistor Q7 is connected to the power supply VIN; the gate is connected to the power supply Vb1; the collector is connected to the gate of transistor Q8 and the emitters of transistors Q9, Q10 and Q11; the collector of transistor Q8 is connected to the power supply V IN; the emitter is connected to resistor R4; the gate of transistor Q9 is connected to the collector of transistor Q10, grounded capacitor C and the collector of transistor Q12; the collector is grounded; the gate of transistor Q10 is connected to the base and collector of transistor Q11 and the collector of transistor Q13; the gate of transistor Q12 is connected to resistors R7 and R5; the emitter is connected to resistor R6 and grounded resistor R8; the gate of transistor Q13 is connected to the other end of resistor R5; the emitter is connected to the other end of resistor R6; the other end of resistor R4 is connected to the other end of resistor R7 and resistor R10; the other end of resistor R10 is connected to grounded resistor R9.
[0007] Furthermore, obtaining the predicted on-chip temperature distribution includes: determining a standard temperature distribution and multiple historical temperature distributions of the power management chip in the current working state, and performing mean processing on the multiple historical temperature distributions to obtain a historical mean; respectively determining the similarities between the multiple historical temperature distributions and the distributions of multiple monitored temperatures, and assigning weights to the multiple historical temperature distributions based on the similarities to obtain the initial temperature of the non-monitoring point; constructing an initial on-chip temperature distribution based on the monitored temperature and the initial temperature; constructing a first eigenvector based on the multiple historical temperature distributions; constructing a correction coefficient based on the first eigenvector and the difference between the initial on-chip temperature distribution and the historical temperature distribution; and correcting the initial on-chip temperature distribution based on the standard temperature distribution, the first eigenvector and the correction coefficient to obtain the predicted on-chip temperature distribution.
[0008] Furthermore, the constructing of the first eigenvector includes: respectively subtracting the multiple historical temperature distributions from the standard temperature distribution to obtain multiple historical difference matrices; performing matrix processing on the multiple historical difference matrices to obtain a characteristic matrix; and performing orthogonal normalization processing on the eigenvectors of the characteristic matrix to obtain multiple first eigenvectors.
[0009] Furthermore, the expression of the matrix processing is:
[0010] , where C represents the characteristic matrix; n represents the total number of historical temperature distributions; i represents the historical temperature distribution variable; represents the i-th historical temperature distribution; represents the standard temperature distribution; Represents the transposed matrix.
[0011] Furthermore, the expression for constructing the correction coefficient is:
[0012] , where j represents the correction variable; represents the correction coefficient of the i-th historical temperature distribution with respect to the j-th first eigenvector; represents the transpose of the j-th first eigenvector; represents the i-th historical temperature distribution; Represents the standard temperature distribution.
[0013] Furthermore, the expression for obtaining the predicted temperature distribution within the chip is:
[0014] ,in, represents the predicted temperature distribution within the chip; represents the standard temperature distribution; j represents the correction variable; m represents the total number of monitoring points; represents the correction coefficient of the i-th historical temperature distribution with respect to the j-th first eigenvector; represents the transpose of the j-th first eigenvector.
[0015] Furthermore, obtaining the current temperature distribution includes: aligning the off-chip temperature distribution with the on-chip predicted temperature distribution; determining the difference between the aligned on-chip predicted temperature distribution and the off-chip temperature distribution to obtain a difference distribution; determining an average difference based on the difference between the monitored temperature and the off-chip monitored temperature; the off-chip monitored temperature refers to the temperature of the monitoring point corresponding to the monitored temperature on the off-chip temperature distribution; correcting the temperature of the non-monitoring point in the difference distribution that is not within the preset difference threshold range to an off-chip correction value to obtain the current temperature distribution; the off-chip correction value is related to the off-chip temperature of the corresponding point and the average difference.
[0016] Furthermore, the calculation formula of the off-chip correction value is:
[0017] ,in, Indicates the off-chip correction value; Indicates the off-chip temperature at the corresponding point; Represents the mean difference.
[0018] The technical solution of the embodiment of the present invention has at least the following advantages and beneficial effects:
[0019] By obtaining the temperature of a small number of points inside the power management chip and combining the historical temperature distribution and the temperature distribution outside the chip, the current temperature distribution and the current monitoring temperature of the power management chip can be determined. The precise value of the temperature inside the power management chip can be obtained using fewer points, avoiding monitoring blind spots caused by too few points.
[0020] By combining the temperature sensing circuit with the circuit in the power management chip, temperature sensing can be achieved using fewer components, thereby reducing the size of the power management chip.
[0021] The predicted temperature distribution within the chip is determined by using the standard temperature distribution and multiple historical temperature distributions, so that the predicted temperature distribution within the chip is more consistent with the actual situation of the power management chip in the current working state, thereby improving the accuracy of temperature monitoring.
[0022] By correcting the predicted temperature distribution on chip through the off-chip temperature distribution, we can avoid the situation where the predicted temperature distribution of the chip differs greatly from the ideal temperature distribution of the power management chip when it is working normally due to power management chip failure or long service life, resulting in the predicted monitoring temperature distribution not matching the actual temperature distribution, thereby further improving the accuracy of the monitoring temperature. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 An exemplary flow chart of a method for monitoring chip temperature provided by the present invention;
[0024] Figure 2 An exemplary circuit diagram of the temperature sensing circuit provided by the present invention. DETAILED DESCRIPTION
[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.
[0026] Figure 1 The following is an exemplary flow chart of a method for monitoring chip temperature provided by the present invention. Figure 1 As shown, the method for monitoring chip temperature includes the following steps:
[0027] Step 1: Obtain monitoring temperatures of multiple points in the power management chip.
[0028] The point may refer to a monitoring point, which may be determined when designing a chip. The monitoring temperature may refer to a monitoring temperature of the monitoring point.
[0029] Obtaining the monitoring temperature of each point includes: setting a temperature sensing circuit at the corresponding point; obtaining a first current I1 and a second current I2 through the temperature sensing circuit; processing the first current and the second current based on the temperature characteristic curve of the current to obtain a first temperature and a second temperature; processing the first temperature and the second temperature to obtain the monitoring temperature of the corresponding point. The processing of the first temperature and the second temperature may be to take the average of the first temperature and the second temperature.
[0030] like Figure 2As shown, the temperature sensing circuit includes a first temperature sensing circuit and a second temperature sensing circuit; the first temperature sensing circuit is used to obtain the first temperature; the first temperature sensing circuit includes transistors Q1, Q2, Q3 and Q4, MOS tubes M1, M2 and M3, resistors R1 and R2 and an amplifier OP; the collector of the transistor Q1 is connected to the power supply Vb1; the emitter is connected to the resistors R1 and R2, the emitters of the transistors Q2, Q3 and Q4, the positive output end of the amplifier OP and the second temperature sensing circuit; the base is connected to the drain of the MOS tube M1 and the other end of the resistor R1; the source of the MOS tube M1 is connected to the power supply V b1; the gate is connected to the input end of the amplifier OP; the source of the MOS tube M2 is connected to the power supply Vb1; the drain is connected to the other end of the resistor R2 and the negative output end of the amplifier OP; the gate is connected to the input end of the amplifier OP and the gate of the MOS tube M3; the source of the MOS tube M3 is connected to the power supply Vb1 and the second temperature sensing circuit; the drain is connected to the positive output end of the amplifier OP; the base and collector of the transistors Q2, Q3 and Q4 are grounded; the second temperature sensing circuit is used to obtain the second temperature; the second temperature sensing circuit includes transistors Q5, Q6, Q7, Q8, Q9, Q 10, Q11, Q12 and Q13, resistors R3, R4, R5, R6, R7, R8, R9 and R10 and capacitor C; the collector of transistor Q5 is connected to power supply Vb1; the base is connected to power supply Vb2; the emitter is connected to the collector of transistor Q6, grounding resistor R3 and the first temperature sensing circuit; the emitter of transistor Q6 is connected to power supply VIN; the base is connected to power supply Vb1; the emitter of transistor Q7 is connected to power supply VIN; the gate is connected to power supply Vb1; the collector is connected to the gate of transistor Q8 and the emitters of transistors Q9, Q10 and Q11; the collector of transistor Q8 is connected to power supply V IN; the emitter is connected to resistor R4; the gate of transistor Q9 is connected to the collector of transistor Q10, grounded capacitor C and the collector of transistor Q12; the collector is grounded; the gate of transistor Q10 is connected to the base and collector of transistor Q11 and the collector of transistor Q13; the gate of transistor Q12 is connected to resistors R7 and R5; the emitter is connected to resistor R6 and grounded resistor R8; the gate of transistor Q13 is connected to the other end of resistor R5; the emitter is connected to the other end of resistor R6; the other end of resistor R4 is connected to the other end of resistor R7 and resistor R10; the other end of resistor R10 is connected to grounded resistor R9.
[0031] Step 2: Based on the current working state of the power management chip, the distribution of the plurality of monitored temperatures is compared with the historical temperature distribution to obtain the predicted temperature distribution within the chip.
[0032] The power management chip can have multiple working states. For example, it can be divided into low-power working state, medium-power working state and high-power working state according to power. The temperature distribution of the power management chip may be different in each working state. The current working state may refer to the current working state of the power management chip, and the current working state can be determined according to needs and settings. The distribution of monitored temperature refers to the distribution of temperatures at multiple monitoring points. The historical temperature distribution refers to the overall temperature distribution of the power management chip obtained in the current working state during normal operation. The historical temperature distribution can be measured before the power management chip is packaged. The on-chip predicted temperature distribution may refer to the predicted overall temperature distribution inside the power management chip.
[0033] The obtaining of the predicted temperature distribution within the chip includes: determining the standard temperature distribution and multiple historical temperature distributions of the power management chip in the current working state, and performing mean processing on the multiple historical temperature distributions to obtain the historical mean; respectively determining the similarity between the multiple historical temperature distributions and the distribution of multiple monitoring temperatures, and assigning weights to the multiple historical temperature distributions based on the similarity to obtain the initial temperature of the non-monitoring point; constructing the initial temperature distribution within the chip based on the monitoring temperature and the initial temperature; and constructing the first eigenvector based on the multiple historical temperature distributions;
[0034] Based on the first eigenvector and the difference between the initial on-chip temperature distribution and the historical temperature distribution, a correction coefficient is constructed; based on the standard temperature distribution, the first eigenvector and the correction coefficient, the initial on-chip temperature distribution is corrected to obtain the predicted on-chip temperature distribution. The standard temperature distribution refers to the most ideal overall temperature distribution of the chip under the current working state of the power management chip. The standard temperature distribution can be obtained by averaging multiple historical temperature distributions. Non-monitoring points refer to points on the power management chip where no temperature sensing circuit is set to obtain the monitoring temperature. The initial temperature can be determined by the sum of the products of multiple historical temperatures and weights. The monitoring points in the initial on-chip temperature distribution can be the values of the corresponding monitoring temperatures, and the non-monitoring points can be the values of the corresponding initial temperatures.
[0035] Constructing the first eigenvector includes: respectively subtracting the multiple historical temperature distributions from the standard temperature distribution to obtain multiple historical difference matrices; performing matrix processing on the multiple historical difference matrices to obtain a characteristic matrix; and performing orthogonal normalization processing on the eigenvectors of the characteristic matrix to obtain multiple first eigenvectors. The expression of the matrix processing is:
[0036] , where C represents the characteristic matrix; n represents the total number of historical temperature distributions; i represents the historical temperature distribution variable; represents the i-th historical temperature distribution; represents the standard temperature distribution; Represents the transposed matrix.
[0037] The expression for constructing the correction factor is:
[0038] , where j represents the correction variable; represents the correction coefficient of the i-th historical temperature distribution with respect to the j-th first eigenvector; represents the transpose of the j-th first eigenvector; represents the i-th historical temperature distribution; Represents the standard temperature distribution.
[0039] The expression for the predicted temperature distribution within the chip is obtained as follows:
[0040] ,in, represents the predicted temperature distribution within the chip; represents the standard temperature distribution; j represents the correction variable; m represents the total number of monitoring points; represents the correction coefficient of the i-th historical temperature distribution with respect to the j-th first eigenvector; represents the transpose of the j-th first eigenvector.
[0041] Step 3, obtaining the off-chip temperature distribution, and based on the off-chip temperature distribution, correcting the on-chip predicted temperature distribution to obtain the current temperature distribution.
[0042] The off-chip temperature distribution may refer to the overall temperature distribution of the chip measured outside the power management chip. The off-chip temperature distribution may be obtained in various ways, including but not limited to temperature sensors and infrared cameras. The current temperature distribution refers to the current on-chip temperature distribution of the power management chip.
[0043] Obtaining the current temperature distribution includes: aligning the off-chip temperature distribution with the on-chip predicted temperature distribution; determining the difference between the aligned on-chip predicted temperature distribution and the off-chip temperature distribution to obtain a difference distribution; determining an average difference based on the difference between the monitored temperature and the off-chip monitored temperature; the off-chip monitored temperature refers to the temperature of the monitoring point corresponding to the monitored temperature on the off-chip temperature distribution; correcting the temperature of the non-monitoring point in the difference distribution that is not within the preset difference threshold range to an off-chip correction value to obtain the current temperature distribution; the off-chip correction value is related to the off-chip temperature of the corresponding point and the average difference. The off-chip temperature distribution and the on-chip predicted temperature distribution can be aligned according to the corner points of the power management chip. The preset difference threshold range refers to the range of normal differences set in advance. The preset difference threshold range can be greater than or equal to the minimum value of the difference between the monitored temperature and the off-chip monitored temperature, and less than or equal to the maximum value of the difference between the monitored temperature and the off-chip monitored temperature. The calculation formula for the off-chip correction value is:
[0044] ,in, Indicates the off-chip correction value; Indicates the off-chip temperature at the corresponding point; Represents the mean difference.
[0045] Step 4: Obtain the maximum temperature in the current temperature distribution, and use the maximum temperature as the current monitoring temperature of the power management chip.
[0046] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A method for monitoring chip temperature, characterized in that: include: Acquire the monitored temperatures of multiple points in the power management chip; wherein acquiring the monitored temperature of each point includes: Set up temperature sensing circuits at corresponding points; Acquiring a first current and a second current through the temperature sensing circuit; Based on the temperature characteristic curve of the current, the first current and the second current are processed respectively to obtain a first temperature and a second temperature; Processing the first temperature and the second temperature to obtain monitoring temperatures at corresponding points; Based on the current working state of the power management chip, the distribution of the plurality of monitored temperatures is compared with the historical temperature distribution to obtain the on-chip predicted temperature distribution; wherein obtaining the on-chip predicted temperature distribution includes: Determine a standard temperature distribution and multiple historical temperature distributions of the power management chip in a current working state, and perform mean processing on the multiple historical temperature distributions to obtain a historical mean; Determine the similarities between the plurality of historical temperature distributions and the plurality of monitoring temperature distributions respectively, and assign weights to the plurality of historical temperature distributions based on the similarities respectively, to obtain initial temperatures of non-monitoring points; constructing an initial on-chip temperature distribution based on the monitored temperature and the initial temperature; Based on the multiple historical temperature distributions, construct a first eigenvector; constructing a correction coefficient based on the first eigenvector and a difference between the initial on-chip temperature distribution and the historical temperature distribution; Based on the standard temperature distribution, the first eigenvector and the correction coefficient, the initial on-chip temperature distribution is corrected to obtain the on-chip predicted temperature distribution; Obtaining an off-chip temperature distribution, and based on the off-chip temperature distribution, correcting the on-chip predicted temperature distribution to obtain a current temperature distribution; wherein obtaining the current temperature distribution includes: aligning the off-chip temperature distribution with the predicted on-chip temperature distribution; Determine the difference between the registered predicted temperature distribution inside the chip and the temperature distribution outside the chip to obtain a difference distribution; Determine an average difference based on a difference between the monitored temperature and an off-chip monitored temperature; the off-chip monitored temperature refers to a temperature of a monitoring point corresponding to the monitored temperature on the off-chip temperature distribution; Correcting the temperature of non-monitoring points in the difference distribution that are not within the preset difference threshold range to an off-chip correction value to obtain the current temperature distribution; the off-chip correction value is related to the off-chip temperature of the corresponding point and the average difference; The maximum temperature in the current temperature distribution is obtained, and the maximum temperature is used as the current monitoring temperature of the power management chip.
2. The method for monitoring chip temperature according to claim 1, characterized in that: The temperature sensing circuit includes a first temperature sensing circuit and a second temperature sensing circuit; The first temperature sensing circuit is used to obtain the first temperature; the first temperature sensing circuit includes transistors Q1, Q2, Q3 and Q4, MOS tubes M1, M2 and M3, resistors R1 and R2 and an amplifier OP; The collector of transistor Q1 is connected to power supply Vb1; the emitter is connected to resistors R1 and R2, emitters of transistors Q2, Q3 and Q4, the positive output end of amplifier OP and the second temperature sensing circuit; the base is connected to the drain of MOS tube M1 and the other end of resistor R1; The source of the MOS tube M1 is connected to the power supply Vb1; the gate is connected to the input end of the amplifier OP; The source of the MOS tube M2 is connected to the power supply Vb1; the drain is connected to the other end of the resistor R2 and the negative output end of the amplifier OP; the gate is connected to the input end of the amplifier OP and the gate of the MOS tube M3; The source of the MOS tube M3 is connected to the power supply Vb1 and the second temperature sensing circuit; the drain is connected to the positive output terminal of the amplifier OP; The bases and collectors of transistors Q2, Q3 and Q4 are grounded; The second temperature sensing circuit is used to obtain the second temperature; the second temperature sensing circuit includes transistors Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12 and Q13, resistors R3, R4, R5, R6, R7, R8, R9 and R10 and a capacitor C; The collector of transistor Q5 is connected to power supply Vb1; the base is connected to power supply Vb2; the emitter is connected to the collector of transistor Q6, grounding resistor R3 and the first temperature sensing circuit; The emitter of transistor Q6 is connected to the power supply VIN; the base is connected to the power supply Vb1; The emitter of transistor Q7 is connected to the power supply VIN; the gate is connected to the power supply Vb1; the collector is connected to the gate of transistor Q8 and the emitters of transistors Q9, Q10 and Q11; The collector of transistor Q8 is connected to the power supply VIN; the emitter is connected to the resistor R4; The gate of transistor Q9 is connected to the collector of transistor Q10, grounded capacitor C and the collector of transistor Q12; the collector is grounded; The gate of transistor Q10 is connected to the base and collector of transistor Q11 and the collector of transistor Q13; The gate of transistor Q12 is connected to resistors R7 and R5; the emitter is connected to resistor R6 and ground resistor R8; The gate of transistor Q13 is connected to the other end of resistor R5; the emitter is connected to the other end of resistor R6; The other end of the resistor R4 is connected to the other end of the resistor R7 and the resistor R10; The other end of the resistor R10 is connected to the grounding resistor R9.
3. The method for monitoring chip temperature according to claim 1, characterized in that: The constructing of the first feature vector comprises: Subtracting the multiple historical temperature distributions from the standard temperature distribution to obtain multiple historical difference matrices; Performing matrix processing on the multiple historical difference matrices to obtain a feature matrix; Orthogonal normalization is performed on the eigenvectors of the characteristic matrix to obtain a plurality of the first eigenvectors.
4. The method for monitoring chip temperature according to claim 3, characterized in that: The expression of the matrix processing is: , where C represents the characteristic matrix; n represents the total number of historical temperature distributions; i represents the historical temperature distribution variable; represents the i-th historical temperature distribution; represents the standard temperature distribution; Represents the transposed matrix.
5. The method for monitoring chip temperature according to claim 1, characterized in that: The expression for constructing the correction coefficient is: , where j represents the correction variable; represents the correction coefficient of the i-th historical temperature distribution with respect to the j-th first eigenvector; represents the transpose of the j-th first eigenvector; represents the i-th historical temperature distribution; Represents the standard temperature distribution.
6. The method for monitoring chip temperature according to claim 1, characterized in that: The expression for obtaining the predicted temperature distribution within the chip is: ,in, represents the predicted temperature distribution within the chip; represents the standard temperature distribution; j represents the correction variable; m represents the total number of monitoring points; represents the correction coefficient of the i-th historical temperature distribution with respect to the j-th first eigenvector; represents the transpose of the j-th first eigenvector.
7. The method for monitoring chip temperature according to claim 1, characterized in that: The calculation formula of the off-chip correction value is: ,in, Indicates the off-chip correction value; Indicates the off-chip temperature at the corresponding point; Represents the mean difference.