Semiconductor device and method for manufacturing the same, and electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, and an electronic device, which relate to the field of semiconductor chip technology and are intended to reduce the driving loss of semiconductor devices. The semiconductor device includes: a substrate, a channel layer, a barrier layer, a P-type GaN layer and a first gate metal layer, the channel layer is located on one side of the substrate, the barrier layer is located on the side of the channel layer away from the substrate, the P-type GaN layer is located on the side of the barrier layer away from the substrate, and the first gate metal layer is located on the side of the P-type GaN layer away from the substrate; wherein the semiconductor device also includes: a second gate metal layer, the second gate metal layer covers the first gate metal layer and the part of the P-type GaN layer away from the substrate, and a first passivation portion is provided between the second gate metal layer and the barrier layer. The above-mentioned semiconductor device is applied to power devices to achieve enhanced gate control capability.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a preparation method thereof, and an electronic device. Background Art

[0002] Enhanced high-electron-mobility transistor (HEMT) includes: heterojunction, the response speed of the two-dimensional electron gas 2DEG (two dimension electron gas) in the heterojunction to the gate control signal will affect the on-resistance R of the HEMT. on The on-resistance R of HEMT has an important impact on The lower the on-resistance R of the HEMT, the less the driving loss of the HEMT. on It is of great significance. Summary of the invention

[0003] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and an electronic device, which are used to increase the response speed of a two-dimensional electron gas (2DEG) in a heterojunction to a gate control signal, thereby reducing the on-resistance of the semiconductor device and reducing the driving loss of the semiconductor device.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a semiconductor device is provided, which includes: a substrate, a channel layer, a barrier layer, a P-type GaN layer and a first gate metal layer, the channel layer is located on one side of the substrate, the barrier layer is located on a side of the channel layer away from the substrate, the P-type GaN layer is located on a side of the barrier layer away from the substrate, and the first gate metal layer is located on a side of the P-type GaN layer away from the substrate; wherein the semiconductor device also includes: a second gate metal layer, the second gate metal layer covers the first gate metal layer and a portion of the P-type GaN layer away from the substrate, and a first passivation portion is arranged between the second gate metal layer and the barrier layer.

[0006] The semiconductor device provided by the above-mentioned embodiments of the present disclosure can increase the control ability of the second gate metal layer over the P-type GaN layer by configuring the second gate metal layer to cover the first gate metal layer and the portion of the P-type GaN layer away from the substrate, thereby increasing the response speed of the 2DEG under the P-type GaN layer to the control signal of the gate metal layer, reducing the channel resistance when the semiconductor device is turned on, and reducing the conduction loss of the semiconductor device.

[0007] In some embodiments, the first gate metal layer forms a Schottky contact with the P-type GaN layer, and the second gate metal layer forms a Schottky contact with the P-type GaN layer.

[0008] In some embodiments, the Schottky barrier between the second gate metal layer and the P-type GaN layer is greater than the Schottky barrier between the first gate metal layer and the P-type GaN layer.

[0009] In some embodiments, the semiconductor device further includes: a second passivation portion filled between the second gate metal layer and the dielectric layer.

[0010] In some embodiments, in an orthographic projection onto the substrate, the P-type GaN layer covers the first gate metal layer.

[0011] In some embodiments, the first passivation portion and the second passivation portion are an integral structure.

[0012] In some embodiments, the P-type GaN layer includes: a first P-type GaN layer and a second P-type GaN layer, wherein the second P-type GaN layer is located on a side of the first P-type GaN layer away from the substrate; wherein the doping concentration of the second P-type GaN layer is less than the doping concentration of the first P-type GaN layer.

[0013] In some embodiments, the first gate metal layer includes a plurality of gate sub-portions, and the plurality of gate sub-portions are spaced apart along a gate width direction; wherein the gate width direction is an extension direction of the second gate metal layer.

[0014] In some embodiments, in an orthographic projection onto the substrate, the gate sub-portion is at least one of a square and a circle.

[0015] In some embodiments, the first gate metal layer includes a plurality of gate sub-portions, the plurality of gate sub-portions are sequentially connected and arranged along a gate width direction, and at least two of the plurality of gate sub-portions have different extension directions.

[0016] In some embodiments, in an orthographic projection onto the substrate, the gate sub-portions are rectangular, and extension directions of two connected gate sub-portions intersect.

[0017] On the other hand, a method for preparing a semiconductor device is provided, the method comprising: forming a channel layer, a barrier layer and a P-type GaN layer in sequence on one side of a substrate; forming a passivation layer, the passivation layer comprising: a first passivation portion, the first passivation portion exposing a portion of the P-type GaN layer away from the substrate; forming a first gate metal layer on a side of the P-type GaN layer away from the substrate; forming a second gate metal layer on a side of the first gate metal layer away from the substrate, the second gate metal layer covering the first gate metal layer and the portion of the P-type GaN layer exposed by the first passivation portion.

[0018] In some embodiments, the passivation layer further includes: a second passivation portion; the forming of the passivation layer further includes: forming a second passivation portion, wherein the second passivation portion covers a portion of the P-type GaN layer away from the substrate, and the second passivation portion exposes a portion of the surface of the P-type GaN layer away from the substrate.

[0019] On the other hand, an electronic device is provided, comprising the semiconductor device and a substrate as described in any one of the above embodiments, wherein the semiconductor device is disposed on the substrate.

[0020] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor device and the electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, etc.

[0022] Figure 1 is a schematic structural diagram of a HEMT according to some embodiments;

[0023] Figure 2 is another structural schematic diagram of a HEMT according to some embodiments;

[0024] Figure 3 is a schematic structural diagram of a semiconductor device according to some embodiments;

[0025] Figure 4 A schematic diagram of a structure in which a depletion region between a second gate metal layer and a P-type GaN layer is developed according to some embodiments;

[0026] Figure 5is another structural schematic diagram of a semiconductor device according to some embodiments;

[0027] Figure 6 is another structural schematic diagram of a semiconductor device according to some embodiments;

[0028] Figure 7 is another structural schematic diagram of a semiconductor device according to some embodiments;

[0029] Figure 8 is another structural schematic diagram of a semiconductor device according to some embodiments;

[0030] Fig. 9 is a flow chart of a method for preparing a semiconductor device according to some embodiments;

[0031] Figure 10 to Figure 12 are structural diagrams corresponding to various steps of a method for manufacturing a semiconductor device according to some embodiments;

[0032] Fig.13 is a schematic structural diagram of an electronic device according to some embodiments. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0034] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0035] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0036] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0037] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0038] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0039] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0040] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0041] In some embodiments, Figure 1 As shown, a high-electron-mobility transistor (HEMT) using p-doped GaN as the P-type GaN layer 24 is widely used in the field of power switches due to its enhancement mode characteristics.

[0042] The structure of an enhanced HEMT is exemplarily introduced below.

[0043] For example, Figure 1 As shown, the HEMT includes: a substrate 11 , and a channel layer 14 and a barrier layer 15 sequentially arranged on one side of the substrate 11 .

[0044] Exemplarily, the material of the channel layer 14 includes GaN, and the material of the barrier layer 15 includes at least one of AlN and AlGaN. The following description is made by taking the example that the material of the channel layer 14 is GaN and the material of the barrier layer 15 is AlGaN.

[0045] AIGaN / GaN can form a heterojunction. The AIGaN / GaN heterojunction forms a high-density two-dimensional electron gas (2DEG) at the heterojunction interface through spontaneous polarization and piezoelectric polarization effects. This two-dimensional electron gas is spatially separated from ionized impurities, so it has a very high mobility, which makes the AIGaN / GaN HEMT have a very low on-resistance.

[0046] For example, Figure 1 As shown, the HEMT further includes: a P-type GaN layer 24 , a gate metal layer 23 located on a side of the P-type GaN layer 24 away from the substrate 11 , and a source 21 and a drain 22 located on both sides of the gate metal layer 23 .

[0047] Exemplarily, the material of the P-type GaN layer 24 includes P-type GaN. For example, the P-type GaN is GaN doped with at least one of Mg, Fe, Zn and C.

[0048] like Figure 1 As shown, the AIGaN / GaN heterojunction composed of the barrier layer 15 and the channel layer 14 forms a 2DEG at its interface, and the 2DEG forms a conductive channel SS. The conductive channel SS can be divided into: a channel region S1 and a drift region S2, the channel region S1 is located below the P-type GaN layer 24, and the drift region S2 is located in the conductive channel SS except the channel region S1.

[0049] It should be noted that according to the working state of HEMT at zero gate voltage, AIGaN / GaN HEMT can be divided into two categories: depletion type (normally open) and enhancement type (normally off): when the gate voltage is zero, the conductive channel SS is turned on, and when a negative bias is applied, the channel is turned off. This is called a depletion type HEMT; on the contrary, a HEMT whose conductive channel SS is turned on only when a certain positive gate voltage is applied is called an enhancement type HEMT.

[0050] like Figure 1 As shown, the P-type GaN layer 24 can deplete the 2DEG in the channel region S1, making the HEMT normally closed. However, the drift region S2 still maintains 2DEG. When a certain voltage is applied to the gate metal layer 23, the 2DEG in the channel region S1 can be re-established, making the HEMT conductive. Therefore, the HEMT is an enhancement-mode HEMT.

[0051] In some embodiments, Figure 1 As shown, when a positive gate voltage is applied to the gate metal layer 23, the 2DEG will pass through the barrier layer 15 along the boundary of the P-type GaN layer 24 to the gate metal layer 23, causing leakage from the side wall of the P-type GaN layer 24 to the gate metal layer 23, resulting in increased driving loss of the HEMT. For example, the leakage path from the side wall of the P-type GaN layer 24 to the gate metal layer 23 is shown as a path L1.

[0052] For example, Figure 1 and Figure 2 As shown, in order to avoid leakage from the sidewall of the P-type GaN layer 24 of the HEMT to the gate metal layer 23, the gate metal layer 23 does not completely cover the P-type GaN layer 24. For example, the P-type GaN layer 24 includes a P-type GaN layer 241 covered by the gate metal layer 23 and a P-type GaN layer 242 not covered by the gate metal layer 23, and the P-type GaN layer 242 is located in the peripheral area of ​​the P-type GaN layer 241.

[0053] When the gate metal layer 23 does not completely cover the P-type GaN layer 24, the leakage path from the side wall of the P-type GaN layer 24 to the gate metal layer 23 is shown as a path L2, and the 2DEG passes through the barrier layer 15 along the side boundary of the P-type GaN layer 24 and part of the upper boundary of the P-type GaN layer 24 to the gate metal layer 23, so as to cause leakage from the side wall of the P-type GaN layer 24 to the gate metal layer 23. Since the length of the path L2 is greater than the path L1, and there is a corner Q at the connection between the side boundary and the upper boundary of the P-type GaN layer 24, the corner Q will hinder the transmission of the 2DEG, thereby achieving the effect of reducing the leakage from the side wall of the P-type GaN layer 24 to the gate metal layer 23, so as to improve the life of the gate metal layer 23.

[0054] However, this will increase the on-resistance R of the HEMT. on (On Resistance) In HEMT, the on resistance Ron (On Resistance) is one of the important factors affecting the conduction loss of HEMT.

[0055] For example, Figure 2 As shown, the total on-resistance of HEMT consists of three parts: the contact resistance R C (Contact Resistance), drift region S2 resistance R drift (Drift Region Resistance) and the channel resistance R of the channel region S1 ch (Channel Resistance).

[0056] Among them, the channel resistance R ch The gate resistance R is regulated by the gate metal layer 23. The stronger the gate signal of the gate metal layer 23 is in controlling the 2DEG of the channel region S1, the greater the channel resistance R ch The smaller the gate signal of the gate metal layer 23 is, the weaker the control capability of the 2DEG of the channel region S1 is, and the channel resistance R ch The bigger.

[0057] However, when a voltage is applied to the gate metal layer 23, the control ability of the gate metal layer 23 on the P-type GaN layer 242 not covered by the gate metal layer 23 is weakened, which reduces the response speed of the 2DEG below this part of the area to the control signal of the gate metal layer 23, which is manifested as an increase in the turn-on and turn-off time of the HEMT, and a channel resistance R ch The conduction loss of HEMT increases significantly.

[0058] Based on this, Figure 3 As shown, an embodiment of the present disclosure provides a semiconductor device 100 , which includes: a substrate 11 , a channel layer 14 , a barrier layer 15 and a P-type GaN layer 24 .

[0059] Exemplarily, the material of the substrate 11 includes at least one of Si, SiC, GaN, sapphire and diamond. The contents of the channel layer 14, the barrier layer 15 and the P-type GaN layer 24 can refer to the above contents and will not be repeated here.

[0060] In some examples, such as Figure 3 As shown, the semiconductor device 100 further includes: a first gate metal layer 231 and a second gate metal layer 232, wherein the first gate metal layer 231 is located on a side of the P-type GaN layer 24 away from the substrate 11. The second gate metal layer 232 covers the first gate metal layer 231 and a portion of the P-type GaN layer 24 away from the substrate 11, and a first passivation portion 161 is disposed between the second gate metal layer 232 and the barrier layer 15.

[0061] That is, the first gate metal layer 231 and the second gate metal layer 232 together form the gate metal layer 23. By the second gate metal layer 232 covering the first gate metal layer 231 and the portion of the P-type GaN layer 24 away from the substrate 11, the control capability of the second gate metal layer 232 on the P-type GaN layer 24 can be increased, so as to increase the response speed of the 2DEG below the P-type GaN layer 24 to the control signal of the gate metal layer 23, and reduce the channel resistance R when the semiconductor device 100 is turned on. c , so as to reduce the conduction loss of the semiconductor device 100.

[0062] Moreover, by setting the first passivation portion 161 between the second gate metal layer 232 and the barrier layer 15, the second gate metal layer 232 and the barrier layer 15 can be separated to effectively prevent the second gate metal layer 232 and the barrier layer 15 from directly contacting each other and causing leakage of the semiconductor device 100 through the second gate metal layer 232.

[0063] Exemplarily, the material of the first gate metal layer 231 includes at least one of Pd, Ni, Al, Au, Pt, Ti and TiN.

[0064] Exemplarily, the material of the second gate metal layer 232 includes at least one of Pd, Ni, Al, Au, Pt, Ti and TiN.

[0065] In some embodiments, Figure 3 As shown, the first gate metal layer 231 forms a Schottky contact with the P-type GaN layer 24 , and the second gate metal layer 232 forms a Schottky contact with the P-type GaN layer 24 .

[0066] That is, the first gate metal layer 231 and the second gate metal layer 232 together form the gate metal layer 23 , and the gate metal layer 23 forms a Schottky contact with the P-type GaN layer 24 .

[0067] It should be noted that the semiconductor device 100 can be divided into an ohmic contact type and a Schottky contact type according to the different contact types between the gate metal layer 23 and the P-type GaN layer 24. When the Schottky contact type semiconductor device 100 is turned on, due to the blocking of the Schottky barrier of the gate metal layer 23, the leakage of the Schottky contact type semiconductor device 100 will be significantly smaller than the leakage of the ohmic contact type semiconductor device 100, so the Schottky contact type semiconductor device 100 has a lower driving loss.

[0068] For example, Figure 3 As shown, when a voltage is applied to the gate metal layer 23 , a portion of the 2DEG is transmitted through the P-type GaN layer 24 and the gate metal layer 23 to cause leakage of the semiconductor device 100 . The path of this portion of leakage is shown as a path L3 .

[0069] By forming a Schottky contact between the first gate metal layer 231 and the P-type GaN layer 24 and a Schottky contact between the second gate metal layer 232 and the P-type GaN layer 24, the existence of the Schottky barrier blocks the leakage of the path L3, thereby achieving the purpose of reducing the leakage of the semiconductor device 100 and reducing the driving loss of the semiconductor device 100.

[0070] In some embodiments, Figure 3 and Figure 4 As shown, the Schottky barrier between the second gate metal layer 232 and the P-type GaN layer 24 is greater than the Schottky barrier between the first gate metal layer 231 and the P-type GaN layer 24 .

[0071] Exemplarily, the work function of the material of the first gate metal layer 231 is higher than the work function of the material of the second gate metal layer 232. The Schottky barrier between the first gate metal layer 231 with a higher work function and the P-type GaN layer 24 is smaller, and the Schottky barrier between the second gate metal layer 232 with a lower work function and the P-type GaN layer 24 is larger.

[0072] For example, the material of the first gate metal layer 231 is Ni, whose work function is 5.1, and the material of the second gate metal layer 232 is Ti, whose work function is 4.3, so that the Schottky barrier between the second gate metal layer 232 and the P-type GaN layer 24 is greater than the Schottky barrier between the first gate metal layer 231 and the P-type GaN layer 24.

[0073] Since the Schottky barrier between the second gate metal layer 232 and the P-type GaN layer 24 is greater than the Schottky barrier between the first gate metal layer 231 and the P-type GaN layer 24, when a voltage is applied to the gate metal layer 23, a depletion region is formed between the second gate metal layer 232 and the P-type GaN layer 24, and the depletion region is expanded along the interface L4 between the second gate metal layer 232 and the P-type GaN layer 24. At this time, the depletion region can pinch off the leakage of the path L3, thereby preventing the 2DEG from transmitting through the P-type GaN layer 24 and the gate metal layer 23 and causing leakage of the semiconductor device 100, so as to reduce the driving loss of the semiconductor device 100.

[0074] In some embodiments, Figure 5 As shown, the semiconductor device 100 further includes: a second passivation portion 162 , and the second passivation portion 162 is filled between the second gate metal layer 232 and the P-type GaN layer 24 .

[0075] Exemplarily, the first passivation portion 161 and the second passivation portion 162 are an integral structure, that is, the first passivation portion 161 and the second passivation portion 162 are formed simultaneously, and the first passivation portion 161 and the second passivation portion 162 can be referred to as a passivation layer 16. In order to facilitate the preparation of the passivation layer 16, the semiconductor device 100 includes a first passivation portion 161 and a second passivation portion 162 of an integral structure. Regarding the formation of the passivation layer 16, reference can be made to the introduction of the subsequent semiconductor device preparation method, which will not be described in detail here.

[0076] Due to the setting of the passivation layer 16, the second gate metal layer 232 and the P-type GaN layer 24 are not in direct contact, and the second gate metal layer 232, the passivation layer 16 and the barrier layer 15 can form a parasitic MIS (Metal-Insulator-Semiconductor) tube, that is, the second gate metal layer 232 can effectively control the 2DEG under the P-type GaN layer 24.

[0077] Moreover, if Figure 1 , Figure 2 and Figure 5 As shown, the passivation layer 16 can effectively shield the leakage of the sidewall of the P-type GaN layer 24 to reduce the risk of leakage from the sidewall of the P-type GaN layer 24 to the gate metal layer 23 , thereby reducing the driving loss of the semiconductor device 100 .

[0078] In some embodiments, Figure 2 and Figure 5 As shown, in the orthographic projection onto the substrate 11 , the P-type GaN layer 24 covers the first gate metal layer 23 .

[0079] That is, the first gate metal layer 231 does not completely cover the P-type GaN layer 24 .

[0080] Exemplarily, the P-type GaN layer 24 includes a P-type GaN layer 241 covered by the first gate metal layer 231 and a P-type GaN layer 242 not covered by the first gate metal layer 231 , and the P-type GaN layer 242 is located in a peripheral region of the P-type GaN layer 241 .

[0081] There is a corner Q at the connection between the side boundary and the upper boundary of the P-type GaN layer 24 , and the corner Q will hinder the transmission of 2DEG, thereby further reducing the leakage from the side wall of the P-type GaN layer 24 to the gate metal layer 23 .

[0082] In some embodiments, Figure 6As shown, the P-type GaN layer 24 includes: a first P-type GaN layer 24a and a second P-type GaN layer 24b, wherein the second P-type GaN layer 24b is located on a side of the first P-type GaN layer 24a away from the substrate 11; wherein the doping concentration of the second P-type GaN layer 24b is less than the doping concentration of the first P-type GaN layer 24a.

[0083] Exemplarily, the doping concentration of the second P-type GaN layer 24b is less than or equal to 1 x 10 18 cm -3 The doping concentration of the first P-type GaN layer 24a is greater than or equal to 1x10 19 cm -3 .

[0084] When a positive gate voltage is applied to the gate metal layer 23, the second P-type GaN layer 24b with a lower doping concentration is more likely to form a depletion region. The fully depleted second P-type GaN layer 24b can block the 2DEG that causes leakage of the semiconductor device 100 through the P-type GaN layer 24 and the gate metal layer 23, so as to reduce the driving loss of the semiconductor device 100.

[0085] The doping concentration of the first P-type GaN layer 24 a is greater than the doping concentration of the second P-type GaN layer 24 b , so that the second P-type GaN layer 24 b is more easily depleted, thereby reducing the risk of electrical leakage of the semiconductor device 100 .

[0086] In some embodiments, Figure 3 to Figure 6 As shown, the semiconductor device 100 further includes: a source 21 and a drain 22 . The source 21 , the P-type GaN layer 24 and the drain 22 are sequentially arranged on a side of the barrier layer 15 away from the substrate 11 .

[0087] Exemplarily, the material of the source electrode 21 and the material of the drain electrode 22 are independently selected from at least one of Ti, Al, TiN, Si and Au.

[0088] In some embodiments, Figure 3 to Figure 6 As shown, the source electrode 21 forms an ohmic contact with the barrier layer 15 , and the drain electrode 22 forms an ohmic contact with the barrier layer 15 .

[0089] The contact resistance R between the source electrode 21 and the drain electrode 22 can be reduced by forming an ohmic contact between the source electrode 21 and the barrier layer 15 and the drain electrode 22 and the barrier layer 15. C Moreover, the contact resistance R can be further reduced by optimizing the composition and formation process of the ohmic metal of the source 21 and the drain 22. C , thereby reducing the on-resistance R of the semiconductor device 100 on .

[0090] In some embodiments, Figure 3 to Figure 6As shown, the resistance R of the drift region S2 can be reduced by reducing the sheet resistance of the AIGaN / GaN heterojunction. drift , thereby reducing the on-resistance R of the semiconductor device 100 on .

[0091] In some embodiments, Figure 7 As shown, the first gate metal layer 231 includes a plurality of gate sub-portions 23 a , and the plurality of gate sub-portions 23 a are arranged at intervals along a gate width direction X; wherein the gate width direction X is an extension direction of the second gate metal layer 232 .

[0092] By disposing a plurality of gate sub-portions 23a disposed at intervals, the contact area between the second gate metal layer 232 and the first gate metal layer 231 is made larger. In the case where the Schottky barrier between the second gate metal layer 232 and the P-type GaN layer 24 is greater than the Schottky barrier between the first gate metal layer 231 and the P-type GaN layer 24, when a voltage is applied to the gate metal layer 23, the depletion region formed by the second gate metal layer 232 is more likely to pinch off the leakage around the first gate metal layer 231, thereby further increasing the barrier effect of the second gate metal layer 232 on the leakage, so as to reduce the driving loss of the semiconductor device 100.

[0093] Illustratively, in an orthographic projection onto the substrate 11 , the gate sub-portion 23 a has at least one of a square and a circle.

[0094] The gate sub-portion 23a can be provided in different shapes to increase the contact area between the second gate metal layer 232 and the first gate metal layer 231 , thereby increasing the barrier effect of the second gate metal layer 232 on leakage and reducing the driving loss of the semiconductor device 100 .

[0095] In some embodiments, Figure 8 As shown, the first gate metal layer 231 includes a plurality of gate sub-portions 23 a , which are sequentially connected along the gate width direction X, and at least two of the plurality of gate sub-portions 23 a extend in different directions.

[0096] For example, Figure 8 As shown, the first gate metal layer 231 is arranged in a folded line.

[0097] Exemplarily, the first gate metal layer 231 is disposed in a curved shape.

[0098] The arrangement of multiple gate sub-portions 23a extending in different directions can achieve the purpose of increasing the contact area between the second gate metal layer 232 and the first gate metal layer 231, thereby increasing the barrier effect of the second gate metal layer 232 on leakage and reducing the driving loss of the semiconductor device 100.

[0099] In some examples, such as Figure 8 As shown, in the orthographic projection onto the substrate 11, the gate sub-portion 23a is rectangular, and the extension directions of every two connected gate sub-portions 23a intersect.

[0100] For example, Figure 8 As shown, the first gate metal layer 231 includes a plurality of long strip-shaped gate sub-portions 23 a , and each two adjacent gate sub-portions 23 a are vertically arranged. The plurality of gate sub-portions 23 a are sequentially connected end to end to form the first gate metal layer 231 .

[0101] By arranging the extension directions of each two connected gate sub-portions 23a to intersect, the contact area between the second gate metal layer 232 and the first gate metal layer 231 is increased, thereby increasing the barrier effect of the second gate metal layer 232 on leakage and reducing the driving loss of the semiconductor device 100.

[0102] In some implementations, such as Figure 8 As shown, the semiconductor device 100 further includes: a nucleation layer 12 and a buffer layer 13 , and the substrate 11 , the nucleation layer 12 , the buffer layer 13 and the channel layer 14 are arranged in sequence.

[0103] Exemplarily, the material of the nucleation layer 12 includes at least one of AlN, GaN and AlGaN.

[0104] Exemplarily, the material of the buffer layer 13 includes at least one of AlN, AlGaN and GaN.

[0105] Since the buffer layer 13 and the substrate 11 are made of different materials and usually have different lattice constants and thermal expansion coefficients, if the buffer layer 13 is directly disposed on the substrate 11, cracks may be generated in the buffer layer 13 due to lattice mismatch and thermal mismatch, resulting in a decrease in crystal quality. Therefore, the nucleation layer 12 is disposed to effectively avoid the generation of cracks in the buffer layer 13.

[0106] The present disclosure also provides a method for preparing a semiconductor device. Fig. 9 As shown, the method for preparing a semiconductor device includes steps: R1 to R4.

[0107] R1, such as Fig.10 As shown, a channel layer 14 , a barrier layer 15 , and a P-type GaN layer 24 are formed on one side of a substrate 11 .

[0108] Exemplarily, a nucleation layer 12 and a buffer layer 13 are further disposed between the substrate 11 and the channel layer 14 .

[0109] Exemplarily, the specific steps of sequentially forming the nucleation layer 12 , the buffer layer 13 , the channel layer 14 , the barrier layer 15 and the P-type GaN layer 24 on one side of the substrate 11 include: R11 and R12 .

[0110] R11 , epitaxially growing a nucleation layer 12 , a buffer layer 13 , a channel layer 14 , a barrier layer 15 and an initial P-type GaN layer 240 in sequence on one side of the substrate 11 .

[0111] Exemplarily, the material of the substrate 11 includes: at least one of Si, SiC, GaN, sapphire and diamond; the material of the nucleation layer 12 includes: at least one of AlIn, GaN and AIGaN; the material of the buffer layer 13 includes: at least one of AlIn, AIGaN and GaN; the material of the channel layer 14 includes: unintentionally doped GaN; the material of the barrier layer 15 includes: at least one of AlN and AlGaN; the material of the initial P-type GaN layer 24 includes: P-type GaN, for example, P-type GaN is GaN doped with at least one of Mg, Fe, Zn and C.

[0112] Exemplarily, the thickness of the initial P-type GaN layer 24 ranges from 30 nm to 100 nm. For example, the thickness of the initial P-type GaN layer 24 is 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, etc., which is not limited here.

[0113] R12, removing part of the initial P-type GaN layer 240 to form a P-type GaN layer 24.

[0114] Exemplarily, a portion of the initial P-type GaN layer 240 is removed by an etching process to form the P-type GaN layer 24 .

[0115] R2, such as Figure 10 to Figure 12 As shown, a passivation layer 16 is formed, and the passivation layer 16 includes a first passivation portion 161 , and the first passivation portion 161 exposes a portion 23 c of the P-type GaN layer 24 away from the substrate 11 .

[0116] In some examples, such as Fig.10 and Fig.11 As shown, the step of forming the passivation layer 16 includes: R21, R22 and R23.

[0117] R21, such as Fig.10 As shown, an initial passivation layer 160 is formed on a side of the P-type GaN layer 24 away from the substrate 11 .

[0118] Exemplarily, the material of the initial passivation layer 160 includes at least one of AlN, SiN and SiO.

[0119] Exemplarily, the thickness of the initial passivation layer 160 ranges from 5 nm to 80 nm. For example, the thickness of the initial passivation layer 160 is 5 nm, 10 nm, 15 nm, 20 nm, 30 nm, 50 nm, 60 nm or 80 nm, etc., which is not limited here.

[0120] Exemplarily, the initial passivation layer 160 is formed by a deposition process.

[0121] R22, such as Fig.10 As shown, a portion of the initial passivation layer 160 is removed to form openings H1 in the source region and the drain region.

[0122] The opening H1 in the source region is used to dispose the source 21 , and the opening H1 in the drain region is used to dispose the drain 22 .

[0123] Exemplarily, the source electrode 21 and the drain electrode 22 are formed by a deposition process.

[0124] R23, such as Fig.11 As shown, a portion of the initial passivation layer 160 is removed to form an opening H2 in the gate region.

[0125] Exemplarily, the passivation layer 16 further includes: a second passivation portion 162. The step of forming the passivation layer 16 further includes: forming the second passivation portion 162, the second passivation portion 162 covers the portion 24c of the P-type GaN layer 24 away from the substrate 11, and the second passivation portion 162 exposes the portion of the surface of the P-type GaN layer 24 away from the substrate 11.

[0126] For example, the opening H2 in the gate region exposes a portion of the P-type GaN layer 24 away from the surface of the substrate 11 , which is used to set the first gate metal layer 231 .

[0127] In the step of removing a portion of the initial passivation layer 160 to form the opening H2 in the gate region, the first passivation portion 161 and the second passivation portion 162 can be formed simultaneously, which facilitates the preparation of the passivation layer 16 .

[0128] In other examples, such as Fig.10 and Fig.12 As shown, the step of forming the passivation layer 16 includes: R21, R22 and R23'.

[0129] For the introduction of R21 and R22, please refer to the above content and will not be repeated here.

[0130] R23', such as Fig.12 As shown, a portion of the initial passivation layer 160 is removed to expose a portion 24 c of the P-type GaN layer 24 away from the substrate 11 .

[0131] R3, such as Fig.11 and Fig.12 As shown, a first gate metal layer 231 is formed on a side of the P-type GaN layer 24 away from the substrate 11 .

[0132] Exemplarily, the first gate metal layer 231 is formed by a deposition process.

[0133] R4, such as Figure 3 , Figure 5 , Fig.11 and Fig.12 As shown, a second gate metal layer 232 is formed on a side of the first gate metal layer 231 away from the substrate 11 , and the second gate metal layer 232 covers the first gate metal layer 231 and a portion 24 c of the P-type GaN layer 24 exposed by the first passivation portion 161 , thereby forming a semiconductor device 100 .

[0134] Exemplarily, the second gate metal layer 232 is formed by a deposition process.

[0135] The above steps R1 to R4 are used to prepare Figure 3 and Figure 5 In the semiconductor device 100 of the structure shown, the nucleation layer 12, the buffer layer 13, the channel layer 14, the barrier layer 15 and the initial P-type GaN layer 240 can be formed by an epitaxial growth method, and the second gate metal layer 232 is formed by a deposition process. There is no need to use an epitaxial growth method, which can reduce manufacturing costs.

[0136] Exemplarily, the semiconductor device 100 is applicable to enhancement-mode GaN power devices of various voltage levels to enhance gate control capability, and is also applicable to discrete devices or system integration.

[0137] like Fig.13 As shown, an embodiment of the present disclosure further provides an electronic device 1000, which includes the semiconductor device 100 provided in any of the above embodiments. The electronic device 1000 also includes a substrate 200, on which the semiconductor device 100 is disposed.

[0138] Exemplarily, the electronic device 1000 may be applied to, but not limited to, power supplies, photovoltaic systems, industrial motors, and electric vehicles.

[0139] like Fig.13 As shown, the electronic device 1000 includes the semiconductor device 100 provided in any of the above embodiments. Therefore, the electronic device 1000 provided in the embodiment of the present disclosure has all the beneficial effects of the semiconductor device 100 provided in any of the above embodiments, which will not be described in detail here.

[0140] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A channel layer, located on one side of the substrate; A barrier layer, located on a side of the channel layer away from the substrate; A P-type GaN layer, located on a side of the barrier layer away from the substrate; A first gate metal layer, located on a side of the P-type GaN layer away from the substrate; Among them, the semiconductor device also includes: a second gate metal layer, the second gate metal layer covers the first gate metal layer and the portion of the P-type GaN layer away from the substrate, and a first passivation portion is arranged between the second gate metal layer and the barrier layer; the first gate metal layer forms a Schottky contact with the P-type GaN layer, and the second gate metal layer forms a Schottky contact with the P-type GaN layer.

2. The semiconductor device according to claim 1, wherein: A Schottky barrier between the second gate metal layer and the P-type GaN layer is greater than a Schottky barrier between the first gate metal layer and the P-type GaN layer.

3. The semiconductor device according to claim 1, wherein: In an orthographic projection onto the substrate, the P-type GaN layer covers the first gate metal layer.

4. The semiconductor device according to claim 1, wherein: The P-type GaN layer includes: a first P-type GaN layer and a second P-type GaN layer, wherein the second P-type GaN layer is located on a side of the first P-type GaN layer away from the substrate; wherein the doping concentration of the second P-type GaN layer is less than the doping concentration of the first P-type GaN layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The first gate metal layer includes a plurality of gate sub-portions, and the plurality of gate sub-portions are arranged at intervals along a gate width direction; wherein the gate width direction is an extension direction of the second gate metal layer.

6. The semiconductor device according to claim 5, characterized in that In an orthographic projection onto the substrate, the gate sub-portion has at least one of a square and a circle.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that: The first gate metal layer includes a plurality of gate sub-portions, the plurality of gate sub-portions are sequentially connected and arranged along a gate width direction, and at least two of the plurality of gate sub-portions extend in different directions.

8. The semiconductor device according to claim 7, characterized in that In the orthographic projection onto the substrate, the gate sub-portions are rectangular, and the extension directions of two connected gate sub-portions intersect.

9. A method for preparing a semiconductor device, characterized in that: include: A channel layer, a barrier layer and a P-type GaN layer are sequentially formed on one side of the substrate; forming a passivation layer, the passivation layer comprising: a first passivation portion, the first passivation portion exposing a portion of the P-type GaN layer away from the substrate; forming a first gate metal layer on a side of the P-type GaN layer away from the substrate; A second gate metal layer is formed on a side of the first gate metal layer away from the substrate, the second gate metal layer covers the first gate metal layer and a portion of the P-type GaN layer exposed by the first passivation portion to form a semiconductor device; the first gate metal layer forms a Schottky contact with the P-type GaN layer, and the second gate metal layer forms a Schottky contact with the P-type GaN layer.

10. An electronic device, characterized in that: include: The semiconductor device according to any one of claims 1 to 8; A substrate, on which the semiconductor device is arranged.

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