SiC MOSFET with optimized forward and reverse conduction characteristics and manufacturing method thereof

Abstract

The present invention discloses a SiC MOSFET with optimized forward and reverse conduction characteristics and a manufacturing method thereof, comprising: a drain; a substrate; an epitaxial layer; a first gate groove; a second gate groove; a body groove; a first well region; a first source region, wherein the first well region and the first source region form a forward conductive channel C1; a second well region; a second source region, wherein the second well region and the second source region form a forward conductive channel C6; a third well region; a third source region, wherein the third well region and the third source region respectively form forward conductive channels C2 and C4 near the side walls of the first gate groove and the second gate groove; a fourth source region, wherein the third well region and the fourth source region respectively form reverse conductive channels C3 and C4 near the side walls of the body groove; a contact region; a first insulating layer; a second insulating layer; a third insulating layer; a first conductor; a second conductor; a third conductor; a first isolation medium; a second isolation medium; a source electrode. The present invention can improve the reverse conduction characteristics of the SiC MOSFET.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a SiC MOSFET with optimized forward and reverse conduction characteristics and a manufacturing method thereof. Background Art

[0002] The development of power electronic systems has put forward higher requirements on the performance of power semiconductor devices. At present, silicon-based power semiconductor devices occupy the main market share of power devices. However, due to the limitations of silicon material properties, the performance of silicon-based power devices has reached its theoretical limit.

[0003] As a representative of the third generation of semiconductor materials, silicon carbide (SiC) has advantages such as a larger bandgap, a higher critical breakdown electric field, and a higher thermal conductivity. Therefore, SiC power devices have obvious advantages in high power and high temperature fields. SiC MOSFET power devices with a planar gate structure have been commercialized, and their market share is also expanding.

[0004] The schematic diagram of the mainstream planar gate SiC MOSFET cell is as follows Figure 3 As shown, it includes drain 1, substrate 2, epitaxial layer 3, well region 4, source region 5, contact region 6, gate dielectric 9, gate 8, isolation dielectric 10 and source 11, and conductive channels C1 and C2 are formed on the surface of the epitaxial layer, and the gate is used to control the opening of the conductive channel. However, with the sharp increase in market demand, downstream manufacturers have higher and higher requirements for the performance of SiC MOSFET devices. There are several problems in the application field of planar gate SiC MOSFET power devices. First, the existing planar gate SiC MOSFET is limited by the cell size, and the channel density is difficult to further increase, resulting in the difficulty of further reducing the on-resistance of the device. Second, the conductive channels C1 and C2 of the existing planar gate SiC MOSFET are located on the surface of the epitaxial layer, so the channel is easily affected by the subsequent process, causing the problem of unstable threshold voltage. Third, when the existing SiC MOSFET device works in the third quadrant, it relies on the body diode to achieve freewheeling, which will inevitably cause bipolar degradation effect and damage the reverse recovery characteristics. Summary of the invention

[0005] Technical purpose: In view of the above-mentioned shortcomings of existing planar gate SiC MOSFET devices, the present invention discloses a SiC MOSFET with optimized forward and reverse conduction characteristics and a manufacturing method thereof, which can increase the channel density, reduce the on-resistance, and improve the reverse conduction characteristics of the SiC MOSFET while accurately controlling the threshold voltage.

[0006] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution:

[0007] A SiC MOSFET with optimized forward and reverse conduction characteristics, comprising:

[0008] Drain;

[0009] a substrate, located above the drain;

[0010] an epitaxial layer, located on the substrate;

[0011] A first gate groove is located in the epitaxial layer; a second gate groove is located in the epitaxial layer; a body groove is located in the epitaxial layer and between the first gate groove and the second gate groove, and the first gate groove and the second gate groove are symmetrically arranged with respect to the body groove;

[0012] A first well region is located on the side and bottom of the first gate groove away from the body groove; a first source region is located in the first well region and on the side and part of the bottom of the first gate groove away from the body groove, the width and depth of the first source region are smaller than the first well region, and the first well region and the first source region form a forward conductive channel C1 at the bottom of the first gate groove;

[0013] The second well region is located at the side and bottom of the second gate groove away from the body groove; the second source region is located in the second well region and at the side and part of the bottom of the second gate groove away from the body groove, the width and depth of the second source region are smaller than the second well region, and the second well region and the second source region form a forward conductive channel C6 at the bottom of the second gate groove;

[0014] A third well region is located between the first gate groove and the body groove, and between the body groove and the second gate groove, and the depth of the third well region is less than the depths of the first gate groove, the second gate groove and the body groove; a third source region is located on one side of the third well region close to the first gate groove and the second gate groove, and the depth of the third source region is less than the depth of the third well region, and the third well region and the third source region respectively form forward conductive channels C2 and C5 near the side walls of the first gate groove and the second gate groove; a fourth source region is located on one side of the third well region close to the body groove, and the depth of the fourth source region is less than the depth of the third well region, and the third well region and the fourth source region respectively form reverse conductive channels C3 and C4 near the two side walls of the body groove;

[0015] A contact region is located in the third well region and between the third source region and the fourth source region;

[0016] A first insulating layer is located on the sidewall and bottom of the first gate groove; a second insulating layer is located on the sidewall and bottom of the second gate groove; and a third insulating layer is located on the sidewall and bottom of the body groove;

[0017] The first conductor is located in the first gate groove; the second conductor is located in the second gate groove; the third conductor is located in the body groove;

[0018] A first isolation dielectric is located on the epitaxial layer and completely covers the first conductor; a second isolation dielectric is located on the epitaxial layer and completely covers the second conductor;

[0019] The source is located on the first isolation medium and the second isolation medium and surrounds the first isolation medium and the second isolation medium on three sides.

[0020] The present invention also provides a method for manufacturing a SiC MOSFET with optimized forward and reverse conduction characteristics, which is used to manufacture the above-mentioned SiC MOSFET with optimized forward and reverse conduction characteristics, and specifically comprises the following steps:

[0021] Step 1, forming an epitaxial layer on a substrate;

[0022] Step 2, forming a first well region and a second well region near the two side walls of the epitaxial layer; and forming a first source region and a second source region in the first well region and the second well region, respectively, wherein the depth and width of the first source region and the second source region are respectively smaller than the depth and width of the first well region and the second well region;

[0023] Step 3, forming a third well region in the epitaxial layer between the first well region and the second well region; forming a third source region in the third well region near the sidewalls of the first well region and the second well region, and forming a fourth source region in the remaining third well region; and forming contact regions in the first well region, the second well region and the third well region respectively;

[0024] Step 4, forming a first gate trench, a second gate trench and a body trench in the epitaxial layer, wherein the side of the first gate trench away from the body trench is surrounded by the first source region, the bottom of the first gate trench is respectively surrounded by the first source region and the first well region, the side of the second gate trench away from the body trench is surrounded by the second source region, the bottom of the second gate trench is respectively surrounded by the second source region and the second well region, and the body trench runs through the fourth source region and the third well region;

[0025] Step 5, forming a first insulating layer, a second insulating layer and a third insulating layer on the sidewalls and the bottom of the first gate trench, the second gate trench and the body trench respectively, and then forming a first conductor, a second conductor and a third conductor in the first gate trench, the second gate trench and the body trench respectively;

[0026] Step 6, forming a first isolation dielectric and a second isolation dielectric respectively on the epitaxial layer; the first isolation dielectric completely covers the first conductor, and one side of both sides of the first isolation dielectric is located on the first gate groove, and the other side is located on the third source region; the second isolation dielectric completely covers the second conductor, and one side of both sides of the second isolation dielectric is located on the second gate groove, and the other side is located on the third source region;

[0027] Step 7: grow source metal on the epitaxial layer to form a source ohmic contact, grow drain metal on the bottom layer of the substrate to form a drain ohmic contact, form a source on the surface of the source ohmic contact, and form a drain on the surface of the drain ohmic contact.

[0028] The present invention also provides a method for manufacturing a SiC MOSFET with optimized forward and reverse conduction characteristics, which is used to manufacture the above-mentioned SiC MOSFET with optimized forward and reverse conduction characteristics, and specifically comprises the following steps:

[0029] Step 1, forming an epitaxial layer on a substrate;

[0030] Step 2, forming a third well region in the epitaxial layer; forming a third source region in the third well region, and forming a fourth source region in the remaining third well region; and forming a contact region in the third well region and between the third source region and the fourth source region;

[0031] Step 3, forming a first gate trench, a second gate trench and a body trench in the epitaxial layer, wherein a side surface of the first gate trench close to a side of the second gate trench contacts the third source region, a side surface of the second gate trench close to a side of the first gate trench contacts the third source region, and the body trench runs through the fourth source region and the third well region;

[0032] Step 4, forming a first well region on the side and bottom of the first gate groove away from the body groove, and forming a second well region on the side and bottom of the second gate groove away from the body groove; forming a first source region and a second source region respectively in the first well region and the second well region, and the first source region and the second source region are respectively located on the side and a part of the bottom surface of the first gate groove away from the body groove and the side and a part of the bottom surface of the second gate groove away from the body groove, and the depth and width of the first source region and the second source region are respectively smaller than the depth and width of the first well region and the second well region; and forming contact regions in the first well region and the second well region respectively;

[0033] Step 5, forming a first insulating layer, a second insulating layer and a third insulating layer on the sidewalls and the bottom of the first gate trench, the second gate trench and the body trench, and then forming a first conductor, a second conductor and a third conductor in the first gate trench, the second gate trench and the body trench respectively;

[0034] Step 6, forming a first isolation dielectric and a second isolation dielectric respectively on the epitaxial layer; the first isolation dielectric completely covers the first conductor, and one side of both sides of the first isolation dielectric is located on the first gate groove, and the other side is located on the third source region; the second isolation dielectric completely covers the second conductor, and one side of both sides of the second isolation dielectric is located on the second gate groove, and the other side is located on the third source region;

[0035] Step 7: grow source metal on the epitaxial layer to form a source ohmic contact, grow drain metal on the bottom layer of the substrate to form a drain ohmic contact, form a source on the surface of the source ohmic contact, and form a drain on the surface of the drain ohmic contact.

[0036] Beneficial effects: The SiC MOSFET with optimized forward and reverse conduction characteristics and the manufacturing method thereof provided by the present invention have the following beneficial effects:

[0037] (1) The SiC MOSFET with optimized forward and reverse conduction characteristics proposed in the present invention forms a forward conductive channel C1 at the bottom of the first gate groove, forms a forward conductive channel C2 on the side wall of the first gate groove, forms a forward conductive channel C6 at the bottom of the second gate groove, and forms a forward conductive channel C5 on the side wall of the second gate groove. On the basis of the planar gate SiC MOSFET cell structure, longitudinal conductive channels C2 and C5 with high mobility are introduced, which greatly improves the channel density of the device and significantly reduces the channel resistance of the device. In addition, the lateral conductive channels C1 and C6 are transferred from the semiconductor surface to the device body, so that the channel area is not affected by subsequent processes, and the concentration of the channel area can be more accurately controlled by adjusting the concentration distribution of the well region, thereby improving the threshold voltage stability of the device.

[0038] (2) The SiC MOSFET with optimized forward and reverse conduction characteristics proposed in the present invention forms reverse conductive channels C3 and C4 on the side walls of the body trench. In the reverse conduction state, C3 and C4 are used to achieve freewheeling and avoid the body diode from turning on, thereby avoiding the bipolar degeneration effect, reducing the conduction loss, and significantly improving the third quadrant characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0040] Figure 1 This is a schematic diagram of the structure of a SiC MOSFET with optimized forward and reverse conduction characteristics according to Example 1 of the present invention;

[0041] Figure 2 This is a schematic diagram of the structure of a SiC MOSFET with optimized forward and reverse conduction characteristics according to Embodiment 2 of the present invention;

[0042] Figure 3 It is a schematic diagram of the structure of the existing planar gate SiC MOSFET;

[0043] Figure 4~Figure 9 Schematic diagram of the preparation process of SiC MOSFET with optimized forward and reverse conduction characteristics of Example 1.

[0044] Explanation of the accompanying drawings: 1. drain; 2. substrate; 3. epitaxial layer; 4. well region; 4-1. first well region; 4-2. second well region; 4-3. third well region; 5. source region; 5-1. first source region; 5-2. second source region; 5-3. third source region; 5-4. fourth source region; 6. contact region; 7-1. first gate groove; 7-2. second gate groove; 7-3. body groove; 8. gate; 8-1. first conductor; 8-2. second conductor; 8-3. third conductor; 9. gate dielectric; 9-1. first insulating layer; 9-2. second insulating layer; 9-3. third insulating layer; 10. isolation dielectric; 10-1. first isolation dielectric; 10-2. second isolation dielectric; 11. source; 12. current spreading layer. DETAILED DESCRIPTION

[0045] The present invention will be described more clearly and completely below by way of a preferred embodiment in conjunction with the accompanying drawings, but the present invention is not limited to the scope of the embodiment. Example

[0046] like Figure 1 As shown, a SiC MOSFET with optimized forward and reverse conduction characteristics includes:

[0047] Drain 1; substrate 2, located on drain 1 and the lower surface of substrate 2 is in contact with the upper surface of drain 1, substrate 2 is a 4H-SiC substrate, the depth of substrate 2 is 80µm ~ 300µm, and the doping concentration is 1e19cm -3 ~ 1e20cm -3 The epitaxial layer 3 is located on the substrate 2 and the lower surface of the epitaxial layer 3 is in contact with the upper surface of the substrate 2. The epitaxial layer 3 is a 4H-SiC epitaxial layer. The depth of the epitaxial layer 3 is 5µm ~ 50µm and the doping concentration is 5e15cm -3 ~ 1e17cm -3 ; The first gate groove 7-1 is located in the epitaxial layer 3, and the depth of the first gate groove 7-1 ranges from 0.5µm to 2.0µm; the second gate groove 7-2 is located in the epitaxial layer 3, and the depth of the second gate groove 7-2 ranges from 0.5µm to 2.0µm; the body groove 7-3 is located in the epitaxial layer 3, between the first gate groove 7-1 and the second gate groove 7-2, the distance between the body groove 7-3 and the first gate groove 7-1 and the second gate groove 7-2 is equal, the first gate groove 7-1 and the second gate groove 7-2 are symmetrically arranged about the body groove 7-3, and the depth of the body groove 7-3 ranges from 0.5µm to 2.0µm.

[0048] The first well region 4-1 surrounds the side of the first gate groove 7-1 away from the body groove 7-3, fully or partially surrounds the bottom surface of the first gate groove 7-1, and the upper surface of the first well region 4-1 is flush with the upper surface of the first gate groove 7-1. When the bottom surface of the first gate groove 7-1 is partially surrounded, the spacing between the first well region 4-1 and the side of the first gate groove 7-1 close to the body groove 7-3 is in the range of 0.01µm to 0.3µm, the spacing between the bottom surface of the first well region 4-1 and the bottom surface of the first gate groove 7-1 is in the range of 0.7µm to 5.0µm, and the doping concentration of the first well region 4-1 is in the range of 1e16cm -3 ~3e18cm -3 The first source region 5-1 is located in the first well region 4-1 and surrounds the side and part of the bottom of the first gate groove 7-1 away from the body groove 7-3. The width and depth of the first source region 5-1 are smaller than the first well region 4-1. The spacing between the boundary of the first source region 5-1 close to the body groove 7-3 and the boundary of the first well region 4-1 away from the side wall of the epitaxial layer 3 is in the range of 0.1µm to 0.5µm. The spacing between the bottom surface of the first source region 5-1 and the bottom surface of the first well region 4-1 is not less than 0.1µm. The upper surface of the first source region 5-1 is flush with the upper surface of the first well region 4-1. The doping concentration range of the first source region 5-1 is 1e19cm -3 ~3e20cm -3 The first well region 4-1 and the first source region 5-1 form a forward conductive channel C1 at the bottom of the first gate groove 7-1, and the position of the forward conductive channel C1 is close to the right side wall of the first gate groove 7-1.

[0049] The second well region 4-2 surrounds the side of the second gate groove 7-2 away from the body groove 7-3, fully or partially surrounds the bottom of the second gate groove 7-2, and partially surrounds the bottom of the second gate groove 7-2. The spacing between the second well region 4-2 and the side of the second gate groove 7-2 close to the body groove 7-3 is in the range of 0.01µm to 0.3µm, the upper surface of the second well region 4-2 is flush with the upper surface of the second gate groove 7-2, the spacing between the bottom of the second well region 4-2 and the bottom of the second gate groove 7-2 is in the range of 0.7µm to 5.0µm, and the doping concentration of the second well region 4-2 is in the range of 1e16cm -3 ~ 3e18cm -3 The second source region 5-2 is located in the second well region 4-2 and surrounds the side and part of the bottom of the second gate groove 7-2 away from the body groove 7-3. The width and depth of the second source region 5-2 are smaller than the second well region 4-2. The spacing between the boundary of the second source region 5-2 close to the body groove 7-3 and the boundary of the second well region 4-2 close to the body groove 7-3 ranges from 0.1µm to 0.5µm. The spacing between the bottom surface of the second source region 5-2 and the bottom surface of the second well region 4-2 is not less than 0.1µm. The doping concentration range of the second source region 5-2 is 1e19cm -3 ~ 3e20cm -3The second well region 4-2 and the second source region 5-2 form a forward conductive channel C6 at the bottom of the second gate groove 7-2, and the forward conductive channel C6 is close to the left side wall of the second gate groove 7-2.

[0050] The third well region 4-3 is located between the first gate groove 7-1 and the body groove 7-3, and between the body groove 7-3 and the second gate groove 7-2, and their side walls are in contact with each other. The upper surface of the third well region 4-3 is flush with the upper surfaces of the first gate groove 7-1, the second gate groove 7-2 and the body groove 7-3. The depth of the third well region 4-3 is less than the depth of the first gate groove 7-1, the second gate groove 7-2 and the body groove 7-3, and the difference is not less than 0.1µm. The depth range of the third well region 4-3 is 0.4µm ~ 1.6µm, and the doping concentration range is 1e16cm -3 ~3e18cm -3 The third source region 5-3 is located in the third well region 4-3 near the first gate groove 7-1 and the second gate groove 7-2, and the sidewalls of the third source region 5-3 are in contact with the right side wall of the first gate groove 7-1 and the left side wall of the second gate groove 7-2, respectively. The depth of the third source region 5-3 ranges from 0.2µm to 0.5µm, and the doping concentration ranges from 1e19cm -3 ~ 3e20cm -3 The depth of the third source region 5-3 is less than the depth of the third well region 4-3, and the difference between the depths of the two ranges from 0.1µm to 0.7µm. The third well region 4-3 and the third source region 5-3 respectively form forward conductive channels C2 and C4 near the side walls of the first gate groove 7-1 and the second gate groove 7-2, wherein the forward conductive channel C2 is located at the right side wall of the first gate groove 7-1, and the forward conductive channel C4 is located at the left side wall of the second gate groove 7-2; the fourth source region 5-4 is located in the third well region 4-3 on one side close to the body groove 7-3 and is in contact with the left side wall and the right side wall of the body groove 7-3 respectively, the depth of the fourth source region 5-4 ranges from 0.2µm to 0.5µm, and the doping concentration ranges from 1e19cm -3 ~ 3e20cm -3The depth of the fourth source region 5-4 is less than that of the third well region 4-3, and the difference between the depths thereof ranges from 0.1µm to 0.7µm. The third well region 4-3 and the fourth source region 5-4 respectively form reverse conductive channels C3 and C4 at the two side walls close to the body groove 7-3, and the reverse conductive channel C3 is located at the left side wall of the body groove 7-3, and the reverse conductive channel C4 is located at the right side wall of the body groove 7-3; the contact region 6 is respectively located in the first well region 4-1, the second well region 4-2 and the third well region 4-3, and the upper surface of the contact region 6 located in the first well region 4-1 is flush with the first well region 4-1, and the lower bottom surface is lower than the lower bottom surface of the first well region 4-1, and the two sides thereof are The sides are in contact with the side of the first well region 4-1 and the side of the first source region 5-1 respectively; the upper surface of the contact region 6 located in the second well region 4-2 is flush with the second well region 4-2, the lower bottom surface is lower than the lower bottom surface of the second well region 4-2, and its two sides are in contact with the side of the second well region 4-2 and the side of the second source region 5-2 respectively; the contact region 6 located in the third well region 4-3 is also between the third source region 5-3 and the fourth source region 5-4, and its two sides are in contact with the third source region 5-3 and the fourth source region 5-4 respectively, the depth range of the contact region 6 is 0.1µm ~ 0.5µm, and the doping concentration range is 1e19cm -3 ~ 3e20cm -3 , and the upper surfaces of the third source region 5-3, the fourth source region 5-4 and the contact region 6 are flush with the upper surface of the third well region 4-3, and the lower bottom surfaces of the third source region 5-3, the fourth source region 5-4 and the contact region 6 are higher than the lower bottom surface of the third well region 4-3.

[0051] The first insulating layer 9-1 is located on the sidewall and bottom of the first gate groove 7-1; the second insulating layer 9-2 is located on the sidewall and bottom of the second gate groove 7-2, the first insulating layer 9-1 and the second insulating layer 9-2 have the same thickness, and the thickness ranges from 30nm to 200nm; the third insulating layer 9-3 is located on the sidewall and bottom of the body groove 7-3, and the thickness of the third insulating layer 9-3 located on the sidewall of the body groove 7-3 is 5nm to 70nm, and the thickness of the third insulating layer 9-3 located on the bottom of the body groove 7-3 is 70nm to 500nm. The materials of the first insulating layer 9-1, the second insulating layer 9-2 and the third insulating layer 9-3 can be one or more dielectric materials such as silicon oxide, silicon nitride, borophosphosilicate glass, aluminum oxide, sapphire or hafnium oxide. The first conductor 8-1 is located in the first gate groove 7-1 and is surrounded on three sides by the first insulating layer 9-1; the second conductor 8-2 is located in the second gate groove 7-2 and is surrounded on three sides by the second insulating layer 9-2; the third conductor 8-3 is located in the body groove 7-3 and is surrounded on three sides by the third insulating layer 9-3; the upper surfaces of the first conductor 8-1, the second conductor 8-2 and the third conductor 8-3 are all flush with the upper surfaces of the first gate groove 7-1, the second gate groove 7-2 and the body groove 7-3.

[0052] The first isolation dielectric 10-1 is located on the epitaxial layer 3 and completely covers the first conductor 8-1, and the bottom surface of the first isolation dielectric 10-1 is in contact with the upper surface of the first conductor 8-1, and one side of the two sides of the first isolation dielectric 10-1 is located on the first gate groove 7-1, and the other side is located on the third source region 5-3; the second isolation dielectric 10-2 is located on the epitaxial layer 3 and completely covers the second conductor 8-2, and the bottom surface of the second isolation dielectric 10-2 is in contact with the upper surface of the second conductor 8-2, and one side of the two sides of the second isolation dielectric 10-2 is located on the second gate groove 7-2, and the other side is located on the third source region 5-3; the source 11 is located on the first isolation dielectric 10-1 and the second isolation dielectric 10-2 and surrounds the two on three sides.

[0053] The layout of the SiC MOSFET device of the present invention can be a strip, square, hexagon, dodecagon or atomic lattice shape, the semiconductor material used in the device can be 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC, the substrate, epitaxial layer and source region doping type are the first conductivity type, the well region and the contact region doping type are the second conductivity type, the first conductivity type is N type or P type, and the corresponding second conductivity type is P type or N type.

[0054] The present invention also discloses a method for manufacturing a SiC MOSFET with optimized forward and reverse conduction characteristics, which is used to manufacture the above-mentioned SiC MOSFET with optimized forward and reverse conduction characteristics, and specifically comprises the following steps:

[0055] Step 1: Figure 4 As shown, an epitaxial layer 3 is formed on the substrate 2, the depth of the epitaxial layer 3 is 5µm ~ 50µm, and the doping concentration is 5e15cm -3 ~ 1e17cm -3 .

[0056] Step 2: Figure 5 As shown, a first well region 4-1 and a second well region 4-2 are formed near the epitaxial layer 3 by an ion implantation process, wherein the first well region 4-1 is located on the left side of the epitaxial layer 3 and the second well region 4-2 is located on the right side of the epitaxial layer 3; and then a first source region 5-1 and a second source region 5-2 are formed respectively in the first well region 4-1 and the second well region 4-2 by an ion implantation process, wherein the depth and width of the first source region 5-1 and the second source region 5-2 are respectively smaller than the depth and width of the first well region 4-1 and the second well region 4-2 and the upper surfaces of the first source region 5-1 and the second source region 5-2 are respectively flush with the upper surfaces of the first well region 4-1 and the second well region 4-2.

[0057] Step 3: Figure 6As shown, a third well region 4-3 is formed in the epitaxial layer 3 and between the first well region 4-1 and the second well region 4-2 by an ion implantation process, and the upper surface of the third well region 4-3 is flush with the upper surfaces of the first well region 4-1 and the second well region 4-2; and a third source region 5-3 is formed in the third well region 4-3 near the first well region 4-1 and the second well region 4-2 by an ion implantation process, and the third source region 5-3 is in contact with the right side wall of the first well region 4-1 and the left side wall of the second well region 4-2, and the third well region 4-3 is in contact with the left side wall of the third well region 4-3. A fourth source region 5-4 is formed in the middle, and the upper surfaces of the third source region 5-3 and the fourth source region 5-4 are flush with the upper surface of the third well region 4-3; then, a contact region 6 is formed in the first well region 4-1, the second well region 4-2 and the third well region 4-3 by ion implantation, and the upper surfaces of the contact region 6 are flush with the upper surfaces of the first well region 4-1, the second well region 4-2 and the third well region 4-3. The contact region 6 located in the third well region 4-3 is between the third source region 5-3 and the fourth source region 5-4, and the upper surfaces of the three are flush.

[0058] Step 4: Figure 7 As shown, a first gate groove 7-1, a second gate groove 7-2 and a body groove 7-3 are formed in the epitaxial layer 3 by an etching process, and a reactive ion etching process or an inductively coupled plasma etching process can be used. The etching gas can be one or more of SF6, HBr, Cl2, O2, Ar and the like. The left side wall of the first gate groove 7-1 is surrounded by the first source region 5-1, and the right side wall of the first gate groove 7-1 is in contact with the side walls of the third well region 4-3 and the third source region 5-3. The bottom of the first gate groove 7-1 is respectively The second gate groove 7-2 is surrounded by the first source region 5-1 and the first well region 4-1, the right side wall of the second gate groove 7-2 is surrounded by the second source region 5-2, the left side wall of the second gate groove 7-2 is in contact with the side walls of the third well region 4-3 and the third source region 5-3, the bottom of the second gate groove 7-2 is surrounded by the second source region 5-2 and the second well region 4-2 respectively, and the body groove 7-3 runs through the fourth source region 5-4 and the third well region 4-3; the depths of the first gate groove 7-1, the second gate groove 7-2 and the body groove 7-3 are the same, and the depth range is 0.5µm The first gate groove 7-1 and the second gate groove 7-2 have the same width, ranging from 0.5µm to 2.5µm, the width of the body groove ranges from 0.5µm to 1.5µm, the sidewall angles of the first gate groove 7-1, the second gate groove 7-2 and the body groove 7-3 are not less than 80 degrees, and the spacing between adjacent grooves is 0.4µm to 2.0µm.

[0059] Step 5: Figure 8As shown, a first insulating layer 9-1, a second insulating layer 9-2 and a third insulating layer 9-3 are formed on the sidewalls and bottoms of the first gate groove 7-1, the second gate groove 7-2 and the body groove 7-3 by a low pressure chemical vapor deposition (LPCVD) process. The materials of the first insulating layer 9-1, the second insulating layer 9-2 and the third insulating layer 9-3 are SiO 2 The first insulating layer 9-1 and the second insulating layer 9-2 have the same thickness, ranging from 30nm to 200nm, the third insulating layer 9-3 located at the sidewall of the body groove 7-3 has a thickness ranging from 5nm to 70nm, and the third insulating layer 9-3 located at the bottom of the body groove 7-3 has a thickness ranging from 70nm to 500nm. The first insulating layer 9-1, the second insulating layer 9-2 and the third insulating layer 9-3 are subjected to high-temperature annealing treatment, and then the first conductor 8-1, the second conductor 8-2 and the third conductor 8-3 are formed in the first gate groove, the second gate groove and the body groove respectively by the LPCVD process. The first conductor 8-1, the second conductor 8-2 and the third conductor 8-3 are formed in the first gate groove, the second gate groove and the body groove respectively. The body 8-2 and the third conductor 8-3 are respectively surrounded on three sides by the first insulating layer 9-1, the second insulating layer 9-2 and the third insulating layer 9-3, and the upper surfaces of the first conductor 8-1, the second conductor 8-2 and the third conductor 8-3 are all flush with the upper surfaces of the first gate groove 7-1, the second gate groove 7-2 and the body groove 7-3. The material of the first conductor 8-1, the second conductor 8-2 and the third conductor 8-3 is polycrystalline silicon, and the first conductor 8-1, the second conductor 8-2 and the third conductor 8-3 are injected and activated annealed.

[0060] After the first conductor 8 - 1 , the second conductor 8 - 2 , and the third conductor 8 - 3 are formed in step 5 , a chemical-mechanical polishing (CMP) process is used to flatten the device surface.

[0061] Step 6: Fig. 9 As shown, a first isolation dielectric 10-1 and a second isolation dielectric 10-2 are respectively formed on the epitaxial layer 3 by the LPCVD process. The first isolation dielectric 10-1 and the second isolation dielectric 10-2 can be silicon dioxide or nitride or a composite of silicon dioxide and nitride; the first isolation dielectric 10-1 completely covers the first conductor 8-1, and one side of the two sides of the first isolation dielectric 10-1 is located on the first gate groove 7-1, and the other side is located on the third source region 5-3; the second isolation dielectric 10-2 completely covers the second conductor 8-2, and one side of the two sides of the second isolation dielectric 10-2 is located on the second gate groove 7-2, and the other side is located on the third source region 5-3. The materials of the first isolation dielectric 10-1 and the second isolation dielectric 10-2 are Si 3 N 4 .

[0062] Step 7: Fig. 9 As shown, a source metal is grown on the epitaxial layer 3 to form a source ohmic contact. The source metal can be one or more of metals such as Ti, Al, Ni, Au, Cu, etc. A drain metal is grown on the bottom layer of the substrate 2 to form a drain ohmic contact. The drain metal can be one or more of metals such as Ti, Ni, Ag, etc. A source 11 is formed on the surface of the source ohmic contact, and a drain 1 is formed on the surface of the drain ohmic contact.

[0063] The present invention also provides a method for manufacturing a SiC MOSFET with optimized forward and reverse conduction characteristics, which is used to manufacture the above-mentioned SiC MOSFET with optimized forward and reverse conduction characteristics, and specifically comprises the following steps:

[0064] Step 1, forming an epitaxial layer 3 on a substrate 2, wherein the upper surface of the substrate 2 is in contact with the lower bottom surface of the epitaxial layer 3;

[0065] Step 2, forming a third well region 4-3 in the epitaxial layer 3 by an ion implantation process; forming a third source region 5-3 in the third well region 4-3 and near both ends of the third well region 4-3 by an ion implantation process, and forming a fourth source region 5-4 in the remaining third well region 4-3 by an ion implantation process; forming a contact region 6 in the third well region 4-3 and between the third source region 5-3 and the fourth source region 5-4 by an ion implantation process, the fourth source region 5-4 is located in the middle of the third well region 4-3, the third source region 5-3 is located on the left and right sides of the third well region 4-3, the contact region 6 is located between the third source region 5-3 and the fourth source region 5-4, and its side surfaces are in contact with the third source region 5-3 and the fourth source region 5-4 respectively;

[0066] Step 3, forming a first gate groove 7-1, a second gate groove 7-2 and a body groove 7-3 in the epitaxial layer 3 by an etching process, wherein the side surface of the first gate groove 7-1 close to the second gate groove 7-2 is in contact with the third source region 5-3, and the side surface of the second gate groove 7-2 close to the first gate groove 7-1 is in contact with the third source region 5-3, the depth of the first gate groove 7-1 and the second gate groove 7-2 are both greater than the third well region 4-3, the body groove 7-3 runs through the fourth source region 5-4 and the third well region 4-3, and the upper surfaces of the first gate groove 7-1, the second gate groove 7-2 and the body groove 7-3 are flush with the upper surface of the third well region 4-3;

[0067] Step 4, forming a first well region 4-1 on the side and bottom of the first gate groove 7-1 away from the body groove 7-3, and forming a second well region 4-2 on the side and bottom of the second gate groove 7-2 away from the body groove 7-3 by an ion implantation process; then forming a first source region 5-1 and a second source region 5-2 in the first well region 4-1 and the second well region 4-2 respectively by an ion implantation process, and the first source region 5-1 and the second source region 5-2 are respectively located on the side and part of the bottom surface of the first gate groove 7-1 away from the body groove 7-3 and the side and part of the bottom surface of the second gate groove 7-2 away from the body groove 7-3, and the depth and width of the first source region 5-1 and the second source region 5-2 are respectively smaller than the depth and width of the first well region 4-1 and the second well region 4-2; then forming a contact region 6 in the first well region 4-1 and the second well region 4-2 by an ion implantation process, and the upper surface of the contact region 6 is flush with the upper surface of the first well region 4-1 and the second well region 4-2.

[0068] Step 5, forming a first insulating layer 9-1, a second insulating layer 9-2 and a third insulating layer 9-3 on the sidewalls and bottoms of the first gate trench 7-1, the second gate trench 7-2 and the body trench 7-3 by an LPCVD process, and then forming a first conductor 8-1, a second conductor 8-2 and a third conductor 8-3 in the first gate trench 7-1, the second gate trench 7-2 and the body trench 7-3 respectively;

[0069] Step 6: Form a first isolation dielectric 10-1 and a second isolation dielectric 10-2 on the epitaxial layer 3 by LPCVD process; the first isolation dielectric 10-1 completely covers the first conductor 8-1, and one side of the two sides of the first isolation dielectric 10-1 is located on the first gate groove 7-1, and the other side is located on the third source region 5-3; the second isolation dielectric 10-2 completely covers the second conductor 8-2, and one side of the two sides of the second isolation dielectric 10-2 is located on the second gate groove 7-2, and the other side is located on the third source region 5-3;

[0070] Step 7: grow source metal on the epitaxial layer 3 to form a source ohmic contact, grow drain metal on the bottom layer of the substrate 2 to form a drain ohmic contact, form a source 11 on the surface of the source ohmic contact, and form a drain 1 on the surface of the drain ohmic contact. Example

[0071] This embodiment provides a SiC MOSFET with optimized forward and reverse conduction characteristics, such as Figure 2As shown, the difference from Example 1 is that a current expansion layer 12 of the first conductivity type doped is formed between the first well region 4-1 and the second well region 4-2, and the bottom surface of the current expansion layer 12 may be flush with or not flush with the bottom surfaces of the first well region 4-1 and the second well region 4-2. If not flush, the lower bottom surface of the current expansion layer 12 may be located above or below the lower bottom surfaces of the first well region 4-1 and the second well region 4-2, and the spacing between the lower bottom surface of the current expansion layer 12 and the lower bottom surfaces of the first well region 4-1 and the second well region 4-2 is 0.1µm ~ 1.0µm, and the doping concentration range of the current expansion layer 12 is 1e16m -3 ~3e17cm -3 The introduction of the current spreading layer 12 can further reduce the on-resistance of the device.

[0072] The manufacturing steps of the SiC MOSFET with optimized forward and reverse conduction characteristics in this embodiment are as follows:

[0073] Step 1, forming an epitaxial layer 3 on a substrate 2, wherein the upper surface of the substrate 2 is in contact with the lower bottom surface of the epitaxial layer 3;

[0074] Step 2, forming a first well region 4-1 and a second well region 4-2 near the epitaxial layer 3 by an ion implantation process, wherein the first well region 4-1 is located on the left side of the epitaxial layer 3, and the second well region 4-2 is located on the right side of the epitaxial layer 3; and then forming a first source region 5-1 and a second source region 5-2 in the first well region 4-1 and the second well region 4-2 respectively by an ion implantation process;

[0075] Step 3, in the epitaxial layer 3, a current spreading layer 12 of the first conductivity type is formed between the first well region 4-1 and the second well region 4-2, and the bottom surface of the current spreading layer 12 is located above or below the bottom surfaces of the first well region 4-1 and the second well region 4-2;

[0076] Step 4: Form a third well region 4-3 between the first well region 4-1 and the second well region 4-2 in the epitaxial layer 3 by an ion implantation process, wherein the upper surface of the third well region 4-3 is flush with the upper surfaces of the first well region 4-1 and the second well region 4-2; and then form a third source region 5-3 in the third well region 4-3 near the first well region 4-1 and the second well region 4-2 by an ion implantation process, wherein the third source region 5-3 is in contact with the right side wall of the first well region 4-1 and the left side wall of the second well region 4-2, and the third well region 4-3 is in contact with the left side wall of the third well region 4-2. A fourth source region 5-4 is formed in the first well region 4-1, the upper surfaces of the third source region 5-3 and the fourth source region 5-4 are flush with the upper surface of the third well region 4-3; and then a contact region 6 is formed in the first well region 4-1, the second well region 4-2 and the third well region 4-3 by an ion implantation process, the upper surfaces of the contact region 6 are flush with the upper surfaces of the first well region 4-1, the second well region 4-2 and the third well region 4-3, and the contact region 6 located in the third well region 4-3 is located between the third source region 5-3 and the fourth source region 5-4, and the upper surfaces of the three are flush;

[0077] Step 5, forming a first gate groove 7-1, a second gate groove 7-2 and a body groove 7-3 in the epitaxial layer 3 by an etching process; the left side wall of the first gate groove 7-1 is surrounded by the first source region 5-1, the right side wall of the first gate groove 7-1 contacts the side walls of the third well region 4-3 and the third source region 5-3, the bottom of the first gate groove 7-1 is respectively surrounded by the first source region 5-1 and the first well region 4-1, the right side wall of the second gate groove 7-2 is surrounded by the second source region 5-2, the left side wall of the second gate groove 7-2 contacts the side walls of the third well region 4-3 and the third source region 5-3, the bottom of the second gate groove 7-2 is respectively surrounded by the second source region 5-2 and the second well region 4-2, and the body groove 7-3 runs through the fourth source region 5-4 and the third well region 4-3;

[0078] Step 6: Form a first insulating layer 9-1, a second insulating layer 9-2 and a third insulating layer 9-3 on the sidewalls and bottoms of the first gate trench 7-1, the second gate trench 7-2 and the body trench 7-3 by an LPCVD process, perform a high temperature annealing treatment on the first insulating layer 9-1, the second insulating layer 9-2 and the third insulating layer 9-3, and then form a first conductive body 8-1, a second conductive body 8-2 and a third conductive body 8-3 in the first gate trench, the second gate trench and the body trench by an LPCVD process. 3. The first conductor 8-1, the second conductor 8-2 and the third conductor 8-3 are respectively surrounded by the first insulating layer 9-1, the second insulating layer 9-2 and the third insulating layer 9-3 on three sides, and the upper surfaces of the first conductor 8-1, the second conductor 8-2 and the third conductor 8-3 are all flush with the upper surfaces of the first gate groove 7-1, the second gate groove 7-2 and the body groove 7-3, and the first conductor 8-1, the second conductor 8-2 and the third conductor 8-3 are implanted and activated by annealing;

[0079] Step 7, forming a first isolation dielectric 10-1 and a second isolation dielectric 10-2 on the epitaxial layer 3 by LPCVD process, respectively. The first isolation dielectric 10-1 and the second isolation dielectric 10-2 can be silicon dioxide or nitride or a composite of silicon dioxide and nitride; the first isolation dielectric 10-1 completely covers the first conductor 8-1, and one side of the two sides of the first isolation dielectric 10-1 is located on the first gate groove 7-1, and the other side is located on the third source region 5-3; the second isolation dielectric 10-2 completely covers the second conductor 8-2, and one side of the two sides of the second isolation dielectric 10-2 is located on the second gate groove 7-2, and the other side is located on the third source region 5-3;

[0080] Step 8: grow source metal on the epitaxial layer 3 to form a source ohmic contact, grow drain metal on the bottom layer of the substrate 2 to form a drain ohmic contact, form a source 11 on the surface of the source ohmic contact, and form a drain 1 on the surface of the drain ohmic contact.

[0081] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A SiC MOSFET with optimized forward and reverse conduction characteristics, characterized in that: include: Drain; a substrate, located above the drain; an epitaxial layer, located on the substrate; A first gate trench is located in the epitaxial layer; Second grid A groove, located in the epitaxial layer; A body groove is located in the epitaxial layer and between the first gate groove and the second gate groove, and the first gate groove and the second gate groove are symmetrically arranged with respect to the body groove; A first well region is located on the side and bottom of the first gate groove away from the body groove; a first source region is located in the first well region and on the side and part of the bottom of the first gate groove away from the body groove, the width and depth of the first source region are smaller than the first well region, and the first well region and the first source region form a forward conductive channel C1 at the bottom of the first gate groove; The second well region is located at the side and bottom of the second gate groove away from the body groove; the second source region is located in the second well region and at the side and part of the bottom of the second gate groove away from the body groove, the width and depth of the second source region are smaller than the second well region, and the second well region and the second source region form a forward conductive channel C6 at the bottom of the second gate groove; A third well region is located between the first gate groove and the body groove, and between the body groove and the second gate groove, and the depth of the third well region is less than the depths of the first gate groove, the second gate groove and the body groove; a third source region is located on one side of the third well region close to the first gate groove and the second gate groove, and the depth of the third source region is less than the depth of the third well region, and the third well region and the third source region respectively form forward conductive channels C2 and C5 near the side walls of the first gate groove and the second gate groove; a fourth source region is located on one side of the third well region close to the body groove, and the depth of the fourth source region is less than the depth of the third well region, and the third well region and the fourth source region respectively form reverse conductive channels C3 and C4 near the two side walls of the body groove; The contact regions are respectively located in the first well region, the second well region and the third well region; A first insulating layer, located on the sidewall and bottom of the first gate groove; A second insulating layer is located on the sidewall and bottom of the second gate groove; A third insulating layer, located on the sidewall and bottom of the body groove; A first conductor is located in the first gate groove; The second conductor is located in the second gate groove; the third conductor is located in the body groove; A first isolation dielectric is located on the epitaxial layer and completely covers the first conductor; A second isolation dielectric is located on the epitaxial layer and completely covers the second conductor; The source is located on the first isolation medium and the second isolation medium and surrounds the first isolation medium and the second isolation medium on three sides.

2. The SiC MOSFET with optimized forward and reverse conduction characteristics according to claim 1, characterized in that: It also includes a current expansion layer, which is located in the epitaxial layer and between the first well region and the second well region, and the current expansion layer is of the first conductivity type.

3. The SiC MOSFET with optimized forward and reverse conduction characteristics according to claim 1, characterized in that: The spacing between the first well region and the side surface of the first gate groove close to the body groove is in the range of 0µm to 0.3µm, and the spacing between the bottom surface of the first well region and the bottom surface of the first gate groove is in the range of 0.7µm to 5.0µm; the spacing between the side surface of the second well region and the second gate groove close to the body groove is in the range of 0µm to 0.3µm, and the spacing between the bottom surface of the second well region and the bottom surface of the second gate groove is in the range of 0.7µm to 5.0µm; the depth and doping concentration of the first well region and the second well region are the same, and the doping concentration range of both is 1e16cm -3 ~ 3e18cm -3 .

4. The SiC MOSFET with optimized forward and reverse conduction characteristics according to claim 1, characterized in that: The spacing between the side of the first source region close to the body groove and the side of the first well region close to the body groove is in the range of 0.1µm to 0.5µm, and the spacing between the bottom surface of the first source region and the bottom surface of the first well region is not less than 0.1µm; the spacing between the side of the second source region close to the body groove and the side of the second well region close to the body groove is in the range of 0.1µm to 0.5µm, and the spacing between the bottom surface of the second source region and the bottom surface of the second well region is not less than 0.1µm; the depth and doping concentration of the first source region and the second source region are the same, and the doping concentration range of both is 1e19cm -3 ~3e20cm -3 .

5. The SiC MOSFET with optimized forward and reverse conduction characteristics according to claim 1, characterized in that: The first gate groove, the second gate groove and the body groove have the same depth, and the depth range of the three is 0.5µm~2.0µm. The side wall angles of the first gate groove, the second gate groove and the body groove are not less than 80 degrees, and the spacing between adjacent gate grooves and body grooves ranges from 0.4µm to 2.0µm.

6. The SiC MOSFET with optimized forward and reverse conduction characteristics according to claim 1, characterized in that: The first gate grooves, the second gate grooves and the body grooves are distributed continuously or discontinuously in a direction perpendicular to the paper surface.

7. The SiC MOSFET with optimized forward and reverse conduction characteristics according to claim 1, characterized in that: The doping concentration range of the third well region is 1e16cm -3 ~3e18cm -3 The depth and doping concentration of the third source region and the fourth source region are the same, the depth range of the two is 0.2µm~0.5µm, and the doping concentration range is 1e19cm -3 ~3e20cm -3 ; The depth of the contact area ranges from 0.1µm to 0.5µm, and the doping concentration ranges from 1e19cm -3 ~3e20cm -3 The bottom surface of the third well region is lower than the bottom surfaces of the third source region and the fourth source region, and the difference between the bottom surface of the third well region and the bottom surface of the third source region or the fourth source region is in the range of 0.1µm to 0.7µm.

8. A method for manufacturing a SiC MOSFET with optimized forward and reverse conduction characteristics, used to manufacture a SiC MOSFET with optimized forward and reverse conduction characteristics as claimed in any one of claims 1 to 7, characterized in that: The specific steps include: Step 1, forming an epitaxial layer on a substrate; Step 2, forming a first well region and a second well region in the epitaxial layer; and forming a first source region and a second source region in the first well region and the second well region, respectively, wherein the depth and width of the first source region and the second source region are respectively smaller than the depth and width of the first well region and the second well region; Step 3, forming a third well region in the epitaxial layer between the first well region and the second well region; forming a third source region in the third well region near the sidewalls of the first well region and the second well region, and forming a fourth source region in the remaining third well region; and forming contact regions in the first well region, the second well region and the third well region respectively; Step 4, forming a first gate trench, a second gate trench and a body trench in the epitaxial layer, wherein the side of the first gate trench away from the body trench is surrounded by the first source region, the bottom of the first gate trench is respectively surrounded by the first source region and the first well region, the side of the second gate trench away from the body trench is surrounded by the second source region, the bottom of the second gate trench is respectively surrounded by the second source region and the second well region, and the body trench runs through the fourth source region and the third well region; Step 5, forming a first insulating layer, a second insulating layer and a third insulating layer on the sidewalls and the bottom of the first gate trench, the second gate trench and the body trench respectively, and then forming a first conductor, a second conductor and a third conductor in the first gate trench, the second gate trench and the body trench respectively; Step 6, forming a first isolation dielectric and a second isolation dielectric respectively on the epitaxial layer; the first isolation dielectric completely covers the first conductor, and one side of both sides of the first isolation dielectric is located on the first gate groove, and the other side is located on the third source region; the second isolation dielectric completely covers the second conductor, and one side of both sides of the second isolation dielectric is located on the second gate groove, and the other side is located on the third source region; Step 7: grow source metal on the epitaxial layer to form a source ohmic contact, grow drain metal on the bottom layer of the substrate to form a drain ohmic contact, form a source on the surface of the source ohmic contact, and form a drain on the surface of the drain ohmic contact.

9. A method for manufacturing a SiC MOSFET with optimized forward and reverse conduction characteristics, used to manufacture a SiC MOSFET with optimized forward and reverse conduction characteristics as claimed in any one of claims 1 to 7, characterized in that: The specific steps include: Step 1, forming an epitaxial layer on a substrate; Step 2, forming a third well region in the epitaxial layer; forming a third source region in the third well region, and forming a fourth source region in the remaining third well region; and forming a contact region in the third well region and between the third source region and the fourth source region; Step 3, forming a first gate trench, a second gate trench and a body trench in the epitaxial layer, wherein a side surface of the first gate trench close to a side of the second gate trench contacts the third source region, a side surface of the second gate trench close to a side of the first gate trench contacts the third source region, and the body trench runs through the fourth source region and the third well region; Step 4, forming a first well region on the side and bottom of the first gate groove away from the body groove, and forming a second well region on the side and bottom of the second gate groove away from the body groove; forming a first source region and a second source region respectively in the first well region and the second well region, and the first source region and the second source region are respectively located on the side and a part of the bottom surface of the first gate groove away from the body groove and the side and a part of the bottom surface of the second gate groove away from the body groove, and the depth and width of the first source region and the second source region are respectively smaller than the depth and width of the first well region and the second well region; and forming contact regions in the first well region and the second well region respectively; Step 5, forming a first insulating layer, a second insulating layer and a third insulating layer on the sidewalls and the bottom of the first gate trench, the second gate trench and the body trench, and then forming a first conductor, a second conductor and a third conductor in the first gate trench, the second gate trench and the body trench respectively; Step 6, forming a first isolation dielectric and a second isolation dielectric respectively on the epitaxial layer; the first isolation dielectric completely covers the first conductor, and one side of both sides of the first isolation dielectric is located on the first gate groove, and the other side is located on the third source region; the second isolation dielectric completely covers the second conductor, and one side of both sides of the second isolation dielectric is located on the second gate groove, and the other side is located on the third source region; Step 7: grow source metal on the epitaxial layer to form a source ohmic contact, grow drain metal on the bottom layer of the substrate to form a drain ohmic contact, form a source on the surface of the source ohmic contact, and form a drain on the surface of the drain ohmic contact.

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