LLC Resonant Converter and Control Method for Its DC Output Ripple

Abstract

The present invention provides an LLC resonant converter and a control method for its DC output ripple, which is applied to the technical field of switching power supply control. The method includes: judging the mode of the LLC resonant converter according to the actual output power value of the LLC resonant converter; in the hiccup intermittent mode, directly switching the switching frequency of the MOS transistor to the highest switching frequency, switching the Timer timing interruption period to the EPWM module underflow interruption period with a shorter interruption time for control, and judging the turn-on and turn-off of the MOS transistor according to the sampled output voltage sampling value and the preset voltage value in the EPWM module underflow interruption period. In the continuous mode, through the optimization processing of the AD sampling position and sampling data of the interleaved full-bridge LLC, it is ensured that the collected output voltage and output current are the most stable, which can further reduce the influence of the interference fluctuation caused by the LLC converter noise on the AD sampling, and reduce the ripple of the output caused by the AD sampling fluctuation. It can greatly reduce the DC output ripple of the LLC resonant converter under no-load and loaded conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supply control, and particularly relates to an LLC resonant converter and a control method for its DC output ripple. Background Art

[0002] With the large-scale construction of 5G base stations, higher requirements are put forward for the high efficiency and energy saving of switching power supplies. The LLC topology has the advantages of high efficiency and high power density. Compared with the traditional switching voltage topology, the LLC converter topology can achieve zero-voltage turn-on of the primary switching tube within the full load range, improve the power conversion efficiency, and reduce energy loss. Due to its excellent performance, it is increasingly used in switching power supply modules. However, when the LLC converter is operating at no load or light load, it will work in the hiccup intermittent mode, which will bring large voltage ripples. Since the LLC converter does not include an output inductor filter and only has output capacitor filtering, the output capacitor will generate high ripple voltage and ripple current. Moreover, due to the relatively high operating switching frequency of the LLC converter, its noise will cause interference fluctuations to the AD sampling, affecting the sampling accuracy. The AD sampling result, in turn, as a control quantity, will affect the output of the LLC converter, causing larger ripples. Currently, the common method is to parallel a relatively large number of capacitors with large capacitance on the load output side to reduce the output ripple. However, this will increase the volume and cost of the power supply, which is not conducive to the design of high-density and small-size power supplies. Summary of the Invention

[0003] In view of this, on the one hand, the present invention provides a control method for reducing the DC output ripple of an LLC resonant converter, including:

[0004] Collect the output voltage and output current of an LLC resonant converter including two interleaved full-bridge inverters, and calculate the actual output power value, wherein the phase difference between the MOS transistors at the same position of the two full-bridge inverters is 90 degrees;

[0005] Judge whether the LLC resonant converter enters the hiccup intermittent mode or the continuous mode according to the actual output power value;

[0006] When the LLC resonant converter enters the hiccup intermittent mode, directly switch the switching frequency of the MOS transistors of the LLC resonant converter to the highest switching frequency, switch the LLC resonant converter from the Timer periodic interrupt control to the EPWM module underflow interrupt period for control, and judge the turn-on and turn-off of the MOS transistors according to the sampled value of the output voltage of the LLC resonant converter collected in the EPWM module underflow interrupt period and the preset voltage value.

[0007] Optionally, collecting the output voltage and output current of an LLC resonant converter including two interleaved full-bridge inverters, and calculating the actual output power value, includes:

[0008] Collect the output voltage and output current of the LLC resonant converter during the underflow interruption of the EPWM module of the LLC resonant converter, and filter the collected output voltage and output current and calculate the actual output power value during the Timer timing interruption of the LLC resonant converter.

[0009] Optionally, during the underflow interruption period of the EPWM module, judge the turn-on and turn-off of the MOS transistor according to the sampled value of the output voltage of the LLC resonant converter collected and the preset voltage value, including:

[0010] If the sampled value of the output voltage is greater than the preset voltage value, use the EPWM1 module and the EPWM2 module to turn off the output PWM signal to turn off the MOS transistor;

[0011] If the sampled value of the output voltage is less than the preset voltage value, use the EPWM1 module and the EPWM2 module to turn on the output PWM signal to turn on the MOS transistor.

[0012] The present invention provides a control method for reducing the DC output ripple of an LLC resonant converter, further including:

[0013] When the LLC resonant converter enters the continuous mode, switch the LLC resonant converter to the Timer timing interruption period for control. The Timer timing interruption period is longer than the EPWM module underflow interruption period. During the Timer timing interruption period, use the EPWM1 module and the EPWM2 module to trigger the AD sampling module to collect the output voltage and output current of two interleaved full-bridge inverters in the LLC resonant converter respectively, and calculate the feedback value Ua for voltage loop control and the feedback value Ia for current loop control according to the output voltage and output current of the two interleaved full-bridge inverters;

[0014] Calculate respectively according to the feedback value Ua and the feedback value Ia to obtain a voltage error quantity Uerror and a current error quantity Ierror;

[0015] Perform PI calculations respectively according to the voltage error quantity Uerror and the current error quantity Ierror to obtain a voltage loop control quantity VCtrl and a current loop control quantity Ictrl;

[0016] Compare the voltage loop control quantity VCtrl and the current loop control quantity Ictrl, and take the smaller value as the control quantity of the LLC resonant converter frequency;

[0017] Convert the control quantity into the switching frequency of the LLC resonant converter, and use the EPWM1 module and the EPWM2 module to output PWM signals respectively according to the switching frequency to control the MOS transistor.

[0018] Optionally, when triggering the AD sampling module to collect the output voltage and output current of two interleaved full-bridge inverters in the LLC resonant converter by using the EPWM1 module and the EPWM2 module respectively during the Timer timing interruption period, the AD sampling module is triggered to collect the output voltage and output current of two interleaved full-bridge inverters in the LLC resonant converter according to the counters of the EPWM1 module and the EPWM2 module respectively, wherein the phase difference between the counters of the EPWM1 module and the EPWM2 module is 90 degrees, and the period values of the EPWM1 module and the EPWM2 module are the same.

[0019] Optionally, triggering the AD sampling module to collect the output voltage and output current of two interleaved full-bridge inverters in the LLC resonant converter according to the counters of the EPWM1 module and the EPWM2 module respectively includes:

[0020] When the counter of the EPWM1 module counts to the period value, triggering the AD sampling module to collect the first output voltage Ua1 and the first output current Ia1 of the first full-bridge inverter respectively;

[0021] When the counter of the EPWM2 module counts to the period value, triggering the AD sampling module to collect the second output voltage Ua2 and the second output current Ia2 of the second full-bridge inverter respectively.

[0022] Optionally, calculating the feedback value Ua for voltage loop control and the feedback value Ia for current loop control according to the output voltage and output current of two interleaved full-bridge inverters includes:

[0023] Adding and averaging the first output voltage Ua1 and the second output voltage Ua2 to obtain the feedback value Ua for voltage loop control;

[0024] Adding and averaging the first output current Ia1 and the second output current Ia2 to obtain the feedback value Ia for current loop control.

[0025] Optionally, calculating the voltage error quantity Uerror and the current error quantity Ierror respectively according to the feedback value Ua and the feedback value Ia includes:

[0026] Performing a difference calculation between the feedback value Ua and the reference voltage Uref to obtain the voltage error quantity Uerror;

[0027] Performing a difference calculation between the feedback value Ia and the reference current Iref to obtain the current error quantity Ierror.

[0028] On the other hand, the present invention provides an LLC resonant converter, comprising:

[0029] A first full-bridge inverter and a second full-bridge inverter, wherein the first full-bridge inverter and the second full-bridge inverter are interleaved and paralleled, and the phase difference between the MOS transistors at the same positions of the first full-bridge inverter and the second full-bridge inverter is 90 degrees;

[0030] A controller for executing the above control method for reducing the DC output ripple of the LLC resonant converter.

[0031] The present invention determines the operating mode of the LLC resonant converter to select corresponding operations to be performed in different interruption periods. In the hiccup intermittent mode, the switching frequency of the LLC resonant converter is relatively high, and the switching cycle time is relatively short. It is not enough time to directly perform complex PI operations in the switching cycle. If the converter operates directly at the highest switching frequency, complex PI operations are not required to obtain the switching frequency of the converter. Only in the EPWM module underflow interruption period, according to the magnitude relationship between the output voltage sampling value and the given value, the output PWM signal is turned on by using the EPWM1 module and the EPWM2 module to control the switching of the MOS transistor. The control cycle is short, which can ensure the stable and smooth output of the voltage and reduce the ripple; in the continuous mode, the control of the LLC converter switches to the Timer timing interruption period. Since the Timer timing interruption period is long, complex PI operation operations can be performed. In the Timer timing interruption period, the output voltage and output current of the two interleaved and paralleled full-bridge inverters in the LLC resonant converter are respectively collected by using the EPWM1 module and the EPWM2 module. The EPWM1 module and the EPWM2 module are respectively set to trigger the AD sampling at the midpoint of their respective counter cycle values, that is, the midpoint of the MOS transistor conduction, to ensure that the sampling frequency is the same as the PWM frequency, the phase is synchronized, and the collected is the average current in the PWM switching cycle, which is minimally affected by the switching of the MOS transistor. At the same time, the two full-bridges are interleaved and paralleled, and the PWM phases emitted by the EPWM1 module and the EPWM2 module of the MOS transistors at the same positions of the two full-bridges differ by 90°. After adding the voltage and current sampling values obtained by the AD triggered by the EPWM1 module and the voltage and current sampling values obtained by the AD triggered by the EPWM2 module and taking the average value, they are used as the control quantities of the continuous mode voltage loop or current loop. After taking the average value and comparing it with the given value, the control signal of the resonant converter is obtained through PI operation. In this way, through the optimization process of the AD sampling of the interleaved LLC resonant converter, the influence of the interference fluctuation caused by the LLC converter noise on the AD sampling can be further reduced, and the ripple caused by the AD sampling fluctuation can be reduced. Description of the Drawings

[0032] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0033] Figure 1 It is the topological block diagram of the LLC resonant converter in the embodiment of the present invention;

[0034] Figure 2 It is the PWM phase offset diagram at the same position of the two-phase interleaved full-bridge inverter in the embodiment of the present invention;

[0035] Figure 3 It is the current diagram of each branch of the two full-bridge interleaved and the current after eliminating the ripple after interleaving in the embodiment of the present invention;

[0036] Figure 4 It is the flow chart of the EPWM underflow interrupt and Timer timing interrupt handling tasks in the embodiment of the present invention;

[0037] Figure 5 It is the flow chart of the control method for reducing the DC output ripple of the LLC resonant converter in the embodiment of the present invention;

[0038] Figure 6 It is the comparison diagram of PWM outputs in the EPWM underflow interrupt period and Timer timing period when working in the hiccup intermittent mode in the embodiment of the present invention;

[0039] Figure 7 It is the diagram of controlling the output ripple in the hiccup intermittent mode in the Timer timing interrupt in the embodiment of the present invention;

[0040] Figure 8 It is the diagram of controlling the output ripple in the hiccup intermittent mode in the EPWM underflow interrupt in the embodiment of the present invention;

[0041] Figure 9 It is the sampling diagram of the interleaved LLC resonant converter triggered by the EPWM module in the embodiment of the present invention. Specific Embodiments

[0042] The following will clearly and completely describe the technical solutions of the present invention with reference to the drawings. Obviously, the described embodiments are some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0043] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0044] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0045] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0046] As Figure 1 shown, an LLC resonant converter is provided in an embodiment of the present invention, including: a controller and two interleaved and parallel parts, where

[0047] The first part includes: a first full-bridge inverter H1, a first resonant circuit 1, a first output rectifier circuit 2, and an output capacitor filtering module 3;

[0048] The first full-bridge inverter H1 is composed of MOS transistors Q1, Q2, Q3, and Q4. The first resonant circuit 1 is composed of an inductor Lr1, a capacitor Cr1, and a transformer T1. The first output rectifier circuit 2 is composed of diodes D1, D2, D3, and D4. The output capacitor filtering module 3 is composed of an output capacitor Co.

[0049] The second part includes: a second full-bridge inverter H2, a second resonant circuit 4, and a second output rectifier circuit 5;

[0050] The second full-bridge inverter H2 is composed of MOS transistors Q5, Q6, Q7, and Q8. The second resonant circuit 4 is composed of an inductor Lr2, a capacitor Cr2, and a transformer T2. The second output rectifier circuit 5 is composed of diodes D5, D6, D7, and D8.

[0051] As Figure 2 shown, the phase difference between MOS transistor Q1 and MOS transistor Q5 is set to 90 degrees, the phase difference between MOS transistor Q2 and MOS transistor Q6 is 90 degrees, the phase difference between MOS transistor Q3 and MOS transistor Q7 is 90 degrees, and the phase difference between MOS transistor Q4 and MOS transistor Q8 is 90 degrees. As Figure 3 is the waveform diagram of the two-phase interleaved output diode current after sampling processing and the total diode current after interleaved convergence. a is the current of the output diodes (D1-D4) of the first full-bridge inverter H1, b is the current of the output diodes (D5-D8) of the second full-bridge inverter H2, and c is the total diode current after interleaved convergence. It can be seen that the ripple is much smaller after interleaving. Therefore, the output voltage ripples of the MOS transistors at the same position in the first full-bridge inverter H1 and the second full-bridge inverter H2 can be out-of-phase canceled, thereby reducing the output ripple. Moreover, the full-bridge interleaved parallel structure is adopted to expand the power capacity, improve the power density, and utilize the interleaved characteristics to reduce the ripples of the output voltage and current.

[0052] The embodiment of the present invention provides a control method for reducing the DC output ripple of an LLC resonant converter, which is executed by a controller. Since the LLC resonant converter is frequency-variable control, there are differences in control compared with the digital power supply of fixed-frequency control. In the control method program, a typical main loop program + interrupt service program structure is adopted. The interrupt service uses two interrupts, namely the EPWM underflow interrupt and the Timer timing interrupt. These two interrupts perform different functions respectively. As Figure 4 shown, the EPWM underflow interrupt time is short and only simple programs can be executed. Specifically: first, clear the interrupt flag bit to ensure that the next interrupt can be correctly detected and responded to. Then, set the permission to respond to the same group of interrupts to ensure that other interrupts in the same group can continue to be responded to after processing the current interrupt. Next, perform AD voltage sampling, and judge the on and off of the MOS transistor in the hiccup intermittent mode according to the voltage sampling to adjust the control strategy. Finally, return from the interrupt service program to the main program; the Timer timing interrupt time is long and more complex programs can be executed. Specifically: first, clear the interrupt flag bit, then set the permission to respond to the same group of interrupts, then perform AD sampling and data processing, judge the hiccup intermittent mode or continuous mode according to the data, and finally perform voltage loop PI calculation and current loop PI calculation according to the judgment result. Finally, return from the interrupt service program to the main program.

[0053] The controller includes an EPWM1 module and an EPWM2 module. Among them, the phase difference between the counters of the EPWM1 module and the EPWM2 module is 90 degrees, the period values of the EPWM1 module and the EPWM2 module are the same. The EPWM1 module can output a PWM signal to control the MOS transistor switch in the first full-bridge inverter H1, and the EPWM2 module can output a PWM signal to control the MOS transistor switch in the second full-bridge inverter H2. The phases of the EPWM1 module and the EPWM2 module are the same as those of the corresponding MOS transistors.

[0054] The control method executed by the controller is as Figure 5 shown and includes:

[0055] S11, collect the output voltage and output current of the LLC resonant converter including two interleaved full-bridge inverters, and calculate the actual output power value. Collect the total output voltage and total output current of the first full-bridge inverter H1 and the second full-bridge inverter H2, and calculate the actual output power value.

[0056] S12, judge whether the LLC resonant converter enters the hiccup intermittent mode according to the actual output power value. If the actual output power is lower than the set threshold, it is determined that the LLC resonant converter is in a light load or no-load state and enters the hiccup intermittent mode to control the output voltage. If the actual output power is higher than the set threshold, it is determined that the LLC resonant converter maintains the continuous mode to maintain output stability and responsiveness.

[0057] S13, if the LLC resonant converter enters the hiccup intermittent mode, directly switch the switching frequency of the MOS transistor of the LLC resonant converter to the highest switching frequency, which does not need to be obtained by PI calculation. Switch the LLC resonant converter from the Timer timing interrupt cycle control to the EPWM module underflow interrupt cycle with a shorter interrupt time for control (executed once per PWM switching cycle). In the EPWM module underflow interrupt cycle, judge the turn-on and turn-off of the MOS transistor according to the sampled value of the output voltage of the LLC resonant converter collected and the preset voltage value.

[0058] When the LLC resonant converter enters the hiccup intermittent mode, the change of the output voltage is not continuous, but there is intermittent switching timing, which will cause ripples in the voltage waveform. If hiccup intermittent control is performed in the Timer timing interrupt, since the Timer timing interrupt time is too long relative to the PWM cycle time of the highest switching frequency, after comparing the sampled value of the output voltage and the reference value in each Timer timing interrupt and issuing a turn-on or turn-off command to the MOS transistor, dozens of pulses with the highest switching frequency may be issued, or there may be a pulse output after being turned off for dozens of microseconds. The effect is as Figure 6The waveform d shown in... ----- Timer timing interrupt periodic intermittent control of PWM. In the hiccup intermittent mode, the hiccup intermittent control is carried out in the EPWM1 underflow interrupt. Since the highest switching frequency is during the hiccup interval, the EPWM1 underflow interrupt time is very short. After comparing the sampled output voltage value with the reference value during the underflow interrupt time and issuing an on or off command to the MOS transistor, only a few pulses are emitted, and the interval time between the hiccup pulses is even shorter, making the controlled output voltage smoother with smaller ripple. The effect is as shown in Figure 6 the waveform c shown in... EPWM underflow interrupt periodic intermittent control of PWM. From Figure 6 it can be seen that the EPWM underflow interrupt time can meet the operation requirements of the hiccup intermittent mode. Therefore, it is necessary to wait until the EPWM1 module and the EPWM2 module are in the EPWM underflow interrupt cycle, that is, after the end of the PWM signal output cycle, and then perform the relevant operations as shown in Figure 4 ... to collect the sampled output voltage value of the LLC resonant converter and the preset voltage value, and compare the sampled output voltage value with the preset voltage value to determine whether to use the EPWM1 module and the EPWM2 module to turn on the output PWM signal to control the switching of the MOS transistor. In the hiccup intermittent mode, when controlling the switching operations of the MOS transistors in the two full-bridge inverters, only a few pulses are emitted, and the control time is short, which can ensure a stable and smooth output of the voltage and reduce the ripple.

[0059] Furthermore, if the LLC resonant converter does not enter the hiccup intermittent mode, that is, when it is in the continuous mode, step S14 is executed.

[0060] S14: Switch the LLC resonant converter to be controlled in the Timer timing interrupt cycle. The Timer timing interrupt cycle time is greater than the EPWM module underflow interrupt cycle time. In the Timer timing interrupt cycle, use the EPWM1 module and the EPWM2 module to trigger the AD sampling module to collect the output voltage and output current of the two interleaved full-bridge inverters in the LLC resonant converter, and calculate the feedback value Ua for voltage loop control and the feedback value Ia for current loop control based on the output voltage and output current of the two interleaved full-bridge inverters.

[0061] When the LLC resonant converter is in the continuous mode, to ensure a relatively stable output voltage of the LLC, it is necessary to perform PI operations on the collected voltage and current values respectively to obtain the output control of the converter. Since the EPWM module underflow interrupt time is short, the complex PI operations of the LLC resonant converter cannot be completed within the EPWM underflow interrupt cycle. Therefore, it needs to be processed in the Timer timing interrupt cycle. The controller will perform the relevant operations as shown in Figure 4 ... specifically, the operations of steps S14 - S18.

[0062] S15. Calculate respectively according to the feedback value Ua and the feedback value Ia to obtain a voltage error quantity Uerror and a current error quantity Ierror.

[0063] S16. Perform PI calculations respectively according to the voltage error quantity Uerror and the current error quantity Ierror to obtain a voltage loop control quantity VCtrl and a current loop control quantity Ictrl.

[0064] S17. Compare the voltage loop control quantity VCtrl and the current loop control quantity Ictrl, and take the smaller value as the control quantity of the LLC resonant converter frequency.

[0065] S18. Convert the control quantity into the switching frequency of the LLC resonant converter, and use the EPWM1 module and the EPWM2 module to output PWM signals respectively according to the switching frequency to control the MOS transistors.

[0066] In this embodiment, by judging the working mode of the LLC resonant converter to select corresponding operations to be executed in different interruption periods. In the hiccup intermittent mode, only in the EPWM underflow interruption period, according to the magnitude relationship between the output voltage sampling value and the given value, use the EPWM1 module and the EPWM2 module to turn on the output PWM signal to control the switching of the MOS transistors. There are few pulses and short control time, which can ensure the stable and smooth output of the voltage and reduce the ripple.

[0067] In the continuous mode, set the EPWM1 module and the EPWM2 module to trigger AD sampling respectively at their respective counter cycle values, that is, the midpoint of the MOS transistor conduction. This is the middle position of the PWM wave and is least affected by the MOS transistor switching. The average voltage and average current in the PWM switching period are collected, ensuring that the collected output voltage and output current are the most stable. At the same time, the sampling frequency is the same as the PWM frequency and the phases are synchronized. Moreover, the two full bridges are interleaved and paralleled. The PWM phases emitted by the EPWM1 module and the EPWM2 module of the MOS transistors at the same position of the two full bridges differ by 90°. After adding the voltage and current sampling values obtained by the AD triggered by the EPWM1 module and the voltage and current sampling values obtained by the AD triggered by the EPWM2 module respectively and taking the average value, it is used as the control quantity of the continuous mode voltage loop or current loop. Compare the average value with the given value, and obtain the resonant converter control signal through PI operation. In this way, through the optimization process of the AD sampling of the interleaved LLC converter, the influence of the interference fluctuation caused by the LLC converter noise on the AD sampling can be further reduced, and the ripple caused by the AD sampling fluctuation can be reduced.

[0068] In one embodiment, step S11 specifically includes:

[0069] Collect the output voltage and output current of the LLC resonant converter during the underflow interruption of the EPWM module of the LLC resonant converter, and filter the collected output voltage and output current and calculate the actual output power value during the Timer timing interruption of the LLC resonant converter.

[0070] Since the AD module sampling is triggered at the EPWM module counting cycle value, which is the middle position of the PWM wave and is least affected by the MOS transistor switching, the collected output voltage and output current are the most stable, ensuring the accuracy of the data. At the same time, the instantaneous fluctuations or noises during sampling may cause the data to contain noises. Therefore, it is necessary to filter the collected output voltage and output current during the Timer timing interruption with a long time to improve the data accuracy. Moreover, since the Timer timing interruption period is long, operations such as filtering and calculation can be performed. Therefore, the relevant operations of the Timer timing interruption in Figure 4 can be executed, that is, the calculation of the actual output power value and the judgment process in step S12 are both carried out during the Timer timing interruption period. After judging the real-time working mode of the LLC resonant converter in step S12, the interruption period can be switched according to the working mode to perform corresponding operations to improve the efficiency.

[0071] In step S13, the switching frequency of the MOS transistor of the LLC resonant converter is adjusted to the maximum, and the output control of the LLC resonant converter is switched from the Timer timing interruption to the EPWM underflow interruption. This is because in the hiccup intermittent mode, to ensure the smooth output of the output voltage, the MOS transistor needs to be intermittently switched at a higher frequency. If the control of the converter is still carried out in the Timer timing interruption during the intermittent mode, since the Timer timing interruption period is dozens or hundreds of EPWM underflow periods, if the intermittent control is carried out in the Timer timing interruption, the control period is long, resulting in the output voltage not being able to be smoothly output and having a large ripple. Therefore, when entering the intermittent mode, the control of the converter switches from the Timer timing interruption period to the EPWM underflow period, and at the same time, the switching frequency of the MOS transistor of the LLC resonant converter is adjusted to the maximum switching frequency. There is no need to obtain the switching frequency of the converter through the load PI operation. Operating at the maximum switching frequency also solves the problem that the EPWM underflow period is too short to perform the load PI operation. The output voltage controlled by the EPWM underflow interruption period in the hiccup intermittent mode will be smoother and have less ripple due to the shorter control period. As Figure 7 is the output voltage ripple of the hiccup intermittent control during the Timer timing interruption period with a long time under light load or no load, Figure 8 is the output voltage ripple of the hiccup intermittent control during the EPWM maximum switching frequency underflow interruption period with a short time under light load or no load. It can be seen from the comparison of the two figures that the output ripple controlled by the EPWM underflow interruption period has decreased significantly.

[0072] In one embodiment, step S13 specifically includes:

[0073] If the output voltage sampling value is greater than the preset voltage value, the EPWM1 module and the EPWM2 module are used to turn off the output PWM signal to turn off the MOS transistor;

[0074] If the output voltage sampling value is less than the preset voltage value, the EPWM1 module and the EPWM2 module are used to turn on the output PWM signal to turn on the MOS transistor.

[0075] Specifically, in the EPWM underflow interrupt period, if the output voltage sampling value is greater than the reference voltage value Vref + 0.005V, the PWM signal output of the LLC converter is turned off. When the output voltage sampling value is less than the reference voltage value Vref - 0.005V, the PWM signal output of the LLC converter is turned on. When operating in the hiccup intermittent mode, the switching of the LLC converter MOS transistor is controlled by switching from the Timer timing interrupt period to the EPWM underflow interrupt period with a higher interrupt frequency, shortening the on and off time intervals of controlling the MOS transistor.

[0076] In one embodiment, in step S14, in the Timer timing interrupt period, the EPWM1 module and the EPWM2 module are used to trigger AD sampling at the counter cycle value respectively to collect the output voltage and output current of two interleaved full-bridge inverters in the LLC resonant converter.

[0077] Furthermore, it is set that the EPWM1 module and the EPWM2 module trigger AD sampling at their respective counter cycle values, that is, the midpoint when the MOS transistor is turned on. The collected are the average voltage and average current in the PWM switching period, ensuring that the collected output voltage and output current are the most stable. At the same time, the sampling frequency is the same as the PWM frequency and the phases are synchronized, including:

[0078] When the counter of the EPWM1 module counts to the cycle value, the AD sampling module is triggered to collect the first output voltage Ua1 and the first output current Ia1 of the first full-bridge inverter respectively;

[0079] When the counter of the EPWM2 module counts to the cycle value, the AD sampling module is triggered to collect the second output voltage Ua2 and the second output current Ia2 of the second full-bridge inverter respectively.

[0080] Since the LLC resonant converter operates at a variable frequency, it is particularly important to ensure that the sampling frequency is synchronized with the PWM switching frequency. When the sampling frequency is different from the PWM switching frequency, the sampled voltage and current will contain a large amount of ripple components, affecting the control effect. When the sampling frequency is the same as the PWM switching frequency but the phases are not synchronized, the sampled voltage and current will contain low-frequency distortion components. Therefore, in the solution of the present invention, the EPWM module is used to trigger the AD sampling to ensure that the sampling frequency is the same as the PWM switching frequency and the phases are synchronized. At the same time, the AD sampling is triggered at the position of the counter period value of the EPWM module, so that the sampling will be performed at the midpoint of the MOS tube turn-on. At this time, the sampled voltage and current are the average voltage and average current of the PWM switching period, as Figure 9 shown. e is the position where the EPWM1 module triggers the AD sampling, f is the carrier wave of the EPWM1 module, g is the PWM wave of the first full-bridge inverter H1, h is the position where the EPWM2 module triggers the AD sampling, i is the carrier wave of the EPWM2 module, and j is the PWM wave of the second full-bridge inverter H2.

[0081] Specifically, when the counter of the EPWM1 module counts to the period value, it will trigger the acquisition of the first output voltage Ua1 and the first output current Ia1 of all MOS tubes in the first full-bridge inverter H1; when the counter of the EPWM2 module counts to the period value, it will trigger the acquisition of the second output voltage Ua2 and the second output current Ia2 of all MOS tubes in the second full-bridge inverter H2. When collecting the output current and output voltage of the MOS tube in the Timer timing interrupt period, triggering the sampling position at the point where the counter of the EPWM module counts to the period value, that is, the midpoint of the MOS tube turn-on, can ensure that the data acquisition frequency is the same as the PWM signal frequency and the phases are synchronized.

[0082] Further, in step S14, calculating the feedback value Ua for voltage loop control and the feedback value Ia for current loop control according to the output voltage and output current of the two interleaved full-bridge inverters includes:

[0083] Adding the first output voltage Ua1 and the second output voltage Ua2 and taking the average to obtain the feedback value Ua for voltage loop control;

[0084] Adding the first output current Ia1 and the second output current Ia2 and taking the average to obtain the feedback value Ia for current loop control.

[0085] Sampling is performed at the midpoint of the MOS transistor turn-on, which is minimally affected by the MOS transistor switching. The sampled values are the average voltage and average current within the PWM switching period, ensuring the most stable sampled output voltage and output current. The sampled voltages and currents triggered by the EPWM1 module and the EPWM2 module are averaged. Specifically: Ua = (Ua1 + Ua2) / 2, Ia = (Ia1 + Ia2) / 2. By summing and averaging the sampled values at two moments, sampling noise can be offset to a certain extent, enabling more accurate and stable output voltage and current values for calculating the actual output power or performing other control operations.

[0086] In one embodiment, step S15 specifically includes:

[0087] Perform a differential calculation on the feedback value Ua and the reference voltage Uref to obtain the voltage error amount Uerror;

[0088] Perform a differential calculation on the feedback value Ia and the reference current Iref to obtain the current error amount Ierror.

[0089] Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0090] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0091] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means implement the functions in Figure 1 one process or multiple processes and / or blocksFigure 1 The functions specified in one or more boxes.

[0092] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the steps of the functions specified in one Figure 1 process or more processes and / or boxes Figure 1 or more boxes.

[0093] Obviously, the above embodiments are merely examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of the present invention.

Claims

1. A control method for reducing the DC output ripple of an LLC resonant converter, characterized in that: include: The output voltage and output current of the LLC resonant converter including two staggered parallel full-bridge inverters are collected, and the actual output power value is calculated, wherein the phase difference between the MOS tubes at the same position of the two full-bridge inverters is 90 degrees; Determining whether the LLC resonant converter enters a hiccup intermittent mode or a continuous mode according to the actual output power value; When the LLC resonant converter enters the hiccup intermittent mode, the switching frequency of the MOS tube of the LLC resonant converter is directly switched to the highest switching frequency, and the LLC resonant converter is switched from the timer interrupt cycle control to the EPWM module underflow interrupt cycle control. In the EPWM module underflow interrupt cycle, the MOS tube is turned on and off according to the collected LLC resonant converter output voltage sampling value and the preset voltage value. Among them, judging whether to turn on or off the MOS tube according to the collected output voltage sampling value of the LLC resonant converter and the preset voltage value in the underflow interruption cycle of the EPWM module includes: If the output voltage sampling value is greater than the preset voltage value, the EPWM1 ​​module and the EPWM2 module are used to turn off the output PWM signal to turn off the MOS tube; If the output voltage sampling value is less than the preset voltage value, the EPWM1 ​​module and the EPWM2 module are used to start the output PWM signal to turn on the MOS tube; When the LLC resonant converter enters the continuous mode, the LLC resonant converter is switched to the Timer timing interrupt cycle for control, the Timer timing interrupt cycle time is greater than the EPWM module underflow interrupt cycle time, and the EPWM1 ​​module and the EPWM2 module are used to trigger the AD sampling module to collect the output voltage and output current of the two staggered parallel full-bridge inverters in the LLC resonant converter, and the feedback value Ua for voltage loop control and the feedback value Ia for current loop control are calculated according to the output voltage and output current of the two staggered parallel full-bridge inverters; Calculate the voltage error Uerror and the current error Ierror respectively according to the feedback value Ua and the feedback value Ia; Perform PI calculations according to the voltage error Uerror and the current error Ierror to obtain a voltage loop control value VCtrl and a current loop control value Ictrl; Compare the voltage loop control quantity VCtrl and the current loop control quantity Ictrl, and take the smaller value as the control quantity of the LLC resonant converter frequency; The control amount is converted into the switching frequency of the LLC resonant converter, and the EPWM1 ​​module and the EPWM2 module are used to output PWM signals according to the switching frequency to control the MOS tube.

2. The control method according to claim 1, characterized in that: Collect the output voltage and output current of the LLC resonant converter consisting of two interleaved full-bridge inverters in parallel, and calculate the actual output power value, including: The output voltage and output current of the LLC resonant converter are collected when the EPWM module of the LLC resonant converter underflows and when the Timer of the LLC resonant converter is interrupted, the collected output voltage and output current are filtered and the actual output power value is calculated.

3. The control method according to claim 1, characterized in that: When the EPWM1 ​​module and the EPWM2 module are used to respectively trigger the AD sampling module to collect the output voltage and output current of the two staggered parallel full-bridge inverters in the LLC resonant converter in the Timer timing interrupt cycle, the AD sampling module is triggered respectively according to the counters of the EPWM1 ​​module and the EPWM2 module to collect the output voltage and output current of the two staggered parallel full-bridge inverters in the LLC resonant converter, wherein the phase difference between the counters of the EPWM1 ​​module and the EPWM2 module is 90 degrees, and the period values ​​of the EPWM1 ​​module and the EPWM2 module are the same.

4. The control method according to claim 3, characterized in that: According to the counters of the EPWM1 ​​module and the EPWM2 module, the AD sampling modules are respectively triggered to collect the output voltage and output current of two staggered parallel full-bridge inverters in the LLC resonant converter, including: When the counter of the EPWM1 ​​module counts to the period value, the AD sampling module is triggered to respectively collect the first output voltage Ua1 and the first output current Ia1 of the first full-bridge inverter; When the counter of the EPWM2 module counts to the period value, the AD sampling module is triggered to respectively collect the second output voltage Ua2 and the second output current Ia2 of the second full-bridge inverter.

5. The control method according to claim 4, characterized in that: The feedback value Ua for voltage loop control and the feedback value Ia for current loop control are calculated based on the output voltage and output current of two staggered parallel full-bridge inverters, including: The first output voltage Ua1 and the second output voltage Ua2 are summed and averaged to obtain a feedback value Ua for voltage loop control; The first output current Ia1 and the second output current Ia2 are summed and averaged to obtain a feedback value Ia for current loop control.

6. The control method according to claim 1, characterized in that: The voltage error Uerror and the current error Ierror are obtained by respectively calculating according to the feedback value Ua and the feedback value Ia, including: Calculate the difference between the feedback value Ua and the reference voltage Uref to obtain a voltage error Uerror; The feedback value Ia and the reference current Iref are differentially calculated to obtain a current error value Ierror.

7. An LLC resonant converter, characterized in that: include: A first full-bridge inverter and a second full-bridge inverter, wherein the first full-bridge inverter and the second full-bridge inverter are staggered in parallel, and a phase difference between MOS tubes at the same position of the first full-bridge inverter and the second full-bridge inverter is 90 degrees; A controller, used to execute the control method for reducing the DC output ripple of an LLC resonant converter according to any one of claims 1-6.

Images