A biomedical analog front-end circuit with built-in low-frequency chopping

Abstract

The present invention belongs to the field of biological signal acquisition technology, specifically a biomedical analog front-end circuit with embedded low-frequency chopping. The biomedical analog front-end circuit of the present invention adopts a direct ADC architecture, and its main body is a two-stage single-loop Δ-ΣADC, and also includes a quantizer, a digital weighted averaging module and a resistive digital-to-analog converter; in the two-stage single-loop Δ-ΣADC, the two-stage integrator adopts Gm-C and Gm-OTA-C architectures respectively, and the second-stage multiplexing transconductance amplifier realizes the signal feedforward of the first-stage output; the quantizer adopts a 4-bit successive approximation quantizer; finally, the output digital signal passes through the digital weighted averaging module and enters the resistive digital-to-analog converter. While eliminating low-frequency flicker noise, the present invention also eliminates the influence of chopping on the input impedance of the acquisition system, so that the circuit can simultaneously achieve extremely high input impedance and extremely low noise.

Description

Technical Field

[0001] The present invention belongs to the technical field of biological signal acquisition, and in particular relates to a biomedical analog front-end circuit with built-in low-frequency chopping. Background Art

[0002] In recent years, wearable biomedical signal (ECG, EEG, EMG) acquisition systems have attracted increasing attention due to their portability and high energy efficiency. They can acquire human activities such as heart rate, EEG, and muscle movement. The size of biomedical signals is usually in the range of μV to tens of mV, but the system is usually subject to some interference, such as motion artifacts, flicker noise, electrode offset, and common-mode interference. Therefore, the biomedical analog front end needs to have very low noise (<100nV / √Hz) to acquire very small physiological signals. At the same time, a large input range (>300mV PP ) to prevent electrode misalignment and motion artifacts from interfering with the system.

[0003] Wearable biosignal acquisition systems often use dry electrodes for signal acquisition. Compared to wet electrodes, dry electrodes increase user comfort and long-term measurement stability. However, dry electrodes have a greater electrode-tissue interface impedance, and the acquisition system must have an input impedance significantly exceeding this impedance (>1GΩ@50Hz) to prevent signal attenuation and maintain a high total mode rejection ratio.

[0004] There are three common biomedical signal acquisition systems: Figure 1 ). The first solution uses a high-gain amplifier plus a medium-precision analog-to-digital converter (ADC) for signal acquisition [1]. This solution can achieve ultra-high input impedance and noise performance. However, due to the high gain, the input range is small, and the system will tend to saturate under large motion artifacts [1]. The second solution uses a low-gain amplifier and a high-resolution ADC [2] for signal acquisition. This system can achieve ultra-high input impedance and good noise performance, and also has a large input range, but the amplifier and high-precision ADC will consume a lot of power, making the entire system energy-efficient. The third solution is a direct ADC, in which the biomedical signal is directly sampled by a high-precision ADC [3-5]. The continuous Δ-Σ ADC based on transconductance input is directly connected to the dry electrode for signal acquisition due to its high input impedance and high energy efficiency. This solution has a large input range and high energy efficiency. After adding chopping technology, the in-band noise is low, but the input impedance will be attenuated. If chopping technology is not added, the in-band noise is high due to flicker noise, but the input impedance is very high.

[0005] However, in the second and third solutions, flicker noise is still a problem that limits the accuracy of the system. To reduce flicker noise, the length of the amplifier input transistor can be selected to be 12μm or 24μm to increase the area of ​​the transistor, but the noise density achieved is still large [3]. Chopping is another method to remove flicker noise [2][4][5]. However, in traditional continuous delta-sigma ADCs, the chopping frequency must be a multiple of half the sampling frequency, which severely attenuates the input impedance [6]. Although auxiliary buffers [2][4] and positive feedback loops (PFL) [5] can restore the attenuated impedance, the former comes at the cost of higher power consumption, noise, and area, while the latter requires manual calibration, which is impractical and unreliable.

[0006] In existing architectures, detecting signals at the μV level requires reducing overall system noise. In biosignal acquisition systems, low-frequency flicker noise accounts for a significant proportion. One approach to reducing low-frequency noise is to simply increase transistor size. However, the downside is that extremely large transistors are required to suppress noise to the μV level, which increases the transistor's parasitic capacitance, reduces overall energy efficiency, and lowers input impedance. Furthermore, this approach has limited effectiveness.

[0007] Another common technique for addressing flicker noise is chopping. Chopping shifts low-frequency flicker noise to the chopping frequency, allowing it to be removed by low-pass filtering in the subsequent stage. However, in traditional continuous-time delta-sigma ADCs, the chopping frequency must be a multiple of half the sampling frequency. Because chopping periodically charges and discharges the subsequent capacitors, this charge and discharge current acts as an impedance, reducing the system's input impedance. Furthermore, this charge and discharge current increases with increasing chopping frequency. Since delta-sigma ADCs are oversampling ADCs with high sampling frequencies, achieving an input impedance significantly exceeding the electrode-tissue contact impedance after chopping is implemented is difficult. Currently proposed solutions include using auxiliary buffers or positive feedback loops to assist in the charging and discharging of the post-chopping capacitors, thereby restoring the attenuated impedance. However, as mentioned above, these techniques come with a trade-off. Even if some impedance recovery is achieved, the input impedance is typically in the tens to hundreds of megohms, rarely reaching gigaohms. Summary of the Invention

[0008] The present invention aims to provide a biomedical analog front-end circuit with built-in low-frequency chopping to overcome the chopping frequency limitations of existing continuous delta-sigma ADCs, thereby achieving an ultra-high input impedance of GΩ (@50Hz) while removing flicker noise.

[0009] The biomedical analog front-end circuit with built-in low-frequency chopping provided by the present invention adopts a direct ADC architecture. Figure 2, its main body is a two-stage single-loop Δ-Σ ADC, which also includes a quantizer, a digital weighted averaging (DWA) module and a resistive digital-to-analog converter (RDAC); in the two-stage single-loop Δ-Σ ADC, the first-stage integrator adopts the Gm-C architecture, the second-stage integrator adopts the Gm-OTA-C architecture, and the second-stage multiplexing transconductance amplifier (OTA) is used to realize the signal feedforward of the first-stage output; the quantizer in the ADC adopts a 4-bit successive approximation register (SAR) quantizer; finally, the output digital signal enters the resistive digital-to-analog converter (RDAC) through the digital weighted averaging (DWA) module; the feedforward coefficients of the first-stage and second-stage integrator outputs are a1 and a2, the gain coefficient of the input signal is b1, and the feedback coefficient of the RDAC is c1; the s-domain transfer function of the integrator is f s / s, fs is the sampling frequency; the coefficients of Δ-Σ ADC can be specifically taken as: a1=0.6, a2=0.4, b1=5.12, b2=1.48;

[0010] The specific timing of ADC is shown in Figure 3 , a 4-bit successive approximation register (SAR) quantizer samples in the first phase (Ф1), converts in the second phase (Ф2), and outputs the conversion result within 1 / 4 cycle.

[0011] In the biomedical analog front-end circuit of the present invention, the first stage adopts the Gm-C integration stage, see Figure 4 As shown; its main body is a telescopic amplifier composed of transistors M1-M8, wherein the source terminals of transistors M1 and M2 are connected through resistors R I connected to form a source degeneration link, which converts the input signal linearly into a current signal and INT,1 In addition, the positive terminals of the two identical amplifiers [A(s)] are connected to the input signal, the negative terminals are connected to the sources of transistors M1 and M2 respectively, and the outputs are connected to the gates of transistors M1 and M2 respectively, to achieve gain bootstrapping and further improve linearity. The RDAC (which can be composed of 15 buffers and 15 unit resistors) of the ADC feedback is connected to the sources of transistors M1 and M2. The feedback signal is sent from the resistive digital-to-analog converter (RDAC) through transistors M1 and M2 to the capacitor C INT,1 The input signal enters the amplifier [A(s)] and the transistors M1 and M2 and enters C INT,1 Since the integration is performed over , there are two paths. Therefore, built-in choppers are added to the input and output of amplifier [A(s)]. Since this does not affect the feedback path, the chopper frequency can be selected to be low. This eliminates flicker noise while reducing the impact on input impedance. Furthermore, since the input chopping of amplifier [A(s)] occurs between the input signal and the sources of transistors M1 and M2, it is a pseudo-static chopping method, further reducing the impact on input impedance.

[0012] In addition, to further reduce flicker noise, the same low-frequency chopper is added to the drains of transistors M5 / M6 and M7 / M8 in the Gm-C integrator. Furthermore, to prevent direct chopping at the source of M1 / M2, cascode transistors M3 / M4 are added to isolate the input transistors M1 / M2 and bias transistors M5 / M6, and to facilitate chopping of the drains of M5 / M6. In this design, the impedance introduced by chopping is:

[0013]

[0014] Among them, f C is the chopping frequency, C GG is the input parasitic capacitance of the amplifier [A(s)]. Compared with the traditional chopping technology, this technology can improve the input impedance by K*A(s), where K is 2*f S / f C , where f S is the sampling frequency, and A(s) is the gain of the gain bootstrap circuit.

[0015] Therefore, the biomedical analog front-end circuit proposed in the present invention eliminates low-frequency flicker noise while also eliminating the impact of chopping on the input impedance of the acquisition system, so that the circuit can simultaneously achieve extremely high input impedance and extremely low noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The system architecture of existing biomedical signal acquisition system.

[0017] Figure 2 This is a diagram of the architecture of the continuous delta-sigma ADC proposed in the present invention.

[0018] Figure 3 This is a timing diagram of the continuous Δ-Σ ADC proposed in the present invention.

[0019] Figure 4 G in the continuous delta-sigma ADC of the present invention m -C input stage structure.

[0020] Figure 5 This is the gain bootstrap operational amplifier structure in the first-stage Gm-C integrator in the embodiment.

[0021] Figure 6 The noise floor spectra obtained by system testing with and without embedded chopping in the embodiment. DETAILED DESCRIPTION

[0022] The present invention is further described below through embodiments in conjunction with the accompanying drawings.

[0023] Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0024] The biomedical analog front-end circuit proposed in this invention is based on TSMC 180nm process and is designed with a 500Hz bandwidth, 256kHz sampling frequency, and 16-bit continuous delta-sigma ADC chip. Figure 2 As shown in Figure 1, it has a two-stage structure. The first-stage integrator is a Gm-C integrator, and the second-stage integrator is a Gm-OTA-C structure. The quantizer is implemented using a 4-bit SAR ADC.

[0025] The first stage Gm-C integrator structure of this embodiment and Figure 3 The specific gain bootstrap op amp in the Gm-C integrator is shown in Figure 5 As shown in the figure, a folded cascode structure with differential input and single-ended output is used, and embedded low-frequency chopping is inserted at its input and output. In addition, to further reduce flicker noise, the amplifier with a folded cascode structure with PMOS input (M9 / M10) performs chopping between the input signals. In order to restore the chopped signal, chopping is also added to the drain of the NMOS. This amplifier has a differential input and single-ended output structure. Figure 5 The PMOS transistor on the right side of the circuit implements differential-to-single-ended conversion. To further reduce flicker noise, chopping is also added to the PMOS transistor on the right side of the circuit.

[0026] In traditional biomedical analog front-end circuits, due to the influence of chopping, the input impedance will be attenuated to:

[0027]

[0028] In the present invention, since the restriction on the chopping frequency is broken, the chopping frequency is selected to be 2kHz, which is 64 times lower than 128kHz (256kHz / 2). And thanks to the embedded chopping, the chopping is pseudo-static, and its impact on the input impedance can be seen in the formula in the previous part. In summary, this embodiment improves the input impedance by 64*A(s). After testing the chip of this embodiment, the input impedance obtained at 50Hz was 4.7GΩ. It can be seen that, as analyzed, the biomedical analog front-end circuit of the present invention eliminates the impact of chopping on the input impedance, and finally the input impedance of the system is limited by the parasitic capacitance outside the chip. After using a small pad and removing the copper plating under the pad, an input impedance of more than 4GΩ (@50Hz) is achieved.

[0029] also, Figure 6This is the noise floor spectrum obtained by system testing with and without the embedded chopping technology added to this embodiment. It can be seen that within a bandwidth of 500Hz, after the embedded chopping technology is added, the noise floor (red line) is flatter, and the noise size at each frequency point is similar, that is, the noise is dominated by thermal noise. Without the embedded chopping technology, the flicker noise in the 10Hz band is more than 10 times the thermal noise. From the perspective of integral noise, after the embedded chopping technology is added, the noise voltage in the 500Hz bandwidth is reduced by about 2.3 times. Finally, the embodiment achieves a noise floor of 58nV / √Hz and an in-band integral noise of 1.3μV (500Hz bandwidth), which has reached the international leading level. In addition, at 335mV PP Under signal input, this embodiment achieves a peak signal-to-noise and distortion ratio (SNDR) of 94.9 dB, which is the highest value achieved in related art articles.

[0030] References:

[0031] [1] N.Van Helleputte et al., "A 345μW Multi-Sensor Biomedical SoC WithBio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP," IEEE J.Solid-State Circuits, vol.50, no.1, pp.230-244, Jan.2015.

[0032] [2]H.Chandrakumar and D.Markovic, “A 15.2-ENOB Continuous-TimeΔΣADC for a 7.3μW 200mV PP -Linear-Input-Range Neural Recording Front-End,” ISSCCDigest.Tech.Papers, pp.232-234, Feb.2018.

[0033] [3] C.Lee, T.Jeon, M.Jang, S.Park, Y.Huh and Y.Chae, "26.6A 6.5μW 10kHz-BW80.4dB-SNDR Continuous-TimeΔΣModulator with Gm-Input and 300mV PPLinearInputRange for Closed-Loop Neural Recording,”ISSCC Digest.Tech.Papers,pp.410-412,Feb.2020.

[0034] [4]C.Pochet,J.Huang,P.P.Mercier and D.A.Hall,“28.4A 400mVpp 92.3dB-SNDR 1kHz-BW 2nd-Order VCO-Based ExG-to-Digital Front-End Using aMultiphaseGated-Inverted Ring-Oscillator Quantizer,”ISSCC Digest.Tech.Papers,pp.392-394,Feb.2021.

[0035] [5]S.Lee et al.,“A 0.7V 17fJ / Step-FOMW 178.1dB-FOMSNDR 10kHz-BW560mVPP True-ExG Biopotential Acquisition System with Parasitic-Insensitive421MΩInputImpedance in 0.18μm CMOS,”ISSCC Digest.Tech.Papers,pp.336-338,Feb.2022.

[0036] [6]S.Billa,A.Sukumaran and S.Pavan,“Analysis and Design ofContinuous-TimeDelta–Sigma Converters Incorporating Chopping,”IEEE J.Solid-StateCircuits,vol.52,no.9,pp.2350-2361,Sept.2017。

Claims

1. A biomedical analog front-end circuit with built-in low-frequency chopper, characterized in that: The direct ADC architecture is adopted, and its main body is a two-stage single-loop Δ-Σ ADC, which includes a quantizer, a digital weighted average module and a resistive digital-to-analog converter. In the two-stage single-loop Δ-Σ ADC, the first-stage integrator adopts the Gm-C architecture. The main body of the Gm-C architecture is a telescopic amplifier composed of transistors M1-M8. The source terminals of transistors M1 and M2 are connected through resistors R I connected to form a source degeneration link, which converts the input signal linearly into a current signal and INT,1 The positive terminals of the first and second amplifiers are connected to the differential input signal, the negative terminals of the first and second amplifiers are connected to the sources of transistors M1 and M2 respectively, and the outputs of the first and second amplifiers are connected to the gates of transistors M1 and M2 respectively to achieve gain bootstrapping; the feedback signal is fed from the resistive digital-to-analog converter through transistors M1 and M2 into the capacitor C INT,1 The input signal enters the first amplifier, the second amplifier and the transistors M1 and M2 and enters C INT,1 Integration is performed on two paths; built-in choppers are added to the input and output of the first and second amplifiers, and the chopping frequency of the chopper is low frequency. While eliminating flicker noise, the impact on input impedance is reduced; the input chopping of the first and second amplifiers is performed between the input signal and the source of transistors M1 and M2, forming pseudo-static chopping, which reduces the impact on input impedance; In the Gm-C architecture, the same low-frequency chopper is added to the drains of transistors M5 / M6 and M7 / M8 to reduce flicker noise. To prevent direct chopping at the source of M1 / M2, cascode transistors M3 / M4 are added to isolate the input transistors M1 / M2 and bias transistors M5 / M6, and chop the drains of M5 / M6. The second-stage integrator adopts a Gm-OTA-C architecture and employs a multiplexed transconductance amplifier to implement signal feedforward for the first-stage output. The quantizer in the two-stage single-loop delta-sigma ADC uses a 4-bit successive approximation quantizer. Finally, the output digital signal passes through a digital weighted averaging module and enters a resistive digital-to-analog converter.

2. The biomedical analog front-end circuit with built-in low-frequency chopper according to claim 1, characterized in that: The feedforward coefficients of the first and second stage integrator outputs are a1 and a2, the gain coefficient of the input signal is b1, and the feedback coefficient of the RDAC is c1; the s-domain transfer function of the integrator is f s / s, fs is the sampling frequency.

3. The biomedical analog front-end circuit with built-in low-frequency chopper according to claim 1, characterized in that: The gain-boosted operational amplifier in the Gm-C architecture adopts a folded common-source common-gate structure with differential input and single-ended output, and has embedded low-frequency choppers inserted at its input and output.

4. The biomedical analog front-end circuit with built-in low-frequency chopper according to claim 1, characterized in that: The specific coefficient values ​​of the Δ-Σ ADC are: a1=0.6, a2=0.4, b1 =5.12, b2=1.48.

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