A low-noise high-precision ADC reference buffer circuit

Abstract

The application belongs to the technical field of data conversion, and particularly relates to a low-noise high-precision ADC reference buffer circuit. The main circuit of the application is a PMOS LDO, which comprises: a multi-stage small-gain cascaded error amplifier, a super source follower serving as an intermediate-stage buffer, feedback resistors R1 and R2, and an off-chip capacitor C L To meet the requirement of driving capability, an off-chip capacitor is adopted, and the overall topology is a multi-stage small-gain cascaded structure to meet the stability of the buffer in the full load range. On the basis of the multi-stage small-gain cascaded topology, the structure is improved to a ping-pong self-zeroing structure, so that the 1 / f noise and the mismatch caused by the error amplifier in the reference buffer are eliminated, and the continuous operation of the circuit is ensured. The feedback resistors are designed to be trimmed, the absolute accuracy of the final output voltage is improved through single-temperature-point trimming, and the simulation results show that, under the condition of meeting the loop gain, the absolute stability of the loop in the entire load range is ensured, and the noise resistance performance is greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of data conversion technology, specifically relating to a reference buffer circuit for an analog-to-digital converter. Background Technology

[0002] The market demand for industrial applications is increasing daily, and data acquisition systems are among the most critical devices. These data acquisition systems mainly consist of modules such as amplifier circuits and analog-to-digital converters (ADCs), among which the conversion accuracy of the ADC has a decisive impact on the system performance.

[0003] The reference voltage source is a key module in a data conversion system, providing the necessary reference voltage for ADC conversion. A stable system reference requires accurate and repeatable data conversion by the ADC, and the accuracy requirements for the reference increase with the number of bits. In ADC systems, since the reference source typically has limited load capacity, and the switching of the switched capacitor array during data conversion generates a large load current, the reference voltage must be output through a reference buffer to prevent interference with the performance of the reference voltage source. Therefore, reference buffers are widely used in ADC systems.

[0004] There are two main strategies for designing reference buffers:

[0005] (1) With external capacitor

[0006] The advantages are low power consumption and low noise, but the disadvantages are that while external capacitors save on-chip area, they increase the number of pins, and the parasitic inductance of bonding wires can cause output voltage oscillations, further deteriorating the stability of the reference voltage.

[0007] (2) No external capacitors

[0008] The advantage is that it has high bandwidth and can achieve fast response, but the cost is huge power consumption.

[0009] In high-precision applications and practical industrial products, solution (1) has been more widely used due to its stability, low power consumption and low noise.

[0010] To reduce conversion errors, the average current of the sampling capacitor must not cause the reference voltage to drop by more than 1 / 2 LSB, which requires the output impedance of the buffer amplifier to be quite low. Traditional ultra-low output impedance op-amps consume a lot of quiescent power; another effective method is to use a low-dropout regulator (LDO) as a reference buffer. LDOs utilize the characteristics of op-amps and closed-loop feedback systems to stabilize the output voltage under varying load currents, and by adjusting the feedback coefficient, accurate output voltage values ​​can be achieved.

[0011] A typical off-chip capacitor LDO includes an error amplifier, a load transistor, a resistor feedback network, and off-chip capacitors. Depending on the type of load transistor, LDOs mainly have two circuit structures, such as... Figure 1 As shown.

[0012] The power stage of a PMOS LDO is a common-source amplifier, while that of an NMOS LDO is a source follower. Therefore, NMOS LDOs have lower output impedance and more stable DC loop gain, which is independent of load, resulting in better line and load regulation. Furthermore, the lower output impedance of NMOS reduces overshoot, improving transient response. Thirdly, because electron mobility is greater than hole mobility, NMOS transistors are smaller for the same load current, leading to lower gate parasitic capacitance and improved circuit stability. However, the biggest drawback of NMOS is that its gate voltage is one V higher than the output voltage. GS This limits the minimum supply voltage. Using a charge pump can solve this problem, but it would significantly increase circuit complexity.

[0013] While providing drive current, the reference buffer also contributes new noise and offset to the output. Some inventions have proposed using chopping to reduce noise, but for amplifiers with dynamic loads, the ripple introduced by chopping is difficult to eliminate, and designing a synchronous clock significantly increases circuit complexity. Auto-zeroing, as another possible solution, has not yet been applied to LDOs and therefore warrants further investigation. Summary of the Invention

[0014] The purpose of this invention is to provide a low-noise, high-precision ADC reference buffer circuit.

[0015] The ADC reference buffer circuit provided by this invention has the following overall architecture: Figure 2 As shown. The main circuit is a PMOS LDO, including a multi-stage cascaded low-gain error amplifier, a super source follower (SSF) as an intermediate buffer, feedback resistors R1 and R2, and an external capacitor C. L To meet the driving capability requirements, the reference buffer adopts an external capacitor configuration, with an overall topology of a multi-stage low-gain cascade structure to ensure stability across the entire load range. To reduce the impact of the reference buffer on accuracy, the multi-stage low-gain cascade topology is improved to a ping-pong self-zeroing structure, thereby eliminating 1 / f noise and offset introduced by the error amplifier in the reference buffer and ensuring continuous circuit operation. Furthermore, the feedback resistor is tuned; single-temperature point tuning further improves the absolute accuracy of the final output voltage.

[0016] The specific connection method is as follows: The error amplifier consists of two cascaded multi-stage low-gain amplifiers with identical structures, divided into Ping and Pong paths. The negative input terminal of the error amplifier is connected to the reference voltage V. BG The positive input terminal is connected to the resistor feedback point V. FB The output is connected to the input of the SSF, the output of the SSF is connected to the gate of the PMOS load transistor, the source of the PMOS transistor is connected to the power supply voltage VDD, and the drain of the PMOS transistor is the output VREF of the LDO. Feedback resistors R1 and R2 are connected in series below, with a trimming resistor R1 connected in series above R1. T R2 is grounded below, and an external capacitor C is connected in parallel at the output. L .

[0017] This invention can be used in conjunction with a high-precision bandgap reference circuit as a reference source for high-precision ADCs, providing a high-precision, low-noise, and low-temperature-drift reference voltage for high-bit ADCs without incurring excessive errors due to power supply voltage and load switching. The reference buffer of this design can meet the accuracy requirements of ADCs with 14 bits or more without affecting their SNR. Attached Figure Description

[0018] Figure 1 These are the two current circuit structures for LDOs. Among them, (a) is a PMOS LDO, and (b) is an NMOS LDO.

[0019] Figure 2 This is the overall architecture of the high-precision reference buffer of the present invention.

[0020] Figure 3 This is the basic circuit structure of the LDO in this invention.

[0021] Figure 4 The structure selection for the intermediate level buffer. Among them, (a) is the source follower and (b) is the super source follower.

[0022] Figure 5 (a) Multi-stage EA structure, (b) Single-stage gain stage EA n structure.

[0023] Figure 6 Bode plot of loop gain at full load for a multi-stage LDO.

[0024] Figure 7 This is a Ping-pong auto-zeroing multi-stage EA circuit structure.

[0025] Figure 8 This is a block diagram illustrating the working principle of Auto-zeroing multi-stage EA.

[0026] Figure 9 To adjust resistor R T The circuit implementation.

[0027] Figure 10 The frequency response of a multi-stage low-gain LDO structure under different load conditions.

[0028] Figure 11 This is the output noise spectrum of the LDO in this design. Detailed Implementation

[0029] The ADC reference buffer circuit of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0030] A. Stability Design

[0031] Figure 3 The basic circuit structure of the LDO of this invention includes an error amplifier EA, used to output the bandgap reference V. BG Converted proportionally to output signal V REF A PMOS load transistor M p A primary stage is used to provide sufficient drive current; an intermediate stage buffer is used to drive M. p And a pair of feedback resistors R1 and R2, used to accurately set the feedback proportional coefficient. The specific connection method is as follows: the negative terminal of the EA input is connected to the reference voltage; the positive terminal of the EA input is connected to the intermediate feedback point of the feedback resistors R1 and R2; the EA output is connected in series with a buffer; and the buffer output is connected to M. p Gate, M p The source is connected to VDD, and the drain is used as the LDO output V. REF And connected in series with R1 and R2, and R1 and R2 are in turn connected with C L Connected in parallel, with the lower end grounded.

[0032] This LDO structure has three poles, located at the output terminal N1 of EA, the output terminal N2 of the buffer, and the output terminal N of the LDO. o The three poles can be represented as follows:

[0033]

[0034] In the formula, r oEA C is the output impedance of the error amplifier. N1 The parasitic capacitance at node N1 is mainly determined by the input capacitance C of the buffer. ib Decision; R ob C is the output impedance of the buffer. N2 For load transistor M p The gate parasitic capacitance at the input terminal; R oC represents the equivalent output impedance seen at the LDO output terminal. L This is the output load capacitor. Theoretically, to achieve a stable single-pole system, the frequencies of p1 and p2 should be much greater than the loop unity-gain bandwidth UGB of the LDO. This poses a challenge to the circuit design of EA and the buffer, requiring the output impedance to be minimized. The following section will analyze these two circuit components in detail.

[0035] (1) Buffer Design

[0036] Figure 4 (a) is a simple PMOS source follower structure with an output impedance r ob This can be expressed as:

[0037]

[0038] In equation (4), g m1 This represents the transconductance of transistor M1. To increase the frequency of p2, r needs to be reduced. o2 The value of g, that is, increasing g m1 The value of g. And increasing g m1 The only solutions are to increase the aspect ratio (W / L) of M1 or increase the bias current I1 flowing through M1. On the one hand, increasing I1 will increase the static power dissipation of the LDO; on the other hand, using a larger M1 will increase the parasitic capacitance C of the N1 node. N1 This causes the p1 frequency to decrease, severely degrading the circuit's stability. Therefore, a simple source follower structure is unsuitable as an intermediate-stage buffer for an LDO.

[0039] To overcome the shortcomings of the above structure, and to maximize its output impedance while reducing power consumption and the size of M1, this circuit uses a super source follower as an intermediate stage buffer, such as... Figure 4 As shown in (b). The specific connection method is as follows: N1 serves as the input terminal of SSF and is connected to the gate of PMOS transistor M1. The drain of M1 is connected in series with a fixed current source I2 to ground, and the source of M1 is connected in series with a fixed current source I2 to VDD. The drain of M1, i.e., node N2, serves as the output terminal of SSF and is connected to the subsequent load transistor M. p The gate of the input transistor M1 is connected in series with an NMOS transistor M2, and the gate of M2 is connected to the drain of the input transistor M1 to form a negative feedback loop.

[0040] Its output impedance can be expressed as:

[0041]

[0042] In equation (5), g m1 For the transconductance of transistor M1, g m2 For the transconductance of the M2 transistor, r o1Let g be the internal resistance of transistor M1. From the equation, it can be seen that compared to a simple source follower, the output impedance of the SSF increases by g. m2 r o1 Therefore, for the same r, ob Size, no longer requiring large bias currents or transistor sizes to increase g m1 Thus, the parasitic capacitance C at node N1 of the buffer input... N1 This can be achieved without sacrificing large static power consumption to push p1 further.

[0043] (2) EA Design

[0044] To ensure the stability of the single-pole loop, the output pole p1 of EA and other secondary poles P within EA are... EAn Both must be much larger than UGB. This requires the circuit to avoid high-impedance nodes as much as possible. However, on the other hand, the improvement of loop gain largely depends on the open-loop gain of EA. In general design, the gain is improved by increasing the output impedance, which conflicts with the stability design.

[0045] Therefore, the EA design in this circuit adopts a multi-stage low-gain cascade structure to avoid the occurrence of high-impedance nodes, while ensuring a considerable loop gain. The circuit is as follows: Figure 5 As shown in (a), EA1 to EA n A series of n amplifier stages are connected end-to-end, with the last stage's single-ended output En connected to the next stage's buffer. Each stage has a small gain EA. n Differential pair of diode loads in structural selection ( Figure 5 (b)), Input terminal Vi n Connect the NMOS differential pair, with a PMOS differential pair transistor connected in series at the upper end, and a fixed current source connected in series to ground at the lower end. The gate and drain of the PMOS transistor are shorted, and the drain serves as the fully differential output Vou. t The final stage is changed to single-ended output.

[0046] To ensure stability, the loop gain should be maximized. As the load current increases, the dominant pole of the LDO moves further away and gradually approaches other non-dominant poles, thus worsening stability. Therefore, as long as the loop phase margin is greater than 60° under full load, the circuit stability across the entire load variation range can be satisfied.

[0047] Figure 6 This is a schematic diagram of the frequency response characteristics of the LDO loop under full load, where βA0 is the loop gain, β is the feedback coefficient, and A0 is the open-loop gain. The expression is as follows:

[0048] A~AgA·gmp(rop / / RL) (6)

[0049]

[0050] In equation (6), A EA Here, gmp is the open-loop gain of the multi-stage EA, gmp is the transconductance of the load transistor Mp, rop is the internal resistance of the load transistor, and R is the open-loop gain of the multi-stage EA. L The load impedance is C. L =1μF, load current I L When the current is 20mA, the dominant pole frequency f is estimated through circuit simulation. o ≈4kHz. If the loop is a single-pole system, all internal poles are much larger than the unity-gain bandwidth UGB. After passing the dominant pole, the loop gain should decrease at a rate of -20dB / dec. Through simulation, it can be found that the internal poles of this LDO are all above 10MHz. Therefore, when UGB≤4MHz, the requirements of a single-pole system can be met, and the DC loop gain is about 60dB.

[0051] The load transistor Mp forms a common-source amplifier with a gain of approximately 6dB at full load and a feedback coefficient β of approximately 0.5. According to equation (7), to achieve the design requirement of a loop gain of 60dB, the open-loop gain provided by EA should be calculated to be 60dB. Since each stage EA... n The provided gain is approximately 10dB to 15dB, and the gain of the last stage is halved, so the multi-stage EA should have 5 stages.

[0052] B. Low-noise design

[0053] The noise and offset of an LDO mainly come from its internal error amplifier EA. To reduce its impact on the accuracy of the output voltage, dynamic offset cancellation technology needs to be applied to EA.

[0054] There are two techniques to choose from: chopping or auto-zeroing. Previous techniques used chopping op-amps in LDOs, but to avoid ripple from chopping, a synchronous clock was required, significantly increasing circuit complexity. Furthermore, considering low-power design, the bias current of the intermediate stage buffer is small, thus limiting the gate slew rate of the LDO load transistor. Therefore, under light load conditions, when the circuit offset is large, the large-signal ripple caused by chopping may saturate the gate of the LDO load transistor, affecting the normal operation of the feedback loop. This makes chopping technology unsuitable for circuits with excessively large load variations. Therefore, this invention adopts a ping-pong auto-zeroing structure, such as... Figure 7 As shown. On the one hand, auto-zeroing can effectively eliminate circuit 1 / f noise and offset; on the other hand, the ping-pong operating mode ensures the continuous operation of the circuit.

[0055] Figure 7In the diagram, A1-A5 are five-stage low-gain amplifiers, G m For auxiliary amplifiers (structured as differential input pair transistors), C AZ This is a sampling capacitor used to store the offset voltage. The Ping and Pong channels have identical structures, but their clock signals are out of phase. The specific connection is as follows: A1 to A4 are all fully differential amplifiers, connected end-to-end in sequence. Two pairs of switches are connected to the input of A1; one pair is connected to the input terminal, and the other pair is connected to the reference voltage V. BG Connected, the control clocks are f respectively A and f Z With opposite phase, the output of A4 is connected to the last stage single-ended output amplifier A5, and further connected through a pair of f... Z Controlled switch connection, G m Feedback is sent to input A3, G m A sampling capacitor C is connected in parallel at each output terminal. AZ To the ground, this serves as a Ping Stage amplifier, with another identical Pong Stage connected in parallel.

[0056] The Ping-Pong working mode works as follows: when ping is sampling, pong is working; when ping is working, pong is sampling, thus enabling the circuit to eliminate offset while ensuring continuous operation.

[0057] The following example, using ping levels, illustrates the principle of this circuit in eliminating offset and low-frequency noise. The circuit can be simplified as follows: Figure 8 As shown in the figure, the multi-stage amplifier structure is simplified to three stages: front, middle, and rear. A1 represents the gain of the first stage, and G... m2 R1 and R2 represent the second-stage transconductance and output impedance, respectively, A3 represents the final-stage gain, and G... m4 This represents the auxiliary transconductance, which, together with R2, forms an auxiliary amplifier. C AZ For offset storage capacitor, V os1 and V os2 These are the equivalent input offset of the multistage amplifier and the equivalent input offset of the auxiliary amplifier, respectively.

[0058] This amplifier employs a closed-loop offset cancellation structure that requires an auxiliary amplifier. According to calculations, the final equivalent input offset can be expressed as:

[0059]

[0060] According to equation (8), it can be seen that in order to minimize the equivalent input offset, A3 should be increased as much as possible. Therefore, for the multi-stage low-gain amplifier in this invention, more gain should be allocated to the later stages.

[0061] C. Single-point adjustment design

[0062] According to design requirements, the standard output voltage of the LDO should be 1.2V. To cover a 3σ error variation range of approximately ±20mV while achieving an initial accuracy of less than 0.1%, the trimming resistor in this invention provides a 5-bit trimming bit depth, achieving a trimming step size of 1.2mV / LSB. Figure 9 As shown in the diagram. The specific circuit implementation involves adding a resistor R across the feedback resistor R1. T We will adjust and redesign it.

[0063] The adjustment process is as follows: First, measure the absolute value of the chip's output voltage at room temperature T = 27℃. If this value is not within 1.2V ± 0.1%, the adjustment bit R<4:0> needs to be estimated and changed to adjust to the desired output voltage value. Initially, R<4:0> is "10010", where "0" indicates the switch is closed and the corresponding resistor is short-circuited; "1" indicates the switch is open and the corresponding resistor is connected to the feedback circuit. The adjustment bit can be extended from "00000" to "11111", providing an adjustment range of ±20mV.

[0064] Simulation results of the ADC reference buffer circuit of this invention.

[0065] Figure 10 This study examines the frequency response of a multi-stage low-gain LDO under different load conditions. The simulation environment was set at process corner tt, ambient temperature T = 27℃, and power supply voltage VDD = 1.8V. As shown in the figure, under no-load conditions, I... L When I = 0, the loop gain is 75dB, the UGB is 5.4kHz, and the phase margin is 90°; at full load I L At 20mA, the loop gain is 59dB, UGB is 3.8MHz, and the phase margin is 62°. The results show that, while satisfying the loop gain, all non-dominant poles are ensured to be much larger than UGB, thus guaranteeing the absolute stability of the loop across the entire load range.

[0066] Figure 11 This is the output noise spectrum of the LDO of this invention. To verify the improvement in noise performance by the DOC technology, the output noise spectrum was simulated with the DOC on and off. The simulation results show that when the DOC is on, the integrated noise from 0.1Hz to 10Hz is 1.3μV. RMS The integral noise is 25.7 μV when DOC is not enabled. RMS Compared to that, it has increased by about 20 times.

[0067] As a concrete example, using a standard 40nm CMOS process, the effective area of ​​the circuit layout is 0.02mm². 2The circuit has a quiescent current of 29μA at a 1.8V supply voltage, a maximum drive load current of 20mA, and an integrated noise level of 1.3μV from 0.1Hz to 10Hz. RMS The initial accuracy can reach 0.1%.

Claims

1. A low-noise, high-precision ADC reference buffer circuit, characterized in that, The main circuit is a PMOS LDO, including: an error amplifier EA consisting of multiple cascaded low-gain amplifiers; a super source follower (SSF) serving as an intermediate stage buffer; feedback resistors R1 and R2; and an external capacitor C. L To meet the driving capability requirements, an external capacitor is used, and the overall topology is a multi-stage low-gain cascade structure to ensure the stability of the buffer across the full load range. Based on the multi-stage low-gain amplifier cascade topology, a ping-pong self-zeroing structure is adopted to eliminate 1 / f noise and offset introduced by the error amplifier in the reference buffer, ensuring continuous circuit operation. The feedback resistor is also tuned, and single-temperature-point tuning improves the absolute accuracy of the final output voltage. Specifically, the error amplifier consists of two identical multi-stage low-gain amplifiers cascaded together, divided into Ping and Pong paths. The negative input terminal of the error amplifier is connected to the reference voltage V. BG The positive input terminal is connected to the resistor feedback point V. FB The output is connected to the input of a Super Source Follower (SSF), and the output of the SSF is connected to the gate of a PMOS load transistor. The source of the PMOS load transistor is connected to the power supply voltage VDD, and the drain of the PMOS load transistor is the LDO output VREF. Feedback resistors R1 and R2 are connected in series below, with a trimming resistor R1 connected in series above R1. T R2 is grounded below, and an external capacitor C is connected in parallel at the output. L .

2. The ADC reference buffer circuit according to claim 1, characterized in that, The error amplifier EA is used to output the bandgap reference V. BG Converted proportionally to output signal V REF A PMOS load transistor M p A primary stage is used to provide sufficient drive current; an intermediate stage buffer is used to drive the PMOS load transistor M. p And a pair of feedback resistors R1 and R2, used to accurately set the feedback ratio coefficient; the specific connection method is as follows: the negative input terminal of the error amplifier EA is connected to the reference voltage, the positive input terminal of the error amplifier EA is connected to the intermediate feedback point of the feedback resistors R1 and R2, the output of the error amplifier EA is connected in series with the buffer, and the output terminal of the buffer is connected to the load transistor M. p Gate, load transistor M p The source is connected to VDD, and the drain is used as the LDO output V. REF It is connected in series with R1 and R2, and R1 and R2 are connected in series with the external capacitor C. L Connected in parallel, with the lower end grounded; This LDO structure has three poles, located at the output N1 of the error amplifier EA, the output N2 of the buffer, and the output N of the LDO. o The three poles are represented as follows: ； In the formula, r oEA C is the output impedance of the error amplifier. N1 The parasitic capacitance at node N1 is mainly determined by the input capacitance C of the buffer. ib Decision; R ob C is the output impedance of the buffer. N2 For load transistor M p The gate parasitic capacitance at the input terminal; R o C represents the equivalent output impedance seen at the LDO output terminal. L The output load capacitor is used; to achieve a stable single-pole system, the frequencies of p1 and p2 are much greater than the loop unity-gain bandwidth UGB of the LDO.

3. The ADC reference buffer circuit according to claim 2, characterized in that, The intermediate-stage buffer uses a super source follower (SSF). Specifically, N1 serves as the input of the SSF, connected to the gate of PMOS transistor M1. The drain of PMOS transistor M1 is connected in series with a fixed current source I2 to ground. The source of PMOS transistor M1 is connected in series with a fixed current source I2 to VDD. The drain of PMOS transistor M1, i.e., node N2, serves as the output of the SSF, connected to the subsequent load transistor M. p The gate of the input PMOS transistor M1 is connected in series with a PMOS transistor M2, and the gate of the PMOS transistor M2 is connected to the drain of the input PMOS transistor M1 to form a negative feedback loop. Its output impedance is expressed as: ； In equation (5), g m1 For the transconductance of NMOS transistor M1, g m2 r is the transconductance of NMOS transistor M2. o1 The internal resistance of NMOS transistor M1 is given.

4. The ADC reference buffer circuit according to claim 3, characterized in that, The error amplifier EA adopts a multi-stage cascaded low-gain amplifier structure, with each stage A... n The structure uses a differential pair with diode load, and the last stage is changed to single-ended output; the specific connection method is: A1 to A n A total of n small-gain amplifiers are connected end to end in sequence, with the last stage being A. n The single-ended output is connected to the next stage buffer; each stage has a small gain A. n The structure uses a differential pair with a diode load, and the specific connection method is as follows: Input terminal V in Connect the NMOS differential pair, with a PMOS differential pair transistor connected in series at the upper end, and a fixed current source connected in series to ground at the lower end. The gate and drain of the PMOS transistor are shorted, and the drain serves as the fully differential output V. out .

5. The ADC reference buffer circuit according to claim 4, characterized in that, The error amplifier EA adopts a ping-pong auto-zeroing structure. On the one hand, auto-zeroing can effectively eliminate circuit 1 / f noise and offset; on the other hand, the ping-pong operating mode ensures continuous operation of the circuit. A1-A5 are five-stage low-gain amplifiers. m As an auxiliary amplifier, its structure consists of a differential input pair of transistors, C AZ The sampling capacitor is used to store the offset voltage; the Ping and Pong channels have identical structures, but their clock signals are out of phase; the specific connection method is as follows: low-gain amplifiers A1 to A4 are all fully differential amplifiers, connected end to end in sequence; the input terminal of low-gain amplifier A1 is connected to two pairs of switches, one pair connected to the input terminal and the other pair connected to the reference voltage V. BG Connected, the control clocks are f respectively A and f Z With opposite phase, the output of the low-gain amplifier A4 is connected to the last stage single-ended output amplifier A5, and further connected through a pair of f... Z Controlled switch connection, G m Feedback is sent to the input of the low-gain amplifier A3, G m A sampling capacitor C is connected in parallel at each output terminal. AZ To the ground, this serves as a Ping Stage amplifier, with another identical PongStage connected in parallel.

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