A pixel-level infrared detector readout circuit

Abstract

The application belongs to the field of readout integrated circuit, and particularly relates to a kind of pixel level infrared detector readout circuit, aiming at solving the problem that current readout circuit with high precision and large dynamic range is difficult to meet the demand of smaller size of pixel.The application comprises: a timing control circuit for counting the main clock pulse of the entire infrared detector circuit; an integration circuit module of a pixel-in-module for integrating photoelectric current to obtain an integrated voltage, and controlling whether the charge of an integration capacitor is discharged according to the comparison result of the integrated voltage and a reference voltage; a programmable bidirectional counter for counting the output first level to obtain a first count value; a second counter for counting the high level of borrow output of the programmable bidirectional counter at the beginning of the second subframe to obtain a second count value; and an operation module for calculating the operation result from the first count value, a storage value, the second count value and the main clock pulse count result.The application can meet the demand of smaller size of pixel.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of readout integrated circuit, and particularly relates to a kind of pixel level infrared detector readout circuit. BACKGROUND

[0002] In recent years, with the continuous development of infrared imaging technology and integrated circuit technology, higher requirements are put forward for the performance of infrared detector. In the future, the development trend of infrared focal plane technology mainly develops towards large array, small pixel size, high frame frequency, low noise, multi-band detection, super long wave detection and other directions, to adapt to the needs of deep space exploration, precision guidance and other application fields. Reducing the area of a single pixel and increasing the array size of the detector mainly aims to improve the spatial resolution of the infrared focal plane. The reduction of pixel area and the increase of array size put forward higher requirements for the infrared readout circuit. In order to break through the limitation of pixel size on integral capacitance, the current infrared readout circuit generally adopts pulse frequency modulation (PFM) type ADC structure for pixel level analog-to-digital conversion (ADC). With this structure, the charge processing capacity of digital pixel architecture increases exponentially relative to the pixel area, rather than linear scaling of traditional analog pixels, which is very suitable for long-wave infrared detection. In order to reduce quantization noise and improve signal-to-noise ratio, there is currently a two-step counting method based on the structure of pulse frequency modulation ADC, which divides the conversion of ADC into two stages: a coarse quantization stage and a fine quantization stage. In the first stage, the circuit works like a normal PFM ADC pixel circuit. In the second stage, the high-frequency clock is counted to measure the residual charge on the integral capacitor. At this time, the quantization noise is a function of the detector photocurrent and the high-frequency clock period, and a more accurate quantization value can be calculated to significantly reduce the quantization noise.

[0003] However, with the current two-step counting method of conversion, high-precision and large-dynamic-range readout circuits still require high-bit counters and registers, making it difficult to meet the demand for smaller pixel size. SUMMARY

[0004] In order to solve the above problems in the prior art, i.e. with the current two-step counting method of conversion, high-precision and large-dynamic-range readout circuits still require high-bit counters and registers, making it difficult to meet the demand for smaller pixel size, the present application provides a kind of pixel level infrared detector readout circuit, the circuit includes: timing control circuit, integral circuit module and operation module of pixel in module;

[0005] The timing control circuit is used for counting and outputting the main clock pulse of the entire infrared detector circuit.

[0006] The integration circuit module of the pixel-in-module is configured to receive injection of the photocurrent of the infrared detector, integrate the photocurrent using an integration capacitor to obtain an integration voltage in n subframe integration times, output a first level according to a comparison result of the integration voltage and a reference voltage, and control whether the charge of the integration capacitor is discharged to the ground according to the first level; n is a natural number, and n>1;

[0007] The pixel-in-module is configured to count the output first level using a programmable bidirectional counter to obtain a first count value, store the count value of the programmable bidirectional counter as a storage value after the end of the first subframe integration time using a register of the pixel-in-module, and count a high level of a borrow output of the programmable bidirectional counter at the start of the second subframe using a second counter of the pixel-in-module to obtain a second count value.

[0008] The operation module is configured to calculate an operation result according to the first count value, the storage value, the second count value, and a result of counting a main clock pulse; and the operation module is divided into a first operation mode and a second operation mode based on precision, and the second operation mode is operated based on the first operation mode.

[0009] In a preferred embodiment, the integration circuit module of the pixel-in-module includes an injection transistor, a reset transistor, a comparator, an integration capacitor, and a reset circuit.

[0010] The injection transistor is configured to control injection of the photocurrent of the infrared detector and stabilize a voltage across the drain and the gate.

[0011] The integration capacitor is configured to integrate the photocurrent of the infrared detector to obtain an integration voltage in a plurality of subframe integration times and transmit the integration voltage to the comparator.

[0012] The comparator is configured to output a first level; if the integration voltage is greater than the reference voltage, the first level output by the comparator is a high level; if the integration voltage is less than the reference voltage, the first level output by the comparator is a low level; and the comparator transmits the output first level to the reset circuit and the programmable bidirectional counter.

[0013] The reset circuit is configured to control whether the reset transistor is turned on or not turned on according to the output first level of the comparator; if the comparator outputs a high level, the reset transistor is turned on; and if the comparator outputs a low level, the reset transistor is not turned on.

[0014] The reset transistor is configured to control discharge of the charge of the integration capacitor; when the reset transistor is turned on, the charge of the integration capacitor is discharged to the ground.

[0015] In a preferred embodiment, the programmable bidirectional counter, the register, and the second counter are the calculation module of the pixel-in-module; and the operation mode of the calculation module is as follows:

[0016] In the first sub-frame integration time, the up-down counter is set to 0 and is set to count up, and when the comparator output is high, the up-down counter is set to count up by 1;

[0017] After the first sub-frame integration time, the up-down counter is set to count down, and when the comparator output is high, the up-down counter is set to count down by 1; the initial value of the up-down counter in each sub-frame integration time after the second sub-frame integration time is the storage value in the register;

[0018] After the first sub-frame integration time, the up-down counter is set to count down, and when the comparator output is high, the up-down counter is set to count down by 1; the initial value of the up-down counter in each sub-frame integration time after the second sub-frame integration time is the storage value in the register;

[0019] In each sub-frame integration time after the second sub-frame integration time, the first count value of the up-down counter can only be reduced to 0 or -1, and when the first count value is 0, the borrow output is 0, and when the first count value is -1, the borrow output is 1;

[0020] The second counter counts the borrow output of the up-down counter at the end of each sub-frame integration time and obtains a second count value.

[0021] In the first sub-frame integration time, the up-down counter is set to 0 and is set to count up, and when the comparator output is high, the up-down counter is set to count up by 1;

[0022] In the first sub-frame integration time, the up-down counter is set to 0 and is set to count up, and when the comparator output is high, the up-down counter is set to count up by 1;

[0023] After the first sub-frame integration time, the up-down counter is set to count down, and when the comparator output is high, the up-down counter is set to count down by 1; the initial value of the up-down counter in each sub-frame integration time after the second sub-frame integration time is the storage value in the register;

[0024] After the first sub-frame integration time, the up-down counter is set to count down, and when the comparator output is high, the up-down counter is set to count down by 1; the initial value of the up-down counter in each sub-frame integration time after the second sub-frame integration time is the storage value in the register;

[0025] In each sub-frame integration time after the second sub-frame integration time, the first count value of the up-down counter can only be reduced to 0 or -1, and when the first count value is 0, the borrow output is 0, and when the first count value is -1, the borrow output is 1;

[0026] The second counter is used to count the borrow output of the programmable bidirectional counter at the end of each sub-frame integration time counting, and obtain a second counting value.

[0027] The first counting value of the programmable bidirectional counter can only decrease to 0 or -1 at the end of each sub-frame integration time after the start of the second sub-frame integration time, and the borrow output is 0 when the first counting value is 0, and the borrow output is 1 when the first counting value is -1.

[0028] The second counter is used to count the borrow output of the programmable bidirectional counter at the end of each sub-frame integration time counting, and obtain a second counting value.

[0029] In a preferred embodiment, the connection mode of the pixel-level infrared detector readout circuit is as follows:

[0030] The input end of the injection transistor receives an external photoelectric current, and the output end of the injection transistor is connected with the first end of the integration capacitor, the first input end of the comparator and the source electrode of the reset transistor.

[0031] The second end of the integration capacitor is grounded, the drain electrode of the reset transistor is connected with the second high level, and the second input end of the comparator is externally connected with a reference voltage.

[0032] The output end of the comparator is connected with the second end of the reset circuit and the input end of the programmable bidirectional counter, respectively; the first end of the reset circuit is connected with the gate electrode of the reset transistor; and the input end of the programmable bidirectional counter is further provided with a high-frequency pulse input end.

[0033] The output end of the programmable bidirectional counter is connected with the input end of the second counter, the input end of the register and the input end of the second operation module, respectively.

[0034] The output end of the register is connected with the input end of the programmable bidirectional counter and the input end of the first operation module, respectively.

[0035] The output end of the second counter is connected with the input end of the first operation module.

[0036] The output end of the first operation module is connected with the input end of the second operation module and the first end of the first switch, respectively.

[0037] The output end of the second operation module is connected with the first end of the second switch.

[0038] The second end of the first switch and the second end of the second switch are connected with a data transmission line.

[0039] In a preferred embodiment, the timing control module comprises a third counter and a fourth counter; the third counter counts the main clock pulses to obtain a main clock pulse count value, outputs a high level when the main clock pulse count value reaches a first set value, and controls the sub-integration time; the fourth counter counts the high level output by the third counter to obtain a third counter high level count value, outputs a high level when the third counter high level count value reaches a second set value, and controls the entire integration time through the high level output by the fourth counter.

[0040] In a preferred embodiment, the operation module comprises a first operation module, a first switch, a second operation module, and a second switch.

[0041] The first operation module comprises a first multiplier and a first adder; the output end of the first multiplier is connected to the input end of the first adder.

[0042] The second operation module comprises a second multiplier, a third multiplier, a second adder, and a divider; the output end of the second multiplier is connected to the input end of the third adder and the input end of the second adder respectively, the output end of the third adder is connected to the input end of the divider, the output end of the second adder is connected to the input end of the divider; the output end of the first adder is connected to the input end of the third multiplier.

[0043] In a preferred embodiment, when the pixel-level infrared detector readout circuit selects the first mode:

[0044] The first switch is closed, the second switch is opened, the first operation module is operated, and the second operation module is not operated; the storage value of the register and the main clock pulse high level count value are multiplied by the first multiplier to obtain a first multiplication result, the first multiplication result and the second count value output by the second counter are added by the first adder to obtain a first addition result; the output value of the first operation module is the first addition result.

[0045] In a preferred embodiment, when the pixel-level infrared detector readout circuit selects the second mode:

[0046] The first switch is opened, the second switch is closed, and the first operation module and the second operation module are both operated; the storage value of the register and the main clock pulse high level count value are multiplied by the first multiplier to obtain a first multiplication result, the first multiplication result is added by the first adder with the second count value output by the second counter to obtain a first addition result, and the first addition result is the output value of the first operation module.

[0047] The main clock pulse count value and the main clock pulse high level count value are multiplied by the second multiplier to obtain a second multiplication result.

[0048] The second multiplication result and the output value of the first operation module are multiplied by a third multiplier to obtain a third multiplication result;

[0049] The second multiplication result and a high-frequency pulse count value are obtained by a second adder to obtain a second addition result; the high-frequency pulse count value is obtained by counting high-frequency pulses of the entire infrared detector by a programmable bidirectional register;

[0050] The second addition result is input to a divider as a dividend, and the third multiplication result is input to the divider as a divisor to obtain a division result as an output value of the second operation module;

[0051] The present application has the following beneficial effects:

[0052] (1) The present application optimizes the conversion mechanism of the PFM ADC, uses a programmable bidirectional counter to ensure the accuracy of analog-to-digital conversion and reduce the area of the pixel circuit under the condition that the number of counter and register bits is small, and through repeated counting of the programmable bidirectional counter controlled by a timing circuit, finally obtains the final conversion result through an operation module. Therefore, while ensuring the high conversion accuracy of the readout circuit, the area of the single pixel circuit is effectively reduced, and the optional two-step conversion is adopted, which can further improve the signal-to-noise ratio of the readout circuit;

[0053] (2) The present application controls the time of the subframe by counting the main clock, and controls the integration time by setting the number of subframes several times, which can realize flexible and effective time control and ensure the synchronization of each pixel;

[0054] (3) The present application can flexibly select the appropriate readout mode in the case of large change of the infrared detector photocurrent by selecting two kinds of counting modes, so as to meet the requirements of high signal-to-noise ratio and low power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0055] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments made with reference to the accompanying drawings:

[0056] Figure 1 is a circuit diagram of a pixel-level infrared detector readout circuit provided by the embodiment of the present application;

[0057] Figure 2 is a structural block diagram of a timing control module provided by the embodiment of the present application;

[0058] Figure 3 is a readout process flow chart of a pixel-level infrared detector readout circuit provided by the embodiment of the present application;

[0059] Figure 4 is a structural diagram of an operation module provided by the embodiment of the present application. DETAILED DESCRIPTION

[0060] The application will be described in further detail below with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the application. In addition, it should be noted that, for the purpose of clarity, only the parts of the drawings that are relevant to the application are shown.

[0061] It should be noted that the embodiments and features in the embodiments of the application can be combined with each other without conflict. The application will be described in further detail below with reference to the drawings and embodiments.

[0062] The application provides a kind of pixel level infrared detector readout circuit, the circuit includes: timing control circuit, integration circuit module of pixel in module and operation module;

[0063] The timing control circuit is used to count and output the main clock pulse of the entire infrared detector circuit;

[0064] The integration circuit module of pixel in module is used to receive the injection of photoelectric current of infrared detector, integrates photoelectric current using integration capacitor to obtain integration voltage in n subframe integration time, outputs first level according to the comparison result of integration voltage and reference voltage, controls whether the charge of integration capacitor is discharged to ground according to the first level;N is natural number, n>1;

[0065] The first count value is obtained by counting the output first level by the settable bidirectional counter of pixel in module;The count value of settable bidirectional counter after the end of the first subframe integration time is stored as storage value by the register of pixel in module;The second count value is obtained by counting the high level of borrow output of settable bidirectional counter by the second counter of pixel in module when the second subframe starts;

[0066] The operation module is used to calculate the operation result by the first count value, storage value, second count value and the result of main clock pulse counting;The operation module is divided into first operation mode and second operation mode based on precision, and the second operation mode is operated based on the first operation mode.

[0067] In order to more clearly describe the application, a kind of pixel level infrared detector readout circuit will be described below in combination with Figure 1 The modules in the embodiments of the application will be described in detail.

[0068] The pixel level infrared detector readout circuit of the first embodiment of the application includes: timing control circuit, integration circuit module of pixel in module and operation module;Each module is described as follows:

[0069] As Figure 2The timing control circuit is shown, the timing control module includes a third counter and a fourth counter; the third counter counts the main clock pulse to obtain a main clock pulse count value, and outputs a high level when the main clock pulse count value reaches a first set value; the fourth counter counts the high level output by the third counter to obtain a third counter high level count value, and outputs a high level when the third counter high level count value reaches a second set value.

[0070] The integration circuit module of the pixel-in-pixel module is configured to receive injection of the photocurrent of the infrared detector, integrate the photocurrent using an integration capacitor to obtain an integration voltage in n sub-frame integration times, output a first level according to a comparison result of the integration voltage and a reference voltage, and control whether the charge of the integration capacitor is discharged to the ground according to the first level; n is a natural number, and n>1;

[0071] The integration circuit module of the pixel-in-pixel module includes an injection transistor, a reset transistor, a comparator, an integration capacitor, and a reset circuit.

[0072] The injection transistor is configured to control injection of the photocurrent of the infrared detector and stabilize the voltage across the drain and the gate through a gate voltage.

[0073] The integration capacitor is configured to integrate the photocurrent of the infrared detector to obtain an integration voltage in a plurality of sub-frame integration times, and transmit the integration voltage to the comparator.

[0074] The comparator is configured to output a first level; if the integration voltage is greater than the reference voltage, the first level output by the comparator is a high level; if the integration voltage is less than the reference voltage, the first level output by the comparator is a low level; and the comparator transmits the output first level to the reset circuit and the programmable bidirectional counter.

[0075] The reset circuit is configured to control opening or non-opening of the reset transistor according to the first level output by the comparator; if the comparator outputs a high level, the reset transistor is turned on; and if the comparator outputs a low level, the reset transistor is not turned on.

[0076] The reset transistor is configured to control discharge of the charge of the integration capacitor; when the reset transistor is turned on, the charge of the integration capacitor is discharged to the ground.

[0077] The programmable bidirectional counter of the pixel-in-pixel module counts the output first level to obtain a first count value; the register of the pixel-in-pixel module is configured to store the count value of the programmable bidirectional counter after the end of the first sub-frame integration time as a storage value; and the second counter of the pixel-in-pixel module counts the high level output by the borrow output of the programmable bidirectional counter at the beginning of the second sub-frame to obtain a second count value.

[0078] The programmable bidirectional counter, the register and the second counter are calculation modules of the pixel-level infrared detector readout circuit;

[0079] In the first sub-frame integration time, the programmable bidirectional counter is set to 0 and is set to counting up, and the programmable bidirectional counter is incremented by 1 when the output of the comparator is high.

[0080] After the first sub-frame integration time ends and before the second sub-frame integration time starts, the programmable bidirectional counter transmits the count value of the first sub-frame integration time to the register for storage as the storage value of the register.

[0081] From the start of the second sub-frame integration time to the end of the nth sub-frame integration time, the programmable bidirectional counter is set to counting down, and the value of the counter is decremented by 1 when the first level of the output of the comparator is high. The initial value of the programmable bidirectional counter in each sub-frame integration time after the second sub-frame integration time is the storage value in the register.

[0082] In each sub-frame integration time after the start of the second sub-frame integration time, the first count value of the programmable bidirectional counter can only be reduced to 0 or -1, and the borrow output is 0 when the first count value is 0, and the borrow output is 1 when the first count value is -1.

[0083] The second counter counts the borrow output of the programmable bidirectional counter at the end of each sub-frame integration time and obtains a second count value.

[0084] The operation module is configured to calculate an operation result based on the first count value, the storage value, the second count value and the count result of the main clock pulse. The operation module is divided into a first operation mode and a second operation mode based on precision, and the second operation mode is operated based on the first operation mode.

[0085] As shown in Figure 4 The operation module includes a first operation module, a first switch, a second operation module and a second switch.

[0086] The first operation module includes a first multiplier and a first adder. The output end of the first multiplier is connected to the input end of the first adder.

[0087] The second operation module includes a second multiplier, a third multiplier, a second adder and a divider. The output end of the second multiplier is connected to the input end of the third adder and the input end of the second adder respectively. The output end of the third adder is connected to the input end of the divider. The output end of the second adder is connected to the input end of the divider. The output end of the first adder is connected to the input end of the third multiplier.

[0088] When the pixel-level infrared detector readout circuit selects the first mode:

[0089] The first switch is closed, the second switch is opened, the first operation module is operated, and the second operation module is not operated; the storage value of the register and the high level count value of the main clock pulse are multiplied by the first multiplier to obtain a first multiplication result, and the first multiplication result and the second count value output by the second counter are added by the first adder to obtain a first addition result; the output value of the first operation module is the first addition result;

[0090] When the pixel-level infrared detector readout circuit selects the second mode:

[0091] The first switch is opened, the second switch is closed, and the first operation module and the second operation module are operated; the storage value of the register and the high level count value of the main clock pulse are multiplied by the first multiplier to obtain a first multiplication result, the first multiplication result and the second count value output by the second counter are added by the first adder to obtain a first addition result, and the first addition result is the output value of the first operation module;

[0092] The count value of the main clock pulse and the high level count value of the main clock pulse are multiplied by the second multiplier to obtain a second multiplication result;

[0093] The second multiplication result and the output value of the first operation module are multiplied by the third multiplier to obtain a third multiplication result;

[0094] The second multiplication result and the high frequency pulse count value are added by the second adder to obtain a second addition result; wherein the high frequency pulse count value is obtained by counting the high frequency pulse of the entire infrared detector by the programmable bidirectional register;

[0095] The second addition result is input to the divider as the dividend, and the third multiplication result is input to the divider as the divisor to obtain a division result as the output value of the second operation module;

[0096] The pixel-level infrared detector readout circuit of the application divides the entire integration process into multiple repeated subframes through the timing control module, the control of the subframe integration time by the timing control module is mainly realized by counting the main clock pulse, the entire integration time is controlled by setting the number of subframes, and the integration of each pixel can be synchronized. The first operation mode or the second operation mode of the readout circuit can be selected to realize one-stage counting and two-stage counting respectively. The one-stage counting obtains the result by outputting the register and the second counter to the first operation module. The two-stage counting transmits the result of the first operation module, the second high frequency count value and the count value of the timing control module to the second operation module to obtain the final result, and the operation result of the second operation mode is the accurate counting with decimal places. Therefore, the large dynamic range can be realized while reducing the quantization noise and improving the signal-to-noise ratio of the conversion circuit.

[0097] The connection mode of the pixel-level infrared detector readout circuit is as follows:

[0098] The input end of the injection transistor receives external photoelectric current, the output end of the injection transistor is connected with the first end of the integration capacitor, the first input end of the comparator and the source of the reset transistor, the second end of the integration capacitor is grounded, the drain of the reset transistor is connected with the second high level, the second input end of the comparator is externally connected with a reference voltage, the output end of the comparator is connected with the second end of the reset circuit and the input end of the programmable bidirectional counter respectively, the first end of the reset circuit is connected with the gate of the reset transistor, the input end of the programmable bidirectional counter is further provided with a high-frequency pulse input end, the output end of the programmable bidirectional counter is connected with the input end of the second counter, the input end of the register and the input end of the second operation module respectively, the output end of the register is connected with the input end of the programmable bidirectional counter and the input end of the first operation module respectively, the output end of the second counter is connected with the input end of the first operation module, the output end of the first operation module is connected with the input end of the second operation module and the first end of the first switch respectively, the output end of the second operation module is connected with the first end of the second switch, and the second end of the first switch and the second end of the second switch are connected with a data transmission line.

[0099] The operation mode of the pixel-level infrared detector readout circuit is as follows:

[0100] The injection transistor controls the injection of the detector photoelectric current and stabilizes the voltage between the drain and the source through the gate voltage, so as to ensure the stability of the detector bias; the comparator compares the voltage on the integration capacitor with the reference voltage, if the voltage on the integration capacitor is smaller than the reference voltage, the comparator does not flip, otherwise the comparator outputs a high level; the reset circuit controls the conduction of the reset transistor according to the output value of the comparator and the time sequence control circuit, when the output of the comparator is high, the reset transistor is turned on, the charge on the integration capacitor is discharged to the ground, at this time, the voltage on the integration capacitor is smaller than the reference voltage, the output of the comparator is low, the reset circuit closes the reset transistor, and the integration capacitor starts to integrate the photoelectric current again. The time sequence control circuit is composed of two counters, the third counter controls the sub-frame integration time by counting the main clock pulse, the fourth counter controls the sub-frame repetition times by counting the output high level of the third counter 3, and the integration of each pixel can be synchronized by counting the main clock.

[0101] The up-down counter receives the output of the comparator. In the first sub-frame integration time, the initial value of the up-down counter is 0, and it is set to count up. When the output of the comparator is high, the count is increased by 1. After the first sub-frame integration time, the value of the up-down counter is transferred to the register. From the second sub-frame, the up-down counter is set to count down, and the initial value of the counter is set to the value stored in the register. At this time, every time the output of the comparator is high, the value of the counter is decreased by 1. When the integration time of each sub-frame ends, the value of the up-down counter can only be reduced to 0 or -1. When the value is 0, the borrow output is 0, and when the value is -1, the borrow output is 1. This is because the integration time is the same, and only at the beginning of the first sub-frame, the charge on the integration capacitor is 0. The charge on the integration capacitor at the beginning of each subsequent sub-frame is different, but it is always less than the charge of a charge packet. Therefore, the number of charge packets in the subsequent sub-frames can only be equal to the number of charge packets in the first sub-frame or one more charge packet. The borrow output of the up-down counter is counted at the end of each sub-frame by the second counter, and then the next sub-frame begins. This is repeated until the set number of repetitions is met, at which time the first stage of counting is complete. For example, Figure 3As shown, if the first operation mode is selected, the entire integration stage is completed at the end of the first stage counting, at which time the reset circuit is opened under the control of the timing circuit, causing the charge on the integration capacitor to be discharged to ground, completing the entire integration stage and starting the readout stage, with the data of the second counter and the register being transmitted to operation module one. Operation module one includes a first multiplier and a first adder, with the inputs of the first multiplier being the value N1 of the register and the pulse count value n2 of the control subframe number, and the inputs of the first adder being the output of the multiplier and the value N2 of the second counter. The value of N1 is the charge packet count value in the first subframe integration time, and the pulse count value n2 represents the number of subframes, i.e., the number of repeated counts. The output value N2 of the second counter represents the number of subframes that is one more than the count value in the first subframe. The result of operation module one is N_1 = N1 x n2 + N2, which represents the total number of charge packets accumulated in the entire integration time. This method can be used to implement a large number of counts using a small number of counters and registers, thereby achieving a high conversion bit number in a small pixel and ensuring a large dynamic range. If the second operation mode is selected, the second stage counting mode needs to be continued after the first stage counting is completed, at which time the reset circuit is not opened, so the integration capacitor continues to integrate the photocurrent. Under the control of the timing circuit, the settable bidirectional counter is reset to the add count mode and the initial value is 0, and then the high-frequency pulse count is started. When the voltage on the integration capacitor reaches the reference voltage, the output of the comparator again flips to high level, and the second stage counting is completed. At this time, the output of the comparator causes the reset circuit to open, discharging the charge on the integration capacitor to ground, thereby completing the entire integration process and starting the readout stage. The count value M of the high-frequency clock pulse of the second stage settable bidirectional counter and the calculation result N1 of the first operation module are both transmitted to the second operation module for calculation. The second operation module includes a second multiplier, a third multiplier, a second adder, and a divider. Before performing the operation, the value n1 of the third counter and the value n2 of the fourth counter are multiplied by the second multiplier. The inputs of the third multiplier are the output of the second multiplier and the output value N 1+1The input of the second adder is the output of the second multiplier and the value M of the number bidirectional counter at the end of the high frequency counting. The input of the divider is the output of the third multiplier and the second adder, wherein the output of the third multiplier is the divisor and the output of the second adder is the dividend. The idea of the second operation module is that the total time of the first stage integration process is divided by the time of accumulating a charge package, and the quotient is the number of accumulated charge packages in the integration process. The final output N_2=(n1*n2*(N_1+1)) / (n1*n2+M) is obtained by operation. The operation result is accurate to the decimal place. Compared with the result of the first operation mode, the output of the second operation mode is accurate counting with decimal places. Therefore, the dynamic range can be guaranteed while reducing the quantization noise and improving the signal-to-noise ratio of the conversion circuit.

[0102] The application can effectively reduce the circuit area while improving the dynamic range of the readout circuit by dividing the integration time into multiple sub-frame integration processes. The application can control the integration time and the repetition number of the sub-frames by counting the main clock to control the entire integration process, so that the integration time can be conveniently controlled and the pixels can be synchronized. The application can meet the requirements of conversion accuracy under different photoelectric currents and control the power consumption by selecting two modes.

[0103] Although the above embodiment describes each step in the above order, those skilled in the art can understand that, in order to achieve the effect of the embodiment, the different steps do not have to be executed in such order, and they can be executed simultaneously (in parallel) or in reverse order, and these simple changes are within the protection scope of the application.

[0104] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related description of the system described above can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

[0105] The computer program product of the present application can be a computer program product comprising a computer readable storage medium and a computer program mechanism embedded in the computer readable storage medium. Such computer program product can further include a computer readable storage medium and program means for causing a processor or other programmable processing apparatus to function in a particular manner, such that the computer program mechanism that can be executed by such a processor or processing apparatus causes the processor or processing apparatus to implement the functions of the system, method and computer program product of the present application.

[0106] The terms "first", "second", etc. are used to distinguish similar objects, rather than to describe or indicate a particular order or sequence.

[0107] The term "comprising" or any other similar term is intended to encompass the inclusion of non-exclusive inclusion, so that the process, method, article or equipment / device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes the elements inherent to the process, method, article or equipment / device.

[0108] So far, the technical solutions of the present application have been described in combination with the preferred embodiments shown in the drawings, but those skilled in the art can easily understand that the protection scope of the present application is obviously not limited to these specific embodiments. Those skilled in the art can make equivalent changes or replacements to the related technical features without departing from the principles of the present application, and the technical solutions after the changes or replacements will fall within the protection scope of the present application.

Claims

1. A pixel level infrared detector readout circuit, characterized in that, The circuit comprises a timing control circuit, an integration circuit module of a pixel-in-module and an operation module; The timing control circuit is used for counting a main clock pulse of the whole infrared detector circuit and outputting; The integration circuit module of the pixel-in-module is used for receiving injection of a photoelectric current of the infrared detector, integrating the photoelectric current using an integration capacitor to obtain an integration voltage in n sub-frame integration times, outputting a first level according to a comparison result of the integration voltage and a reference voltage, and controlling whether the charge of the integration capacitor is discharged to the ground according to the first level; n is a natural number, and n>1; A settable number bidirectional counter of the pixel-in-module counts the output first level to obtain a first count value; a register of the pixel-in-module is used for storing the count value of the settable number bidirectional counter after the end of the first sub-frame integration time as a storage value; a second counter of the pixel-in-module counts a high level of borrow output of the settable number bidirectional counter at the beginning of the second sub-frame to obtain a second count value; The operation module is used for calculating an operation result according to the first count value, the storage value, the second count value and the counting result of the main clock pulse; the operation module is divided into a first operation mode and a second operation mode based on precision, and the second operation mode is operated based on the first operation mode.

2. The readout circuit for a pixel-level infrared detector according to claim 1, wherein, The integration circuit module of the pixel-in-module comprises an injection transistor, a reset transistor, a comparator, an integration capacitor and a reset circuit; The injection transistor is used for controlling injection of the photoelectric current of the infrared detector and stabilizing the voltage between the drain and the source through the gate voltage; The integration capacitor is used for continuously integrating the photoelectric current of the infrared detector in multiple sub-frame integration times to obtain an integration voltage and transmitting the integration voltage to the comparator; The comparator is used for outputting the first level; If the integration voltage is greater than the reference voltage, the first level output by the comparator is a high level; if the integration voltage is less than the reference voltage, the first level output by the comparator is a low level; The comparator transmits the output first level to the reset circuit and the settable number bidirectional counter; The reset circuit is used for controlling conduction or non-conduction of the reset transistor according to the output first level of the comparator; if the comparator outputs a high level, the reset transistor is turned on; if the comparator outputs a low level, the reset transistor is not turned on; The reset transistor is used for controlling discharge of the charge of the integration capacitor; when the reset transistor is turned on, the charge of the integration capacitor is discharged to the ground.

3. The readout circuit for a pixel-level infrared detector according to claim 2, wherein, The settable number bidirectional counter, the register and the second counter are calculation modules of the pixel-in-module; the operation mode of the calculation modules is as follows: In the first sub-frame integration time, the initial value of the settable number bidirectional counter is 0, and the settable number bidirectional counter is set to count up when the comparator outputs a high level; The settable number bidirectional counter transmits the count value of the first sub-frame integration time to the register to store as a storage value of the register from the end of the first sub-frame integration time to the beginning of the second sub-frame integration. From the beginning of the second sub-frame integration time to the end of the n-th sub-frame integration time, the settable bidirectional counter is set to count down, and the value of the counter is reduced by one when the first level output by the comparator is high; the initial value of the settable bidirectional counter at each sub-frame integration time after the second sub-frame integration time is the stored value in the register; At each sub-frame integration time after the beginning of the second sub-frame integration time, the first count value of the settable bidirectional counter can only be reduced to 0 or -1, and the borrow output is 0 when the first count value is 0, and the borrow output is 1 when the first count value is -1; The second counter counts the borrow output of the settable bidirectional counter at the end of each sub-frame integration time and obtains a second count value.

4. The readout circuit for a pixel-level infrared detector according to claim 3, wherein, The connection mode of the pixel-level infrared detector readout circuit is as follows: The input end of the injection transistor receives an external photocurrent, and the output end of the injection transistor is connected with the first end of the integration capacitor, the first input end of the comparator and the source electrode of the reset transistor; The second end of the integration capacitor is grounded, the drain electrode of the reset transistor is connected with a second high level, and the second input end of the comparator is externally connected with a reference voltage; The output end of the comparator is connected with the second end of the reset circuit and the input end of the settable bidirectional counter respectively; the first end of the reset circuit is connected with the gate electrode of the reset transistor; and the input end of the settable bidirectional counter is further provided with a high-frequency pulse input end; The output end of the settable bidirectional counter is connected with the input end of the second counter, the input end of the register and the input end of the second operation module respectively; The output end of the register is connected with the input end of the settable bidirectional counter and the input end of the first operation module respectively; The output end of the second counter is connected with the input end of the first operation module; The output end of the first operation module is connected with the input end of the second operation module and the first end of the first switch respectively; The output end of the second operation module is connected with the first end of the second switch; The second end of the first switch and the second end of the second switch are connected with a data transmission line.

5. A readout circuit for a pixel-level infrared detector as claimed in claim 4, characterized in that The timing control module comprises a third counter and a fourth counter; the third counter counts the main clock pulse to obtain a main clock pulse count value, and outputs a high level when the main clock pulse count value reaches a first set value; the fourth counter counts the high level output by the third counter to obtain a third counter high level count value, and outputs a high level when the third counter high level count value reaches a second set value.

6. A readout circuit for a pixel-level infrared detector as claimed in claim 5, characterized in that The operation module comprises a first operation module, a first switch, a second operation module and a second switch; The first operation module comprises a first multiplier and a first adder; the output end of the first multiplier is connected with the input end of the first adder; The second operation module comprises a second multiplier, a third multiplier, a second adder and a divider; the output end of the second multiplier is connected with the input end of the third multiplier and the input end of the second adder respectively, the output end of the third multiplier is connected with the input end of the divider, and the output end of the second adder is connected with the input end of the divider; the output end of the first adder is connected with the input end of the third multiplier.

7. A readout circuit for a pixel-level infrared detector as claimed in claim 6, characterized in that When the pixel-level infrared detector readout circuit selects the first mode: The first switch is closed, the second switch is opened, the first operation module is running, and the second operation module is not running; the storage value of the register and the high level count value of the main clock pulse are multiplied by the first multiplier to obtain a first multiplication result, and the first multiplication result and the second count value output by the second counter are added by the first adder to obtain a first addition result; the output value of the first operation module is the first addition result.

8. The readout circuit for a pixel-level infrared detector according to claim 7, wherein, When the pixel-level infrared detector readout circuit selects the second mode: The first switch is opened, the second switch is closed, and the first operation module and the second operation module are running; the storage value of the register and the high level count value of the main clock pulse are multiplied by the first multiplier to obtain a first multiplication result, the first multiplication result and the second count value output by the second counter are added by the first adder to obtain a first addition result, and the first addition result is the output value of the first operation module; The count value of the main clock pulse and the high level count value of the third counter are multiplied by the second multiplier to obtain a second multiplication result; The second multiplication result and the output value of the first operation module are multiplied by the third multiplier to obtain a third multiplication result; The second multiplication result and the high frequency pulse count value are added by the second adder to obtain a second addition result; wherein the high frequency pulse count value is obtained by counting the high frequency pulse of the entire infrared detector by the bidirectional register with a settable number; The second addition result is input to the divider as the dividend, and the third multiplication result is input to the divider as the divisor to obtain a division result, which is the output value of the second operation module.

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