Data processing device, electronic device and method for manufacturing data processing device

Abstract

A data processing device, an electronic device and a method for preparing the data processing device. The data processing device includes a logic processing layer, an in-memory computing layer and a storage array layer. The logic processing layer, the in-memory computing layer and the storage array layer are at least partially stacked; the logic processing layer is configured to perform logic operations and / or control processing; the in-memory computing layer is configured to perform neural network operations on received data, and the storage array layer is configured to store data for the in-memory computing layer; the storage array layer includes a storage array, the storage array includes a plurality of storage cells arranged in multiple rows and columns, and each of the plurality of storage cells includes a transistor and a magnetic random access memory device electrically connected to the transistor. The data processing device can improve data processing efficiency and integration.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data processing device, an electronic device, and a method for manufacturing a data processing device. Background Art

[0002] The memristor-based in-memory computing system can effectively execute matrix-vector multiplication in neural networks. However, the input and output data need to be cached, and the transfer efficiency has become a performance bottleneck. The cache bandwidth is limited by the bus interconnection under the two-dimensional integration architecture. Therefore, the transmission efficiency within one operation time is relatively low, resulting in limited parallel computing capabilities. Even with multi-level bus optimization, it is still restricted by the inefficiency of two-dimensional connections. In addition, traditional memristor chips are based on analog resistive switching characteristics. Although multiple resistance states can be used for analog computing, they are affected by non-ideal characteristics (such as conductance drift, large randomness, or limited number of write / erase cycles), making it difficult to achieve high-precision computing. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a data processing device, including: a logic processing layer, an in-memory computing layer, and a storage array layer, wherein at least part of the logic processing layer, the in-memory computing layer, and the storage array layer are stacked; the logic processing layer is configured to perform logical operations and / or control processing; the in-memory computing layer is configured to perform neural network operations on the received data, and the storage array layer is configured to store data for the in-memory computing layer; the storage array layer includes a storage array, and the storage array includes a plurality of memory cells arranged in multiple rows and columns, and each of the plurality of memory cells includes a transistor and a magnetic random access memory device electrically connected to the transistor.

[0004] For example, in the data processing device provided by an embodiment of the present disclosure, the magnetic random access memory device includes a first electrode layer, a free layer, a barrier layer, a pinned layer, and a second electrode layer stacked in sequence.

[0005] For example, in the data processing device provided by an embodiment of the present disclosure, the free layer includes an antiferromagnetic layer and a ferromagnetic layer stacked in sequence.

[0006] For example, in the data processing device provided by an embodiment of the present disclosure, the in-memory computing layer includes at least one in-memory computing array, and each in-memory computing array includes at least one memristor array, and the memristor array includes a plurality of memristors arranged in multiple rows and columns; the magnetic random access memory device includes a magnetic tunnel junction, and the magnetic tunnel junction is placed at a staggered position with respect to the memristor.

[0007] For example, in the data processing device provided by an embodiment of the present disclosure, the transistor includes at least one of a carbon nanotube transistor, an indium-based oxide transistor, or a low-temperature polysilicon transistor.

[0008] For example, in the data processing device provided in an embodiment of the present disclosure, the magnetic random access memory device includes a spin-transfer torque magnetic random access memory device or a spin-orbit torque magnetic random access memory device.

[0009] At least one embodiment of the present disclosure provides an electronic device, including the data processing device provided in any embodiment of the present disclosure.

[0010] At least one embodiment of the present disclosure provides a method for manufacturing a data processing device, including: preparing an in-memory computing layer and a storage array layer that is at least partially stacked with the in-memory computing layer by using semiconductor manufacturing processes, where the in-memory computing layer is configured to perform neural network operations on received data, and the storage array layer is configured to store data for the in-memory computing layer; the storage array layer is configured to store data for the in-memory computing layer, the storage array layer includes a storage array, the storage array includes a plurality of memory cells arranged in multiple rows and multiple columns, and each of the plurality of memory cells includes a transistor and a magnetic random access memory device electrically connected to the transistor.

[0011] For example, in the manufacturing method provided in an embodiment of the present disclosure, the manufacturing of the magnetic random access memory device includes: preparing a mask to define a graphic region of the magnetic random access memory device, where the mask includes a photoresist mask or a hard mask; using the mask to prepare a magnetic tunnel junction.

[0012] For example, in the manufacturing method provided in an embodiment of the present disclosure, the preparing a mask to define a graphic region of the magnetic random access memory device includes: defining a graphic of the magnetic tunnel junction region by using a bilayer resist process.

[0013] For example, in the manufacturing method provided in an embodiment of the present disclosure, the using the mask to prepare a magnetic tunnel junction includes: etching other regions outside the graphic region of the magnetic random access memory device through a dry etching process to retain the graphic region of the magnetic random access memory device.

[0014] For example, in the manufacturing method provided in an embodiment of the present disclosure, the in-memory computing layer includes at least one in-memory computing array, each in-memory computing array includes at least one memristor array, and the memristor array includes a plurality of memristors arranged in multiple rows and multiple columns; the manufacturing of the magnetic random access memory device further includes: selecting a region on the surface of the memristor with a root mean square roughness less than 1 nm or 0.2 nm to arrange the magnetic tunnel junction, and placing the magnetic tunnel junction at a staggered position with respect to the memristor.

[0015] For example, the preparation method provided by an embodiment of the present disclosure further includes: providing a silicon substrate; preparing a logic processing layer on the silicon substrate by using a semiconductor manufacturing process, wherein the logic processing layer is configured to perform logic operations and / or control processing, the in-memory computing layer is formed on a side of the logic processing layer away from the silicon substrate, and the storage array layer is formed on a side of the in-memory computing layer away from the silicon substrate. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0017] Figure 1 Shows a schematic structural diagram of an MRAM storage cell;

[0018] Figure 2 Shows a schematic structural diagram of a SOT-MRAM storage cell;

[0019] Figure 3 Shows a schematic structural diagram of a STT-MRAM storage cell;

[0020] Figure 4 Shows a schematic diagram of the working principle of an in-memory computing array;

[0021] Figure 5 Shows a schematic structural diagram of a data processing device provided by at least one embodiment of the present disclosure;

[0022] Figure 6 Shows a schematic block diagram of a data processing device provided by at least one embodiment of the present disclosure;

[0023] Figure 7 Shows a schematic diagram of a preparation method of a magnetic random access memory device provided by at least one embodiment of the present disclosure;

[0024] Figure 8 Shows a schematic flow diagram of a preparation method of a magnetic random access provided by at least one embodiment of the present disclosure; and

[0025] Figure 9 Shows a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. Detailed Embodiments

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0027] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, the terms "a", "an", or "the" and similar terms do not denote a quantity limitation, but mean that there is at least one. The terms "comprising", "including", or similar terms are intended to mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0028] Figure 1 A schematic structural diagram of an MRAM memory cell is shown. Figure 1 An MRAM (Magnetic Random Access Memory) with a 2T1M (Two Transistor One Magnetic Tunnel Junction) structure is shown. The 2T1M memory cell includes two transistors (2T) and one MRAM memory device (1M).

[0029] As Figure 1 shown, an exemplary MRAM memory device includes a heavy metal layer (HM), a free layer (FL), a tunnel barrier layer (TBL, e.g., magnesium oxide MgO), and a pinned layer (PL) stacked in sequence.

[0030] The two transistors (2T) include a first transistor and a second transistor. Among them, the first transistor is connected to the read word line (RWL), and is connected to the bit line (BL) and the pinned layer (PL) of the MRAM storage device. The second transistor is connected to the write word line (WWL), and is connected to the bit line (BL) and the heavy metal layer (HM) of the MRAM storage device. Thus, the bit line (BL) is connected to the pinned layer (PL) and the heavy metal layer (HM) of the MRAM storage device through the two transistors respectively, and the source line (SL) is connected to the heavy metal layer (HM) of the MRAM storage device. The first transistor is configured to control the data reading of the MRAM storage cell by the read word line (RWL), and the second transistor is configured to control the data writing of the MRAM storage cell by the write word line (WWL).

[0031] The MRAM storage cell with a 2T1M structure can improve the reliability and selectivity of data access, reduce the crosstalk between adjacent cells, and achieve non-volatile, high-speed, and high-density storage through double-transistor control and magneto-tunnel junction magnetoresistance effect. It can effectively read and write data by finely regulating the current and magnetic field, and has good anti-interference ability and data stability.

[0032] Figure 2 The structural schematic diagram of a SOT-MRAM storage cell is shown. As Figure 2 shown, in the 2T1M storage cell based on SOT-MRAM (Spin-Orbit Torque Magnetic Random Access Memory), the MRAM storage device includes a heavy metal layer (HM), a free layer (FL), a barrier layer (TBL), and a pinned layer (PL) stacked in sequence. The bit line (BL) is connected to the heavy metal layer (HM) of the MRAM storage device through a transistor, and the source line (SL) is connected to the heavy metal layer (HM) of the MRAM storage device, which is used to provide a read current or a write current. The read word line (RWL) is connected to the gate of the transistor connected between the bit line and the pinned layer (PL) of the MRAM storage device, and the write word line (WWL) is connected to the gate of the transistor connected between the bit line and the heavy metal layer (HM) of the MRAM storage device.

[0033] In a write operation, the transistor connects the bit line to the heavy metal layer (HM) of the MRAM storage device under the control of the enable signal on the write word line, and corresponding currents can be provided through the bit line and the source line, causing the magnetization direction of the free layer to flip. By adjusting the direction and magnitude of the current, the switching of the magnetization direction of the free layer can be achieved. When the magnetization direction of the free layer is aligned with that of the pinned layer, the written bit is 0; when the magnetization direction of the free layer is opposite to that of the pinned layer, the written bit is 1.

[0034] In a read operation, the transistor connects to the pinned layer (PL) of the MRAM storage device under the control of the enable signal on the read word line, and corresponding currents can be provided through the bit line and the source line, preventing the magnetization direction of the free layer from flipping. Then, data is read by detecting the magnetization direction of the free layer. When the magnetization direction of the free layer is aligned with that of the pinned layer, the stored bit is 0; when the magnetization direction of the free layer is opposite to that of the pinned layer, the stored bit is 1.

[0035] Figure 3 Fig. shows a schematic structural diagram of an STT-MRAM storage cell. As Figure 3 shown, in an STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) storage cell, the MRAM storage device includes a stacked free layer (FL), a barrier layer, and a pinned layer (PL). The bit line (BL) is connected to the free layer of the MRAM storage device and is used to provide read or write currents; the source line (SL) is connected to the pinned layer of the MRAM storage device through a transistor and is used to provide read or write currents; the word line (WL) is connected to the gate of the transistor and is used to select the cell to be read or written.

[0036] In a write operation, the transistor can be controlled to conduct through the control signal on the word line, so as to provide corresponding currents flowing through the MRAM storage device through the bit line and the source line. The generated current component passes through the barrier layer, causing the magnetization direction of the free layer to flip. According to the direction of the current, the magnetization direction of the free layer can be flipped from top to bottom or from bottom to top. Therefore, different data can be written by changing the direction of the current.

[0037] During a read operation, the transistor can be turned on by a word line control signal to provide a corresponding current flowing through the MRAM storage device via the bit line and the source line, so that the magnetization direction of the free layer does not flip. Then, the magnetization direction of the free layer is determined by detecting the voltage change on the bit line. If the magnetization direction of the free layer is the same as that of the pinned layer, the voltage on the bit line is low; if the magnetization direction of the free layer is opposite to that of the pinned layer, the voltage on the bit line is high. Therefore, the data stored in the MRAM storage device can be determined by reading the voltage on the bit line.

[0038] Figure 4 FIG. shows a schematic diagram of the working principle of an in-memory computing array. As Figure 4 shown, the in-memory computing array (i.e., the in-memory computing array) includes memristor units arranged in rows and columns. The memristor unit includes a memristor (such as a resistive random access memory (RRAM), a phase change memory (PRAM), etc.). The in-memory computing array can complete the operation process of matrix-vector multiplication according to Kirchhoff's law. The weight matrix data to be processed can be mapped to the resistance values of each memristor and written into the in-memory computing array. The input vector is mapped to the input signals (voltage signals) of each row of the in-memory computing array. The output signals (current signals) of each column are the product of the input voltage and the resistive conductance, which is the output vector, that is:

[0039] ∑I = ∑V * G,

[0040] where I represents the output current of each column in the in-memory computing array, V represents the input voltage of each row in the in-memory computing array, and G represents the conductance of the memristor in the memristor unit. Thus, the above in-memory computing array can be used for neural network computing.

[0041] Compared with the von Neumann architecture, the in-memory computing architecture has the advantages of fast operation speed, low power consumption, and high integration density. In-memory computing integrates the computing function into the storage unit, reducing the frequent transfer of data between the data storage module and the computing module, and also reducing the data transmission delay. In addition, in-memory computing integrates the computing and storage functions on the same chip, reducing the need for external connections and wiring, making the chip more integrated and applicable to smaller and thinner electronic devices. Neural network is a key technology in the field of deep learning, etc. Its computing volume is huge and the requirement for computing efficiency is extremely high. In-memory computing can not only meet the computing needs of neural networks, but also achieve high-performance computing under the condition of low power consumption.

[0042] However, the inventors of the present disclosure have noticed that in-memory computing chips face technical problems regarding cache capacity, chip area, cache bandwidth, and single-precision computing. For example, for a 32×32 in-memory computing array, the required cache is at least 512 bit (i.e., for a 1k array, 0.5k data needs to be cached). When using 6T-SRAM to implement the same cache capacity, the number of transistors required in the cache is three times that of the memristor array (using a 1T1R structure), resulting in the area of the cache being significantly larger than the in-memory computing array, which limits the integration density.

[0043] Moreover, in practical applications, considering the requirements of residual connections in neural networks, the cache capacity may need to be further expanded by 2-3 times. In addition, in a two-dimensional integration mode, the memristor array and the cache are interconnected through a bus, resulting in limited bandwidth. For example, for a 128bit / 200MHz bus, only about 3 parallel calculations of 32×32 arrays can be supported within one operation cycle, which restricts the overall computing efficiency of multi-memristor array chips.

[0044] Furthermore, the inventors of the present disclosure have also noticed that although memristor chips can achieve multiple resistance states to complete analog computing based on analog resistive switching characteristics, due to the influence of non-ideal characteristics (such as conductance drift, randomness, or write / erase cycle limitations), it is difficult to perform high-precision computing. While MRAM is based on binary magnetic tunnel junctions and has advantages such as stability and unlimited write / erase cycles, it can only achieve two resistance states. Although it is suitable for high-precision computing, it is not suitable for high-computing-power matrix computing. Therefore, how to construct a high-computing-power chip with mixed precision has become an urgent problem to be solved.

[0045] At least one embodiment of the present disclosure provides a data processing device and a preparation method for the data processing device.

[0046] The data processing device includes a logic processing layer, an in-memory computing layer, and a storage array layer. Among them, at least part of the logic processing layer, the in-memory computing layer, and the storage array layer are stacked; the logic processing layer is configured to perform logic operations and / or control processing; the in-memory computing layer is configured to perform neural network operations on the received data, and the storage array layer is configured to store data for the in-memory computing layer; the storage array layer includes a storage array, and the storage array includes a plurality of storage units arranged in multiple rows and columns. Each of the plurality of storage units includes a transistor and a magnetic random access memory device electrically connected to the transistor. The data processing device integrates in-memory computing and subsequent compatible transistor technologies, and in at least one embodiment, it can also be used to implement mixed-precision computing, breaking through the von Neumann bottleneck, significantly improving data processing efficiency and integration density, and realizing a chip design that combines high computing power and versatility. The data processing device can also be, for example, a chip, a semiconductor device, an integrated circuit device, etc. using three-dimensional integration technology. The embodiments of the present disclosure are not limited thereto.

[0047] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the present disclosure is not limited to these specific embodiments.

[0048] Figure 5 FIG. shows a schematic block diagram of a data processing device provided by at least one embodiment of the present disclosure.

[0049] In some embodiments of the present disclosure, as Figure 5 shown, the data processing device may include a logic processing layer, an in-memory computing layer, and a storage array layer. The logic processing layer, the in-memory computing layer, and the storage array layer are at least partially stacked. The logic processing layer is configured to perform logical operations and / or control processing, the in-memory computing layer is configured to perform neural network operations on the received data, and the storage array layer is configured to store data for the in-memory computing layer.

[0050] For example, the logic processing layer may perform operations such as combining, comparing, and filtering data from the in-memory computing layer, the storage array layer, or other input sources, generating new logical signals or data streams to support corresponding data processing tasks.

[0051] For example, data and / or control signals may be transmitted between the logic processing layer, the storage array layer, and the in-memory computing layer through interlayer metal interconnects.

[0052] For example, the in-memory computing layer may perform neural network operations such as matrix multiplication on the received external input or data provided by the storage array layer through an in-memory computing array (such as a memristor) included in the in-memory computing layer, and may also perform operations such as convolution, pooling, and activation functions as needed. For example, reference may be made to the relevant description of the working principle of the in-memory computing array in the foregoing embodiments, which will not be elaborated herein. Compared with the mode of first fetching data and then sending it to the processor for calculation, the in-memory computing layer can significantly reduce the overhead of data transfer, thereby greatly improving the computing efficiency, and is particularly suitable for large-scale parallel computing scenarios.

[0053] For example, the in-memory computing layer may include at least one in-memory computing array, the in-memory computing array includes at least one memristor array, the memristor array may include a plurality of memristor units arranged in multiple rows and columns, and each memristor unit includes a memristor and a switching element (such as a transistor).

[0054] For example, the material structure of at least one of the memristors may include: TiN / HfAlO x / TaO x / TiN or TiN / HfO 2 / TaO x / TiN or TiN / HfO 2 / TiN or TiN / HfZrO x / TaO x / TiN or TiN / HfAlZrO x / TaO x / TiN or TiN / SiO 2 / TiN or TiN / HfO x / TaO x / Stacked structures such as TiN, etc., which are not limited in the embodiments of the present disclosure. It should be noted that in the embodiments of the present disclosure, the above X is not necessarily an integer, and the metal oxide may have different oxygen contents or oxygen-containing ratios. For example, the oxygen content in each layer can be determined according to the amount of oxygen introduced during the manufacturing process. For example, in the actual manufacturing process, it may include metal oxides with unfixed oxygen contents, such as Ta 2 O 5 Mixtures with TaO, etc., which are not limited in the embodiments of the present disclosure.

[0055] For example, the storage array layer can cache data for the in-memory computing layer.

[0056] For example, the storage array layer may include a storage array, and the storage array may include a plurality of storage units arranged in multiple rows and columns. Each of the plurality of storage units may include a transistor and a magnetic random access memory (MRAM) electrically connected to the transistor.

[0057] For example, the transistor can be configured to act as an access control. By applying an appropriate control voltage signal to the gate of the transistor, the transistor can be accurately turned on or off, thereby performing operations on the connected MRAM storage device to achieve read, write, or erase operations on the stored data.

[0058] For example, the transistor may include at least one of a carbon nanotube (CNT) transistor, an indium-based oxide transistor, or a low-temperature polycrystalline silicon (LTPS) transistor, which is not limited in the embodiments of the present disclosure.

[0059] For example, the indium-based oxide transistor may include an IGZO transistor, an IGO transistor, or an In 2 O 3 Transistor, etc.

[0060] For example, each of the plurality of storage units may include a 2T1M storage unit. The specific content of the 2T1M storage unit can be referred to the relevant descriptions of the foregoing embodiments, and will not be elaborated here.

[0061] For example, a plurality of 2T1M storage units arranged in multiple rows and columns can form a storage array, thereby forming a storage array layer.

[0062] For example, the magnetic random access memory device may include a spin transfer torque magnetic random access memory device (STT-MRAM), a spin orbit torque magnetic random access memory device (SOT-MRAM), etc., and the embodiments of the present disclosure are not limited thereto. For the relevant descriptions of the spin transfer torque magnetic random access memory device and the spin orbit torque magnetic random access memory device, reference may be made to the relevant descriptions of STT-MRAM and SOT-MRAM in the foregoing embodiments, which will not be elaborated herein.

[0063] The storage array layer can quickly and reliably store the neural network model parameters, training data, or intermediate calculation results in the in-memory computing layer on the premise of high density and low power consumption, providing corresponding data storage support for the in-memory computing layer.

[0064] In some embodiments of the present disclosure, the magnetic random access memory device may include a first electrode layer, a free layer, a barrier layer (i.e., a tunneling layer), a pinned layer, and a second electrode layer, which are stacked in sequence.

[0065] For example, the first electrode layer may be a metal with a relatively strong spin-orbit coupling effect (such as metal materials such as Pt, W, or Ta, or alloy materials). The film thickness of the first electrode layer may be, for example, 0 to 6 nm.

[0066] For example, the free layer may include an antiferromagnetic layer and a ferromagnetic layer (i.e., an antiferromagnetic / ferromagnetic exchange coupling layer) stacked in sequence.

[0067] For example, the antiferromagnetic layer in the free layer may also be directly used as the first electrode of the magnetic random access memory device.

[0068] For example, the material of the antiferromagnetic layer in the free layer may include collinear antiferromagnetic materials (such as Mn 2 Au), non-collinear antiferromagnetic materials (such as IrMn 3 , PtMn 3 or Mn 3 Sn) or spin-split antiferromagnetic materials (such as RuO 2 , Mn 5 Si 3 ), etc., and the embodiments of the present disclosure are not limited thereto. The film thickness of the antiferromagnetic layer in the free layer may be, for example, 4 - 8 nm.

[0069] For example, the material of the ferromagnetic layer in the free layer may include CoFeB, Co materials, etc., and the embodiments of the present disclosure are not limited thereto. The film thickness of the ferromagnetic layer in the free layer may be, for example, 0.8 - 1.4 nm to obtain perpendicular magnetic anisotropy, that is, the easy magnetization direction is perpendicular or approximately perpendicular to the film surface.

[0070] For the free layer, due to the characteristic that the antiferromagnetic layer has adjacent magnetic moments arranged in opposite directions, the overall external magnetic moment is zero. The magnetization direction of the antiferromagnetic layer is extremely stable and is not easily changed by external influences. The magnetic moments inside the ferromagnetic layer can be arranged in the same direction to form a net magnetic moment, and the magnetization direction of the ferromagnetic layer can be regulated by external stimuli (such as current or magnetic field).

[0071] Since the antiferromagnetic layer is in close contact with the ferromagnetic layer, an exchange coupling effect will occur between the antiferromagnetic layer and the ferromagnetic layer, that is, a direct magnetic interaction between adjacent magnetic moments. This interaction can cause the magnetization direction of the ferromagnetic layer to be pinned in a specific direction by the antiferromagnetic magnetic moment, and an exchange bias magnetic field will be generated inside even without an external magnetic field.

[0072] When there is no current or magnetic field, due to the constraint of the pinned layer (with a fixed magnetization direction) and the influence of the exchange bias magnetic field provided by the antiferromagnetic layer / ferromagnetic layer, the magnetization direction of the free layer can be stabilized in a specific state. For example, it can correspond to storing a binary bit ("0" or "1").

[0073] Since the exchange bias magnetic field is generated inside the free layer, it breaks the symmetry of the magnetization reversal of the spin-orbit torque (SOT). When a current in a specific direction is applied, the spin-orbit torque (SOT) generated by the current can more effectively drive the perpendicular magnetization direction of the ferromagnetic layer to flip along a specific direction, rather than the random flipping that might occur without the bias. This enables the magnetization reversal process of the free layer to be directionally controlled by the current direction and without relying on an external magnetic field.

[0074] When performing a data writing operation, by applying a current in a specific direction to the first electrode layer, the SOT effect is generated due to the strong spin-orbit coupling effect in the metal electrode material when the current flows through the first electrode layer. The SOT effect generates an effective torque inside the ferromagnetic layer, acting on the magnetization vector to cause it to rotate. Due to the existence of the exchange bias magnetic field, the current only needs to overcome the coercivity of the ferromagnetic layer itself (i.e., the minimum energy required to maintain the magnetization state) to directionally flip the magnetization direction from one stable state to another, thus completing the data writing.

[0075] When performing a data reading operation, the magnetization state can be determined by measuring the change in the tunneling resistance between the free layer and the pinned layer. When the magnetization directions of the two layers are parallel (in the same direction), the tunneling resistance is low, which can represent that the stored binary bit is "0"; when the magnetization directions of the two layers are antiparallel (in opposite directions), the tunneling resistance is high, which can represent that the stored binary bit is "1".

[0076] By introducing an antiferromagnetic / ferromagnetic exchange coupling layer, the free layer obtains a strong in-plane exchange bias magnetic field, so that under the condition of no external magnetic field, the directional magnetization reversal can be achieved only by relying on current, which improves the operation efficiency of data storage, reduces the power consumption, and enhances the adaptability of MRAM in specific application environments.

[0077] For example, the material of the barrier layer can be an insulating layer, such as including MgO, and the film thickness of the barrier layer can be 1-2 nm.

[0078] For example, the pinned layer can include an artificial antiferromagnetic structure. The pinned layer can include a ferromagnetic layer, a non-magnetic metal layer, a ferromagnetic layer, and an antiferromagnetic layer stacked in sequence.

[0079] For example, the material of the ferromagnetic layer in the pinned layer can include CoFeB or Co material, etc., and the embodiments of the present disclosure are not limited thereto. The film thickness of the ferromagnetic layer in the pinned layer can be, for example, 0.8-1.4 nm.

[0080] For example, the material of the antiferromagnetic layer in the pinned layer can include IrMn 3 or PtMn 3 etc., and the embodiments of the present disclosure are not limited thereto. The film thickness of the antiferromagnetic layer in the pinned layer can be, for example, 5-10 nm.

[0081] For example, the material of the non-magnetic metal layer in the pinned layer can include Ru or Ta, etc., and the embodiments of the present disclosure are not limited thereto. The film thickness of the non-magnetic metal layer in the pinned layer can be, for example, 0.4-1.5 nm.

[0082] In addition, the directions of the easy magnetization axes of the free layer and the pinned layer can be perpendicular or approximately perpendicular to the film surfaces of the free layer and the pinned layer.

[0083] For example, the material of the second electrode can include metal materials such as Pt, W, or Ta, or alloy materials. The film thickness of the second electrode can be, for example, 5-20 nm.

[0084] It should be noted that considering the mass production process error, the actual film thickness can have an error of 5-10 nm. Exemplarily, the range of the film thickness of the second electrode can also be 1-30 nm.

[0085] In some embodiments of the present disclosure, the magnetic random access memory device includes a magnetic tunnel junction (MTJ, Magnetic Tunnel Junction).

[0086] A magnetic tunnel junction may include a ferromagnetic layer, an insulating layer, and a ferromagnetic layer stacked in sequence. The insulating layer (e.g., a tunnel barrier layer) may be sandwiched by two ferromagnetic layers (e.g., one ferromagnetic layer has a fixed magnetization direction and the other ferromagnetic layer can switch its magnetization direction). When the magnetization directions of the upper and lower ferromagnetic layers are parallel, electrons can efficiently cross the insulating layer through the tunneling effect, showing a low-resistance state; when the magnetization directions of the upper and lower ferromagnetic layers are antiparallel, the tunneling effect weakens, showing a high-resistance state, and the change in the resistance state can correspond to the storage of binary data "0" and "1".

[0087] In addition, the inventors of the present disclosure also noticed that the surface roughness of the in-memory computing layer may affect the performance of the magnetic random access memory device. The rough surface of the in-memory computing layer may cause the non-uniformity of the structure of the magnetic tunnel junction (MTJ), affecting the precise control of the electron tunneling efficiency, magnetic anisotropy, or spin-orbit torque effect, thereby affecting the key performance indicators such as the stability, read / write speed, power consumption, and data retention ability of the MRAM memory device.

[0088] Therefore, when selecting the setting area of the magnetic tunnel junction of the MRAM, a position with a root mean square roughness (RMS) of the in-memory computing layer surface less than or equal to 1 nanometer (or 0.2 nanometer) can be selected to ensure the high-performance operation of the MRAM magnetic tunnel junction.

[0089] For example, the memristor in the in-memory computing layer and the magnetic tunnel junction of the MRAM can also be placed at staggered positions.

[0090] In at least one embodiment of the present disclosure, placing the memristor and the magnetic tunnel junction of the MRAM at staggered positions can help avoid mutual process interference, ensure the high-quality manufacturing of each device, and also ensure that the magnetic tunnel junction is disposed in a specific area that meets its roughness requirements, while the memristor can select a suitable area for integration according to its own surface quality requirements. Moreover, since both the memristor and the MRAM generate electric and magnetic fields during operation, although both the memristor and the MRAM are non-volatile components, if they are too close to each other, their electrical behaviors may interfere with each other, resulting in problems such as read / write errors, signal crosstalk, or increased power consumption. Therefore, staggering the positions of the memristor and the magnetic tunnel junction of the MRAM can avoid direct electrical coupling and maintain the independence of their respective read / write operations and data integrity. Since the memristor and the MRAM have different heat dissipation requirements, different heat distributions may be generated during the data read / write process. Staggering their positions can also help optimize thermal management, prevent the formation of local hot spots, and maintain the stability and reliability of the data processing device. In addition, placing the memristor and the magnetic tunnel junction of the MRAM at staggered positions can make the layout of the data processing device more flexible, and can reasonably allocate space according to the requirements of each circuit layer and process limitations, which helps to improve the integration density of the data processing device.

[0091] Figure 6 FIG. shows a schematic block diagram of a data processing device provided by at least one embodiment of the present disclosure. As Figure 6 shown, in some embodiments of the present disclosure, the data processing device 100 may include a logic processing layer 101, an in-memory computing layer 102, and a storage array layer 103. The logic processing layer 101, the in-memory computing layer 102, and the storage array layer 103 are at least partially stacked.

[0092] For example, the logic processing layer 101 may be disposed on a silicon substrate, the in-memory computing layer 102 is disposed on a side of the logic processing layer 101 away from the silicon substrate, and the storage array layer 103 is disposed on a side of the in-memory computing layer 102 away from the silicon substrate.

[0093] For example, the data processing device 100 further includes an interlayer dielectric layer disposed between the logic processing layer 101, the in-memory computing layer 102, and the storage array layer 103. The interlayer dielectric layer includes a plurality of vias, and the logic processing layer 101, the in-memory computing layer 102, and the storage array layer 103 communicate with each other through the plurality of vias respectively.

[0094] For example, an interlayer dielectric 1 is disposed between the logic processing layer 101 and the in-memory computing layer 102, and an interlayer dielectric 2 is disposed between the in-memory computing layer 102 and the storage array layer 103.

[0095] For example, the logic processing layer 101 can be configured to perform logic operations and / or control processing, the in-memory computing layer 102 can be configured to perform neural network operations on the received data, and the storage array layer 103 can be configured to store data for the in-memory computing layer.

[0096] For example, the logic processing layer 101 can perform operations such as combining, comparing, and filtering data from the in-memory computing layer 102, the storage array layer 103, or other input sources, generating new logic signals or data streams to support corresponding data processing tasks.

[0097] For example, the in-memory computing layer 102 can include at least one in-memory computing array, and each in-memory computing array includes at least one memristor array, and the memristor array can include a plurality of memristors arranged in multiple rows and columns.

[0098] For example, the storage array layer 103 can include a storage array, and the storage array can include a plurality of storage units arranged in multiple rows and columns, and each of the plurality of storage units can include a transistor and a magnetic random access memory device electrically connected to the transistor.

[0099] Again, for example, the transistor and the magnetic random access memory device can be arranged in a stacked form on the storage array layer 103, or can also be arranged in a planar form on the storage array layer 103.

[0100] Through the stacked design of the logic processing layer 101, the in-memory computing layer 102, and the storage array layer 103 in the embodiments of the present disclosure, it is not only beneficial to reduce the volume of the data processing device and improve the integration degree, but also can reduce the data transmission distance and delay between each circuit layer and improve the data processing speed.

[0101] In at least one embodiment of the present disclosure, a method for manufacturing a data processing device is further provided. The method for manufacturing the data processing device includes: preparing the in-memory computing layer using a semiconductor manufacturing process and preparing a storage array layer that is at least partially stacked with the in-memory computing layer, where the storage array layer includes a storage array, and the storage array includes a plurality of storage units arranged in multiple rows and columns, and each of the plurality of storage units includes a transistor and a magnetic random access memory device electrically connected to the transistor.

[0102] For example, the in-memory computing layer is prepared using a semiconductor manufacturing process, and the storage array layer is prepared using a semiconductor manufacturing process, and the storage array layer is at least partially stacked with the in-memory computing layer.

[0103] For example, the in-memory computing arrays in the in-memory computing layer are prepared using a semiconductor manufacturing process, and each in-memory computing array includes at least one memristor array, and the memristor array includes a plurality of memristors arranged in multiple rows and columns.

[0104] For example, in the process of fabricating the memory array in the memory array layer using semiconductor manufacturing processes, either the transistors can be fabricated first and then the magnetic random access memory (MRAM) devices, or the MRAM devices can be fabricated first and then the transistors. The embodiments of the present disclosure do not limit the order of fabricating the MRAM devices and the transistors.

[0105] For fabricating the transistors, for example, a low-temperature back-end transistor fabrication process can be used. Here, the fabrication temperature can be, for example, a low-temperature process of less than or equal to 300 degrees Celsius (or 400 degrees Celsius). The transistors can include, for example, at least one of carbon nanotube transistors, indium-based oxide transistors, or low-temperature polysilicon transistors.

[0106] In some embodiments of the present disclosure, the method for fabricating the data processing device further includes providing a silicon substrate, fabricating a logic processing layer on the silicon substrate using semiconductor manufacturing processes, the in-memory computing layer being formed on a side of the logic processing layer away from the silicon substrate, and the memory array layer being formed on a side of the in-memory computing layer away from the silicon substrate.

[0107] For example, fabricating the logic processing layer can be implemented using a CMOS logic circuit fabrication process (or a silicon-based CMOS process) to manufacture CMOS transistors and other components to fabricate the logic processing circuit.

[0108] In some embodiments of the present disclosure, fabricating the MRAM devices in the memory array layer can include fabricating a mask to define a graphic region of the MRAM devices and using the mask to fabricate magnetic tunnel junctions.

[0109] For example, the mask can include a photoresist mask or a hard mask.

[0110] For example, the material of the mask can include a metal or an insulating medium.

[0111] To fabricate the hard mask, for example, a bilayer photoresist can be used to fabricate the hard mask through photolithography, depositing a metal or an insulating medium, and a lift-off process to define the graphic region of the MRAM devices.

[0112] For example, a bilayer resist process can also be used to define the pattern of the magnetic tunnel junction region. Exemplarily, a bottom resist and a top resist can be sequentially coated on the substrate for fabricating the magnetic tunnel junction region, and by controlling the exposure and development processes, the bottom resist can be patterned into a shape of a predetermined design, wherein after being processed, the top resist can form a partially suspended "eaves" structure above the edge of the pattern defined by the bottom resist.

[0113] For example, based on such an "eaves" bilayer resist structure, an insulating medium can also be deposited, and then immersed in a resist stripping solution to dissolve and strip off the photoresist, and the insulating medium attached above the photoresist can also be stripped off, thereby fabricating the interconnecting holes of the magnetic tunnel junctions.

[0114] It should be noted that the bottom photoresist in the embodiments of the present disclosure refers to the photoresist first coated on the substrate in the magnetic tunnel junction region, and the top photoresist refers to the photoresist coated on top of the bottom photoresist.

[0115] For the preparation of a photoresist mask, for example, various micro-nano sized photoresist masks can be prepared by methods such as ultraviolet lithography, direct write lithography (DWL), electron beam lithography (EBL), and ion beam lithography (IBL).

[0116] For example, a double-layer resist process can also be used to make a photoresist mask. The bottom photoresist is coated on the substrate in the magnetic tunnel junction region using the top photoresist to form a double-layer photoresist mask with a suspended upper layer.

[0117] For the preparation of a magnetic tunnel junction using a mask, for example, through a dry etching process, other regions outside the patterned area of the magnetic random access memory device can be etched to retain the patterned area of the magnetic random access memory device.

[0118] For example, the dry etching process adopted in the embodiments of the present disclosure may include: ion beam etching (IBE), atomic layer etching (ALE), reactive ion etching (RIE), or inductively coupled plasma etching (ICP), etc. The embodiments of the present disclosure do not limit the specific dry etching process adopted.

[0119] It should be noted that during the process of preparing a magnetic tunnel junction using the ion beam etching (IBE) process, if a vertical etching method is adopted, that is, when the ion beam current is at a 90-degree right angle (or close to 90 degrees) to the surface of the magnetic tunnel junction, a large number of protruding "burrs" may appear at the top edge of the fabricated magnetic tunnel junction. These "burrs" may have a negative impact on subsequent processes and device performance. Therefore, a variable angle etching method can be adopted. The magnetic tunnel junction is etched through the vertical angle component, and then the sidewalls of the magnetic tunnel junction are etched through other angle components (i.e., sidewall angle component etching) to reduce or even eliminate the "burr" phenomenon, and the secondary sputtering effect caused by ion beam etching can also be reduced, thereby improving the flatness, insulation, and magnetoresistance change rate of the magnetic tunnel junction and avoiding device failure.

[0120] Figure 7The figure shows a schematic diagram of a method for fabricating a magnetic random access memory device provided by at least one embodiment of the present disclosure. As Figure 7 shown, the magnetic tunnel junction can be etched first through the vertical angle component. For example, a relatively large angle can be used for etching (for example, the ion beam is at a 60-degree angle to the surface of the magnetic tunnel junction). Most of the material to be etched can be quickly removed, but this step may still generate a certain amount of burrs.

[0121] Subsequently, sidewall angle component etching is performed. For example, a relatively small angle can be used for etching (for example, the ion beam is at a 30-degree angle to the surface of the magnetic tunnel junction). In this step, the bombardment of the sidewalls by the ion beam is more effective, which can specifically remove the burrs generated during the previous etching process and further smooth the sidewalls.

[0122] In addition, attention should also be paid to the issues of cycling and cooling during the etching process. For example, after etching at each of the above different angles for a certain period of time (for example, 1 minute), the etching can be paused and the sample can be cooled for a certain period of time (for example, 3 minutes). Cooling can help reduce the probability of secondary sputtering of the material due to the thermal effect during the etching process, and is also beneficial to the stability of the sample structure and prevent the deterioration of the morphology caused by overheating.

[0123] For example, it can be carried out according to Figure 7 the etching steps at the two angles shown and repeated several times to gradually optimize the surface quality and sidewall morphology of the magnetic tunnel junction until the required etching effect is achieved.

[0124] In at least one embodiment of the present disclosure, through the variable angle etching technique, the burrs at the top edge of the magnetic tunnel junction can be effectively reduced or even eliminated, improving the flatness, insulation, and magnetoresistance change rate of the device, thereby enhancing the overall performance and yield of the device. By regulating the incident angle of the ion beam and the etching steps, the etching characteristics of the ion beam on the material at different angles and the removal effect on the generated burrs are cleverly utilized to achieve precise control of the fabrication process of the magnetic tunnel junction.

[0125] In some embodiments of the present disclosure, fabricating the magnetic random access memory device further includes: selecting a region on the surface of the in-memory computing layer with a root mean square roughness less than 1 nm or 0.2 nm to arrange the magnetic tunnel junction, and placing the magnetic tunnel junction at a staggered position from the memristor.

[0126] Here, when fabricating the in-memory computing layer, a polishing operation (such as chemical mechanical polishing (CMP)) is required. Through the synergistic effect of chemical etching and mechanical grinding, the undulations of the in-memory computing layer are removed to ensure an extremely low surface roughness (for example, the root mean square roughness is below 1 nm, or even below 0.2 nm).

[0127] In the process of manufacturing a magnetic random access memory device, for the method and beneficial effects of arranging the specific position of the magnetic tunnel junction, reference may also be made to the relevant descriptions of the foregoing embodiments, which will not be elaborated herein.

[0128] Taking the manufacturing method of a data processing device formed by stacking RRAM and SOT-MRAM as an example, the manufacturing method of the data processing device will be described exemplarily. For example, the following steps (1) to (5) of the manufacturing method are as follows:

[0129] (1) Provide a silicon substrate.

[0130] (2) Fabricate a logic circuit layer on the silicon substrate.

[0131] (3) Fabricate an in-memory computing layer on the logic circuit layer.

[0132] (4) Fabricate an MRAM memory device on the in-memory computing layer.

[0133] (5) Fabricate a transistor for the MRAM memory device on the in-memory computing layer.

[0134] For example, CMOS transistors and other components can be fabricated on the silicon substrate using a CMOS logic circuit fabrication process (or a silicon-based CMOS process) to fabricate a logic processing circuit.

[0135] For example, a back-end integration process at a low temperature (e.g., less than or equal to 400 degrees Celsius) can be used to fabricate the RRAM in-memory computing layer. For example, an exemplary method for fabricating a storage computing circuit layer may include the following steps:

[0136] (a) Deposit a stack of "lower electrode layer / random resistance layer / thermal enhancement layer / upper electrode layer".

[0137] (b) Use photolithography and dry etching processes to selectively etch the stack to achieve patterning of the resistive random access memory device.

[0138] (c) Use plasma-enhanced chemical vapor deposition to deposit a passivation layer (such as a SiO2 thin film).

[0139] (d) Use photolithography, dry etching or wet etching processes to etch the passivation layer to form via holes for interconnects.

[0140] (e) Electroplate to deposit a layer of tungsten (W), and then use chemical mechanical polishing to polish away the W except for the SiO2 holes (forming metal vias).

[0141] (f) Use physical vapor deposition to deposit metal Al.

[0142] (g) Use photolithography and dry etching processes to selectively etch Al to form Al metal interconnects.

[0143] Figure 8 The flowchart shows a method for fabricating a magnetoresistive random access memory cell provided by at least one embodiment of the present disclosure. As Figure 8 shown, the method for fabricating an MRAM storage device may include steps S210 - S250.

[0144] (a) S210, fabricate the SOT - MRAM stack.

[0145] For example, techniques such as magnetron sputtering or molecular beam epitaxy (MBE) can be used to sequentially deposit: an insulating dielectric layer, a first electrode layer, a free layer, a barrier layer, a pinned layer,

[0146] a multi - layer thin - film stack of a second electrode layer.

[0147] The material of the first electrode layer can include, for example, metals with a relatively strong spin - orbit coupling effect

[0148] (such as Pt, W, Ta, or alloys, etc.). The film thickness of the first electrode layer can be 0 - 6 nm; for example, the antiferromagnetic layer in the free layer can be used as the first electrode layer.

[0149] The free layer can include an exchange - coupled layer formed by sequentially laminating an antiferromagnetic layer and a ferromagnetic layer. The ferromagnetic layer material can use CoFeB or Co material systems, and the film thickness of the ferromagnetic layer can be 0.8 - 1.4 nm. The material of the antiferromagnetic layer in the free layer can include collinear antiferromagnetic materials

[0150] (such as Mn 2 Au), non - collinear antiferromagnetic materials (such as IrMn 3 , PtMn 3 or Mn 3 Sn) or spin - splitting antiferromagnetic materials (such as, RuO 2 , Mn 5 Si 3 ) etc. The film thickness of the antiferromagnetic layer in the free layer can be, for example, 4 - 8 nm.

[0151] The material of the barrier layer can be an insulating material, for example, it can include MgO. The film thickness of the barrier layer can be 1 - 2 nm.

[0152] The pinning layer may include an artificial antiferromagnetic structure. The pinning layer may include a ferromagnetic layer, a nonmagnetic metal layer, a ferromagnetic layer, and an antiferromagnetic layer stacked in sequence. The material of the ferromagnetic layer in the pinning layer may include CoFeB or Co material, etc. The film thickness of the ferromagnetic layer in the pinning layer may be, for example, 0.8 - 1.4 nm. The material of the antiferromagnetic layer in the pinning layer may include IrMn3 or PtMn3, etc. The film thickness of the antiferromagnetic layer in the pinning layer may be, for example, 5 - 10 nm. The material of the nonmagnetic metal layer in the pinning layer may include Ru or Ta, etc. The film thickness of the nonmagnetic metal layer in the pinning layer may be, for example, 0.4 - 1.5 nm. The material of the second electrode may include metal materials such as Pt, W, or Ta

[0153] or alloy materials. The film thickness of the second electrode may be, for example, 5 - 20 nm.

[0154] (b) S220, fabricate the SOT - MRAM magnetic tunnel junction.

[0155] For example, various micro - and nano - sized photoresist masks can be fabricated first using process methods such as ultraviolet lithography, laser direct writing, electron beam lithography, ion beam lithography, etc., or a hard mask can be made using a bilayer photoresist through processes such as lithography, deposition, and lift - off to define the graphic area of the MRAM. Additionally, a photoresist mask can be made using a bilayer resist process, where the top resist forms a partially suspended magnetic tunnel junction structure on the bottom resist of the magnetic tunnel junction. Then, through dry etching processes such as ion beam etching, atomic layer etching, reactive ion etching, or inductively coupled plasma etching, the area outside the MRAM pattern is etched away, and the MRAM pattern area is retained. It should be noted that if a photoresist mask is used to fabricate the magnetic tunnel junction, the photoresist mask needs to be removed finally.

[0156] (c) S230, fabricate the insulating layer.

[0157] For example, methods such as magnetron sputtering, chemical vapor deposition, plasma - enhanced chemical vapor deposition, or atomic layer deposition can be used to deposit an insulating layer (e.g., silicon oxide SiO 2 or aluminum oxide Al 2 O 3 and other insulating dielectric films) over the entire device surface.

[0158] (d) S240, fabricate the interconnect vias.

[0159] For example, the opening area patterns of the second electrode and the first electrode can be defined first using a lithography process, and then the insulating layer can be etched using a dry etching process or a wet etching process to complete the opening, exposing the connection holes of the two first electrodes and one second electrode, forming an interconnect connection point, and finally removing the photoresist.

[0160] In some embodiments of the present disclosure, during the process of fabricating the SOT-MRAM magnetic tunnel junction, for example, after performing lithography and etching processes, the photoresist mask may not be removed, and the insulating layer may be directly deposited. Then, the photoresist mask may be stripped through a corresponding photoresist removal process, and via holes may be fabricated.

[0161] (e) S250, fabricate the interconnect electrodes and wires.

[0162] For example, an electroplating process or a chemical vapor deposition process may be used to deposit a conductive layer, such as depositing tungsten (W). Then, chemical mechanical polishing (CMP) may be used for planarization processing to grind away the conductive layer outside the opening, such as tungsten W, and only retain the conductive layer inside the opening, such as tungsten W, to form a metal via. Then, a physical vapor deposition (PVD) process is used to deposit a conductive layer, such as aluminum (Al). Then, dry etching processes such as lithography and ICP are used to selectively etch the conductive layer, such as aluminum Al, to form conductive interconnect leads.

[0163] It should be noted that when fabricating the interconnect electrodes and wires, a double-layer resist lithography process may also be used to define the pattern of the wire region to achieve the conductive interconnection between the second electrode and the first electrode of the MRAM and external devices or circuits. Since this lithography uses a double-layer resist process, a double-layer photoresist structure with the top resist edge suspended on the bottom resist of the magnetic tunnel junction will be formed. Then, a conductive layer (such as Au, Pt, Pd, Al, Cu, W, or TiN) is deposited using techniques such as electron beam evaporation coating or magnetron sputtering. If the adhesion of the conductive layer is poor, an adhesion layer (such as Ti, Cr, or Ta) may be deposited first, and then the conductive layer. The thickness of the deposited conductive layer may be less than half of the thickness of the bottom resist, for example. Then, the conductive layer region supported by the photoresist may be removed in acetone or other photoresist removal solutions, and the conductive layer pattern in the region without photoresist is retained. In addition, this step may also be assisted by auxiliary operations such as long-term soaking, ultrasonic treatment, or heating.

[0164] (f) Annealing operation.

[0165] For example, after the deposition of the SOT-MRAM multi-layer thin film is completed, an annealing operation is required to achieve the crystallization of the MgO barrier layer, improve the interface quality between the ferromagnetic layer and the barrier layer, and thus increase the magnetoresistance value of the tunnel junction. This annealing operation may be performed, for example, in a high-temperature combined magnetic field environment. The annealing temperature may be set to 200 - 350 degrees Celsius, the magnetic field direction may be set to the easy axis direction of the SOT-MRAM free layer, such as perpendicular (or approximately perpendicular) to the film surface, and the magnetic field intensity may be set to 500 - 10000 Oe.

[0166] For example, the transistor for MRAM in step (5) above can adopt a back-end integration preparation method at a low temperature (less than or equal to four hundred degrees Celsius). Here, the channel material of the transistor can include: carbon nanotubes, indium gallium zinc oxide, low-temperature polysilicon, indium oxide In 2 O 3 and other semiconductor channel materials.

[0167] The following takes the preparation method of a carbon nanotube transistor as an example to exemplarily describe the method for preparing a back-end transistor. For example, the preparation method of a carbon nanotube transistor can include the following steps:

[0168] (a) Adopt a photolithography process, deposit a metal target Pd by electron beam evaporation coating deposition process, and then strip to form a pattern as the back gate structure of the carbon nanotube transistor.

[0169] (b) Use atomic layer deposition technology to grow Al 2 O 3 and HfO 2 insulating layer as the gate oxide dielectric.

[0170] (c) Adopt photolithography and wet etching processes to selectively etch Al 2 O 3 and HfO 2 regions to achieve gate oxide opening.

[0171] (d) Adopt a wet transfer process to deposit a layer of carbon nanotubes.

[0172] (e) Adopt photolithography, electron beam evaporation of 80 nm Pd, and then strip to form a pattern as the source and drain electrodes of the carbon nanotube transistor.

[0173] (f) Adopt photolithography and oxygen plasma etching processes to selectively etch carbon nanotubes to isolate different devices.

[0174] (g) Use atomic layer deposition to grow 45 nm Al 2 O 3 as the passivation layer.

[0175] (h) Adopt photolithography and wet etching processes to selectively etch Al 2 O 3 to form electrode contact holes.

[0176] (i) Adopt subsequent passivation processes and metal interconnection processes to form a metal interconnection pattern.

[0177] Figure 9 shows a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. As Figure 9 shown, the electronic device 300 includes a data processing device 400.

[0178] For example, the data processing device 400 may be the data processing device provided in any of the above embodiments. For example, the electronic device 300 may further include other devices, such as a central processing unit (CPU), a data bus, a memory, etc. The electronic device 300 may be a signal processing device, a computing device, etc. For example, it may be used for a controller, a terminal device, or a server device, etc.

[0179] In addition to the above exemplary description, the following points of the present disclosure need to be noted:

[0180] (1) The drawings of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0181] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0182] (3) It should be understood that in the embodiments of the present disclosure, the magnitudes of the sequence numbers of the above steps do not mean the order of execution. The order of execution of each step should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure.

[0183] As described above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claimed rights.

Claims

1. A data processing device, comprising: Logical processing layer, in-memory computing layer, and storage array layer, wherein the logic processing layer, the in-memory computing layer and the storage array layer are at least partially stacked; The logic processing layer is configured to perform logic operations and / or control processing; The in-memory computing layer is configured to perform a neural network operation on received data, and the storage array layer is configured to store data for the in-memory computing layer; The memory array layer includes a memory array, the memory array includes a plurality of memory cells arranged in a plurality of rows and columns, each of the plurality of memory cells includes a transistor and a magnetic random access memory device electrically connected to the transistor; The logic processing layer is arranged on a silicon substrate, the in-memory computing layer is arranged on a side of the logic processing layer away from the silicon substrate, and the storage array layer is arranged on a side of the in-memory computing layer away from the silicon substrate.

2. The data processing device according to claim 1, wherein: The magnetic random access memory device includes a first electrode layer, a free layer, a barrier layer, a pinned layer and a second electrode layer which are stacked in sequence.

3. The data processing device according to claim 2, wherein: The free layer includes an antiferromagnetic layer and a ferromagnetic layer stacked in sequence.

4. The data processing device according to any one of claims 1 to 3, wherein: The in-memory computing layer includes at least one in-memory computing array, each of the in-memory computing arrays includes at least one memristor array, and the memristor array includes a plurality of memristors arranged in a plurality of rows and columns; The magnetic random access memory device comprises a magnetic tunnel junction, and the magnetic tunnel junction and the memristor are placed at staggered positions.

5. The data processing device according to any one of claims 1 to 3, wherein: The transistor includes at least one of a carbon nanotube transistor, an indium-based oxide transistor, or a low-temperature polysilicon transistor.

6. The data processing device according to any one of claims 1 to 3, wherein: The magnetic random access memory device includes a spin transfer torque magnetic random access memory device or a spin orbit torque magnetic random access memory device.

7. An electronic device, comprising the data processing device as claimed in any one of claims 1 to 6.

8. A method for preparing a data processing device, comprising: A semiconductor manufacturing process is used to prepare an in-memory computing layer and a storage array layer at least partially stacked with the in-memory computing layer. wherein the in-memory computing layer is configured to perform a neural network operation on received data, and the storage array layer is configured to store data for the in-memory computing layer; The memory array layer includes a memory array, the memory array includes a plurality of memory cells arranged in a plurality of rows and columns, each of the plurality of memory cells includes a transistor and a magnetic random access memory device electrically connected to the transistor; Wherein, the preparation method further comprises: providing a silicon substrate; A logic processing layer is prepared on the silicon substrate by using a semiconductor preparation process. The logic processing layer is configured to perform logic operations and / or control processing, the in-memory computing layer is formed on a side of the logic processing layer away from the silicon substrate, and the storage array layer is formed on a side of the in-memory computing layer away from the silicon substrate.

9. The preparation method according to claim 8, wherein: The preparation of the magnetic random access memory device comprises: Preparing a mask to define a pattern area of ​​the magnetic random access memory device, wherein the mask comprises a photoresist mask or a hard mask; A magnetic tunnel junction is fabricated using the mask.

10. The preparation method according to claim 9, wherein: The step of preparing a mask to define a pattern area of ​​the magnetic random access memory device comprises: A double-layer glue process is used to define the pattern of the magnetic tunnel junction area.

11. The preparation method according to claim 9, wherein: The method of using the mask to prepare a magnetic tunnel junction comprises: Through a dry etching process, other areas outside the graphic area of ​​the magnetic random access memory device are etched to retain the graphic area of ​​the magnetic random access memory device.

12. The preparation method according to claim 8, wherein: The in-memory computing layer includes at least one in-memory computing array, each of the in-memory computing arrays includes at least one memristor array, and the memristor array includes a plurality of memristors arranged in a plurality of rows and columns; The method of preparing the magnetic random access memory device further comprises: A region on the surface of the memristor with a root mean square roughness of less than 1 nm or 0.2 nm is selected to arrange a magnetic tunnel junction, and the magnetic tunnel junction and the memristor are placed at staggered positions.

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