A correction system and correction method for storage particle reading voltage

Abstract

The present invention provides a correction system and correction method for storage particle read voltage, the correction system for storage particle read voltage comprises: a power module, used to supply power to storage particles; a controller, electrically connected to the storage particles, the controller adjusts a certain threshold voltage of the storage unit by several offset intervals, obtains an offset voltage corresponding to the threshold voltage, and keeps other threshold voltages of the storage unit as initial voltages; after writing host data to the storage particles, when the storage unit is a certain offset voltage and other initial voltages, reads the original data on the storage particles, compares the host data with the original data, and counts the number of error bits corresponding to a certain offset voltage; counts the number of error bits corresponding to each offset voltage, and generates each offset voltage corresponding to the error bit number less than the threshold number as the read voltage of the storage unit. The present invention can improve the accuracy of the storage unit read voltage and improve the error correction performance of the storage particles.

Description

Technical Field

[0001] The present invention relates to the field of static storage technology, and in particular to a correction system and method for storage particle reading voltage. Background Art

[0002] In the field of storage where flash memory is used as a storage medium, as the number of bits stored in a storage cell increases, the storage density will increase significantly, but it will also be accompanied by a tighter distribution of the threshold voltage (Vth) of each state in the storage cell. When a storage cell read error occurs, the prior art determines the best read voltage in the storage cell in two ways: one is to traverse all read voltages and then select the read voltage with the smallest number of error bits as the best read voltage, but the smallest number of error bits has a certain degree of randomness. Another way is to select the voltage at the intersection of each state as the best read voltage in the threshold voltage curve, but the threshold voltage curve has a large volatility, and it is difficult to accurately select the best read voltage. Therefore, there is room for improvement. Summary of the invention

[0003] The present invention provides a correction system and correction method for storage particle read voltage, so as to solve the technical problem that it is difficult to accurately determine the best read voltage of the existing storage unit after a read error occurs.

[0004] The present invention provides a storage particle reading voltage correction system, comprising:

[0005] A power module, used to supply power to a storage cell, on which a threshold voltage of a storage unit is marked, and the threshold voltage has a corresponding offset interval;

[0006] A controller electrically connected to the memory cell, wherein the controller adjusts a threshold voltage of the memory cell by a plurality of offset intervals to obtain an offset voltage corresponding to the threshold voltage, and maintains other threshold voltages of the memory cell as initial voltages;

[0007] After the controller writes the host data to the storage particle, the controller reads the original data on the storage particle when the storage unit is a certain offset voltage and other initial voltages, compares the host data with the original data, and counts the number of error bits corresponding to the certain offset voltage;

[0008] The controller counts the number of error bits corresponding to each offset voltage, and generates each offset voltage corresponding to a number of error bits less than a threshold number as a read voltage of the memory cell.

[0009] In one embodiment of the present invention, after counting the number of error bits corresponding to each offset voltage, the controller generates each offset voltage corresponding to the minimum value of the number of error bits as a read voltage of the storage unit.

[0010] In one embodiment of the present invention, the threshold number is ,satisfy:

[0011] ;

[0012] ;

[0013] ;

[0014] in, , ,……, The number of error bits corresponding to the offset voltage adjusted for the continuous offset interval, for , ,……, The average value of is the offset, which takes into account the random value of the number of error bits corresponding to the offset voltage and the rate of change of the number of error bits on both sides of the offset voltage. , is a non-zero constant to reflect the robustness of the offset voltage.

[0015] In one embodiment of the present invention, after a certain threshold voltage is adjusted for 2P consecutive offset intervals, multiple offset voltages are obtained. On the side where the multiple offset voltages have smaller values, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number, When , the offset voltage with the smallest value among (3 / 5~4 / 5)P is recorded as the minimum voltage, and P is a non-zero constant;

[0016] On the side where the multiple offset voltage values ​​are larger, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number When , the offset voltage with the largest value in (3 / 5~4 / 5)P is recorded as the maximum voltage;

[0017] Generate an offset voltage between a minimum voltage and a maximum voltage as a read voltage of the memory cell;

[0018] A center voltage between the minimum voltage and the maximum voltage is generated as an optimal read voltage for the memory cell.

[0019] In one embodiment of the present invention, in one of the storage units, the controller increases or decreases a threshold voltage by several offset intervals to obtain a plurality of offset voltages corresponding to the threshold voltage.

[0020] In one embodiment of the present invention, in one of the storage units, the controller sequentially adjusts one of the threshold voltages to an offset voltage according to the order of magnitude of the multiple threshold voltages, keeps the other threshold voltages as initial voltages, and counts the number of error bits corresponding to each offset voltage.

[0021] The present invention also provides a method for correcting a storage particle read voltage, comprising:

[0022] Acquire a threshold voltage of a storage unit marked on a storage particle, the threshold voltage having a corresponding offset interval, and perform power-on processing on the storage particle;

[0023] After adjusting a certain threshold voltage of the memory cell by several offset intervals, an offset voltage corresponding to the threshold voltage is obtained, and other threshold voltages of the memory cell are kept as initial voltages;

[0024] After writing host data to the storage particle, when the storage unit is at a certain offset voltage and other initial voltages, reading the original data on the storage particle, comparing the host data with the original data, and counting the number of error bits corresponding to the certain offset voltage;

[0025] The number of error bits corresponding to each offset voltage is counted, and each offset voltage corresponding to a number of error bits less than a threshold number is generated as a read voltage of the memory cell.

[0026] In one embodiment of the present invention, the step of generating each offset voltage corresponding to the error bit number being less than the threshold number as the read voltage of the storage unit includes:

[0027] After counting the number of error bits corresponding to each offset voltage, each offset voltage corresponding to the minimum value of the number of error bits is generated as a read voltage of the memory cell.

[0028] In one embodiment of the present invention, the threshold number is ,satisfy:

[0029] ;

[0030] ;

[0031] ;

[0032] in, , ,……, The number of error bits corresponding to the offset voltage adjusted for the continuous offset interval, for , ,……, The average value of is the offset, which takes into account the random value of the number of error bits corresponding to the offset voltage and the rate of change of the number of error bits on both sides of the offset voltage. , is a non-zero constant to reflect the robustness of the offset voltage.

[0033] In one embodiment of the present invention, the step of generating each offset voltage corresponding to the number of error bits being less than a threshold number as a read voltage of the memory cell comprises:

[0034] After a certain threshold voltage is adjusted for 2P consecutive offset intervals, multiple offset voltages are obtained. On the side where the multiple offset voltages have smaller values, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number When , the offset voltage with the smallest value among (3 / 5~4 / 5)P is recorded as the minimum voltage, and P is a non-zero constant;

[0035] On the side where the multiple offset voltage values ​​are larger, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number When , the offset voltage with the largest value in (3 / 5~4 / 5)P is recorded as the maximum voltage;

[0036] Generate an offset voltage between a minimum voltage and a maximum voltage as a read voltage of the memory cell;

[0037] A center voltage between the minimum voltage and the maximum voltage is generated as an optimal read voltage for the memory cell.

[0038] Beneficial effects of the present invention: The present invention provides a storage cell read voltage correction system and correction method, which can greatly improve the accuracy and robustness of the storage cell read voltage and improve the error correction performance of the storage cell. When a storage cell read error occurs, the host data can be successfully read by switching the read voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A schematic diagram of the distribution of the threshold voltage of a memory cell is provided for the prior art.

[0041] Figure 2 A schematic diagram of the structure of a correction system for storage particle reading voltage provided by an embodiment of the present invention.

[0042] Figure 3 A schematic diagram of the distribution of threshold voltages of memory cells provided by an embodiment of the present invention.

[0043] Figure 4 A schematic diagram of the distribution of the number of error bits of a memory cell under different offset voltages provided by an embodiment of the present invention.

[0044] Figure 5 An embodiment of the present invention provides Figure 4 Schematic diagram of the distribution of the number of error bits and offset voltage near the valley bottom corresponding to the V2 voltage.

[0045] Figure 6 A schematic diagram showing a comparison between the present embodiment and the prior art when a storage unit provided by an embodiment of the present invention writes host data at a low temperature and reads original data at a high temperature.

[0046] Figure 7 A schematic diagram showing a comparison between a storage unit provided in an embodiment of the present invention and the prior art after the storage unit has been erased and written multiple times and has been baked at high temperature.

[0047] Figure 8 A schematic diagram of the steps of a method for correcting a storage particle read voltage provided by an embodiment of the present invention.

[0048] Fig. 9 An embodiment of the present invention provides Figure 8 Schematic diagram of steps after step S40 in FIG.

[0049] Description of Figure Numbers

[0050] 10. Controller; 20. Power module; 30. Storage particles; 31. Block; 410. Waveform segment; 420. Valley bottom segment. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0052] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0053] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0054] See also Figures 1 to 9 The present invention proposes a correction system and correction method for storage particle read voltage, which can be applied to storage devices such as eMMC (Embedded Multi Media Card), SSD (Solid State Disk), and UFS (Univeral Flash Storage). The present invention can greatly improve the accuracy and robustness of the storage unit read voltage, and can improve the error correction performance of the controller 10 for the storage particle 30. When a read error occurs in the storage particle 30, the present application can switch the read voltage to successfully read the host data, and the host data refers to the application data written by the controller 10. The following is a detailed description through specific embodiments.

[0055] See also Figure 2In one embodiment of the present invention, a correction system for reading voltage of a storage particle is proposed, which may include a controller 10, a power module 20 and a storage particle 30, wherein the power module 20 is used to supply power to the storage particle. The storage particle 30 is provided with a bus interface, and the storage particle 30 is electrically connected to the controller 10 and the power module 20 through the bus interface. The controller 10 may write host data and send instructions to the storage particle 30, or the controller 10 may read host data and receive instructions from the storage particle 30. The controller 10 may be a processor in a communication device such as a personal computer (PC), a tablet computer (Pad), or a mobile phone (Cell Phone).

[0056] See also Figure 2 In one embodiment of the present invention, the storage particle 30 may be a flash memory particle, which is a non-volatile memory, usually used to store host data and system programs. The storage particle 30 may include a plurality of blocks 31, and the block 31 may be used to store the host data written by the controller 10. A block 31 may also include a plurality of pages. The block 31 is an erase unit of the host data on the storage particle 30, and the page is a read unit of the host data on the storage particle 30. The storage unit of the block 31 may be a single-level cell (SLC), a double-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and the like.

[0057] See also Figure 2 and Figure 3 In one embodiment of the present invention, the storage particles 30 are read in units of pages. For example, for a single-layer storage cell, one threshold voltage (A) is used to distinguish between two storage states 0 or 1. A single-layer storage cell is a one-bit storage and has only one page. For a two-layer storage cell, three threshold voltages (A, B, C) are used to distinguish between four storage states 11, 01, 10 or 00. A double-layer storage cell is a two-bit storage, with two pages, namely a low page (Low Page) and an upper page (UpPage), where the low page (1, 0, 1, 0) is read with threshold voltages A and C to determine whether the stored information is 0 or 1. The upper page (1, 1, 0, 0) is read with threshold voltage B to determine whether the stored information is 0 or 1.

[0058] See also Figure 2 and Figure 3In one embodiment of the present invention, for a three-layer storage cell, seven threshold voltages (A, B, C, D, E, F, G) are used to distinguish eight storage states 111, 101, 100, 110, 010, 011, 001 or 000. The three-layer storage cell is a three-bit storage, with three pages, namely, a low page (Low Page), a middle page (Middle Page) and an up page (Up Page). In the storage cell of the storage particle 30, data is read by a read voltage. When the storage state of the storage cell is lower than the read voltage, the storage cell is turned on when the read voltage is applied to the gate of the storage cell. Conversely, when the storage state of the storage cell is higher than the read voltage, the storage cell is turned off when the read voltage is applied to the gate of the storage cell.

[0059] Specifically, Figure 3 As shown, the lower page (1, 1, 1, 1, 0, 0, 0, 0) is distinguished by the threshold voltage D to determine whether the storage information is 0 or 1. When the read voltage is greater than the threshold voltage D, the storage information on the lower page is 0, otherwise when the read voltage is less than or equal to the threshold voltage D, the storage information on the lower page is 1.

[0060] Specifically, Figure 3 As shown, the middle page (1, 0, 0, 1, 1, 1, 0, 0) is distinguished by threshold voltages A, C, and F to determine whether the storage information is 0 or 1. When the read voltage is less than or equal to the threshold voltage A, the storage information on the middle page is 1, when the read voltage is greater than the threshold voltage A and less than or equal to the threshold voltage C, the storage information on the middle page is 0, when the read voltage is greater than the threshold voltage C and less than or equal to the threshold voltage F, the storage information on the middle page is 1, and when the read voltage is greater than the threshold voltage F, the storage information on the middle page is 0.

[0061] Specifically, Figure 3 As shown, the high page (1, 1, 0, 0, 0, 1, 1, 0) is distinguished by threshold voltages B, E, and G to determine whether the storage information is 0 or 1. When the read voltage is less than or equal to the threshold voltage B, the storage information on the high page is 1, when the read voltage is greater than the threshold voltage B and less than or equal to the threshold voltage E, the storage information on the middle page is 0, when the read voltage is greater than the threshold voltage E and less than or equal to the threshold voltage G, the storage information on the middle page is 1, and when the read voltage is greater than the threshold voltage G, the storage information on the middle page is 0.

[0062] It can be seen that the raw data (Raw Data) on the least significant bit (LSB) corresponding to the low page is distinguished by the threshold voltage D. The raw data refers to the initial data directly read by the controller 10 from the storage particle 30, which has not been processed by the error checking and correction technology (ECC). For the host data written by the controller 10 to the storage particle 30, and the raw data directly read by the controller 10 from the storage particle 30, the number of error bits on the storage particle 30 can be obtained by comparing the host data with the raw data. When a read error occurs in the storage particle 30, the number of error bits (Error BitCount) generated after the raw data on the low page is read is only related to the selection of the threshold voltage D, and has nothing to do with the selection of the threshold voltages A, B, C, E, F, and G. Similarly, when a read error occurs in the storage particle 30, the number of error bits generated after the raw data on the middle page is read is only related to the threshold voltages A, C, and F, and the number of error bits generated after the raw data on the high page is read is only related to the threshold voltages B, E, and G.

[0063] See also Figure 2 and Figure 3 In one embodiment of the present invention, the threshold voltage of the storage unit is marked on the storage particle 30, and the threshold voltage has a corresponding offset range. When the storage particle 30 leaves the factory, the manufacturer can configure the threshold voltage and reread table (Read Retry Table) corresponding to the storage unit. When the storage particle 30 is in normal use, by comparing the read voltage and the threshold voltage (Vth), it can be determined whether the storage information on the storage cell is 0 or 1. When a storage particle 30 read error occurs, for example, the number of bit flips on the storage particle 30 is too large, the reread gear in the reread table provided by the manufacturer of the storage particle 30 is required for rereading. The reread gear in the reread table has certain limitations and cannot cover many real application scenarios, so it is necessary to adaptively adjust the reread gear.

[0064] See also Figure 2 and Figure 3In one embodiment of the present invention, when the storage particle 30 leaves the factory, a number of offset intervals offset to the left and right with the threshold voltage as the center will be provided accordingly, for example, 128 offset intervals. After the threshold voltage (Vth) is offset to the left and right by a number of offset intervals, for example, 128 offset intervals, 256 offset voltages can be obtained. When a read error occurs in the storage particle 30, the controller 10 can adjust the offset intervals of several threshold voltages to obtain several corresponding offset voltages, retain other threshold voltages as the initial voltage provided by the manufacturer, and reread the flash memory particles to test the number of error bits of the storage particles 30.

[0065] Specifically, Figure 3 and Figure 4 As shown, a three-layer storage unit is used for illustration. The number of error bits generated after reading the original data on the middle page is related to the threshold voltages A, C, and F. Therefore, when considering the number of error bits corresponding to a certain offset voltage, the other two offset voltages should be configured as the optimal reading voltage, that is, the number of error bits corresponding to the other two offset voltages should be the minimum value. When a read error occurs in the storage particle 30, the local optimum can be used to obtain the global optimum for analysis.

[0066] Specifically, Figure 3 and Figure 4 As shown, a certain offset voltage can be set and other initial voltages can be maintained to test the number of error bits corresponding to a certain offset voltage of the storage particle 30, and then the number of error bits corresponding to each offset voltage can be obtained. At each offset voltage, the number of error bits is compared with the threshold number. When the number of error bits is less than the threshold number, the offset voltage corresponding to the number of error bits can be recorded as the best reading voltage. The threshold number is a non-zero constant, such as 5, 10 or 15. The threshold number is used to reflect the number of error bits. It can be considered that when the number of error bits is less than the threshold number, the offset voltage corresponding to the number of error bits can be used as the best reading voltage.

[0067] Specifically, each offset voltage corresponding to the number of error bits being less than the threshold number is used to generate a read voltage of the storage unit, and when a read error occurs in the storage particle 30, the storage particle 30 is reread according to the read voltage. When a read error occurs in the storage particle 30, the read voltage can be switched to successfully read the host data on the storage particle 30. This embodiment can greatly improve the accuracy and robustness of the storage unit read voltage, and can improve the error correction performance of the storage particle 30.

[0068] Specifically, Figure 3 and Figure 4As shown, by comparing the magnitude relationship between the read voltage and the read voltage, it is determined whether the storage information on the storage cell is 0 or 1. For example, in a three-layer storage cell, after the threshold voltage D is adjusted by the offset interval, and the number of error bits is less than the threshold number, a read voltage D' can be obtained. When the read voltage is greater than the read voltage D' obtained above, the storage information on the low page is 0, and conversely when the read voltage is less than or equal to the read voltage D' obtained above, the storage information on the low page is 1. This embodiment can greatly improve the accuracy of the optimal read voltage of the storage particle 30.

[0069] See also Figure 4 and Figure 5 In one embodiment of the present invention, Figure 4 and Figure 5 The horizontal axis is the value of the read voltage, and the vertical axis is the number of error bits. The read voltage is represented by symbols V1, V2, V3, V4, V5, V6 and V7, which correspond to threshold voltages A, B, C, E, F, G, that is, the read voltage V1 corresponds to the threshold voltage A. In a storage unit, the controller 10 increases or decreases a certain threshold voltage by several offset intervals to obtain multiple offset voltages corresponding to the threshold voltage. Taking V2 as an example, in this embodiment, after the threshold voltage B is offset to the left and right by several offset intervals, for example, after being offset to the left and right by 128 offset intervals, 256 offset voltages can be obtained. For example, taking V2[0×00] as the center line, the left side includes 128 offset voltages of V2[0×00], V2[0×01], V2[0×02], ... V2[0×ff], and the right side includes 128 offset voltages of V2[0×00], V2[0×01], V2[0×02], ... V2[0×ff].

[0070] See also Figure 4 and Figure 5 In one embodiment of the present invention, after counting the number of error bits corresponding to each offset voltage, the controller 10 generates each offset voltage corresponding to the minimum number of error bits as the read voltage of the storage unit. In a storage unit, the controller 10 adjusts one of the threshold voltages to the offset voltage in sequence according to the magnitude of multiple threshold voltages, keeps the other threshold voltages as the initial voltage, and counts the number of error bits corresponding to each offset voltage.

[0071] Specifically, Figure 5 As shown, the number of error bits corresponding to V2[0×00] is the smallest, so V2[0×00] can be used as the read voltage corresponding to threshold voltage B. Similarly, for V1, V3, V4, V5, V6 and V7, the offset voltage at the minimum number of error bits can be generated as the read voltage of the storage cell.

[0072] See also Figure 4 and Figure 5 In one embodiment of the present invention, the threshold number can be recorded as ,satisfy:

[0073] ;

[0074] ;

[0075] ;

[0076] in, , ,……, The number of error bits corresponding to the offset voltage adjusted for the continuous offset interval, for , ,……, The average value of is the offset, which takes into account the random value of the number of error bits corresponding to the offset voltage and the rate of change of the number of error bits on both sides of the offset voltage. , is a non-zero constant to reflect the robustness of the offset voltage.

[0077] Specifically, Figure 5 As shown, for the distribution of the number of error bits and the offset voltage near the valley corresponding to the V2 voltage, if the offset voltage V2[0×00] corresponding to the minimum number of error bits is selected as the reading voltage corresponding to the threshold voltage B, the curve on the right side of the offset voltage V2[0×00] rises quickly. When the storage particle 30 is affected by some factors such as data retention, the threshold voltage (Vth) curve may be biased to the left, and the number of error bits (Error Bit Count) will rise rapidly when V2[0×00] is used as the reading voltage. Therefore, in order to consider the robustness of the reading voltage, the offset voltage V2[0×00] corresponding to the minimum number of error bits as the reading voltage is not necessarily the best choice.

[0078] Specifically, Figure 5 As shown, in order to improve the robustness of the read voltage, the optimal read voltage value may be determined by determining the optimal read voltage window width. The bigger, The smaller the value, the larger the window of the optimal read voltage. In order to improve the robustness of the read voltage, the offset is a non-zero constant, the offset The random value of the number of error bits corresponding to the offset voltage and the rate of change of the number of error bits on both sides of the offset voltage can be taken into account. The changing rate of the number of error bits on the left and right sides of the reading voltage and the randomness of the number of error bits can be taken into consideration.

[0079] Specifically, Figure 5 As shown, after a certain threshold voltage is adjusted for 2P consecutive offset intervals, multiple offset voltages are obtained. On the side with smaller values ​​of multiple offset voltages, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number When the offset voltage with the smallest value among (3 / 5~4 / 5)P is recorded as the minimum voltage, P is a non-zero constant. On the side with larger values ​​of multiple offset voltages, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number When (3 / 5~4 / 5)P is equal to the maximum value, the offset voltage with the largest value is recorded as the maximum voltage. The offset voltage between the minimum voltage and the maximum voltage is generated as the read voltage of the memory cell. The center voltage between the minimum voltage and the maximum voltage is generated as the optimal read voltage of the memory cell. Figure 5 In the example, V2[0×f2] can be recorded as the minimum value, V2[0×f2] can be recorded as the maximum value, and the offset voltage between V2[0×f2] and V2[0×f2] can be generated as the read voltage of the memory cell.

[0080] In addition, Figure 5 In the above example, the number of error bits corresponding to the read voltage V2[0×f7] is greater than that corresponding to V2[0×f5], V2[0×f6], V2[0×f8], V2[0×f9], and V2[0×fa]. Therefore, if we do not consider the randomness of the number of error bits, that is, only consider the read voltage No consideration of offset , it is possible that the read voltage is only from V2[0×f8] to V2[0×00], which will result in a smaller range of read voltage values ​​and may be difficult to adapt to different usage scenarios.

[0081] See also Figure 6In one embodiment of the present invention, after the storage particles 30 are worn according to the number of erase cycles (PEC, ProgramErase Cycle) of 1 to 5001, low-temperature writing and high-temperature reading are taken as examples, for example, low-temperature writing is at -40°C and high-temperature reading is at 85°C, and a relationship curve between the maximum number of error bits (Max FBC) and the reread level (RR_Set) is obtained. Among them, the first 6 groups of the horizontal axis are the best read voltages selected by the embodiment of the present application, and the remaining 49 groups are the alternative voltages in the reread table (Read Retry Table) given by the manufacturer. It can be seen that the optimal voltage selected by the embodiment of the present application corresponds to the maximum number of error bits (Max FBC), which is obviously lower than the number of error bits corresponding to the alternative voltage given by the manufacturer.

[0082] See also Figure 7 In one embodiment of the present invention, taking the data retention test as an example, the storage particles 30 are worn according to the number of erase and write cycles (PEC, Program Erase Cycle) of 1~5001, and then baked at a high temperature of 100°C for 13 hours to obtain a relationship curve between the maximum number of error bits (Max FBC) and the reread level (RR_Set). Among them, the first 6 groups of the horizontal axis are all the best read voltages selected by the embodiment of the present application, and the remaining 49 groups are all the alternative voltages in the reread table (Read Retry Table) given by the manufacturer. It can be seen that the maximum number of error bits (Max FBC) of the best voltage selected by the embodiment of the present application is obviously lower than the number of error bits corresponding to the alternative voltage given by the manufacturer.

[0083] See also Figure 8 In one embodiment of the present invention, a method for correcting a storage particle read voltage is proposed, which may include the following steps.

[0084] Step S10: acquiring a threshold voltage of a storage unit marked on a storage particle, wherein the threshold voltage has a corresponding offset interval, and performing power-on processing on the storage particle.

[0085] Step S20 , after adjusting a threshold voltage of the memory cell by a plurality of offset intervals, an offset voltage corresponding to the threshold voltage is obtained, and other threshold voltages of the memory cell are kept at initial voltages.

[0086] Step S30, after writing the host data to the storage particle, read the original data on the storage particle when the storage unit is at a certain offset voltage and other initial voltages, compare the host data with the original data, and count the number of error bits corresponding to a certain offset voltage.

[0087] Step S40 , counting the number of error bits corresponding to each offset voltage, and generating each offset voltage corresponding to a number of error bits less than a threshold value as a read voltage of the memory cell.

[0088] The following is a detailed description through specific embodiments.

[0089] Step S10: acquiring a threshold voltage of a storage unit marked on a storage particle, wherein the threshold voltage has a corresponding offset interval, and performing power-on processing on the storage particle.

[0090] In one embodiment of the present invention, when the storage particle 30 leaves the factory, a number of offset intervals offset to the left and right with the threshold voltage as the center will be provided accordingly, for example, 128 offset intervals. After the threshold voltage (Vth) is offset to the left and right by a number of offset intervals, for example, 128 offset intervals, 256 offset voltages can be obtained. When a read error occurs in the storage particle 30, the controller 10 can adjust the offset intervals of several threshold voltages to obtain several corresponding offset voltages, retain other threshold voltages as the initial voltage provided by the manufacturer, and reread the flash memory particles to test the number of error bits of the storage particles 30.

[0091] Step S20 , after adjusting a threshold voltage of the memory cell by a plurality of offset intervals, an offset voltage corresponding to the threshold voltage is obtained, and other threshold voltages of the memory cell are kept at initial voltages.

[0092] In one embodiment of the present invention, Figure 4 and Figure 5 As shown, the horizontal axis is the value of the read voltage, and the vertical axis is the number of error bits. The read voltage is represented by symbols V1, V2, V3, V4, V5, V6 and V7, which correspond to the threshold voltages A, B, C, E, F, G, that is, the read voltage V1 corresponds to the threshold voltage A. In a storage unit, the controller 10 increases or decreases a certain threshold voltage by several offset intervals to obtain multiple offset voltages corresponding to the threshold voltage. Taking V2 as an example, in this embodiment, after the threshold voltage B is offset to the left and right by several offset intervals, for example, after being offset to the left and right by 128 offset intervals, 256 offset voltages can be obtained. For example, taking V2[0×00] as the center line, the left side includes 128 offset voltages of V2[0×00], V2[0×01], V2[0×02], ... V2[0×ff], and the right side includes 128 offset voltages of V2[0×00], V2[0×01], V2[0×02], ... V2[0×ff].

[0093] Step S30, after writing the host data to the storage particle, read the original data on the storage particle when the storage unit is at a certain offset voltage and other initial voltages, compare the host data with the original data, and count the number of error bits corresponding to a certain offset voltage.

[0094] In one embodiment of the present invention, a certain offset voltage can be set and other initial voltages can be maintained to test the number of error bits corresponding to a certain offset voltage of the storage particle 30, and then the number of error bits corresponding to each offset voltage can be obtained. At each offset voltage, the number of error bits is compared with the threshold number. When the number of error bits is less than the threshold number, the offset voltage corresponding to the number of error bits can be recorded as the best reading voltage. The threshold number is a non-zero constant, such as 5, 10 or 15. The threshold number is used to reflect the number of error bits. It can be considered that when the number of error bits is less than the threshold number, the offset voltage corresponding to the number of error bits can be used as the best reading voltage.

[0095] Step S40 , counting the number of error bits corresponding to each offset voltage, and generating each offset voltage corresponding to a number of error bits less than a threshold value as a read voltage of the memory cell.

[0096] In one embodiment of the present invention, each offset voltage corresponding to the error bit number being less than the threshold number is used to generate a read voltage of the storage unit. When a read error occurs in the storage cell 30 , the storage cell 30 is reread according to the read voltage.

[0097] See also Figure 5 and Figure 8 In one embodiment of the present invention, in step S40, the threshold number is ,satisfy:

[0098] ;

[0099] ;

[0100] ;

[0101] in, , ,……, The number of error bits corresponding to the offset voltage adjusted for the continuous offset interval, for , ,……, The average value of is the offset, which takes into account the random value of the number of error bits corresponding to the offset voltage and the rate of change of the number of error bits on both sides of the offset voltage. , is a non-zero constant to reflect the robustness of the offset voltage.

[0102] Specifically, Figure 5 As shown, in order to improve the robustness of the read voltage, the optimal read voltage value may be determined by determining the optimal read voltage window width. The bigger, The smaller it is, the larger the window of optimal reading voltage is.

[0103] Specifically, Figure 5 As shown, in order to improve the robustness of the read voltage, the offset is a non-zero constant, the offset The random value of the number of error bits corresponding to the offset voltage and the rate of change of the number of error bits on both sides of the offset voltage can be taken into account. It can take into account the change rate of the number of error bits on the left and right sides of the reading voltage and the randomness of the number of error bits. Figure 5 In the example, V2[0×f2] can be recorded as the minimum value, V2[0×f2] can be recorded as the maximum value, and the offset voltage between V2[0×f2] and V2[0×f2] can be generated as the read voltage of the memory cell.

[0104] In addition, Figure 5 In the above example, the number of error bits corresponding to the read voltage V2[0×f7] is greater than that corresponding to V2[0×f5], V2[0×f6], V2[0×f8], V2[0×f9], and V2[0×fa]. Therefore, if we do not consider the randomness of the number of error bits, that is, only consider the read voltage No consideration of offset , it is possible that the read voltage is only from V2[0×f8] to V2[0×00], which will result in a smaller range of read voltage values ​​and may be difficult to adapt to different usage scenarios.

[0105] See also Fig. 9 In one embodiment of the present invention, step S40 may include step S410, step S420 and step S430. Step S410 may be expressed as: after a certain threshold voltage is adjusted for 2P consecutive offset intervals, multiple offset voltages are obtained. On the side with smaller values ​​of the multiple offset voltages, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number, When the offset voltage with the smallest value among (3 / 5~4 / 5)P is recorded as the minimum voltage, P is a non-zero constant. Step S420 can be represented as: on the side with larger values ​​of multiple offset voltages, when the number of error bits corresponding to the (3 / 5~4 / 5)P offset voltages is less than the threshold number When (3 / 5~4 / 5) P is equal to the maximum voltage, the offset voltage with the largest value is recorded as the maximum voltage. Step S430 can be represented as generating the offset voltage between the minimum voltage and the maximum voltage as the read voltage of the memory cell, and generating the center voltage between the minimum voltage and the maximum voltage as the optimal read voltage of the memory cell.

[0106] In summary, the present invention proposes a correction system and correction method for storage cell read voltage, which can greatly improve the accuracy and robustness of storage cell read voltage and improve the error correction performance of storage cells. When a storage cell read error occurs, the host data can be successfully read by switching the read voltage.

[0107] The flow chart and block diagram in the accompanying drawings illustrate the possible implementation architecture, function and operation of the method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

Claims

1. A correction system for storage particle reading voltage, characterized in that: include: A power module, used to supply power to a storage cell, on which a threshold voltage of a storage unit is marked, and the threshold voltage has a corresponding offset interval; A controller electrically connected to the memory cell, wherein the controller adjusts a threshold voltage of the memory cell by a plurality of offset intervals to obtain an offset voltage corresponding to the threshold voltage, and maintains other threshold voltages of the memory cell as initial voltages; After the controller writes the host data to the storage particle, the controller reads the original data on the storage particle when the storage unit is a certain offset voltage and other initial voltages, compares the host data with the original data, and counts the number of error bits corresponding to the certain offset voltage; The controller counts the number of error bits corresponding to each offset voltage, and generates each offset voltage corresponding to a number of error bits less than a threshold number as a read voltage of the storage unit, wherein the threshold number is a non-zero constant; The threshold number is ,satisfy: ； ； ； in, , ,……, The number of error bits corresponding to the offset voltage adjusted for the continuous offset interval, for , ,……, The average value of is the offset, which takes into account the random value of the number of error bits corresponding to the offset voltage and the rate of change of the number of error bits on both sides of the offset voltage. , is a non-zero constant to reflect the robustness of the offset voltage.

2. The memory cell read voltage correction system according to claim 1, characterized in that: After counting the number of error bits corresponding to each offset voltage, the controller generates each offset voltage corresponding to a minimum value of the number of error bits as a read voltage of the memory cell.

3. The memory cell read voltage correction system according to claim 1, characterized in that: After a certain threshold voltage is adjusted for 2P consecutive offset intervals, multiple offset voltages are obtained. On the side where the multiple offset voltages have smaller values, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number When , the offset voltage with the smallest value among (3 / 5~4 / 5)P is recorded as the minimum voltage, and P is a non-zero constant; On the side where the multiple offset voltage values ​​are larger, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number When , the offset voltage with the largest value in (3 / 5~4 / 5)P is recorded as the maximum voltage; Generate an offset voltage between a minimum voltage and a maximum voltage as a read voltage of the memory cell; A center voltage between the minimum voltage and the maximum voltage is generated as an optimal read voltage for the memory cell.

4. The memory cell read voltage correction system according to claim 1, characterized in that: In one of the storage units, the controller increases or decreases a threshold voltage by several offset intervals to obtain a plurality of offset voltages corresponding to the threshold voltage.

5. The memory cell read voltage correction system according to claim 1, characterized in that: In one of the storage units, the controller sequentially adjusts one of the threshold voltages to an offset voltage according to the order of magnitude of the multiple threshold voltages, keeps the other threshold voltages as initial voltages, and counts the number of error bits corresponding to each offset voltage.

6. A method for correcting a storage particle reading voltage, characterized in that: include: Acquire a threshold voltage of a storage unit marked on a storage particle, the threshold voltage having a corresponding offset interval, and perform power-on processing on the storage particle; After adjusting a certain threshold voltage of the memory cell by several offset intervals, an offset voltage corresponding to the threshold voltage is obtained, and other threshold voltages of the memory cell are kept as initial voltages; After writing host data to the storage particle, when the storage unit is at a certain offset voltage and other initial voltages, reading the original data on the storage particle, comparing the host data with the original data, and counting the number of error bits corresponding to the certain offset voltage; Counting the number of error bits corresponding to each offset voltage, and generating each offset voltage corresponding to a number of error bits less than a threshold value as a read voltage of the memory cell; The threshold number is ,satisfy: ； ； ； in, , ,……, The number of error bits corresponding to the offset voltage adjusted for the continuous offset interval, for , ,……, The average value of is the offset, which takes into account the random value of the number of error bits corresponding to the offset voltage and the rate of change of the number of error bits on both sides of the offset voltage. , is a non-zero constant to reflect the robustness of the offset voltage.

7. The method for correcting the storage particle read voltage according to claim 6, characterized in that: The step of generating each offset voltage corresponding to the error bit number being less than the threshold number as the read voltage of the memory cell includes: After counting the number of error bits corresponding to each offset voltage, each offset voltage corresponding to the minimum value of the number of error bits is generated as a read voltage of the memory cell.

8. The method for correcting the storage particle read voltage according to claim 6, characterized in that: The step of generating each offset voltage corresponding to the error bit number being less than the threshold number as the read voltage of the memory cell comprises: After a certain threshold voltage is adjusted for 2P consecutive offset intervals, multiple offset voltages are obtained. On the side where the multiple offset voltages have smaller values, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number When , the offset voltage with the smallest value among (3 / 5~4 / 5)P is recorded as the minimum voltage, and P is a non-zero constant; On the side where the multiple offset voltage values ​​are larger, when the number of error bits corresponding to (3 / 5~4 / 5)P offset voltages is less than the threshold number When , the offset voltage with the largest value in (3 / 5~4 / 5)P is recorded as the maximum voltage; Generate an offset voltage between a minimum voltage and a maximum voltage as a read voltage of the memory cell; A center voltage between the minimum voltage and the maximum voltage is generated as an optimal read voltage for the memory cell.

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