Oscillation circuit with improved fault detection

Abstract

Apparatus and methods for non-invasively monitoring an oscillating signal to provide a more reliable oscillating signal. An example oscillation circuit generally includes an oscillator configured to generate an oscillating signal, the oscillator including an oscillator core circuit to couple to a resonator and configured to generate the oscillating signal to enable the resonator to resonate, and an adjustable current source coupled to the oscillator core circuit and configured to control an amplitude of the oscillating signal; a first automatic gain control (AGC) circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable current source; a second AGC circuit configured to replicate the first AGC circuit; and logic having a first input coupled to the output of the first AGC circuit and having a second input coupled to an output of the second AGC circuit.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of U.S. Patent Application No. 17 / 652,716, filed February 28, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Certain aspects of this disclosure relate generally to electronic circuits, and more specifically to circuits for monitoring oscillating signals. Background Technology

[0004] Electronic devices include computing devices such as desktop computers, laptops, tablets, smartphones, wearable devices such as smartwatches, and internet servers. These diverse electronic devices provide human users with information, entertainment, social interaction, security, safety, productivity, transportation, manufacturing, and / or other services. Many functions of these various electronic devices rely on wireless communication and can generate and utilize one or more oscillating signals for wireless communication and / or for synchronizing digital logic clock signals. Oscillating signals can be generated, for example, using a resonator (e.g., a quartz crystal or an inductor-capacitor (LC) resonant circuit, also known as a resonant circuit) and an oscillating core circuit to enable the resonator to resonate.

[0005] Wireless communication can include various types of communication content, such as voice, video, packet data, message sending and receiving, broadcasting, etc. Wireless communication devices can transmit and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobile Communications (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, and Wireless Local Area Network (WLAN) RATs (e.g., IEEE 802.11). To transmit or receive data and / or control information, the RF front-end of the wireless communication device may include one or more frequency synthesizers to generate oscillating signals for up-converting baseband signals and down-converting RF signals. For example, at least one of the frequency synthesizers may include a voltage-controlled oscillator (VCO) for tuning the oscillating signal to different frequencies.

[0006] To ensure reliable operation of electronic devices in many applications, the oscillation signal should be robust regardless of variations in process, voltage, and temperature (PVT). For example, it may be desirable for the oscillation signal to have a sufficiently high amplitude, even though the oscillation circuitry may vary due to PVT. Summary of the Invention

[0007] The systems, methods, and apparatus of this disclosure each have several aspects, none of which is solely responsible for their desired characteristics. Without limiting the scope of this disclosure as set forth in the appended claims, some features will now be briefly discussed. Upon consideration of this discussion, and particularly after reading the section entitled "Detailed Description," one will understand how the features of this disclosure provide the advantages described herein.

[0008] Certain aspects of this disclosure relate generally to techniques and apparatus for monitoring oscillating signals.

[0009] Some aspects provide an oscillation circuit. The circuit typically includes: an oscillator configured to generate an oscillating signal, the oscillator including an oscillator core circuit and an adjustable current source, the oscillator core circuit being coupled to a resonator and configured to generate the oscillating signal such that the resonator resonates, the adjustable current source being coupled to the oscillator core circuit and configured to control the amplitude of the oscillating signal; a first automatic gain control (AGC) circuit having an input coupled to the output of the oscillator and an output coupled to a control input of the adjustable current source; a second AGC circuit configured to replicate the first AGC circuit; and a logic element having a first input coupled to the output of the first AGC circuit and a second input coupled to the output of the second AGC circuit.

[0010] Some aspects provide an oscillation monitoring method. This method typically includes: generating an oscillation signal using an oscillator that drives a resonator; generating a first signal based on the oscillation signal using a first AGC circuit; controlling a bias current for the oscillator based on the first signal; generating a second signal using a second AGC circuit that replicates the first AGC circuit; and effectively monitoring the oscillation signal based on the first and second signals.

[0011] Some aspects provide an apparatus for oscillation monitoring. The apparatus typically includes: components for generating an oscillation signal; components for generating a first AGC signal based on the oscillation signal; components for controlling a bias current of the component for generating the oscillation signal based on the first AGC signal; components for generating a second AGC signal, the component for generating the second AGC signal replicating the component for generating the first AGC signal; and components for effectively monitoring the oscillation signal based on the first and second AGC signals.

[0012] To achieve the foregoing and related objectives, one or more aspects include the features fully described below and specifically pointed out in the claims. The following description and drawings illustrate certain exemplary features of these one or more aspects in detail. However, these features indicate only a few of the various ways in which the principles of the various aspects can be employed. Attached Figure Description

[0013] To gain a more detailed understanding of the foregoing features of this disclosure, a more specific description, some of which is illustrated in the accompanying drawings, may be obtained by referring to various aspects. However, it should be noted that the drawings illustrate only certain typical aspects of this disclosure and are therefore not intended to limit its scope, as other equally valid aspects may be acknowledged in the specification.

[0014] Figure 1 This is a diagram illustrating an example wireless communication network in which various aspects of the present disclosure can be practiced.

[0015] Figure 2 It is a block diagram of an example access point (AP) and an example user terminal in which various aspects of this disclosure can be practiced.

[0016] Figure 3 It is a block diagram of an example transceiver circuit in which various aspects of the present disclosure can be practiced.

[0017] Figure 4A This is a block diagram of an example oscillating circuit in which various aspects of the present disclosure can be practiced, the oscillating circuit having a master oscillator and a backup oscillator.

[0018] Figure 4B This is a graph illustrating an example of detecting a system fault after the system's output oscillation signal is lost.

[0019] Figure 4C This is a graph illustrating an improved fault detection method that detects a system fault before the system's output oscillation signal is lost, according to certain aspects of this disclosure.

[0020] Figure 5A This is a graph illustrating a constant fault threshold output of an automatic gain control (AGC) circuit that does not change in response to variations in process, voltage, and temperature (PVT).

[0021] Figure 5B This is a graph illustrating the fault threshold that changes in response to PVT variations in the output of an AGC circuit according to certain aspects of this disclosure.

[0022] Figure 6 This is a block diagram of an example oscillating circuit according to certain aspects of this disclosure, the oscillating circuit including a process monitor coupled to an AGC circuit.

[0023] Figure 7A Based on certain aspects of this disclosure Figure 6 A block diagram illustrating an example implementation of a process monitor and AGC circuit.

[0024] Figure 7B Based on certain aspects of this disclosure Figure 6 and Figure 7A A schematic diagram illustrating a specific implementation of a process monitor and AGC circuit.

[0025] Figure 8 This is a flowchart illustrating example operations for oscillation monitoring according to certain aspects of this disclosure.

[0026] For ease of understanding, the same reference numerals have been used where possible to denote common elements in the accompanying drawings. It is conceivable that elements disclosed in one aspect may be usefully applied to other aspects without specific description. Detailed Implementation

[0027] Certain aspects of this disclosure generally relate to techniques and apparatus for non-invasively monitoring oscillating signals. In this approach, the amplitude of the oscillating signal and the gain of an automatic gain control (AGC) circuit can be evaluated without monitoring. For example, a master AGC circuit and a replica AGC circuit can be used to evaluate the amplitude of the oscillating signal and the gain of the AGC circuit without sensing the amplitude of the oscillating signal. The master AGC circuit and the replica AGC circuit consist of transistors manufactured using the same semiconductor process and powered by the same voltage rail, each using a constant transconductance bias generator to generate process-, voltage, and temperature (PVT) related references. In this way, a process tracking threshold (e.g., an AGC output current amplitude threshold) is effectively generated, against which the master AGC circuit is tested, instead of using a fixed threshold. In this way, weak faults (where the oscillating signal amplitude has just begun to decrease, but the device can still operate using the oscillating signal) can be detected earlier before more serious faults occur (e.g., the device fails to operate) (and in some cases corrected by switching to a backup oscillator). Therefore, certain aspects of this disclosure can provide a more robust oscillating signal.

[0028] The various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of protection of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will appreciate that the scope of this disclosure is intended to cover any aspect of this disclosure disclosed herein, whether implemented independently or in combination with any other aspect of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Furthermore, the scope of this disclosure is intended to cover such apparatus or methods practiced using structures, functions, or structures and functions other than or different from the aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of the claims.

[0029] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as preferred or superior to other aspects.

[0030] As used herein, the term “connected to” in various tenses of the verb “connect” can mean that element A is directly connected to element B or that other elements can be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term “connected to” can also be used herein to mean that a conductor, trace, or other conductive material is used to electrically connect element A and element B (and any components electrically connected between them).

[0031] Example wireless system

[0032] Figure 1 A wireless communication system 100 with access point 110 and user terminal 120 is illustrated, in which various aspects of this disclosure can be practiced. For simplicity, Figure 1 Only one access point 110 is shown. An access point (AP) is typically a fixed station that communicates with a user terminal and may also be referred to as a base station (BS), evolved Node B (eNB), or some other term. A user terminal (UT) can be fixed or mobile and may also be referred to as a mobile station (MS), access terminal, user equipment (UE), station (STA), client, wireless device, or some other term. A user terminal can be a wireless device such as a cellular phone, personal digital assistant (PDA), handheld device, wireless modem, laptop computer, tablet computer, personal computer, etc.

[0033] Access point 110 can communicate with one or more user terminals 120 at any given time, on both the downlink and uplink. The downlink (i.e., the forward link) is the communication link from the access point to the user terminal, while the uplink (i.e., the reverse link) is the communication link from the user terminal to the access point. User terminals can also communicate peer-to-peer with other user terminals. System controller 130 can be coupled to the access point and provides coordination and control for the access point.

[0034] The wireless communication system 100 uses multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. The access point 110 may be equipped with multiple (N) ap (N) antennas to achieve transmit diversity for downlink transmission and / or receive diversity for uplink transmission. u The selected user terminals 120 can receive downlink transmissions and transmit uplink transmissions. Each selected user terminal transmits user-specific data to and / or receives user-specific data from the access point. Typically, each selected user terminal may be equipped with one or more antennas (i.e., N). ut ≥1). N u Each selected user terminal may have the same number of antennas or a different number of antennas.

[0035] The wireless communication system 100 can be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. In a TDD system, the downlink and uplink share the same frequency band. In an FDD system, the downlink and uplink use different frequency bands. The wireless communication system 100 can also use a single carrier or multiple carriers for transmission. Each user terminal 120 may be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., where cost is feasible). In some aspects of this disclosure, the access point 110 and / or user terminal 120 may include circuitry for monitoring oscillation signals, as described in more detail herein.

[0036] Figure 2 A block diagram of an access point 110 and two user terminals 120m and 120x in a wireless communication system 100 is shown. Access point 110 is equipped with N... ap Each antenna is 224a to 224ap. The user terminal 120m is equipped with N... ut,m Each antenna is 252 mA to 252 mA, while the user terminal 120x is equipped with N ut,xEach antenna ranges from 252xa to 252xu. Access point 110 is a transmitting entity for the downlink and a receiving entity for the uplink. Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a “transmitting entity” is an independently operating device or apparatus capable of transmitting data via a frequency channel, and a “receiving entity” is an independently operating device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript “dn” denotes the downlink, the subscript “up” denotes the uplink, and N... up N user terminals are selected for simultaneous transmission on the uplink. dn N user terminals are selected for simultaneous transmission on the downlink. up It is possible or may not be equal to N dn And N up and N dn It can be a static value, or it can be changed for each scheduling interval. Beam control or some other spatial processing technology can be used at the access point and user terminal.

[0037] On the uplink, at each user terminal 120 selected for uplink transmission, the TX data processor 288 receives service data from the data source 286 and control data from the controller 280. The TX data processor 288 processes the service data {d} for that user terminal based on a decoding and modulation scheme associated with the selected rate for that user terminal. up} is processed (e.g., encoding, interleaving, and modulation), and is N ut,m One of the antennas provides a data symbol stream {s} up The transceiver front end (TX / RX) 254 (also referred to as the radio frequency front end (RFFE)) receives and processes the corresponding symbol stream (e.g., converts to analog, amplifies, filters, and up-converts) to generate the uplink signal. The transceiver front end 254 can also route the uplink signal to the N-channel for transmit diversity via, for example, a radio frequency (RF) switch. ut,m One of the antennas. Controller 280 can control the routing within transceiver front-end 254. Memory 282 can store data and program code for user terminal 120 and can interact with controller 280.

[0038] Multiple (N) can be scheduled up (120) user terminals simultaneously transmit on the uplink. Each of these user terminals transmits its processed set of symbol streams to the access point on the uplink.

[0039] At access point 110, N ap Antennas 224a to 224ap from all N upA user terminal receives uplink signals transmitted on the uplink. For receive diversity, transceiver front-end 222 can select signals received from one of antennas 224 for processing. Signals received from multiple antennas 224 can be combined to enhance receive diversity. The access point's transceiver front-end 222 also performs processing complementary to that performed by the user terminal's transceiver front-end 254 and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is a response to the data symbol stream {s} transmitted by the user terminal. up The RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the uplink data symbol stream used for recovery based on its rate to obtain decoded data. The decoded data from each user terminal can be provided to the data sink 244 for storage and / or to the controller 230 for further processing.

[0040] In some aspects, the transceiver front end (TX / RX) 222 of access point 110 and / or the transceiver front end 254 of user terminal 120 may include one or more frequency synthesizers to generate oscillating signals for signal transmission and / or reception. In some aspects, the controller 230 of access point 110 and / or the controller 280 of user terminal 120 may include or be coupled to an oscillating circuit for generating an oscillating signal for clocking synchronization logic. At least one of the frequency synthesizers and / or at least one of the oscillating circuits may include or be coupled to circuitry for monitoring the oscillating signal, as described in more detail herein.

[0041] On the downlink, at access point 110, TX data processor 210 receives N data from data source 208, which is scheduled for downlink transmission. dn The data includes service data from individual user terminals, control data from controller 230, and other data that may come from scheduler 234. Various types of data can be transmitted over different transport channels. TX data processor 210 processes the service data for each user terminal (e.g., encoding, interleaving, and modulation) based on a selected rate for that user terminal. TX data processor 210 can provide services for N... dn One or more user terminals from N user terminals need to be from N ap A downlink data symbol stream is transmitted by one of the antennas. Transceiver front-end 222 receives this symbol stream and processes it (e.g., converts to analog, amplifies, filters, and up-converts) to generate a downlink signal. For example, transceiver front-end 222 can also route this downlink signal via an RF switch to N antennas for transmit diversity. apOne or more antennas from antenna 224. Controller 230 can control routing within transceiver front end 222. Memory 232 can store data and program code for access point 110 and can interact with controller 230.

[0042] At each user terminal 120, N ut,m Antenna 252 receives downlink signals from access point 110. For receive diversity at user terminal 120, transceiver front-end 254 can selectively process signals received from one of antennas 252. Signals received from multiple antennas 252 can be combined to enhance receive diversity. The transceiver front-end 254 of the user terminal also performs processing complementary to that performed by the transceiver front-end 222 of the access point and provides a recovered downlink data symbol stream. RX data processor 270 processes the recovered downlink data symbol stream (e.g., demodulation, deinterleaving, and decoding) to obtain decoded data for the user terminal.

[0043] Figure 3 This is an example transceiver circuit 300 (such as) that can implement various aspects of this disclosure. Figure 2 The block diagram shows the transceiver front-end 222, 254. The transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a "transmit chain") for transmitting signals via one or more antennas and at least one receive (RX) path 304 (also referred to as a "receive chain") for receiving signals via these antennas. When the TX path 302 and RX path 304 share antenna 303, these paths can be connected to the antenna via interface 306, which can include any of a variety of suitable RF devices such as a duplexer, switch, double-ended converter, etc.

[0044] Receiving in-phase (I) or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 308, the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The BBF 310, mixer 312, and DA 314 may be included in one or more radio frequency integrated circuits (RFICs). In some specific implementations, the PA 316 may be external to the RFIC.

[0045] BBF 310 filters the baseband signal received from DAC 308, and mixer 312 mixes the filtered baseband signal with the transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., up-convert from baseband to RF). This frequency conversion process produces a sum and difference frequency of the LO frequency and the frequency of the signal of interest. This sum and difference frequency is called the "beat frequency". The beat frequency can be in the RF range, such that the signal output from mixer 312 can be an RF signal, which can be amplified by DA 314 and / or PA 316 before being transmitted through antenna 303. Although one mixer 312 is illustrated, several mixers can be used to up-convert the filtered baseband signal to one or more intermediate frequencies and then up-convert the intermediate frequency (IF) signal to the frequency used for transmission.

[0046] The RX path 304 includes a low-noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. The LNA 322, mixer 324, and BBF 326 can be included in one or more RFICs, which can be the same RFIC as the one including the TX path components, or they can be different RFICs. The RF signal received via antenna 303 can be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., down-conversion). The baseband signal output from the mixer 324 can be filtered by the BBF 326 before being converted to digital I or Q signals by the analog-to-digital converter (ADC) 328 for digital signal processing.

[0047] Some transceivers may employ a frequency synthesizer with a voltage-controlled oscillator (VCO) to generate a stable, tunable LO with a specific tuning range. Therefore, the transmit LO frequency may be generated by a TX frequency synthesizer 318, which may be buffered or amplified by an amplifier 320 before being mixed with the baseband signal in mixer 312. Similarly, the receive LO frequency may be generated by an RX frequency synthesizer 330, which may be buffered or amplified by an amplifier 332 before being mixed with the RF signal in mixer 324. In some aspects, the TX frequency synthesizer 318 and / or the RX frequency synthesizer 330 may include or be coupled to circuitry for monitoring the oscillation signal, as described in more detail herein.

[0048] Although Figures 1 to 3 Wireless communication systems in which certain aspects of this disclosure are implemented are provided as example applications for understanding purposes, but certain aspects described herein can be used to monitor oscillating signals in any of a variety of other suitable systems.

[0049] Example oscillator circuit with improved fault detection

[0050] Electronic devices (e.g., wireless communication devices) may include oscillation circuits and performance monitoring systems to ensure robust operation within the oscillation circuit and to switch to a backup circuit (if indicated). In some oscillation circuits (e.g., oscillation circuits in automotive safety systems), non-intrusive performance monitoring systems are desirable. One or more automatic gain control (AGC) circuits may be used as first-order monitors for the oscillation circuit. The AGC circuit monitors the amplitude of the output signal of the oscillator in the oscillation circuit and adjusts the oscillator's bias current based on the amplitude of the output signal.

[0051] Figure 4A This is a block diagram of an example oscillator circuit 400A. The oscillator circuit 400A may include a first AGC circuit 402, a second AGC circuit 408, a safety monitor 416, a resonator 418, a first oscillator 420 (e.g., a master oscillator), and a second oscillator 422 (e.g., a backup oscillator). The first oscillator 420 may include a first oscillator core circuit 404 and a first current source 406, and the second oscillator 422 may include a second oscillator core circuit 410 and a second current source 412. The first oscillator core circuit 404 and the second oscillator core circuit 410 may be coupled to the resonator 418 and configured to generate an oscillating signal such that the resonator 418 can resonate. The first oscillator core circuit 404 and the second oscillator core circuit 410 may include any suitable type of oscillator core for driving the resonator, such as a crystal oscillator core. The output node 426 of the oscillator circuit 400A may provide a clock signal to one or more other systems.

[0052] As shown in the figure, the first AGC circuit 402 may have an input coupled to the output of the first oscillator 420 and an output coupled to a control input of the first current source 406. Similarly, the second AGC circuit 408 may have an input coupled to the output of the second oscillator 422 and an output coupled to a control input of the second current source 412. The first current source 406 and the second current source 412 may be adjustable current sources.

[0053] The first AGC circuit 402 can be configured to monitor the amplitude of the signal output from the first oscillator 420. In one example, if the first AGC circuit 402 senses that the amplitude of the signal output from the first oscillator 420 is too low, the first AGC circuit 402 can control the first current source 406 to increase the current supplied to the core circuit 404 of the first oscillator. The second AGC circuit 408 can be configured to monitor the amplitude of the signal output from the second oscillator 422 in a similar manner and control the second current source 412.

[0054] If one of the AGC circuits 402 and 408 fails, the oscillation circuit 400A may lose its first-order monitoring system to monitor the health of oscillators 420 and 422. Therefore, both the first AGC circuit 402 and the second AGC circuit 408 are communicatively coupled to the safety monitor 416. The safety monitor 416 can be configured to monitor the performance (e.g., health) of the first AGC circuit 402 and the second AGC circuit 408. In some aspects, the safety monitor 416 may transmit an inquiry (e.g., a check) to each of the first AGC circuit 402 and the second AGC circuit 408. In response to this inquiry, the first AGC circuit 402 and / or the second AGC circuit 408 may respond with a status signal indicating whether each AGC circuit is operating correctly. In other aspects, the first AGC circuit 402 and / or the second AGC circuit 408 may periodically or continuously transmit such a status signal to the safety monitor 416.

[0055] The oscillation circuit 400A (more specifically, the safety monitor 416) can select between a signal generated by the first oscillator 420 and a signal generated by the second oscillator 422 as the output signal at the output node 426. In some aspects, the safety monitor 416 can (e.g., via a bus) output a first enable signal for enabling and / or disabling the first oscillator 420 and a second enable signal for enabling and / or disabling the second oscillator 422, such as... Figure 4A As shown in the diagram. In some respects, for example, the first oscillator 420 may be initially enabled, while the second oscillator 422 may be initially disabled. If the first AGC circuit 402 malfunctions (e.g., as indicated by its associated status signal), or if the first AGC circuit 402 detects a fault from the first oscillator 420, the safety monitor 416 may (e.g., via an enable signal) instruct the oscillator circuit 400A to switch to using the signal generated by the second oscillator 422 as the output signal (e.g., the safety monitor 416 may disable the first oscillator 420 and enable the second oscillator 422). Thus, the first oscillator 420 may be considered the master oscillator, and the second oscillator 422 may be considered the backup oscillator.

[0056] In one example, the oscillation circuit 400A may include additional circuitry (not shown) configured to monitor the output signal of the first oscillator 420 at output node 426. In response to a fault detected at this location, the oscillation circuit 400A may switch to using a signal generated by the second oscillator 422 as its output signal. However, sensing the output node 426 of the oscillation circuit 400A may introduce frequency shift and / or phase noise degradation into the oscillation signal. In one example, the additional circuitry may include a clock stop detector. However, stop detectors are typically configured to monitor complete clock failures (e.g., after the clock signal has been lost), which may result in fault detection occurring too late.

[0057] Figure 4B This is a graph 400B illustrating an example of fault detection after the output signal (e.g., the signal at output node 426) of an oscillator (e.g., the first oscillator 420) is lost. As shown, the system can operate using the master oscillator (e.g., the first oscillator 420) before time 430. At time 430, a fault may occur in the core circuitry of the master oscillator (e.g., the first oscillator core circuitry 404), and the output signal may begin to decay (e.g., the amplitude of the output signal may decrease). As illustrated, the system (and more specifically, circuitry such as a clock stop detector) may not detect the fault until time 440 when the output signal has significantly decayed (e.g., been lost). Once the fault is detected, the system can switch to a backup oscillator (e.g., the second oscillator 422). However, once the output signal is lost, even if the system switches to the backup oscillator, other systems using the output signal may be reset, restarted, or placed in an unexpected state, which is undesirable.

[0058] Therefore, certain aspects of the present invention provide a system with improved fault detection, wherein a fault can be detected before the output signal is lost. Figure 4C This is a graph 400C illustrating an example of an improved fault detection according to certain aspects of this disclosure. As shown, when the master oscillator fails at time 430, the system with improved fault detection detects the fault at time 450 before the output signal is lost. Therefore, the system is able to switch to a backup oscillator before the output signal is lost, thereby avoiding undesirable consequences for other components that use the output signal as a clock signal.

[0059] To achieve this improved fault detection, various aspects of this disclosure provide means and techniques for monitoring the health of the oscillator core circuit using the output of the AGC circuit (as opposed to the output of the oscillator) and logic elements (as opposed to, for example, a stop detector).

[0060] Several methods exist for monitoring the health of the oscillator core circuit and the AGC circuit based on the output of the AGC circuit. However, these methods are often invasive, unreliable, and / or negatively impact the performance of the oscillator circuit. For example, one method involves disconnecting the feedback loop between the oscillator and the AGC circuit and using a test input signal with a known amplitude to verify the gain of the AGC circuit. However, this invasive method can only be used when the oscillator system is in factory test mode (as opposed to mission mode) and does not provide real-time fault detection in mission mode. Another method involves using an analog-to-digital converter (ADC) to measure the amplitude of the AGC input signal, but this ADC may generate kickback noise, which can cause frequency shift and / or phase noise degradation in the oscillator circuit. This ADC also consumes additional power and occupies additional area. Yet another method involves monitoring only the amplitude of the output signal of the AGC circuit. In this case, only the output amplitude (not the input amplitude) is known, so the gain cannot be accurately calculated. This method may be unreliable because the amplitude of the AGC output signal is sensitive to changes in process, voltage, and temperature (PVT) conditions, so the monitoring system may not be able to capture all faults across PVT variations.

[0061] For example, Figure 5A This is a graph 500A illustrating a constant fault threshold for the AGC circuit output that does not change in response to PVT variations. In this case, the fixed threshold for the AGC output can be set high enough to avoid false faults across PVT variations. As illustrated, when using a constant threshold to indicate a fault, the system may fail to detect the fault across all PVT variations. That is, even if the oscillator circuit (and more specifically, the AGC circuit and / or the oscillator core circuit of the oscillator circuit) fails, the amplitude of the AGC circuit output may be below the fault threshold (by indication) under certain PVT conditions. Therefore, a constant fault threshold may cause the monitoring system to generate false "pass" indications. Furthermore, using a constant threshold cannot detect situations known as "weak faults" across PVT variations, where the oscillator circuit is still operating, but its performance has deteriorated (e.g., in terms of phase noise and / or frequency accuracy).

[0062] Therefore, certain aspects of this disclosure provide techniques and apparatus for detecting faults based on the output of an AGC circuit, which takes into account the PVT variation of the system and effectively provides a PVT tracking threshold for oscillation monitoring. Figure 5B Graph 500B illustrates the fault threshold that changes in response to PVT variations in the AGC circuit output according to certain aspects of this disclosure. Regardless of PVT variations, the PVT tracking threshold allows the system to avoid false passes and detect even “weak” faults (e.g., before the clock signal is lost, such as in…). Figure 4C(At time 450). The PVT tracking threshold can be effectively generated by a constant transconductance bias generator, which will be discussed further below.

[0063] Figure 6 This is a block diagram of an example oscillator circuit 600 according to certain aspects of this disclosure. The oscillator circuit 600 may be similar to the oscillator circuit 400A, but has a process monitor 604 (also referred to herein as a "logic element"). In addition to the process monitor 604, the oscillator circuit 600 may also typically include an oscillator health monitor 602, an AGC circuit 606, an oscillator core circuit 608, a current source 610, and a resonator 618. The oscillator core circuit 608 and the current source 610 may constitute an oscillator, such as... Figure 4A The oscillator 420 or 422 is used. In some respects, at least a portion of the process monitor 604 may be integrated with the AGC circuit 606.

[0064] The oscillator core circuit 608 can be configured to generate an oscillation signal so that the resonator 618 can resonate. The current source 610 can be adjustable and can be configured to control the amplitude of the oscillation signal by providing an adjustable bias current.

[0065] The AGC circuit 606 may have an input coupled to the output of the oscillator core circuit 608. The AGC circuit 606 may be configured to output a first output signal at 614 to control the current source 610, as referenced above. Figure 4A As illustrated in 616, the first output signal can also be used as a first input to the process monitor 604. The AGC circuit 606 can be further configured to output a second output at 612 as a second input to the process monitor. The second output of the AGC circuit 606 can be a replica output generated by a replica AGC circuit configured to replicate the main AGC circuit in the AGC circuit 606, as described below. For example, the replica AGC circuit may have the same or similar topology as the main AGC circuit and can be manufactured using the same semiconductor process as the main AGC circuit.

[0066] Oscillator health monitor 602 can be configured to check (e.g., periodically, intermittently, or continuously) whether the oscillator is operating properly (e.g., generating sufficient output signal). For example, oscillator health monitor 602 can transmit a request (e.g., a check) to process monitor 604 regarding an indication of the oscillator's health status. Process monitor 604 can be configured to compare a first output signal (e.g., at 616) of AGC circuit 606 with a second output signal (e.g., at 612) and report this comparison to oscillator health monitor 602. Thus, process monitor 604 can be configured to effectively monitor the oscillation signal generated by the oscillator based on the two outputs of AGC circuit 606. In this way, AGC amplitude and gain are evaluated without monitoring the AGC input amplitude. Instead, process tracking amplitude sensing is used to monitor the AGC output amplitude, as explained below.

[0067] Figure 7A Based on certain aspects of this disclosure Figure 6 A block diagram illustrating an example implementation of the process monitor 604 and the AGC circuit 606. The AGC circuit 606 may include a first AGC circuit 702 and a second AGC circuit 704 configured to replicate the first AGC circuit 702. The process monitor 604 may include a comparator 706, which may be tunable. The comparator 706 may have a first input (e.g., a negative input) coupled to the output of the first AGC circuit 702 and a second input (e.g., a positive input) coupled to the output of the second AGC circuit 704. The comparator 706 may be configured to compare the output signals from the first AGC circuit 702 and the second AGC circuit 704 to determine whether the oscillation circuit 600 (and more specifically, the AGC circuit 606 and / or the oscillator core circuit 608) has malfunctioned.

[0068] The output (labeled "OUT") of the first AGC circuit 702 can be determined as

[0069] OUT = (REF – IN) * A

[0070] Where IN is the input signal of the first AGC circuit 702 (from the output signal of the oscillator), and A is the gain of the first AGC circuit 702. REF can be a self-generated reference signal. That is, the oscillator circuit (e.g., the first AGC circuit 702 and the second AGC circuit 704) can generate REF via a constant transconductance bias generator.

[0071] When the oscillation circuit is operating normally, the amplitude of the input signal IN will be high enough, and the amplitude of the output signal OUT will be relatively low (due to the reduced difference between REF and IN). Therefore, in some cases, the health of the oscillation circuit can be monitored by monitoring the output of the first AGC circuit 702 and determining when the output signal OUT is high enough.

[0072] An example method for monitoring when the output signal OUT is high enough involves comparing the output signal OUT with another signal (e.g., a threshold). (See also: ...) Figure 5A and Figure 5B As explained, it is desirable for the threshold to vary according to the PVT, so that weak faults can be detected across PVT conditions. Therefore, certain aspects of this disclosure provide a method for comparing an output signal OUT with a replica output signal from a second AGC circuit 704. The output of the second AGC circuit 704 (labeled "OUT") REP ”) can be identified as

[0073] OUT REP =REF*A REP

[0074] Where A REP This is the gain of the second AGC circuit 704. Because the second AGC circuit 704 is configured to replicate the first AGC circuit 702, the output signal OUT... REP It will vary according to PVT in a manner similar to the output signal OUT, thus providing a threshold related to PVT. Therefore, OUT and OUT are executed. REP It is a relative comparison between them, rather than an absolute comparison with a fixed threshold.

[0075] Comparator 706 can be configured to effectively monitor the output of the first AGC circuit 702 and the second AGC circuit 704 based on the output of the oscillator (e.g., Figure 6 The oscillation signal is generated by the oscillator core circuit 608 and the current source 610. Therefore, the oscillation circuit can effectively monitor the oscillation signal generated by the oscillator without directly sensing the amplitude of the oscillation signal. According to some aspects, the comparator 706 can be configured to compare the output signal OUT with the output signal OUT. REP Compare, and when OUT REP When the amplitude of the oscillation is greater than or equal to the amplitude of the OUT, a logic high signal (e.g., logic 1) is output (marked as "AGC_OK"), indicating that the oscillation circuit is operating normally.

[0076] Based on the above formula and the circuit setup, when OUT REP When the value is greater than or equal to OUT, comparator 706 should indicate that the oscillation circuit is normal (AGC_OK = 1). In this case,

[0077] REF*A REP ≥(REF–IN)*A

[0078] Rearranging these formulas to solve for IN yields the following formula:

[0079]

[0080] Therefore, A REP The gain ratio of A can be set such that the formula holds true when the amplitude of IN is acceptable (e.g., when the oscillator circuit, and more specifically, when the oscillator core circuit and AGC circuit are operating normally).

[0081] The ratio of the gain of the second AGC circuit 704 to the gain of the first AGC circuit 702 (e.g., A REP The ratio of A to A can be calculated as follows:

[0082]

[0083] Where n depends on the transistor size ratio between the transistors in the first AGC circuit 702 and the transistors in the comparator 706, and m depends on the transistor size ratio between the transistors in the second AGC circuit 704 and the transistors in the comparator 706, as discussed further below. Therefore, A REP The gain ratio with A can be set by designing (and in some cases adjusting during factory calibration) the transistor dimensions in the first AGC circuit 702, the second AGC circuit 704, and the comparator 706, as discussed further below.

[0084] Figure 7B It is based on certain aspects of this disclosure. Figure 7A A schematic diagram of an oscillator circuit 700 specifically implemented with an example of a first AGC circuit 702, a second AGC circuit 704, and a comparator 706 is shown. As shown, the oscillator circuit 700 also includes an oscillator 701 coupled to the first AGC circuit 702.

[0085] Oscillator 701 can be similar to Figure 4A The oscillator 420 or 422 may include an adjustable current source (implemented by, for example, transistor 708) and an oscillator core circuit 705 having an input coupled to the drain of transistor 708 and an output coupled to resonator 707. Oscillator 701 may be configured to generate an oscillating signal. More specifically, oscillator core circuit 705 may be configured to generate an oscillating signal such that resonator 707 can resonate. The adjustable current source (implemented by transistor 708) may be configured to provide an adjustable bias current (labeled "I"). OUTThe amplitude of the oscillation signal is controlled by the ''.

[0086] Comparator 706 may include a first transistor 718, a second transistor 720, and an inverter 730. Comparator 706 may have a first input (e.g., the gate of transistor 708) coupled to the output of the first AGC circuit 702 (e.g., node 711 coupled to the gate of transistor 718), and a second input (e.g., the gate of transistor 720) coupled to the output (node ​​721) of the second AGC circuit 704. Transistor 718 may be a p-type transistor and may have a source coupled to a power rail (labeled “VDD”) of the oscillator circuit 700. Transistor 720 may be an n-type transistor, may have a source coupled to a reference potential node (e.g., electrically ground) of the oscillator circuit 700, and may have a drain coupled to the drain of transistor 718. In some examples, at least one of transistors 718 and 720 may be tunable. Inverter 730 may have an input coupled to the drain of transistor 718 and the drain of transistor 720, and an output coupled to the output of comparator 706 (labeled “AGC_OK”).

[0087] The first AGC circuit 702 may have an input coupled to the output of the oscillator 701 and an output coupled to a control input (e.g., the gate of transistor 708) of an adjustable current source (e.g., at node 711). The first AGC circuit 702 may include a first transistor 710 having a source coupled to a power rail. Transistor 710 may be a p-type transistor. The first AGC circuit 702 may also include a second transistor 712 having a source coupled to a reference potential node and a drain coupled to the drain of transistor 710. Transistor 712 may be an n-type transistor. The first AGC circuit 702 may also include a third transistor 714 having a source coupled to a power rail and a gate coupled to the drain of transistor 714, the gate of transistor 710, and the gate of transistor 718 of comparator 706. Transistor 714 may be a p-type transistor. The first AGC circuit 702 may also include a fourth transistor 716 having a drain coupled to the drain and gate of transistor 714. Transistor 716 may be an n-type transistor. The first AGC circuit 702 may also include a first resistive element R1 coupled between the source of transistor 716 and the reference potential node.

[0088] In some examples, the first AGC circuit 702 may further include a second resistive element R2 coupled between the gate and drain of transistor 712, and a third resistive element R3 coupled between the drain of transistor 712 and the gate of transistor 716. In some examples, the first AGC circuit 702 may further include a first capacitive element C1 coupled between the gate of transistor 716 and a reference potential node. According to some aspects, transistors 710, 712, 714, 716, the first resistive element R1, the second resistive element R2, and the third resistive element R3 form at least a portion of a constant transconductance bias generator configured to generate a reference current (labeled "I") that is process, voltage, and temperature (PVT) related to the voltage, current, and temperature (PVT). REF (The reference current is mentioned above.) Figure 7A The formula described is represented by REF.

[0089] According to some aspects, the oscillator circuit 700 may also include a second capacitor element C2 coupled between the gate of the transistor 712 and the output of the oscillator 701. The second capacitor element C2 can be used to couple the output AC of the oscillator 701 to the input of the first AGC circuit 702.

[0090] The second AGC circuit 704 may be configured to replicate the first AGC circuit 702. For example, the second AGC circuit 704 may have the same or similar topology as the first AGC circuit 702 and may be manufactured using the same semiconductor process as the first AGC circuit 702. The second AGC circuit 704 may include: a first transistor 722 having a source coupled to a power rail; and a second transistor 726 having a source coupled to a reference potential node and a drain coupled to the drain of transistor 722, the gate of transistor 726, and the gate of transistor 720 (e.g., node 721). Transistor 722 may be a p-type transistor, and transistor 726 may be an n-type transistor. The second AGC circuit 704 may also include a third transistor 724 having a source coupled to a power rail and a drain coupled to the gate of transistor 724 and the gate of transistor 722. Transistor 724 may be a p-type transistor. The second AGC circuit 704 may further include: a fourth transistor 728 having a drain coupled to the drain and gate of transistor 724 and a gate coupled to the gate and drain of transistor 726; and a resistive element R4 coupled between the source of transistor 728 and a reference potential node. Transistor 728 may be an n-type transistor.

[0091] Transistors 722, 726, 724, and 728 form at least a portion of another constant transconductance bias generator, which is configured to generate another reference current (also labeled "I"). REF According to certain aspects and such Figure 7B As shown, the input of the second AGC circuit 704 is open-circuited, thus configuring the input of the second AGC circuit 704 to have zero current. In this way, the second AGC circuit 704 amplifies the difference between REF and 0, as... Figure 7A exemplified.

[0092] According to certain aspects, the transistor size ratio between transistors 720, 726, and 728 can be m:1:1 (where m ≥ 1), and the transistor size ratio between transistors 718, 710, and 714 can be n:1:1 (where n ≥ 1). The value of m can represent the gain of the second AGC circuit 704, and the value of n can represent the gain of the first AGC circuit 702 (or at least the ratio of m to n can be considered to represent A...). REP The ratio of A to A). Therefore, as described above, the gain (e.g., A) of the second AGC circuit 704 can be set by adjusting the transistor sizes in the first AGC circuit 702, the second AGC circuit 704, and the comparator 706. REP The ratio of the gain (e.g., A) of the first AGC circuit 702 to the gain of the first AGC circuit 702.

[0093] As described above, the first AGC circuit 702 may include a first reference current (e.g., IT) configured to generate a first reference current related to the PVT conditions of the first AGC circuit 702. REF The first AGC circuit 704 may include a constant transconductance bias generator configured to generate a second reference current. If the transistors in the first and second AGC circuits are manufactured using the same semiconductor process, receive the same power rail voltage (Vdd), and are subjected to the same temperature, then the second reference current should be equal to the first reference current. In this case, the ratio of m to n can be set such that comparator 706 is configured to output a logic high signal when the amplitude of the oscillation signal is estimated to be greater than or equal to the amplitude of the reference current multiplied by (1-m / n).

[0094] In some aspects, the adjustable current source can be implemented using transistor 708. As shown, transistor 708 may have a source coupled to a power rail, a drain coupled to the oscillator core circuit 705, and a gate coupled to the gate of transistor 710 and transistor 714. In some aspects, transistor 708 may be a p-type transistor. In some aspects, the transistor size ratio between transistor 708, transistor 710, and transistor 714 is x:1:1, where x ≥ 1.

[0095] Depending on certain aspects, the oscillation circuit 700 may also include a backup oscillator configured to generate another oscillation signal (e.g., as per [reference]). Figure 4A The discussed and similar components include an oscillator 701, a third AGC circuit (similar to the first AGC circuit 702), a fourth AGC circuit (similar to the second AGC circuit 704), and another comparator (similar to comparator 706). In some aspects, the backup oscillator may include another oscillator core circuit for coupling to the resonator, and another adjustable current source coupled to the other oscillator core circuit and configured to control the amplitude of the other oscillation signal. In this case, the third AGC circuit may have an input coupled to the output of the backup oscillator and an output coupled to a control input of the other adjustable current source. In some aspects, the process monitor 604 (or another comparator similar to comparator 706) may have a third input coupled to the output of the third AGC circuit and a fourth input coupled to the output of the fourth AGC circuit. In some aspects, the fourth AGC circuit may be configured to replicate the third AGC circuit (e.g., replicate its topology).

[0096] Example operation for oscillation monitoring

[0097] Figure 8 This is a flowchart illustrating an example operation 800 for oscillation monitoring according to certain aspects of this disclosure. Operation 800 may be provided by an oscillation circuit (such as...) Figure 6 600 or oscillating circuit Figure 7B The oscillating circuit 700 is executed. The flowchart includes boxes representing operation 800.

[0098] Operation 800 can begin at block 802, where an oscillator (e.g., oscillator 701) generates an oscillation signal (e.g., IN) using a driver resonator (e.g., resonators 618, 707). At block 804, a first automatic gain control (AGC) circuit (e.g., first AGC circuit 702) can generate a first signal (e.g., OUT) based on this oscillation signal. At block 806, the first AGC circuit can control the bias current (e.g., I) for the oscillator based on the first signal. OUTAt block 808, a second AGC circuit (e.g., second AGC circuit 704) can generate a second signal (e.g., OUT). REP The second AGC circuit can replicate the first AGC circuit. For example, the second AGC circuit may have the same or similar topology as the first AGC circuit and may be manufactured using the same semiconductor process as the first AGC circuit. At block 810, the oscillation circuit may effectively monitor the oscillation signal based on the first and second signals (e.g., using logic devices such as comparator 706 or process monitor 604).

[0099] According to some aspects, effectively monitoring the oscillation signal at box 810 may involve effectively monitoring the oscillation signal without directly sensing the amplitude of the oscillation signal.

[0100] According to some aspects, effectively monitoring the oscillation signal at block 810 may involve comparing a first signal with a second signal, and outputting a status signal indicating a fault (e.g., AGC_OK is logic low) when the amplitude of the second signal is lower than the amplitude of the first signal. According to some aspects, operation 800 may also involve utilizing a backup oscillator (e.g., Figure 4A The oscillator 422 generates another oscillation signal and switches to use the other oscillation signal instead of the oscillation signal in response to a status signal indicating the fault.

[0101] According to some aspects, the first transistor size ratio between the first n-type transistor of the comparator (e.g., transistor 720) and the second n-type transistor of the second AGC circuit (e.g., transistor 726 or transistor 728) is m:1, and the second transistor size ratio between the first p-type transistor of the comparator (e.g., transistor 718) and the second p-type transistor of the first AGC circuit (e.g., transistor 710 or transistor 714) is n:1. In some aspects, a second signal from the second AGC circuit controls the first n-type transistor of the comparator and the second n-type transistor of the second AGC circuit, and a first signal from the first AGC circuit controls the first p-type transistor of the comparator and the second p-type transistor of the first AGC circuit. According to some aspects, the ratio of m to n is equal to the gain of the second AGC circuit (e.g., gain A). REP The ratio of the gain of the first AGC circuit to the gain (e.g., gain A).

[0102] According to some aspects, generating the first signal may involve using a constant transconductance bias generator (e.g., transistors 710, 712, 714, and 716) of the first AGC circuit to generate a first reference current (e.g., via the IT of transistor 710) that is related to the process, voltage, and temperature (PVT) of the first AGC circuit. REFIn some aspects, generating the second signal may involve using a second AGC circuit to generate a second reference current equal to the first reference current (e.g., via IC of transistor 726). REF ).

[0103] According to some aspects, effectively monitoring the oscillation signal at block 810 may involve outputting a logic high signal from the comparator when the amplitude of the oscillation signal is estimated to be greater than or equal to the amplitude of the first reference current multiplied by (1-m / n).

[0104] Example

[0105] In addition to the aspects mentioned above, specific combinations of these aspects are also within the scope of this disclosure, some of which are detailed below:

[0106] Aspect 1: An oscillation circuit comprising: an oscillator configured to generate an oscillation signal, the oscillator including: an oscillator core circuit for coupling to a resonator and configured to generate the oscillation signal such that the resonator resonates; and an adjustable current source coupled to the oscillator core circuit and configured to control the amplitude of the oscillation signal; a first automatic gain control (AGC) circuit having an input coupled to an output of the oscillator and an output coupled to a control input of the adjustable current source; a second AGC circuit configured to replicate the first AGC circuit; and a logic element having a first input coupled to the output of the first AGC circuit and a second input coupled to the output of the second AGC circuit.

[0107] Aspect 2: The oscillation circuit according to aspect 1, wherein the logic element is configured to effectively monitor the oscillation signal based on the output of the first AGC circuit and the output of the second AGC circuit.

[0108] Aspect 3: The oscillation circuit according to aspect 1 or 2, wherein the oscillation circuit is configured to effectively monitor the oscillation signal without directly sensing the amplitude of the oscillation signal.

[0109] Aspect 4: An oscillation circuit according to any one of the preceding aspects, wherein the logic element includes a comparator having a first input coupled to the output of the first AGC circuit and a second input coupled to the output of the second AGC circuit.

[0110] Aspect 5: The oscillation circuit according to Aspect 4, wherein the comparator comprises: a first p-type transistor having a source coupled to a power rail; a first n-type transistor having a source coupled to a reference potential node of the oscillation circuit and a drain coupled to the drain of the first p-type transistor, wherein at least one of the first p-type transistor or the first n-type transistor is tunable; and an inverter having an input coupled to the drain of the first p-type transistor and the drain of the first n-type transistor, and an output coupled to the output of the comparator.

[0111] Aspect 6: The oscillation circuit according to Aspect 5, wherein the first AGC circuit comprises: a second p-type transistor having a source coupled to the power rail; a second n-type transistor having a source coupled to the reference potential node and a drain coupled to the drain of the second p-type transistor; a third p-type transistor having a source coupled to the power rail and a gate coupled to the drain of the third p-type transistor, the gate of the second p-type transistor, and the gate of the first p-type transistor; a third n-type transistor having a drain coupled to the drain of the third p-type transistor and the gate; and a first resistive element coupled between the source of the third n-type transistor and the reference potential node.

[0112] Aspect 7: The oscillation circuit according to Aspect 6, wherein the first AGC circuit further comprises: a second resistive element coupled between the gate of the second n-type transistor and the drain of the second n-type transistor; a third resistive element coupled between the drain of the second n-type transistor and the gate of the third n-type transistor; and a first capacitive element coupled between the gate of the third n-type transistor and the reference potential node.

[0113] Aspect 8: The oscillation circuit according to aspect 7 further includes a second capacitor element coupled between the gate of the second n-type transistor and the output of the oscillator.

[0114] Aspect 9: The oscillating circuit according to aspect 7 or 8, wherein the second n-type transistor, the third n-type transistor, the first resistive element, the second resistive element and the third resistive element form at least a portion of a constant transconductance bias generator, the constant transconductance bias generator being configured to generate a reference current related to process, voltage and temperature (PVT).

[0115] Aspect 10: An oscillating circuit according to any one of Aspects 6 to 9, wherein the transistor size ratio between the first p-type transistor, the second p-type transistor and the third p-type transistor is n:1:1, where n≥1.

[0116] Aspect 11: An oscillation circuit according to any one of Aspects 6 to 10, wherein: the adjustable current source includes a fourth p-type transistor having a source coupled to the power rail, a drain coupled to the oscillator core circuit, and a gate coupled to the gate of the second p-type transistor and the third p-type transistor; and the transistor size ratio between the fourth p-type transistor, the second p-type transistor, and the third p-type transistor is x:1:1, where x≥1.

[0117] Aspect 12: An oscillation circuit according to any one of Aspects 6 to 10, wherein the second AGC circuit comprises: a fourth p-type transistor having a source coupled to the power rail; a fourth n-type transistor having a source coupled to the reference potential node and a drain coupled to the drain of the fourth p-type transistor, the gate of the fourth n-type transistor, and the gate of the first n-type transistor; a fifth p-type transistor having a source coupled to the power rail and a drain coupled to the gate of the fifth p-type transistor and the gate of the fourth p-type transistor; a fifth n-type transistor having a drain coupled to the drain of the fifth p-type transistor and the gate of the fourth p-type transistor; and a second resistive element coupled between the source of the fifth n-type transistor and the reference potential node.

[0118] Aspect 13: The oscillation circuit according to aspect 12, wherein the transistor size ratio between the first n-type transistor, the fourth n-type transistor and the fifth n-type transistor is m:1:1, where m≥1.

[0119] Aspect 14: The oscillating circuit according to aspect 13, wherein the transistor size ratio between the first p-type transistor, the second p-type transistor and the third p-type transistor is n:1:1, where n≥1.

[0120] Aspect 15: The oscillation circuit according to aspect 14, wherein the ratio m / n is equal to the ratio of the gain of the second AGC circuit to the gain of the first AGC circuit.

[0121] Aspect 16: The oscillation circuit according to aspect 15, wherein: the first AGC circuit includes a constant transconductance bias generator configured to generate a reference current; and the ratio m / n is set such that the comparator is configured to output a logic high signal when the amplitude of the oscillation signal is estimated to be greater than or equal to the amplitude of the reference current multiplied by (1-m / n).

[0122] Aspect 17: An oscillation circuit according to any one of Aspects 4 to 16, wherein the comparator is configured to output a logic high signal when the amplitude of the signal at the output of the second AGC circuit is greater than or equal to the amplitude of the signal at the output of the first AGC circuit.

[0123] Aspect 18: An oscillation circuit according to any one of the preceding aspects, wherein the first AGC circuit includes a constant transconductance bias generator configured to generate a first reference current relating to the process, voltage, and temperature (PVT) of the first AGC circuit.

[0124] Aspect 19: The oscillation circuit according to aspect 18, wherein the second AGC circuit is configured to generate a second reference current equal to the first reference current.

[0125] Aspect 20: The oscillation circuit according to any one of the preceding aspects, wherein the input of the second AGC circuit is open-circuited, such that the input of the second AGC circuit is configured to have zero current.

[0126] Aspect 21: The oscillation circuit according to any one of the preceding aspects further includes: a backup oscillator configured to generate another oscillation signal, the backup oscillator including: another oscillator core circuit for coupling to the resonator; and another adjustable current source coupled to the other oscillator core circuit and configured to control the amplitude of the other oscillation signal; and a third AGC circuit having an input coupled to the output of the backup oscillator and an output coupled to a control input of the other adjustable current source, wherein the logic element has a third input coupled to the output of the third AGC circuit.

[0127] Aspect 22: The oscillation circuit according to aspect 21 further includes a fourth AGC circuit configured to replicate the topology of the third AGC circuit, wherein the logic element has a fourth input coupled to the output of the fourth AGC circuit.

[0128] Aspect 23: An oscillation monitoring method, the method comprising: generating an oscillation signal using an oscillator driving a resonator; generating a first signal based on the oscillation signal using a first automatic gain control (AGC) circuit; controlling a bias current for the oscillator based on the first signal; generating a second signal using a second AGC circuit, the second AGC circuit replicating the first AGC circuit; and effectively monitoring the oscillation signal based on the first signal and the second signal.

[0129] Aspect 24: The method according to aspect 23, wherein the effective monitoring includes effectively monitoring the oscillation signal without directly sensing the amplitude of the oscillation signal.

[0130] Aspect 25: The method according to aspect 23 or 24, wherein the effective monitoring includes comparing the first signal with the second signal, and outputting a status signal indicating a fault when the amplitude of the second signal is lower than the amplitude of the first signal.

[0131] Aspect 26: The method according to aspect 25 further includes generating another oscillation signal using a backup oscillator, and switching to use the other oscillation signal instead of the oscillation signal in response to the status signal indicating the fault.

[0132] Aspect 27: The method according to any one of Aspects 23 to 26, wherein: the first transistor size ratio between the first n-type transistor of the comparator and the second n-type transistor of the second AGC circuit is m:1; the second transistor size ratio between the first p-type transistor of the comparator and the second p-type transistor of the first AGC circuit is n:1; the second signal from the second AGC circuit controls the first n-type transistor of the comparator and the second n-type transistor of the second AGC circuit; the first signal from the first AGC circuit controls the first p-type transistor of the comparator and the second p-type transistor of the first AGC circuit; and the ratio m / n is equal to the ratio of the gain of the second AGC circuit to the gain of the first AGC circuit.

[0133] Aspect 28: The method according to any one of Aspects 23 to 27, wherein generating the first signal includes generating a first reference current related to the process, voltage, and temperature (PVT) of the first AGC circuit using a constant transconductance bias generator of the first AGC circuit.

[0134] Aspect 29: According to the method of aspect 28, generating the second signal includes generating a second reference current equal to the first reference current using the second AGC circuit.

[0135] Aspect 30: The method according to aspect 28 or 29, wherein the effective monitoring includes outputting a logic high signal from the comparator when the amplitude of the oscillation signal is estimated to be greater than or equal to the amplitude of the first reference current multiplied by (1-m / n).

[0136] Aspect 31: An apparatus for oscillation monitoring, the apparatus comprising: a component for generating an oscillation signal; a component for generating a first automatic gain control (AGC) signal based on the oscillation signal; a component for controlling a bias current of the component for generating the oscillation signal based on the first AGC signal; a component for generating a second AGC signal, the component for generating the second AGC signal replicating the component for generating the first AGC signal; and a component for effectively monitoring the oscillation signal based on the first AGC signal and the second AGC signal.

[0137] Additional considerations

[0138] The various operations described above can be performed by any suitable component capable of performing the corresponding function. This component may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Typically, where the operations illustrated in the figures exist, those operations may have corresponding components with similar numbering, plus functional components.

[0139] For example, components used to generate oscillating signals may include a driving resonator (e.g., Figure 4A The resonator 418 depicted in the image Figure 6 The resonator 618 or depicted in the image Figure 7B The oscillator of the resonator 707 shown (e.g., Figure 4A The oscillator 420 or 422 depicted in the image, or Figure 7B The oscillator 701 shown is used to generate the first AGC signal. Components for generating the first AGC signal may include a main AGC circuit (e.g., Figure 7A and Figure 7B The first AGC circuit 702 depicted in the diagram. The component used to control the bias current of the component used to generate the first signal may include an adjustable current source (e.g., Figure 4A The current source shown is 406 or 412. Figure 6 The current source 610 depicted in the text Figure 7B The transistor 708 illustrated herein). Components for generating the second AGC signal may include a replica AGC circuit (e.g., Figure 7A and Figure 7B The second AGC circuit 704 is depicted in the diagram. Components for effective monitoring may include logic components, such as processors or process monitors (e.g., Figure 4AThe security monitor 416 depicted in the image Figure 6 The process monitor 604 and / or oscillator health monitor 602 illustrated herein, or Figure 7A and Figure 7B The comparator 706 shown is an example.

[0140] As used herein, the term "determine" encompasses a wide variety of actions. For example, "determine" can include calculation, operation, processing, deduction, investigation, lookup (e.g., searching in a table, database, or other data structure), assertion, etc. Furthermore, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), etc. Additionally, "determine" can include parsing, selecting, choosing, building, etc.

[0141] As used in this article, the phrase “at least one of” in a list of entries refers to any combination of those entries (including a single member). As an example, “at least one of a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0142] The various exemplary logic blocks, modules, and circuits described in this disclosure can be implemented or executed using discrete hardware components designed to perform the functions described herein.

[0143] The methods disclosed herein include one or more steps or actions for implementing the described methods. Method steps and / or actions may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of particular steps and / or actions may be modified without departing from the scope of the claims.

[0144] It should be understood that the claims are not limited to the precise configurations and components illustrated above. Various modifications, variations, and alterations may be made to the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An oscillation circuit, the oscillation circuit comprising: An oscillator configured to generate an oscillating signal, the oscillator comprising: An oscillator core circuit, which is coupled to a resonator and configured to generate the oscillation signal such that the resonator can resonate; and An adjustable current source is coupled to the core circuit of the oscillator and configured to control the amplitude of the oscillation signal; A first automatic gain control (AGC) circuit, the first automatic gain control (AGC) circuit having an input coupled to the output of the oscillator and an output coupled to a control input of the adjustable current source; A second AGC circuit, configured to replicate a first AGC circuit, such that the first AGC circuit is configured to generate a first reference signal and the second AGC circuit is configured to generate a second reference signal that replicates the first reference signal; and A logic element having a first input coupled to the output of the first AGC circuit and a second input coupled to the output of the second AGC circuit.

2. The oscillation circuit of claim 1, wherein the logic element is configured to effectively monitor the oscillation signal based on the output of the first AGC circuit and the output of the second AGC circuit.

3. The oscillation circuit of claim 1, wherein the oscillation circuit is configured to effectively monitor the oscillation signal without directly sensing the amplitude of the oscillation signal.

4. The oscillation circuit of claim 1, wherein the logic element includes a comparator having a first input coupled to the output of the first AGC circuit and a second input coupled to the output of the second AGC circuit.

5. The oscillation circuit according to claim 4, wherein the comparator comprises: A first p-type transistor, the first p-type transistor having a source coupled to a power rail; A first n-type transistor has a source coupled to a reference potential node of the oscillation circuit and a drain coupled to a drain of a first p-type transistor, wherein at least one of the first p-type transistor or the first n-type transistor is tunable. and An inverter having an input coupled to the drain of the first p-type transistor and the drain of the first n-type transistor, and an output coupled to the output of the comparator.

6. The oscillation circuit according to claim 5, wherein the first AGC circuit comprises: A second p-type transistor, the second p-type transistor having a source coupled to the power rail; The second n-type transistor has a source coupled to the reference potential node and a drain coupled to the drain of the second p-type transistor; A third p-type transistor has a source coupled to the power rail and a gate coupled to the drain of the third p-type transistor, the gate of the second p-type transistor and the gate of the first p-type transistor. A third n-type transistor, the third n-type transistor having a drain that is coupled to the drain and the gate of the third p-type transistor; and A first resistive element is coupled between the source of the third n-type transistor and the reference potential node.

7. The oscillation circuit according to claim 6, wherein the first AGC circuit further comprises: A second resistive element is coupled between the gate of the second n-type transistor and the drain of the second n-type transistor; A third resistive element is coupled between the drain of the second n-type transistor and the gate of the third n-type transistor; and A first capacitor element is coupled between the gate of the third n-type transistor and the reference potential node.

8. The oscillation circuit according to claim 7, further comprising a second capacitor element coupled between the gate of the second n-type transistor and the output of the oscillator.

9. The oscillating circuit of claim 7, wherein the second n-type transistor, the third n-type transistor, the first resistive element, the second resistive element, and the third resistive element form at least a portion of a constant transconductance bias generator configured to generate a reference current related to process, voltage, and temperature (PVT).

10. The oscillation circuit according to claim 6, wherein the transistor size ratio between the first p-type transistor, the second p-type transistor and the third p-type transistor is n:1:1, where n≥1.

11. The oscillation circuit according to claim 6, wherein: The adjustable current source includes a fourth p-type transistor having a source coupled to the power rail, a drain coupled to the oscillator core circuit, and a gate coupled to the gate of the second p-type transistor and the third p-type transistor; and The transistor size ratio between the fourth p-type transistor, the second p-type transistor, and the third p-type transistor is x:1:1, where x≥1.

12. The oscillation circuit according to claim 6, wherein the second AGC circuit comprises: A fourth p-type transistor having a source coupled to the power rail; A fourth n-type transistor having a source coupled to the reference potential node and a drain coupled to the drain of the fourth p-type transistor, the gate of the fourth n-type transistor and the gate of the first n-type transistor; A fifth p-type transistor having a source coupled to the power rail and a drain coupled to the gate of the fifth p-type transistor and the gate of the fourth p-type transistor; A fifth n-type transistor, the fifth n-type transistor having a drain that is coupled to the drain and the gate of the fifth p-type transistor; and A second resistive element is coupled between the source of the fifth n-type transistor and the reference potential node.

13. The oscillation circuit according to claim 12, wherein the transistor size ratio between the first n-type transistor, the fourth n-type transistor and the fifth n-type transistor is m:1:1, where m≥1.

14. The oscillation circuit according to claim 13, wherein the transistor size ratio between the first p-type transistor, the second p-type transistor and the third p-type transistor is n:1:1, where n≥1.

15. The oscillation circuit of claim 14, wherein the ratio m / n is equal to the ratio of the gain of the second AGC circuit to the gain of the first AGC circuit.

16. The oscillation circuit according to claim 15, wherein: The first AGC circuit includes a constant transconductance bias generator configured to generate a reference current; and The ratio m / n is set such that the comparator is configured to output a logic high signal when the amplitude of the oscillation signal is estimated to be greater than or equal to the amplitude of the reference current multiplied by (1-m / n).

17. The oscillation circuit of claim 4, wherein the comparator is configured to output a logic high signal when the amplitude of the signal at the output of the second AGC circuit is greater than or equal to the amplitude of the signal at the output of the first AGC circuit.

18. The oscillation circuit of claim 1, wherein the first AGC circuit includes a constant transconductance bias generator configured to generate a first reference current relating to the process, voltage, and temperature (PVT) of the first AGC circuit.

19. The oscillation circuit of claim 18, wherein the second AGC circuit is configured to generate a second reference current equal to the first reference current.

20. The oscillation circuit of claim 1, wherein the input of the second AGC circuit is open-circuited, such that the input of the second AGC circuit is configured to have zero current.

21. The oscillation circuit according to claim 1, further comprising: A backup oscillator, configured to generate another oscillation signal, includes: Another oscillator core circuit for coupling to the resonator; and Another adjustable current source, coupled to the other oscillator core circuit and configured to control the amplitude of the other oscillation signal; and A third AGC circuit, the third AGC circuit having an input coupled to the output of the standby oscillator and an output coupled to the control input of the other adjustable current source, wherein the logic element has a third input coupled to the output of the third AGC circuit.

22. The oscillation circuit of claim 21, further comprising a fourth AGC circuit configured to replicate the topology of the third AGC circuit, wherein the logic element has a fourth input coupled to the output of the fourth AGC circuit.

23. An oscillation monitoring method, the method comprising: An oscillating signal is generated using an oscillator that drives a resonator. Based on the oscillation signal, a first signal is generated using a first automatic gain control (AGC) circuit; The bias current for the oscillator is controlled based on the first signal; A second signal is generated using a second AGC circuit, which replicates the first AGC circuit. as well as The oscillation signal is effectively monitored based on the first signal and the second signal, wherein the effective monitoring includes indicating a fault when the amplitude of the second signal is lower than the amplitude of the first signal.

24. The method of claim 23, wherein the effective monitoring comprises effectively monitoring the oscillation signal without directly sensing the amplitude of the oscillation signal.

25. The method of claim 23, wherein the effective monitoring further comprises comparing the first signal with the second signal, wherein the fault is indicated based on the comparison.

26. The method according to claim 25, further comprising: Use a backup oscillator to generate another oscillation signal; as well as In response to the indicated fault, the system switches to using the other oscillation signal instead of the oscillation signal.

27. The method according to claim 23, wherein: The size ratio of the first n-type transistor in the comparator to the second n-type transistor in the second AGC circuit is m:1; The size ratio of the second transistor between the first p-type transistor of the comparator and the second p-type transistor of the first AGC circuit is n:1; The second signal from the second AGC circuit controls the first n-type transistor of the comparator and the second n-type transistor of the second AGC circuit; The first signal from the first AGC circuit controls the first p-type transistor of the comparator and the second p-type transistor of the first AGC circuit; and The ratio m / n is equal to the ratio of the gain of the second AGC circuit to the gain of the first AGC circuit.

28. The method of claim 27, wherein generating the first signal comprises generating a first reference current related to the process, voltage, and temperature (PVT) of the first AGC circuit using a constant transconductance bias generator of the first AGC circuit.

29. The method of claim 28, wherein generating the second signal comprises using the second AGC circuit to generate a second reference current equal to the first reference current.

30. The method of claim 28, wherein effective monitoring includes outputting a logic high signal from the comparator when the amplitude of the oscillation signal is estimated to be greater than or equal to the amplitude of the first reference current multiplied by (1-m / n).

31. A device for oscillation monitoring, the device comprising: Components used to generate oscillating signals; A component for generating a first automatic gain control (AGC) signal based on the oscillation signal; A component for controlling the bias current of the component used to generate the oscillation signal based on a first AGC signal; The component for generating the second AGC signal is a copy of the component for generating the first AGC signal; and A component for effectively monitoring the oscillation signal based on the first AGC signal and the second AGC signal, wherein the component for effective monitoring includes a component for indicating a fault when the amplitude of the second AGC signal is lower than the amplitude of the first AGC signal.

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