Diagnostic Methods for Gate Oxide Degradation Mechanisms in Semiconductor Devices

Abstract

The present application relates to a method for diagnosing the gate oxide degradation mechanism of a semiconductor device, including: providing a semiconductor device, measuring and obtaining first dynamic capacitance data of the semiconductor device in an initial state and second dynamic capacitance data after an aging test; analyzing the first dynamic capacitance data and the second dynamic capacitance data to obtain a dynamic capacitance change trend of the semiconductor device; obtaining a charge change of a gate oxide layer in the semiconductor device according to the dynamic capacitance change trend analysis; and diagnosing the degradation mechanism of the gate oxide layer in the semiconductor device according to the charge change. The present application realizes accurate diagnosis of the degradation of different regions in the gate oxide layer of a semiconductor device, which helps to accurately analyze the specific degradation location and defect type in the gate oxide layer.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device detection, and in particular to a method for diagnosing a gate oxide degradation mechanism of a semiconductor device. Background Art

[0002] Metal Oxide Semiconductor Field Effect Transistor (MOSFET) based on silicon carbide (SiC) is considered to be the most promising silicon (Si)-based MOSFET device in the medium and high voltage field due to its advantages of high temperature, high voltage, high frequency and low loss.

[0003] However, due to the immaturity of the interface process between silicon carbide (SiC) and silicon dioxide (SiO2), the interface trap density of SiC MOSFET is usually 1-2 orders of magnitude higher than that of Si MOSFET. This phenomenon seriously affects the durability and reliability of the gate oxide-related parts of SiC MOSFET. Damage and degradation of the gate oxide at different locations will cause degradation of the capacitance or other electrical parameters and switching characteristics of the MOSFET to varying degrees. The degradation of the gate oxide will lead to unstable threshold voltage, while the positive drift of the threshold voltage will lead to increased loss and junction temperature, and the negative drift will lead to parasitic conduction, which will further affect the reliability of the MOSFET.

[0004] In view of this, a method is needed to diagnose the gate oxide degradation mechanism of the MOSFET device so as to improve the stability and reliability of the MOSFET device. Summary of the invention

[0005] Based on this, it is necessary to provide a method for diagnosing the gate oxide degradation mechanism of a semiconductor device, so as to achieve accurate diagnosis of the degradation conditions of different regions in the gate oxide layer of the semiconductor device.

[0006] The present application provides a method for diagnosing the gate oxide degradation mechanism of a semiconductor device, comprising:

[0007] Providing a semiconductor device, measuring and obtaining first dynamic capacitance data of the semiconductor device in an initial state and second dynamic capacitance data after an aging test;

[0008] Analyze the first dynamic capacitance data and the second dynamic capacitance data to obtain a dynamic capacitance change trend of the semiconductor device;

[0009] Obtaining a charge change condition of a gate oxide layer in the semiconductor device according to the dynamic capacitance change trend analysis;

[0010] The degradation mechanism of the gate oxide layer in the semiconductor device is diagnosed according to the charge change.

[0011] In one of the embodiments, the first dynamic capacitance data includes the input capacitance, output capacitance and reverse transfer capacitance of the semiconductor device before the aging test, and the second dynamic capacitance data includes the input capacitance, output capacitance and reverse transfer capacitance of the semiconductor device after the aging test.

[0012] In one embodiment, analyzing the first dynamic capacitance data and the second dynamic capacitance data to obtain a dynamic capacitance change trend of the semiconductor device includes:

[0013] Obtaining changes in the input capacitance, the output capacitance, and the reverse transfer capacitance before and after the aging test;

[0014] According to the changes of the input capacitance, the output capacitance and the reverse transfer capacitance, the changes of the gate-drain capacitance, the drain-source capacitance and the gate-source capacitance in the semiconductor device are analyzed to characterize the dynamic capacitance change trend of the semiconductor device.

[0015] In one embodiment, the changes of the gate-drain capacitance, the drain-source capacitance and the gate-source capacitance in the semiconductor device are obtained according to the following first set of expressions for characterizing the input capacitance, the output capacitance and the reverse transfer capacitance:

[0016] ;

[0017] ;

[0018] ;

[0019] in, is the input capacitance, is the output capacitance, is the reverse transfer capacitance, is the gate-drain capacitance, is the drain-source capacitance, is the gate-source capacitance.

[0020] In one embodiment, the obtaining the charge change of the gate oxide layer in the semiconductor device according to the dynamic capacitance change trend analysis includes:

[0021] Obtaining changes in the drift region depletion layer capacitance and the channel region depletion layer capacitance in the semiconductor device according to changes in the gate-drain capacitance, the drain-source capacitance and the gate-source capacitance;

[0022] Analyzing and acquiring charge changes of a gate oxide layer in the semiconductor device according to changes of the depletion layer capacitance of the drift region and the depletion layer capacitance of the channel region;

[0023] The drift region depletion layer capacitance is the equivalent capacitance of the depletion layer in the drift region of the semiconductor device, and the channel region depletion layer capacitance is the equivalent capacitance of the depletion layer in the channel region of the semiconductor device.

[0024] In one embodiment, the method for obtaining changes in the depletion layer capacitance of the drift region and the depletion layer capacitance of the channel region in the semiconductor device includes:

[0025] Obtaining a second set of expressions for characterizing the gate-source capacitance and the drain-source capacitance when the gate-source voltage is zero;

[0026] According to the change of the gate-source capacitance and the drain-source capacitance, analysis is performed to obtain the change of the drift region depletion layer capacitance and the channel region depletion layer capacitance.

[0027] In one embodiment, the second set of expressions includes:

[0028] ;

[0029] ;

[0030] in, represents the gate-source capacitance, represents the gate-drain capacitance, represents the depletion layer capacitance of the drift region, represents the channel region depletion layer capacitance, represents the characteristic capacitance between gate and source, represents the characteristic capacitance between the gate and source regions, represents the characteristic capacitance of the channel region, represents the characteristic capacitance of the drift region; where, , , and Remains constant and does not change with the charge of the gate oxide layer. and Varies with the charge of the gate oxide.

[0031] In one embodiment, the step of analyzing and obtaining a charge change of a gate oxide layer in the semiconductor device according to a change of the depletion layer capacitance of the drift region and the depletion layer capacitance of the channel region includes:

[0032] In the case where the depletion layer capacitance of the drift region decreases after the aging test, negative charges are injected into a first portion of the gate oxide layer close to the drift region;

[0033] In the case where the depletion layer capacitance of the channel region increases after the aging test, negative charges are injected into a second portion of the gate oxide layer close to the channel region.

[0034] In one embodiment, diagnosing the degradation mechanism of the gate oxide layer in the semiconductor device according to the charge change includes:

[0035] In the case where negative charges are injected into the gate oxide layer, the position where degradation occurs in the gate oxide layer is obtained according to the portion of the gate oxide layer into which the negative charges are injected.

[0036] In one of the embodiments, the semiconductor device includes at least one of a planar gate device and an asymmetric trench gate device.

[0037] In summary, the present application provides a method for diagnosing the gate oxide degradation mechanism of a semiconductor device, by respectively measuring first capacitance data and second capacitance data of the semiconductor device before and after an aging test, analyzing and obtaining a dynamic capacitance change trend of the semiconductor device, and obtaining a charge change of a gate oxide layer in the semiconductor device based on the dynamic capacitance change trend analysis, thereby diagnosing the degradation mechanism of the gate oxide layer in the semiconductor device based on the charge change, so as to achieve accurate diagnosis of the degradation conditions of different regions in the gate oxide layer in the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 Schematic diagram of capacitance distribution of a planar gate device in a related art.

[0040] Figure 2 Schematic diagram of a Cg-Vg characteristic curve of a planar gate device in the related art.

[0041] Figure 3 A flow chart of a method for diagnosing gate oxide degradation mechanism of a semiconductor device provided in one embodiment of the present application.

[0042] Figure 4 A schematic diagram of the structure of a semiconductor device in a method for diagnosing a gate oxide degradation mechanism of a semiconductor device provided in an embodiment of the present application.

[0043] Figure 5 A curve diagram of the dynamic capacitance change of a semiconductor device in a method for diagnosing a gate oxide degradation mechanism of a semiconductor device provided in an embodiment of the present application.

[0044] Figure 6 A schematic diagram of charge capture in the gate oxide layer in a method for diagnosing gate oxide degradation mechanisms of a semiconductor device provided in one embodiment of the present application.

[0045] Explanation of the reference numerals: 100 - first substrate; 110 - first drift region; 120 - body region; 130 - first gate; 131 - gate oxide layer; 140 - first source; 141 - first source region; 150 - first drain; X1 - first channel region; X2 - junction field effect transistor region; 200 - second substrate; 210 - second drift region; 220 - well region; 230 - second gate; 231 - gate oxide layer; 240 - second source; 241 - second source region; 250 - second drain; Y1 - second channel region. DETAILED DESCRIPTION

[0046] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0048] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0049] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0050] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] In the general semiconductor device gate oxide degradation mechanism, the gate capacitance-gate voltage method (i.e. Cg-Vg method) is mainly used to analyze the gate oxide damage of semiconductor devices. Figure 1 For a planar gate metal oxide semiconductor field effect transistor (MOSFET) based on silicon carbide (SiC), its structure generally includes a first substrate 100, a first drift region 110 and a body region 120 arranged in sequence from bottom to top, wherein a first gate 130 and a first source 140 are also arranged on the first drift region 110 and the body region 120, the first gate 130 is isolated from other parts by a gate oxide layer 131, a first source region 141 in contact with the first source 140 is arranged in the body region 120, and a first drain 150 is arranged below the first substrate 100.

[0052] Figure 1 The interface between the first drift region 110, the body region 120 and the gate oxide layer 131 is the interface between silicon carbide and silicon dioxide (SiO2), which is referred to as the gate oxide interface for convenience. As the external gate voltage changes, the first channel region X1 and the junction field effect transistor region X2 (Junction Field-Effect Transistor Region, JFET region) near the gate oxide interface will be in different accumulation, depletion and inversion states, so that the gate capacitance Cg of the planar gate device shows a trend of first decreasing and then increasing as the gate voltage Vg decreases.

[0053] See also Figure 2, under the conditions that the source voltage Vs and the drain voltage Vd are both 0V, the test voltage Vac is 25mv, and the test frequency f is 1MHz, the gate capacitance-gate voltage curve (Cg-Vg curve) can be divided into five relatively independent regions according to different interface states. In regions I and V, the value of the gate capacitance Cg is equal to the gate oxide capacitance of the planar gate device; in region II, the value of the gate capacitance Cg is mainly affected by the depletion layer capacitance of the first channel region X1; in regions III and IV, the value of the gate capacitance Cg is mainly affected by the depletion layer capacitance of the junction field effect transistor region X2. According to this characteristic, the region II of the Cg-Vg curve can be used to characterize the gate oxide interface degradation of the first channel region X1 in the planar gate device, while the regions III and IV of the curve can characterize the gate oxide interface degradation of the junction field effect transistor region X2 in the planar gate device. The extra positive charge injected into different regions of the gate oxide interface will cause a negative drift of the Cg-Vg curve of the corresponding region, and the extra negative charge injected into different regions of the gate oxide interface will cause a positive drift of the Cg-Vg curve of the corresponding region. At the same time, the injected charge density of the corresponding region can also be extracted according to the drift of the Cg-Vg curve. Therefore, the degradation mechanism of the planar gate device can be diagnosed according to its Cg-Vg curve.

[0054] However, the above method is only applicable to the degradation mechanism diagnosis of planar gate devices. For trench gate devices (especially asymmetric trench gate devices), the general Cg-Vg method cannot accurately analyze the specific degradation position and defect type of the gate oxide layer in the trench gate device. In addition, when measuring and obtaining the Cg-Vg characteristic curve, since the source and drain are connected to zero potential, the AC small signal is loaded on the gate, and the gate-drain capacitance Cgd cannot be measured. Therefore, when using the Cg-Vg method, the change of the gate-drain capacitance Cgd in the trench gate device is not taken into account, thereby affecting the accuracy of the trench gate device degradation mechanism diagnosis results.

[0055] In view of this, the present application provides a method for diagnosing the gate oxide degradation mechanism of a semiconductor device. Figure 3 A flowchart of a method for diagnosing gate oxide degradation mechanism of a semiconductor device provided in an embodiment of the present application is used to diagnose the degradation mechanism of a semiconductor device. Figure 3 , a method for diagnosing the gate oxide degradation mechanism of a semiconductor device provided by an embodiment of the present application is as follows.

[0056] Step S01: providing a semiconductor device, measuring and obtaining first dynamic capacitance data of the semiconductor device in an initial state and second dynamic capacitance data after an aging test.

[0057] Step S02: Analyze the first dynamic capacitance data and the second dynamic capacitance data to obtain a dynamic capacitance variation trend of the semiconductor device.

[0058] Step S03: acquiring the charge change of the gate oxide layer in the semiconductor device according to the dynamic capacitance change trend analysis.

[0059] Step S04: diagnosing the degradation mechanism of the gate oxide layer in the semiconductor device according to the charge change.

[0060] The method for diagnosing the gate oxide degradation mechanism of semiconductor devices as described above extracts the degradation conditions corresponding to different regions of the gate oxide layer during the stress process of the semiconductor device based on the dynamic capacitance change, thereby realizing the diagnosis of the gate oxide degradation mechanism and solving the problem that the general Cg-Vg method cannot accurately extract the gate oxide interface degradation mechanism in, for example, asymmetric trench gate devices.

[0061] In one embodiment, the first dynamic capacitance data and the second dynamic capacitance data of the semiconductor device can be measured at a measurement frequency of 1 MHz. In other embodiments of the present application, the dynamic capacitance change of the semiconductor device at other typical frequencies (typical frequencies range from 1 kHz to 1 MHz) can be measured according to the actual application scenario of the semiconductor device, and the present application does not limit this.

[0062] In one embodiment, the first dynamic capacitance data includes the input capacitance, output capacitance and reverse transfer capacitance of the semiconductor device before the aging test, and the second dynamic capacitance data includes the input capacitance, output capacitance and reverse transfer capacitance of the semiconductor device after the aging test. In other embodiments of the present application, the first dynamic capacitance data and the second dynamic capacitance data may also include other capacitance data that can directly or indirectly reflect the degradation of the gate oxide layer. This is common knowledge known to those skilled in the art and will not be expanded in this application.

[0063] In one of the embodiments, the dynamic capacitance variation trend of the semiconductor device is obtained based on the analysis of the first dynamic capacitance data and the second dynamic capacitance data, including: obtaining the changes of the input capacitance, the output capacitance and the reverse transfer capacitance before and after the aging test; analyzing the changes of the input capacitance, the output capacitance and the reverse transfer capacitance to obtain the changes of the gate-drain capacitance, the drain-source capacitance and the gate-source capacitance in the semiconductor device to characterize the dynamic capacitance variation trend of the semiconductor device.

[0064] In one of the embodiments, the difference between the input capacitance in the first dynamic capacitance data and the second dynamic capacitance data can be used to reflect the change in the input capacitance of the semiconductor device before and after the aging test, the difference between the output capacitance in the first dynamic capacitance data and the second dynamic capacitance data can be used to reflect the change in the output capacitance of the semiconductor device before and after the aging test, and the difference between the reverse transfer capacitance in the first dynamic capacitance data and the second dynamic capacitance data can be used to reflect the change in the reverse transfer capacitance of the semiconductor device before and after the aging test.

[0065] In one embodiment, according to the first set of expressions for characterizing input capacitance, output capacitance and reverse transfer capacitance, i.e., expressions (1) to (3), changes in gate-drain capacitance, drain-source capacitance and gate-source capacitance in a semiconductor device are obtained.

[0066] ; (1)

[0067] ; (2)

[0068] ; (3)

[0069] in, is the input capacitance, is the output capacitor, is the reverse transfer capacitance, is the gate-drain capacitance, is the drain-source capacitance, is the gate-source capacitance.

[0070] It should be noted that according to the first set of expressions (1) to (3), the gate-drain capacitance The change of reverse transfer capacitance The change of drain-source capacitance is the same as The change in output capacitance can be Changes in reverse transfer capacitance The difference between the changes in gate-source capacitance The change in input capacitance can be Changes in reverse transfer capacitance The difference between the changes in the

[0071] In one of the embodiments, the charge change of the gate oxide layer in the semiconductor device is obtained according to the dynamic capacitance change trend analysis, including: obtaining the change of the drift region depletion layer capacitance and the channel region depletion layer capacitance in the semiconductor device according to the change of the gate-drain capacitance, the drain-source capacitance and the gate-source capacitance, wherein the drift region depletion layer capacitance is the equivalent capacitance of the depletion layer in the drift region of the semiconductor device, and the channel region depletion layer capacitance is the equivalent capacitance of the depletion layer in the channel region of the semiconductor device; obtaining the charge change of the gate oxide layer in the semiconductor device according to the change analysis of the drift region depletion layer capacitance and the channel region depletion layer capacitance.

[0072] In one embodiment, a method for obtaining changes in depletion layer capacitance of a drift region and depletion layer capacitance of a channel region in a semiconductor device includes: obtaining a second set of expressions for characterizing gate-source capacitance and drain-source capacitance when the gate-source voltage is zero; and obtaining changes in depletion layer capacitance of a drift region and depletion layer capacitance of a channel region by analyzing changes in gate-source capacitance and drain-source capacitance.

[0073] In one embodiment, when the gate-source voltage is zero, a second set of expressions for characterizing the gate-source capacitance and the drain-source capacitance are as follows.

[0074] ; (4)

[0075] ; (5)

[0076] in, represents the gate-source capacitance, represents the gate-drain capacitance, represents the depletion layer capacitance of the drift region, represents the channel region depletion layer capacitance, represents the characteristic capacitance between gate and source, represents the characteristic capacitance between the gate and source regions, represents the characteristic capacitance of the channel region, represents the characteristic capacitance of the drift region; where, , , and Remains constant and does not change with the charge of the gate oxide layer. and Varies with the charge of the gate oxide.

[0077] In one of the embodiments, the charge change of the gate oxide layer in the semiconductor device is obtained based on the change of the depletion layer capacitance of the drift region and the depletion layer capacitance of the channel region, including: when the depletion layer capacitance of the drift region decreases after an aging test, negative charge is injected into the first part of the gate oxide layer near the drift region; when the depletion layer capacitance of the channel region increases after an aging test, negative charge is injected into the second part of the gate oxide layer near the channel region.

[0078] In one embodiment, the degradation mechanism of the gate oxide layer in the semiconductor device is diagnosed based on the charge change, including: when negative charge is injected into the gate oxide layer, the degradation position in the gate oxide layer is obtained based on the part of the gate oxide layer where the negative charge is injected.

[0079] Figure 4 A schematic diagram of the structure of a semiconductor device in a method for diagnosing a gate oxide degradation mechanism of a semiconductor device provided in an embodiment of the present application, Figure 5 for Figure 4 Dynamic capacitance change curve of semiconductor devices in the Figure 6 for Figure 5 Schematic diagram of charge capture in the gate oxide layer. Figures 4 to 6 The application of the method for diagnosing the gate oxide degradation mechanism of a semiconductor device provided by an embodiment of the present application is described in detail.

[0080] For example, Figure 4 Schematic diagram of the structure of an asymmetric trench gate SiC MOSFET (hereinafter referred to as a trench gate device). Figure 4 The trench gate device includes a second substrate 200, a second drift region 210 located on the second substrate 200, a well region 220 and a second gate 230 located on the second drift region 210, a second source 240 located on the second gate 230, and a second drain 250 located below the second substrate 200, wherein the second gate 230 is isolated from the second source 240 and the second drift region 210 by a gate oxide layer 231, a second source region 241 is provided on a side of the gate oxide layer 231 away from the second gate 230, and the second source region 241 is in contact with the second source 240 and the well region 220, and a second channel region Y1 of the trench gate device is located between the second source region 241, the well region 220, the gate oxide layer 231 and the second drift region 210.

[0081] For example, see Figure 5 , the input capacitance of the trench gate device After aging test, the output capacitance increases changes very little, while the reverse transfer capacitance This indicates that the gate-source capacitance Increase, while the gate-drain capacitance Reduced, and gate-source capacitance The increase exceeds the gate-drain capacitance of reduction.

[0082] See also Figure 6 , gate-source capacitance and gate-drain capacitance Affected by the thickness of the depletion layer (not marked in the figure). When negative charges are injected into the portion of the gate oxide layer 231 close to the second channel region Y1, the thickness of the depletion layer of the second channel region Y1 decreases, and the channel region depletion layer capacitance The gate-source capacitance of the trench gate device Since the majority carriers of the second drift region 210 are electrons, when negative charges are injected into the portion of the gate oxide layer 231 close to the second drift region 210, the depletion layer thickness increases, and the depletion layer capacitance of the drift region decreases, resulting in the gate-drain capacitance of the trench gate device Therefore, for Figure 6 For the trench gate device shown in FIG. 1 , the portion of the gate oxide layer 231 close to the second channel region Y1 (ie Figure 6 The portion where the gate oxide layer 231 and the second channel region Y1 meet (hereinafter referred to as the second portion of the gate oxide layer 231) and the portion close to the second drift region 210 (ie, Figure 6 The portion where the gate oxide layer 231 and the second drift region 210 meet (hereinafter referred to as the first portion of the gate oxide layer 231) are all injected with negative charges. At the same time, since the portion where the gate oxide layer 231 has interface state defects is more likely to capture electrons (i.e., negative charges), the first portion and the second portion of the trench gate device both have interface state defects.

[0083] It should be noted that the method for diagnosing the gate oxide degradation mechanism of a semiconductor device provided in the present application can be used not only to diagnose the degradation mechanism of a trench gate device, but can also be used to diagnose the degradation mechanism of other semiconductor devices (such as a planar gate device), and the present application does not impose any limitation on this.

[0084] In summary, the present application provides a method for diagnosing the gate oxide degradation mechanism of a semiconductor device, which is used to diagnose the degradation mechanism of a semiconductor device. By respectively measuring the first capacitance data and the second capacitance data of the semiconductor device before and after an aging test, the dynamic capacitance change trend of the semiconductor device is analyzed, and the charge change of the gate oxide layer in the semiconductor device is obtained according to the dynamic capacitance change trend analysis, thereby diagnosing the degradation mechanism of the gate oxide layer in the semiconductor device according to the charge change, so as to achieve accurate diagnosis of the degradation conditions of different regions in the gate oxide layer in the semiconductor device.

[0085] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0086] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for diagnosing gate oxide degradation mechanism of a semiconductor device, characterized in that: include: Providing a semiconductor device, measuring and obtaining first dynamic capacitance data of the semiconductor device in an initial state and second dynamic capacitance data after an aging test; Analyze the first dynamic capacitance data and the second dynamic capacitance data to obtain a dynamic capacitance change trend of the semiconductor device; Obtaining a charge change condition of a gate oxide layer in the semiconductor device according to the dynamic capacitance change trend analysis; diagnosing a degradation mechanism of the gate oxide layer in the semiconductor device according to the charge change; Wherein, obtaining the charge change of the gate oxide layer in the semiconductor device according to the dynamic capacitance change trend analysis includes: Obtaining changes in the depletion layer capacitance of the drift region and the depletion layer capacitance of the channel region in the semiconductor device according to changes in the gate-drain capacitance, the drain-source capacitance, and the gate-source capacitance, wherein the depletion layer capacitance of the drift region is an equivalent capacitance of the depletion layer in the drift region of the semiconductor device, and the depletion layer capacitance of the channel region is an equivalent capacitance of the depletion layer in the channel region of the semiconductor device; Analyzing and acquiring charge changes of a gate oxide layer in the semiconductor device according to changes of the depletion layer capacitance of the drift region and the depletion layer capacitance of the channel region; The method for obtaining the change of the depletion layer capacitance of the drift region and the depletion layer capacitance of the channel region in the semiconductor device comprises: An expression used to characterize the gate-source capacitance and the drain-source capacitance when the gate-source voltage is zero is defined as a second group of expressions, and the second group of expressions is obtained. When the semiconductor device is an asymmetric trench gate device, the second group of expressions includes: ； ； in, represents the gate-source capacitance, represents the gate-drain capacitance, represents the depletion layer capacitance of the drift region, represents the channel region depletion layer capacitance, represents the characteristic capacitance between gate and source, represents the characteristic capacitance between the gate and source regions, represents the characteristic capacitance of the channel region, that is, the characteristic capacitance between the gate and the channel region, represents the characteristic capacitance of the drift region, that is, the characteristic capacitance between the gate and the drift region; wherein, , , and Remains constant and does not change with the charge of the gate oxide layer. and It changes with the charge of the gate oxide layer; Analyzing the changes of the gate-source capacitance and the drain-source capacitance to obtain the changes of the drift region depletion layer capacitance and the channel region depletion layer capacitance includes: In a case where the depletion layer capacitance of the drift region decreases after the aging test, negative charges are injected into a first portion of the gate oxide layer, the first portion being a portion of the gate oxide layer close to the drift region; In the case where the capacitance of the depletion layer in the channel region increases after the aging test, negative charges are injected into a second portion of the gate oxide layer, the second portion being a portion of the gate oxide layer close to the channel region; The diagnosing the degradation mechanism of the gate oxide layer in the semiconductor device according to the charge change includes: In the case where negative charges are injected into the gate oxide layer, the position where degradation occurs in the gate oxide layer is obtained according to the portion of the gate oxide layer into which the negative charges are injected.

2. The method for diagnosing gate oxide degradation mechanism of a semiconductor device according to claim 1, characterized in that: The first dynamic capacitance data includes input capacitance, output capacitance, and reverse transfer capacitance of the semiconductor device before the aging test, and the second dynamic capacitance data includes input capacitance, output capacitance, and reverse transfer capacitance of the semiconductor device after the aging test.

3. The method for diagnosing gate oxide degradation mechanism of semiconductor device according to claim 2, characterized in that: The analyzing the first dynamic capacitance data and the second dynamic capacitance data to obtain a dynamic capacitance change trend of the semiconductor device includes: Obtaining changes in the input capacitance, the output capacitance, and the reverse transfer capacitance before and after the aging test; According to the changes of the input capacitance, the output capacitance and the reverse transfer capacitance, the changes of the gate-drain capacitance, the drain-source capacitance and the gate-source capacitance in the semiconductor device are analyzed to characterize the dynamic capacitance change trend of the semiconductor device.

4. The method for diagnosing gate oxide degradation mechanism of a semiconductor device according to claim 3, characterized in that: According to the following first set of expressions for characterizing the input capacitance, the output capacitance and the reverse transfer capacitance, the changes of the gate-drain capacitance, the drain-source capacitance and the gate-source capacitance in the semiconductor device are obtained: ； ； ； in, is the input capacitance, is the output capacitance, is the reverse transfer capacitance, is the gate-drain capacitance, is the drain-source capacitance, is the gate-source capacitance.

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