Methods for optimizing memory transmission signals, memory controllers, and electronic devices.

Abstract

This application relates to a method for optimizing the transmission signals of a memory, a memory controller, and an electronic device, belonging to the field of electronic technology. The method includes adjusting the value of a first DCA register group and generating a DQ data signal based on the optimal value of the adjusted first DCA register group; the value of the first DCA register group is phase-dependent with a first system clock signal in the memory, and the first system clock signal is used to generate the DQ data signal; based on the optimal value of the adjusted first DCA register group, the value of a second DCA register group is adjusted, and a DQS clock signal is generated based on the optimal value of the adjusted second DCA register group; the value of the second DCA register group is phase-dependent with a second system clock signal in the memory, and the second system clock signal is used to generate the DQS clock signal, wherein the DQS clock signal and the DQ data signal are transmission signals between the memory and the memory controller. By improving the quality of the memory's transmission signals, the read / write reliability of the memory is improved.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, and specifically relates to a method for optimizing the transmission signals of a memory, a memory controller, and an electronic device. Background Technology

[0002] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is a type of memory where the data rate is twice the clock rate; it is often simply referred to as DDR memory. For example... Figure 1 As shown, in a DDR system, the transmitted data DQ is synchronized with the rising and falling edges of the clock DQS. The memory controller interacts with the DDR memory through the physical layer interface (PHY), which is referred to as the DDR interface. The reliability of DDR interface reads and writes determines the reliability of the memory controller.

[0003] As the operating frequency of the Central Processing Unit (CPU) increases, the required frequency of the DDR interface also increases. Higher frequencies can easily lead to problems such as signal duty cycle distortion and clock jitter, and the resulting decrease in read and write reliability is becoming increasingly significant. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a method, a memory controller, and an electronic device for optimizing the transmission signals of a memory, so as to improve the quality of the transmission signals of the memory and thereby improve the read and write reliability of the memory.

[0005] The embodiments of this application are implemented as follows:

[0006] In a first aspect, embodiments of this application provide a method for optimizing transmission signals in a memory, comprising: adjusting the value of a first DCA register group, and generating a DQ data signal based on the optimal value of the adjusted first DCA register group; wherein the value of the first DCA register group is phase-dependent with a first system clock signal in the memory, and the first system clock signal is used to generate the DQ data signal; adjusting the value of a second DCA register group based on the optimal value of the adjusted first DCA register group, and generating a DQS clock signal based on the optimal value of the adjusted second DCA register group; wherein the value of the second DCA register group is phase-dependent with a second system clock signal in the memory, and the second system clock signal is used to generate the DQS clock signal; wherein the DQS clock signal and the DQ data signal are transmission signals between the memory and the memory controller.

[0007] In the above embodiments, the DDR5 (5th generation DDR) specification provides a set of DCA registers that can improve the system clock phase relationship. The value of the DCA register is related to the phase of the system clock signal in the DDR memory. The system clock signal is used to generate the transmission signals of the DDR memory (including the DQS clock signal and the DQ data signal). Therefore, this application adopts a novel approach: by adjusting the value of the DCA register, the change in the value of the DCA register will change the phase of the system clock signal, thereby changing the high and low level times of the DQS clock signal and the DQ data signal. This method improves the duty cycle distortion and clock jitter of the memory's transmission signals, thereby enhancing the read / write reliability of the memory. Furthermore, when adjusting the value of the DCA register, the value of the first DCA register group is first adjusted through training, so that the training result of the DQ data signal is not affected by the initial duty cycle and period jitter of the DQS clock signal. Based on the optimized DQ data signal, the duty cycle and period jitter of the DQS clock signal are further optimized. The entire process does not require multiple iterations of mutual optimization between the DQS clock signal and the DQ data signal, nor does it require additional hardware circuitry, thus reducing hardware overhead and training time.

[0008] In one possible implementation of the first aspect embodiment, the first system clock signal includes 2 n There are several phase clock signals, each with an independent DCA register, where n is an integer greater than or equal to 2. Adjusting the values ​​of the first DCA register group includes: adjusting the values ​​of the DCA registers corresponding to the first type of phase clock signals in the first DCA register group to obtain the optimal values ​​of the DCA registers corresponding to the first type of phase clock signals to optimize the clock jitter of the DQ data signal, wherein the first type of phase clock signal is a phase clock signal related to the clock jitter of the DQ data signal; based on the optimal values ​​of the DCA registers corresponding to the first type of phase clock signals obtained from the adjustment, adjusting the values ​​of the DCA registers corresponding to the second type of phase clock signals in the first DCA register group to obtain the optimal values ​​of the DCA registers corresponding to the second type of phase clock signals, wherein the second type of phase clock signal is a phase clock signal related to the duty cycle of the DQ data signal.

[0009] In the above embodiment, the value of the DCA register corresponding to the first type of phase clock signal is first adjusted to optimize the clock jitter of the DQ data signal. Then, the value of the DCA register corresponding to the second type of phase clock signal is adjusted to optimize the duty cycle distortion of the DQ data signal. This can achieve the goal while reducing the adjustment time, so that the training optimization time and the number of phases of the system clock satisfy a linear relationship.

[0010] In one possible implementation of the first aspect embodiment, the first system clock signal includes 2 n There are 1 phase clock signal, each with an independent DCA register, where n is an integer greater than or equal to 2; adjusting the value of the first DCA register group includes: adjusting the value of the first DCA register group, and generating a DQ data signal based on the adjusted value of the first DCA register group; obtaining 2 correctly sampled data by sampling the DQ data signal using the DQS clock signal. n Each eye diagram width represents the phase difference between the corresponding phase clock signal and the next phase clock signal; based on 2 n The eye diagram width is adjusted to change the value of the first DCA register group so that the new DQ data signal is sampled using the DQS clock signal to obtain correctly sampled data. n Each eye diagram has the same width, and the new DQ data signal is generated based on the adjusted value of the first DCA register group.

[0011] In the above embodiments, by obtaining 2 n The eye diagram width is used to adjust the value of the first DCA register group so that the new DQ data signal (generated based on the adjusted value of the first DCA register group) is sampled using the DQS clock signal to obtain the correct sampled data. n Each eye diagram has the same width, which optimizes the duty cycle of the DQ data signal.

[0012] In conjunction with one possible implementation of the first aspect embodiment, based on 2 n The eye diagram width adjustment of the first DCA register group includes: n rounds of adjusting the value of the first DCA register group; wherein, the first round of adjusting the value of the first DCA register group includes: based on the previous 2 n-1 Eye width and the last 2 n-1 The eye diagram width is adjusted, and the second eye diagram in the first DCA register group is adjusted. n-1 +1 phase clock signal value of DCA register, so that the first 2 n-1 The sum of the widths of each eye diagram and the last two n-1 The sum of the widths of the eye diagrams is the same; i takes values ​​from 2 to n-1 sequentially. The adjustment of the first DCA register group in the i-th round includes: generating a new DQ data signal based on the optimal value of the first DCA register group obtained in the (i-1)-th round of adjustment, and obtaining a new 2 based on the new DQ data signal. n Eye diagram width; based on the new 2 n The eye diagram width is adjusted in the m*2th register group of the first DCA register group. n-i The value of the DCA register is increased by 1 phase clock signal to make the sum of the widths of each eye diagram the same, and the sum of the widths of each eye diagram is 2 for adjacent eyes.n-i The sum of the widths of the eye diagrams, where m takes values ​​from [1, 2] in sequence. i Odd numbers within the range of ); the nth round of adjusting the value of the first DCA register group includes: generating a new DQ data signal based on the optimal value of the first DCA register group obtained in the (n-1)th round of adjustment, and obtaining a new 2 based on the new DQ data signal. n Eye diagram width; based on the new 2 n The eye diagram width is adjusted by changing the value of the DCA register of the (k+1)th phase clock signal in the first DCA register group to make each eye diagram width the same, where k takes values ​​from [1, 2] to [3]. n Odd numbers within the range of ).

[0013] In the above embodiment, by adjusting the value of the first DCA register group in n rounds, the duty cycle of the DQ data signal can be adjusted to the optimal value. This method is applicable to 2... n The DQS clock signal and DQ data signal generated by the -phase system clock greatly improve the application scenarios of this application.

[0014] In one possible implementation of the first aspect embodiment, the first system clock signal includes 2 n There are n phase clock signals, each with an independent DCA register, where n is an integer greater than or equal to 2; adjusting the value of the first DCA register group includes: involving n rounds of adjusting the value of the first DCA register group; wherein, the first round of adjusting the value of the first DCA register group includes: adjusting the value of the second phase clock signal in the first DCA register group based on the first eye width and the second eye width. n-1 +1 phase clock signal value of DCA register, so that the first 2 n-1 The sum of the eye diagram widths corresponding to each phase clock signal and the following 2 n-1 The sum of the eye diagram widths corresponding to each phase clock signal is the same, wherein the sum of the widths of the first eye diagram is equal to the sum of the widths of the previous two phase clock signals. n-1 The sum of the eye diagram widths corresponding to each phase clock signal, and the sum of the widths of the second eye diagram is the sum of the widths of the last two phase clock signals. n-1 The sum of the eye diagram widths corresponding to each phase clock signal, where each eye diagram width represents the phase difference between the corresponding phase clock signal and the next phase clock signal; i takes values ​​from 2 to n-1 sequentially, and the i-th round of adjusting the value of the first DCA register group includes: generating a new DQ data signal based on the optimal value of the first DCA register group obtained in the (i-1)-th round of adjustment, and obtaining 2 i The sum of the widths of the two eye diagrams, where the sum of the widths of each eye diagram is equal to the sum of the widths of the two adjacent eye diagrams. n-i The sum of the eye diagram widths corresponding to each phase clock signal; based on 2 i The eye diagram width and adjustment of the m*2th eye in the first DCA register group n-iThe value of the DCA register for +1 phase clock signals is used to make the width of each eye diagram the same, where m takes values ​​from [1, 2] in sequence. i Odd numbers within the range of ); the nth round of adjusting the value of the first DCA register group includes: generating a new DQ data signal based on the optimal value of the first DCA register group obtained in the (n-1)th round of adjustment, and obtaining 2 based on the new DQ data signal. n Eye width; based on 2 n The eye diagram width is adjusted by changing the value of the DCA register of the (k+1)th phase clock signal in the first DCA register group to make each adjacent eye diagram width the same, where k takes values ​​from [1, 2] to [3]. n Odd numbers within the range of ).

[0015] In the above embodiment, by adjusting the value of the first DCA register group in n rounds, the duty cycle of the DQ data signal can be adjusted to the optimal value. This method is applicable to 2... n The DQS clock signal and DQ data signal generated by the -phase system clock greatly improve the application scenarios of this application. At the same time, during the first n-1 rounds of adjustment, instead of obtaining the eye diagram width of each phase sequentially and then calculating the sum of the eye diagram widths of multiple phases, the sum of the eye diagram widths of multiple phases is obtained directly, which can improve efficiency.

[0016] In one possible implementation of the first aspect embodiment, the second system clock signal includes 2 n There are 1 phase clock signal, each phase clock signal has an independent DCA register, and n is an integer greater than or equal to 2; adjusting the value of the second DCA register group includes: adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group to obtain the optimal value of the DCA register corresponding to the first type of phase clock signal, so as to optimize the clock jitter of the DQS clock signal, wherein the first type of phase clock signal is a phase clock signal related to the clock jitter of the DQS clock signal; based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment, adjusting the value of the DCA register corresponding to the second type of phase clock signal in the second DCA register group to obtain the optimal value of the DCA register corresponding to the second type of phase clock signal, wherein the second type of phase clock signal is a phase clock signal related to the duty cycle of the DQS clock signal.

[0017] In the above embodiment, the value of the DCA register corresponding to the first type of phase clock signal is first adjusted to optimize the clock jitter of the DQS clock signal. Then, the value of the DCA register corresponding to the second type of phase clock signal is adjusted to optimize the duty cycle distortion of the DQS clock signal. This can achieve the goal while reducing the adjustment time, so that the training optimization time and the number of phases of the system clock satisfy a linear relationship.

[0018] In one possible implementation of the first aspect embodiment, adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group includes: adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group to obtain a first maximum eye diagram of correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal; and taking the value of the DCA register corresponding to the first maximum eye diagram as the optimal value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group.

[0019] In the above implementation scheme, when adjusting the value of the DCA register corresponding to the first type of phase clock signal, by continuously adjusting the value of the DCA register, an eye diagram interval that can correctly sample data can be obtained each time the value of the DCA register is adjusted. After multiple adjustments, multiple eye diagrams can be obtained. The largest eye diagram is selected from them, and the value of the DCA register corresponding to the largest eye diagram is taken as the optimal value of the DCA register. In this way, the optimal DCA setting can be obtained, so that the period of adjacent clock cycles is consistent, which can solve the jitter problem during the DQS clock signal cycle and improve the read and write speed and reliability of the memory.

[0020] In one possible implementation of the first aspect embodiment, adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group to obtain the first maximum eye diagram of correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal includes: involving n-1 rounds of adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group; the first round of adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group includes: adjusting the value of the second... n-1 The value of the DCA register corresponding to the +1 phase clock signal is used to obtain the first maximum eye diagram of the correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal; i is sequentially taken from 2 to n-1, and the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group is adjusted in the i-th round, including: based on the optimal value of the second DCA register group obtained in the (i-1)-th round, the value of the m*2-th phase clock signal in the second DCA register group is adjusted multiple times. n-iThe value of the DCA register with +1 phase clock signal is used to obtain the first maximum eye diagram of the correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal, where m takes values ​​of [1, 2]. i Odd numbers within the range of ).

[0021] In the above embodiment, by adjusting the value of the second DCA register group in the above-described n-1 rounds, the second... n-1 The value of the DCA register corresponding to the +1 phase clock signal, the m*2nd... n-i By optimizing the value of the DCA register for the +1 phase clock signal, the jitter problem during the DQS clock signal cycle can be resolved, and the above method can be applied to 2 n The DQS clock signal and DQ data signal generated by the -phase system clock greatly improve the application scenarios of this application.

[0022] In one possible implementation of the first aspect embodiment, based on the optimal value of the DCA register corresponding to the second type of phase clock signal in the second DCA register group, the value of the DCA register corresponding to the second type of phase clock signal in the second DCA register group is adjusted, including: generating a new DQS clock signal based on the optimal value of the DCA register corresponding to the first type of phase clock signal.

[0023] Adjust the value of the DCA register corresponding to the second type of phase clock signal to obtain the second maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the new DQS clock signal; take the value of the DCA register corresponding to the second maximum eye diagram as the optimal value of the DCA register corresponding to the second type of phase clock signal.

[0024] In the above implementation scheme, when adjusting the value of the DCA register corresponding to the second type of phase clock signal, by continuously adjusting the value of the DCA register, an eye diagram interval that can correctly sample data can be obtained each time the value of the DCA register is adjusted. After multiple adjustments, multiple eye diagrams can be obtained. The largest eye diagram is selected from them, and the value of the DCA register corresponding to the largest eye diagram is taken as the optimal value of the DCA register. In this way, the optimal duty cycle setting can be obtained, so that the duty cycle of odd and even periods is adjusted to the optimal, thereby improving the read and write speed and reliability of the memory.

[0025] In one possible implementation of the first aspect embodiment, adjusting the value of the DCA register corresponding to the second type of phase clock signal to obtain the second maximum eye diagram for correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the new DQS clock signal includes: repeatedly adjusting the value of the DCA register of the (k+1)th phase clock signal in the second DCA register group to obtain the width of the second eye diagram for correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the new DQS clock signal, wherein k sequentially takes values ​​from [1, 2...]. n Odd numbers within the range of ).

[0026] In the above embodiment, through the aforementioned adjustments, the value of the DCA register corresponding to the (k+1)th phase clock signal can be optimized, thereby optimizing the duty cycle of the DQS clock signal. Furthermore, the above method is applicable to 2... n The DQS clock signal and DQ data signal generated by the -phase system clock greatly improve the application scenarios of this application.

[0027] Secondly, embodiments of this application also provide a memory controller, which is connected to a memory via a DQS clock line and a DQ data line. The DQS clock line is used to transmit a DQS clock signal, and the DQ data line is used to transmit a DQ data signal. The memory controller includes: a training engine configured to instruct the memory to adjust the value of a first DCA register group to obtain an optimal value for the first DCA register group; wherein the value of the first DCA register group is phase-dependent with a first system clock signal in the memory, and the first system clock signal is used to generate the DQ data signal; the training engine is further configured to, based on the adjusted optimal value of the first DCA register group, instruct the memory to adjust the value of a second DCA register group to obtain an optimal value for the second DCA register group; wherein the value of the second DCA register group is phase-dependent with a second system clock signal in the memory, and the second system clock signal is used to generate the DQS clock signal.

[0028] In one possible implementation of the second aspect embodiment, the memory controller further includes: a measurement unit configured to acquire the eye diagram width of correctly sampled data obtained by sampling data transmitted by the DQ data signal using the DQS clock signal, and to acquire the maximum eye diagram width of correctly sampled data obtained by sampling data transmitted by the DQ data signal using the DQS clock signal; the training engine is further configured to instruct the memory to adjust the value of the first DCA register group based on the eye diagram width, and to instruct the memory to adjust the value of the second DCA register group based on the maximum eye diagram width.

[0029] Thirdly, embodiments of this application also provide an electronic device, including: a memory and a memory controller as shown in the second aspect embodiment above. The memory controller is connected to the memory via a DQS clock line and a DQ data line. The DQS clock line is used to transmit a DQS clock signal, and the DQ data line is used to transmit a DQ data signal. The memory includes a first DCA register group, a second DCA register group, and a signal generation unit. The signal generation unit is configured to adjust the phase of a first system clock signal based on the value of the first DCA register group and generate the DQ data signal based on the first system clock signal, and to adjust the phase of a second system clock signal based on the value of the second DCA register group and generate the DQS clock signal based on the second system clock signal.

[0030] For the beneficial effects of the second and third aspect embodiments, please refer to the effective effects of the first aspect embodiment and any possible implementation of the first aspect embodiment.

[0031] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0033] Figure 1 A schematic diagram showing the connection between the memory controller and the DDR memory in a DDR system is shown.

[0034] Figure 2 This illustration shows a schematic diagram of the principle of generating a memory transmission signal based on a 4-phase system clock, according to an embodiment of this application.

[0035] Figure 3 A flowchart illustrating a method for optimizing the transmission signals of a memory according to an embodiment of this application is shown.

[0036] Figure 4 This illustration shows a data pattern with optimized duty cycle provided by an embodiment of this application.

[0037] Figure 5This illustration shows a schematic diagram of the principle of adjusting the value of the DCA register of the IBCLK_DQ phase clock signal according to an embodiment of this application.

[0038] Figure 6 This illustration shows a data pattern for optimizing the clock jitter and duty cycle of a DQS clock signal according to an embodiment of this application.

[0039] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0042] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0043] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can refer to a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0044] To optimize the transmission signals of the memory (including the DQS clock signal and the DQ data signal) and improve the quality of the transmission signals, such as by reducing the duty cycle distortion of the memory transmission signals, or clock jitter (including period jitter, i.e., different durations of different clock cycles) and duty cycle distortion, this application provides a method for optimizing the transmission signals of the memory by adjusting the value of the DCA (Duty Cycle Adjuster) register.

[0045] The DDR5 (5th generation DDR) specification provides a set of features to improve system clock speed (including 2...). n A register, referred to as the DCA register, is used to determine the phase relationship of each phase clock signal. Each phase clock signal has its own independent DCA register, and the value of the DCA register is related to the phase of the system clock signal in the DDR memory. The system clock signal is used to generate the DDR memory's transmission signals, specifically the DQS clock signal and the DQ data signal. Changes in the DCA register value alter the phase of the system clock signal, thereby changing the high and low levels of the DQS and DQ data signals, thus optimizing duty cycle distortion. Furthermore, changes in the DCA register value may also alter the duration distribution between different clock cycles of the DQS and DQ data signals, thus optimizing clock jitter. Therefore, by training the values ​​of these registers, the duty cycle and clock jitter of the memory's transmission signals can be improved, thereby enhancing the read / write reliability of the memory. The method described in this application can be applied to other memories that also generate memory transmission signals based on the system clock signal and use DCA registers to change the phase of the system clock signal.

[0046] The memory is connected to the memory controller via the DQS clock line and the DQ data line. The DQS clock line is used to transmit the DQS clock signal, and the DQ data line is used to transmit the DQ data signal. The DQ data signal is used to transmit data, and the DQS clock signal is used to sample the DQ data signal to obtain the data transmitted by the DQ data signal.

[0047] In the DDR5 specification, the DQS clock signal and DQ data signal of DDR can be generated by 2-phase and 4-phase system clock signals. A 2-phase system clock consists of two clock signals with different phases, corresponding to ideal phases of 0° and 180°. A 4-phase system clock consists of four clock signals with different phases, corresponding to ideal phases of 0°, 90°, 180°, and 270°. Similarly, an 8-phase system clock consists of eight clock signals with different phases, corresponding to ideal phases of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°.

[0048] like Figure 2 This diagram illustrates the generation of DQ data and DQS clock signals using a 4-phase system clock (containing four phase clock signals, such as ICLK, QCLK, IBCLK, and QBCLK). "0", "1", "2", and "3" represent phase 0, phase 1, phase 2, and phase 3 of the DQ data and DQS clock signals, respectively. The phase relationship between the ICLK and QCLK phase clock signals determines the eye diagram width of phase 0; the phase relationship between the QCLK and IBCLK phase clock signals determines the eye diagram width of phase 1; the phase relationship between the IBCLK and QBCLK phase clock signals determines the eye diagram width of phase 2; and the phase relationship between the QBCLK and ICLK phase clock signals determines the eye diagram width of phase 3. Four different phase clock signals can cause phase 0, phase 1, phase 2, and phase 3 mismatch in the DQS clock signal or DQ data signal. This not only worsens the duty cycle distortion problem within the DDR interface cycle, but also makes the clock jitter problem more serious, and the magnitude of duty cycle distortion in adjacent cycles is also inconsistent.

[0049] in, Figure 2 The ICLK, QCLK, IBCLK, and QBCLK shown can also be represented by other numbers or letters, only to distinguish different phase clock signals. Clock jitter can cause inconsistencies in cycle length between adjacent cycles, such as the length of odd-numbered cycles differing from that of even-numbered cycles. For example, for... Figure 2 In the DQS clock signal, the first r0 to r1 represents one cycle (which can be called an even cycle), and r1 to the next r0 represents the next cycle (which can be called an odd cycle). Due to clock jitter, the duration of these two cycles will be different. For example, the duration of the first cycle is 9ns and the duration of the second cycle is 11ns. The purpose of optimization is to make the duration of these two cycles consistent, such as both being 10ns.

[0050] In some implementations, the DQ data signal and the DQS clock signal can be generated based on the same system clock signal; in other possible implementations, the DQ data signal and the DQS clock signal can be generated based on different system clock signals, such as... Figure 2 In the schematic diagram shown, the DQ data signal is generated based on the first system clock signal (ICLK_DQ, QCLK_DQ, IBCLK_DQ, QBCLK_DQ), and the DQS clock signal is generated based on the second system clock signal (ICLK_DQS, QCLK_DQS, IBCLK_DQS, QBCLK_DQS).

[0051] Since the DQ data signal and DQS clock signal can be generated based on different system clock signals, the duty cycle and period jitter of the DQS clock signal and the DQ data signal are not completely consistent. To reduce the impact of duty cycle distortion and period jitter of the DQS clock signal and DQ data signal on the training results, this application adopts a novel approach. By adjusting the value of the first DCA register group during training, the eye diagram width of each phase of the DQ data signal becomes the same (in this paper, "same" means the same within a certain error range; that is, the difference between the two is considered the same if it is within the error range). This ensures that the training results of the DQ data signal are not affected by the initial duty cycle and period jitter of the DQS clock signal. Based on the optimized DQ data signal, the duty cycle and period jitter of the DQS clock signal are further optimized. The entire process does not require multiple iterations of mutual optimization between the DQS clock signal and the DQ data signal. By adjusting the value of the DCA register, the duty cycle of the DQS clock signal and the DQ data signal generated by the memory itself is optimized directly from the source. Instead of adjusting the duty cycle of the DQS clock signal and the DQ data signal through additional hardware circuitry at the memory controller after the DQS clock signal and the DQ data signal are generated, the process eliminates the need for additional hardware circuitry and reduces hardware overhead.

[0052] The method for optimizing the transmission signals of memory provided in this application allows for the initial training and optimization of the DQ data signal in the memory, followed by the training and optimization of the DQS data signal based on the optimized DQ data signal. When training and optimizing the DQ or DQS data signal, the clock jitter of the DQ or DQS data signal can be trained and optimized first, followed by the duty cycle distortion of the DQ or DQS data signal. The total training and optimization time is linearly related to the number of phases of the system clock and does not increase exponentially with the number of phases. Assuming the training and optimization time required for each round of adjusting the DCA register value is T, and the number of phases of the system clock generating the DQS clock signal or DQ data signal is N, then the total training and optimization time for the values ​​of the first or second DCA register group is T*logN, for example:

[0053] When using a 2-phase clock to generate the DQS clock signal (or DQ data signal), the total training and optimization time is 1*T. When using a 4-phase clock to generate the DQS clock signal (or DQ data signal), the total training and optimization time is 2*T. When using an 8-phase clock to generate the DQS clock signal (or DQ data signal), the total training and optimization time is 3*T.

[0054] Specifically, for DQS clock signals or DQ data signals generated by 2-phase clocks, only duty cycle distortion may exist, without clock jitter. For DQS clock signals or DQ data signals generated by 4-phase and more phase clocks, both duty cycle distortion and clock jitter may exist.

[0055] The method for optimizing memory transmission signals disclosed in this application can improve the problems of duty cycle distortion and clock jitter in memory transmission signals. Furthermore, it also provides significant improvement when the duty cycle and period jitter amplitude of the DQS clock signal and DQ data signal are inconsistent. This method can improve not only the DQS clock signal and DQ data signal generated by a 4-phase system clock, but also the DQS clock signal and DQ data signal generated by a 2-phase or more-phase system clock. The following will combine... Figure 1 The method for optimizing the transmission signal of a memory provided in the embodiments of this application will be described. This method for optimizing the transmission signal of a memory can be applied to a memory controller.

[0056] S1: Adjust the value of the first DCA register group and generate the DQ data signal based on the optimal value of the first DCA register group obtained by adjustment.

[0057] The value of the first DCA register group is phase-dependent with the first system clock signal in the memory. This first system clock signal is used to generate the DQ data signal. By adjusting the value of the first DCA register group, the duty cycle distortion of the DQ data signal in the memory can be optimized, or the clock jitter and duty cycle distortion of the DQ data signal can be optimized. The first system clock signal contains 2... n There are 1 phase clock signal, each with its own independent DCA register, where n is an integer greater than or equal to 1.

[0058] In one implementation, when adjusting the value of the first DCA register group, the value of the first DCA register group can be adjusted based on the value obtained from experiments or simulations. By adjusting the value of the first DCA register group, the phase of the first system clock signal can reach (or approach) the ideal phase. For example, taking a 4-phase system clock as an example, by adjusting the value of the first DCA register group, the phases of the four phase clock signals can be made to be close to 0°, 90°, 180°, and 270°, respectively. This can optimize the clock jitter and duty cycle distortion of the DQ data signal.

[0059] When n is an integer greater than or equal to 2, the process of adjusting the value of the first DCA register group can be as follows: Adjust the value of the first DCA register group (containing 2...) n The optimal value of the DCA register corresponding to the first type of phase clock signal in the first DCA register group is obtained to optimize the clock jitter of the DQ data signal. Based on the optimal value of the DCA register corresponding to the first type of phase clock signal, the value of the DCA register corresponding to the second type of phase clock signal in the first DCA register group is adjusted to obtain the optimal value of the DCA register corresponding to the second type of phase clock signal, thereby optimizing the duty cycle distortion of the DQ data signal. By first training and optimizing the clock jitter of the memory's transmission signal, and then training and optimizing the duty cycle distortion of the memory's transmission signal, the adjustment time can be reduced while achieving the objective, making the training and optimization time linearly related to the number of phases of the system clock.

[0060] In one implementation, the value of the DCA register corresponding to the first type of phase clock signal can be adjusted directly without adjusting the value of the DCA register corresponding to the second type of phase clock signal. This method, compared to first adjusting the value of the DCA register corresponding to the first type of phase clock signal and then adjusting the value of the DCA register corresponding to the second type of phase clock signal, requires more time for adjustment.

[0061] When n=1, the process of adjusting the value of the first DCA register group can be: directly adjusting the value of the DCA register corresponding to the second type of phase clock signal in the first DCA register group to optimize the duty cycle distortion of the DQ data signal.

[0062] The first type of phase clock signal is a phase clock signal related to the clock jitter of the DQ data transmission signal of the memory, and the second type of phase clock signal is a phase clock signal related to the duty cycle of the DQ data signal of the memory.

[0063] In one implementation, the process of adjusting the value of the first DCA register group may be: adjusting the value of the first DCA register group, obtaining 2 n Each eye diagram has a width of 2, where each eye diagram width is the width of the eye diagram used to sample the DQ data signal using the DQS clock signal to obtain correctly sampled data (i.e., correct data can be sampled within this eye diagram width). Each eye diagram width represents the phase difference between the corresponding phase clock signal and the next phase clock signal; based on 2 n The eye diagram width is adjusted to change the value of the first DCA register group so that the new DQ data signal is sampled using the DQS clock signal to obtain correctly sampled data. n Each eye diagram has the same width, and the new DQ data signal is generated based on the adjusted value of the first DCA register group.

[0064] For example, taking a 4-phase system clock as an example, there are 4 eye diagram widths, assuming they are phase 0 eye diagram width (or simply phase 0), phase 1 eye diagram width (or simply phase 1), phase 2 eye diagram width (or simply phase 2), and phase 3 eye diagram width (or simply phase 3). Figure 2 It can be seen that the eye diagram width of phase 0 represents the phase difference between the corresponding phase clock signal ICLK and the next phase clock signal QCLK; the eye diagram width of phase 1 represents the phase difference between the corresponding phase clock signal QCLK and the next phase clock signal IBCLK; the eye diagram width of phase 2 represents the phase difference between the corresponding phase clock signal IBCLK and the next phase clock signal QBCLK; and the eye diagram width of phase 3 represents the phase difference between the corresponding phase clock signal QBCLK and the next phase clock signal ICLK. Similarly, taking an 8-phase system clock as an example, there are 8 eye diagram widths, assumed to be the eye diagram widths of phase 0, phase 1, phase 2, phase 3, phase 4, phase 5, phase 6, and phase 7.

[0065] The eye diagram width can be obtained as follows: When sampling the data transmitted by the DQ data signal using the DQS clock signal, the first delay of the DQS clock signal when the first sampled data changes from erroneous to correct can be recorded. Then, the DQS clock signal is continuously delayed. If correct data is sampled each time, the DQS clock signal is delayed until erroneous data is sampled. The second delay of the DQS clock signal when the first sampled data changes from correct to erroneous is recorded. The eye diagram width can then be the delay difference between the first and second delays.

[0066] Among them, the correct sampled data is obtained by sampling the DQ data signal (or the new DQ data signal) using the DQS clock signal. n When the eye diagram width is 2, it can be that the DQ data signal (or a new DQ data signal) is transmitted using the DQS clock signal. n Two sets of data were sampled separately to obtain the correct sampled data. n Each type of data corresponds to one eye diagram width.

[0067] For example, taking n=2 as an example, there are 4 data modes involved, which can be 1000 (or 0111), 0100 (or 1011), 0010 (or 1101), and 0001 (or 1110). Setting the data transmitted by the DQ data signal to 1000, and using the DQS clock signal to adopt the DQ data signal, gradually delaying the DQS clock signal, we can obtain the interval where the rising edge of the DQS clock signal returns data of 1. This interval is the phase 0 eye diagram width. Similarly, setting the data transmitted by the DQ data signal to 0100, and using the DQS clock signal to adopt the DQ data signal, gradually delaying the DQS clock signal, we can obtain the interval where the falling edge of the DQS clock signal returns data of 1. This interval is the phase 1 eye diagram width. Similarly, by setting the transmitted DQ data signal to 0010 and using the DQS clock signal to gradually delay the DQS clock signal, the interval where the rising edge of the DQS clock signal returns a data value of 1 can be obtained. This interval is the eye diagram width of phase 2. Likewise, by setting the transmitted DQ data signal to 0001 and using the DQS clock signal to gradually delay the DQS clock signal, the interval where the falling edge of the DQS clock signal returns a data value of 1 can be obtained. This interval is the eye diagram width of phase 3. Alternatively, by setting the transmitted DQ data signal to 0111 and using the DQS clock signal to gradually delay the DQS clock signal, the interval where the rising edge of the DQS clock signal returns a data value of 0 can be obtained. This interval is the eye diagram width of phase 0. Examples for other phases are not provided. Here, the rising edge of r0, the falling edge of f0, the rising edge of r1, and the falling edge of f1 are the sampling clock edges for phases 0, 1, 2, and 3, respectively.

[0068] For example, taking n=3 as an example, there are 8 data patterns involved, which can be 10000000 (or 01111111), 01000000 (or 10111111), 00100000 (or 11011111), 00010000 (or 11101111), 00001000 (or 11110111), 000000100 (or 11111011), 000000010 (or 11111101), 00000001 (or 11111101), 00000001 (or 11111110). If the data transmitted by the DQ data signal is set to 01111111, and the DQ data signal is used with the DQS clock signal, and the DQS clock signal is gradually delayed, the interval in which the data returned by the rising edge r0 of the DQS clock signal is 0 can be obtained. This interval is the phase 0 eye diagram width. Similarly, setting the DQ data signal to 10111111, and using the DQS clock signal to transmit the DQ data signal while gradually delaying the DQS clock signal, we can obtain the interval where the falling edge of the DQS clock signal f0 returns 0 data. This interval is the eye diagram width of phase 1. Likewise, setting the DQ data signal to 11111101, and using the DQS clock signal to transmit the DQ data signal while gradually delaying the DQS clock signal, we can obtain the interval where the rising edge of the DQS clock signal r3 returns 0 data. This interval is the eye diagram width of phase 6. Similarly, setting the DQ data signal to 11111110, and using the DQS clock signal to transmit the DQ data signal while gradually delaying the DQS clock signal, we can obtain the interval where the falling edge of the DQS clock signal f3 returns 0 data. This interval is the eye diagram width of phase 7.

[0069] Adjusting the value of the first DCA register group involves multiple adjustments to the DCA register values. Each adjustment requires generating a new DQ data signal based on the adjusted DCA register value. Then, the new DQ data signal is sampled using the DQS clock signal to obtain correctly sampled data. n Eye width (referred to as the new 2) n (eye diagram width), relatively new 2 n If the widths of the two eye diagrams are the same, stop adjusting the value of the DCA register; otherwise, continue repeating the adjustment process. After multiple adjustments, it is possible to make the two eye diagrams as close as possible to the correct width. n Each eye diagram has the same width. In this implementation, the optimal value of the first DCA register group is 2, which allows for the correct sampling of the DQ data signal using the DQS clock signal. n The value of the first DCA register group when all eye diagrams have the same width.

[0070] Understandably, the first DCA register set contains 2 nEach time the value of the first DCA register group is adjusted, it is possible to adjust only the value of some DCA registers in the first DCA register group, rather than adjusting the value of all DCA registers in the first DCA register group.

[0071] In one implementation, based on 2 n The process of adjusting the value of the first DCA register group for each eye diagram width can involve n rounds of adjusting the value of the first DCA register group. For example, if n=2, it involves 2 rounds of adjusting the value of the first DCA register group; if n=3, it involves 3 rounds of adjusting the value of the first DCA register group.

[0072] The first round of adjustments to the value of the first DCA register group includes: based on the previous two... n-1 Eye width and the last 2 n-1 The eye diagram width is adjusted, and the second eye diagram in the first DCA register group is adjusted. n-1 +1 phase clock signal value of DCA register, so that the first 2 n-1 The sum of the widths of each eye diagram and the last two n-1 The sum of the widths of all eye diagrams is the same. When n=2, the third phase clock signal in the first DCA register group (corresponding to...) is adjusted. Figure 2 The value of the DCA register of IBCLK_DQ in the first DCA register group is adjusted; when n=3, the value of the DCA register of the 5th phase clock signal in the first DCA register group is adjusted.

[0073] i is sequentially selected from 2 to n-1. The adjustment of the first DCA register group in the i-th round includes: generating a new DQ data signal based on the optimal value of the first DCA register group obtained in the (i-1)-th round, and obtaining a new 2 based on the new DQ data signal. n Eye diagram width; based on the new 2 n The eye diagram width is adjusted in the m*2th register group of the first DCA register group. n-i The value of the DCA register is increased by 1 phase clock signal to make the sum of the widths of each eye diagram the same, and the sum of the widths of each eye diagram is 2 for adjacent eyes. n-i The sum of the widths of the eye diagrams, involving a total of 2 i Eye width and.

[0074] Where m takes values ​​of [1, 2] in sequence. iThe value of m varies with i. For example, when i = 2, m takes values ​​of 1 and 3; when i = 3, m takes values ​​of 1, 3, 5, and 7; and when i = 4, m takes values ​​of 1, 3, 5, 7, 9, 11, 13, and 15. Assuming n = 3 (8 phases in total), when i = 2, there are 4 eye diagram widths involved. Each eye diagram width is the sum of the widths of two adjacent eye diagrams. For example, it is the sum of the eye diagram widths of phase 0 + phase 1, phase 2 + phase 3, phase 4 + phase 5, and phase 6 + phase 7. Assuming n = 4 (16 phases in total), when i = 2, there are 4 (i.e., 2...) 2 The sum of the widths of the four adjacent eye diagrams is used. For example, it's the sum of the widths of the eye diagrams for phase 0 + phase 1 + phase 2 + phase 3, phase 4 + phase 5 + phase 6 + phase 7, phase 8 + phase 9 + phase 10 + phase 11, and phase 12 + phase 13 + phase 14 + phase 15. Assuming n = 4 (a total of 16 phases), when i = 3, it involves 8 (i.e., 2...) eye diagrams. 3 The sum of eye widths is the sum of the widths of two adjacent eye diagrams. For example, it is the sum of the eye widths of phase 0 + phase 1, phase 2 + phase 3, phase 4 + phase 5, phase 6 + phase 7, phase 8 + phase 9, phase 10 + phase 11, phase 12 + phase 13, and phase 14 + phase 15.

[0075] The nth round of adjusting the value of the first DCA register group includes: generating a new DQ data signal based on the optimal value of the first DCA register group obtained in the (n-1)th round of adjustment, and obtaining a new 2 based on the new DQ data signal. n Eye diagram width; based on the new 2 n Each eye diagram width is adjusted by changing the value of the DCA register of the (k+1)th phase clock signal in the first DCA register group to make each eye diagram width the same, where k takes values ​​from [1, 2] to [3]. nThe range of odd numbers is i. The value of k changes as i increases. For example, when n = 2, k takes the values ​​1 and 3; when n = 3, k takes the values ​​1, 3, 5, and 7; when i = 4, k takes the values ​​1, 3, 5, 7, 9, 11, 13, and 15.

[0076] In each round of adjusting the value of the first DCA register group, the value of the DCA register may be adjusted multiple times. Each adjustment of the DCA register value can generate a new DQ data signal based on the adjusted DCA register value, and then a new 2 can be generated based on the new DQ data signal. n Each eye diagram width, and then based on the new 2 n The eye diagram width is adjusted by changing the value of the DCA register, and then the above process is repeated until the optimal DCA value is obtained. (The process is repeated to obtain the new 2...) n When the eye diagram width is 2, the process involves sampling the new DQ data signal using the DQS clock signal to obtain the correctly sampled data. n Eye width.

[0077] In the phase clock signals shown above, the phase clock signal corresponding to the DCA optimized in the last round (nth round) of training is the second type of phase clock signal, while the remaining phase clock signals are all first type of phase clock signals. For example, for a 4-phase system clock, the first type of phase clock signal is the 3rd phase clock signal, and the second type of phase clock signals include the 2nd and 4th phase clock signals. As another example, for an 8-phase system clock, the first type of phase clock signals includes the 5th, 3rd, and 7th phase clock signals; and the second type of phase clock signals includes the 2nd, 4th, 6th, and 8th phase clock signals.

[0078] To better understand the adjustment process described above, an example will be provided below.

[0079] Example 1

[0080] Taking n=2 as an example, four different data modes, namely 1000, 0100, 0010, and 0001, are used to train and optimize the duty cycle of the DQ data signal. The DQS clock signal's r0, f0, r1, and f1 are the sampling clock edges of the four phases of the sampled DQ data signal, as illustrated in the diagram below. Figure 4 As shown.

[0081] Step 1: Set the DQ data signal transmission data to 1000, sample the DQ data with the DQS clock signal, and determine whether the data returned by the rising edge of the DQS clock signal r0 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the rising edge of r0 is 1 can be obtained. This is the eye diagram width of phase 0.

[0082] Step 2: Set the DQ data signal transmission data to 0100, sample the DQ data with the DQS clock signal, and determine whether the data returned by the falling edge of the DQS clock signal f0 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the falling edge of f0 is 1 can be obtained. This is the eye diagram width of phase 1.

[0083] Step 3: Set the DQ data signal transmission data to 0010, sample the DQ data with the DQS clock signal, and determine whether the data returned by the rising edge of the DQS clock signal r1 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the rising edge of r1 is 1 can be obtained. This is the eye diagram width of phase 2.

[0084] Step 4: Set the DQ data signal transmission data to 0001, sample the DQ data with the DQS clock signal, and determine whether the data returned by the falling edge of the DQS clock signal f1 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the falling edge of f1 is 1 can be obtained. This is the eye diagram width of phase 3.

[0085] Thus, the eye diagram widths for phase 0, phase 1, phase 2, and phase 3 are obtained.

[0086] Step 5: Compare the eye diagram widths of phase 0 + phase 1 and phase 2 + phase 3:

[0087] 1. After obtaining the eye diagram widths of phases 0, 1, 2, and 3, the eye diagram widths of phase 0 + phase 1 and phase 2 + phase 3 can be compared. If phase 0 + phase 1 > phase 2 + phase 3, the value of the DCA register of IBCLK_DQ (the third phase clock signal) is decreased. Then, based on the new DQ data signal, new eye diagram widths of phases 0, 1, 2, and 3 are obtained until phase 0 + phase 1 <= phase 2 + phase 3. The value of the DCA register when the absolute value of (phase 0 + phase 1) - (phase 2 + phase 3) is minimized is the optimal value of the DCA register of IBCLK_DQ.

[0088] 2. If phase0 + phase1 < phase2 + phase3, increase the value of the DCA register of IBCLK_DQ until phase0 + phase1 >= phase2 + phase3. The value of the DCA register when |(phase0 + phase1) - (phase2 + phase3)| is minimized is the optimal value of the DCA register of IBCLK_DQ.

[0089] 3. If phase0 + phase1 = phase2 + phase3, there is no need to adjust the value of the DCA register of IBCLK_DQ. Here, the equality means equality within a certain precision range. At this point, the phase of IBCLK_DQ is at the optimal phase.

[0090] Step 6, compare the eye diagram widths of phase0 and phase1:

[0091] 1. If phase0 > phase1, decrease the value of the DCA register of QCLK_DQ (the second phase clock signal). Then, based on the new DQ data signal, obtain the new eye diagram widths of phase0 and phase1 until phase0 <= phase1. The value of the DCA register when the absolute value of phase0 - phase1 is minimized is the optimal value of the DCA register of QCLK_DQ.

[0092] 2. If phase0 < phase1, increase the value of the DCA register of QCLK_DQ. Then, based on the new DQ data signal, obtain the new eye diagram widths of phase0 and phase1 until phase0 >= phase1. The value of the DCA register when the absolute value of phase0 - phase1 is minimized is the optimal value of the DCA register of QCLK_DQ.

[0093] 3. If phase0 = phase1, there is no need to adjust the value of the DCA register of QCLK_DQ. Here, the equality means equality within a certain precision range. At this point, the phase of QCLK_DQ is at the optimal phase.

[0094] Step 7, compare the eye diagram widths of phase2 and phase3:

[0095] 1. If phase2 > phase3, then decrease the value of the DCA register of QBCLK_DQ (the fourth phase clock signal). After that, based on the new DQ data signal, obtain the eye diagram widths of the new phase2 and phase3 until phase2 <= phase3. The value of the DCA register when the absolute value of phase2 - phase3 is the smallest is the optimal value of the DCA register of QBCLK_DQ.

[0096] 2. If phase2 < phase3, then increase the value of the DCA register of QBCLK_DQ. After that, based on the new DQ data signal, obtain the eye diagram widths of the new phase2 and phase3 until phase2 >= phase3. The value of the DCA register when the absolute value of phase2 - phase3 is the smallest is the optimal value of the DCA register of QBCLK_DQ.

[0097] 3. If phase2 = phase3, then there is no need to adjust the value of the DCA register of QBCLK_DQ. Here, the equality refers to equality within a certain precision range.至此, the adjustment of the optimal values of the DCA of QCLK_DQ, IBCLK_DQ, and QBCLK_DQ is completed, and the duty cycle of the DQ data signal reaches the optimal value.

[0098] The above sixth and seventh steps can be carried out simultaneously.

[0099] Embodiment 2

[0100] Taking n = 3 as an example, eight different data patterns, namely 10000000, 01000000, 00100000, 00010000, 00001000, 00000100, 00000010, 00000001, are used to train and optimize the duty cycle of the DQ data signal. r0, f0, r1, f1, r2, f2, r3, f3 of the DQS clock signal are the sampling clock edges for sampling 8 phase data of the DQ data signal respectively.

[0101] First step: Set the data transmitted by the DQ data signal to 10000000, sample the DQ data with the DQS clock signal, and determine whether the data returned at the rising edge of r0 of the DQS clock signal is 1. Gradually delay the DQS clock signal to obtain the interval where the data returned at the rising edge of r0 is 1, which is the eye diagram width of phase0.

[0102] Step 2: Set the DQ data signal transmission data to 01000000, sample the DQ data with the DQS clock signal, and determine whether the data returned by the falling edge of the DQS clock signal f0 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the falling edge of f0 is 1 can be obtained. This is the eye diagram width of phase 1.

[0103] Step 3: Set the DQ data signal transmission data to 00100000, sample the DQ data with the DQS clock signal, and determine whether the data returned by the rising edge of the DQS clock signal r1 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the rising edge of r1 is 1 can be obtained. This is the eye diagram width of phase 2.

[0104] Step 4: Set the DQ data signal transmission data to 00010000, sample the DQ data with the DQS clock signal, and determine whether the data returned by the falling edge of the DQS clock signal f1 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the falling edge of f1 is 1 can be obtained. This is the eye diagram width of phase 3.

[0105] Step 5: Set the DQ data signal transmission data to 00001000, sample the DQ data with the DQS clock signal, and determine whether the data returned by the rising edge of the DQS clock signal r2 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the rising edge of r2 is 1 can be obtained. This is the eye diagram width of phase 4.

[0106] Step 6: Set the DQ data signal transmission data to 00000100, sample the DQ data with the DQS clock signal, and determine whether the data returned by the falling edge of the DQS clock signal f2 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the falling edge of f2 is 1 can be obtained. This is the eye diagram width of phase 5.

[0107] Step 7: Set the DQ data signal transmission data to 00000010, sample the DQ data with the DQS clock signal, and determine whether the data returned by the rising edge of the DQS clock signal r3 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the rising edge of r3 is 1 can be obtained. This is the eye diagram width of phase 6.

[0108] Step 8: Set the DQ data signal transmission data to 00000001, sample the DQ data with the DQS clock signal, and determine whether the data returned by the falling edge of the DQS clock signal f3 is 1. By gradually delaying the DQS clock signal, the interval in which the data returned by the falling edge of f3 is 1 can be obtained. This is the eye diagram width of phase 7.

[0109] At this point, the eye diagram widths of phase0, phase1, phase2, phase3, phase4, phase5, phase6, and phase7 are obtained.

[0110] Step 9: Compare the eye diagram widths of phase0 + phase1 + phase2 + phase3 and phase4 + phase5 + phase6 + phase7:

[0111] 1. If phase0 + phase1 + phase2 + phase3 > phase4 + phase5 + phase6 + phase7, then decrease the value of the DCA register of the 5th phase clock signal. After that, based on the new DQ data signal, obtain the new eye diagram widths of phase0, phase1, phase2, phase3, phase4, phase5, phase6, and phase7 until phase0 + phase1 + phase2 + phase3 <= phase4 + phase5 + phase6 + phase7.

[0112] The value of the DCA register when the absolute value of (phase0 + phase1 + phase2 + phase3) - (phase4 + phase5 + phase6 + phase7) is the smallest is the optimal value of the DCA register of the 5th phase clock signal.

[0113] 2. If phase0 + phase1 + phase2 + phase3 < phase4 + phase5 + phase6 + phase7, then increase the value of the DCA register of the 5th phase clock signal until phase0 + phase1 + phase2 >= phase4 + phase5 + phase6 + phase7.

[0114] The value of the DCA register when |(phase0 + phase1 + phase2 + phase3) - (phase4 + phase5 + phase6 + phase7)| is the smallest is the optimal value of the DCA register of the 5th phase clock signal.

[0115] 3. If phase0 + phase1 + phase2 + phase3 = phase4 + phase5 + phase6 + phase7, then there is no need to adjust the value of the DCA register of the 5th phase clock signal. Here, the equality means equality within a certain precision range. At this point, the phase of the 5th phase clock signal is at the optimal phase.

[0116] Step 10: Compare the eye diagram widths of phase0+phase1 and phase2+phase3.

[0117] If phase0+phase1>phase2+phase3, then decrease the value of the DCA register of the 3rd phase clock signal. After that, obtain the eye diagram widths of the new phase0, phase1, phase2, and phase3 based on the new DQ data signal until phase0+phase1<=phase2+phase3. The value of the DCA register when the absolute value of (phase0+phase1)-(phase2+phase3) is the smallest is the optimal value of the DCA register of the 3rd phase clock signal.

[0118] 2. If phase0+phase1<phase2+phase3, then increase the value of the DCA register of the 3rd phase clock signal until phase0+phase1>=phase2+phase3. The value of the DCA register when |(phase0+phase1)-(phase2+phase3)| is the smallest is the optimal value of the DCA register of the 3rd phase clock signal.

[0119] 3. If phase0+phase1 = phase2+phase3, then there is no need to adjust the value of the DCA register of the 3rd phase clock signal. Here, equality means equality within a certain precision range.至此, the phase of the 3rd phase clock signal is at the optimal phase.

[0120] Step 11: Compare the eye diagram widths of phase4+phase5 and phase6+phase7:

[0121] 1. If phase4+phase5>phase6+phase7, then decrease the value of the DCA register of the 7th phase clock signal. After that, obtain the eye diagram widths of the new phase4, phase5, phase6, and phase7 based on the new DQ data signal until phase4+phase5<=phase6+phase7. The value of the DCA register when the absolute value of (phase4+phase5)-(phase6+phase7) is the smallest is the optimal value of the DCA register of the 7th phase clock signal.

[0122] 2. If phase4 + phase5 < phase6 + phase7, increase the value of the DCA register of the 7th phase clock signal until phase4 + phase5 >= phase6 + phase7. The value of the DCA register when |(phase4 + phase5) - (phase6 + phase7)| is minimized is the optimal value of the DCA register of the 7th phase clock signal.

[0123] 3. If phase4 + phase5 = phase6 + phase7, there is no need to adjust the value of the DCA register of the 3rd phase clock signal. Here, the equality refers to equality within a certain precision range.至此, the phase of the 3rd phase clock signal is at the optimal phase.

[0124] The above-mentioned tenth and eleventh steps can be carried out simultaneously.

[0125] Twelfth step: Compare the eye diagram widths of phase0 and phase1, and compare the eye diagram widths of phase2 and phase3, and compare the eye diagram widths of phase4 and phase5, and compare the eye diagram widths of phase6 and phase7:

[0126] 1. By comparing the eye diagram widths of phase0 and phase1, thereby adjusting the value of the DCA register of the 2nd phase clock signal. If phase0 > phase1, reduce the value of the DCA register of the 2nd phase clock signal. After that, based on the new DQ data signal, obtain the new eye diagram widths of phase0 and phase1 until phase0 <= phase1. The value of the DCA register when the absolute value of phase0 - phase1 is minimized is the optimal value of the DCA register of the 2nd phase clock signal. If phase0 < phase1, increase the value of the DCA register of the 2nd phase clock signal. After that, based on the new DQ data signal, obtain the new eye diagram widths of phase0 and phase1 until phase0 >= phase1. The value of the DCA register when the absolute value of phase0 - phase1 is minimized is the optimal value of the DCA register of the 2nd phase clock signal. If phase0 = phase1, there is no need to adjust the value of the DCA register of the 2nd phase clock signal.

[0127] Note: In the translation of "", the part "至此, the phase of the 3rd phase clock signal is at the optimal phase." seems to have an incorrect "至此" which might be a leftover from the Chinese and not a proper English expression. It should be something like "At this point, the phase of the 3rd phase clock signal is at the optimal phase." But according to the rules, the text as provided is translated as is.2. By comparing the eye diagram widths of phase2 and phase3, the value of the DCA register of the fourth phase clock signal is adjusted accordingly. If phase2 > phase3, the value of the DCA register of the fourth phase clock signal is decreased. Then, based on the new DQ data signal, the eye diagram widths of the new phase2 and phase3 are obtained until phase2 <= phase3. The value of the DCA register when the absolute value of phase2 - phase3 is the smallest is the optimal value of the DCA register of the fourth phase clock signal. If phase2 < phase3, the value of the DCA register of the fourth phase clock signal is increased. Then, based on the new DQ data signal, the eye diagram widths of the new phase2 and phase3 are obtained until phase2 >= phase3. The value of the DCA register when the absolute value of phase2 - phase3 is the smallest is the optimal value of the DCA register of the fourth phase clock signal. If phase2 = phase3, there is no need to adjust the value of the DCA register of the fourth phase clock signal.

[0128] 3. By comparing the eye diagram widths of phase4 and phase5, the value of the DCA register of the sixth phase clock signal is adjusted accordingly. If phase4 > phase5, the value of the DCA register of the sixth phase clock signal is decreased. Then, based on the new DQ data signal, the eye diagram widths of the new phase4 and phase5 are obtained until phase4 <= phase5. The value of the DCA register when the absolute value of phase4 - phase5 is the smallest is the optimal value of the DCA register of the sixth phase clock signal. If phase4 < phase5, the value of the DCA register of the sixth phase clock signal is increased. Then, based on the new DQ data signal, the eye diagram widths of the new phase4 and phase5 are obtained until phase4 >= phase5. The value of the DCA register when the absolute value of phase4 - phase5 is the smallest is the optimal value of the DCA register of the sixth phase clock signal. If phase4 = phase5, there is no need to adjust the value of the DCA register of the sixth phase clock signal.

[0129] 4. By comparing the eye diagram widths of phase6 and phase7, the value of the DCA register of the eighth phase clock signal is adjusted accordingly. If phase6 > phase7, the value of the DCA register of the eighth phase clock signal is decreased. Then, based on the new DQ data signal, the eye diagram widths of the new phase6 and phase7 are obtained until phase6 <= phase7. The value of the DCA register when the absolute value of phase6 - phase7 is the smallest is the optimal value of the DCA register of the eighth phase clock signal. If phase6 < phase7, the value of the DCA register of the eighth phase clock signal is increased. Then, based on the new DQ data signal, the eye diagram widths of the new phase6 and phase7 are obtained until phase6 >= phase7. The value of the DCA register when the absolute value of phase6 - phase7 is the smallest is the optimal value of the DCA register of the eighth phase clock signal. If phase6 = phase7, there is no need to adjust the value of the DCA register of the eighth phase clock signal.

[0130] At this point, the adjustment of the optimal DCA values of the fifth phase clock signal, the third phase clock signal, the seventh phase clock signal, the second phase clock signal, the fourth phase clock signal, the sixth phase clock signal, and the eighth phase clock signal is completed, and the duty cycle of the DQ data signal reaches the optimum.

[0131] In a possible implementation, when adjusting the values of the first DCA register group, instead of sequentially obtaining the eye diagram width of each phase and then calculating the sum of the eye diagram widths of multiple phases, the sum of the eye diagram widths of multiple phases can be directly obtained, which can improve the efficiency. In this implementation, when adjusting the values of the first DCA register group, there are also n rounds of adjusting the values of the first DCA register group.

[0132] Among them, the first round of adjusting the values of the first DCA register group includes: adjusting the value of the DCA register of the (2 n-1 + 1)-th phase clock signal in the first DCA register group based on the sum of the first eye diagram width and the sum of the second eye diagram width, so that the sum of the eye diagram widths corresponding to the first 2 n-1 phase clock signals is the same as the sum of the eye diagram widths corresponding to the last 2 n-1 phase clock signals. Here, the sum of the first eye diagram width is the sum of the eye diagram widths corresponding to the first 2 n-1 phase clock signals, and the sum of the second eye diagram width is the sum of the eye diagram widths corresponding to the last 2 n-1 phase clock signals. Each eye diagram width represents the phase difference between the corresponding phase clock signal and the next phase clock signal.

[0133] i is sequentially selected from 2 to n-1. The adjustment of the first DCA register group in the i-th round includes: generating a new DQ data signal based on the optimal value of the first DCA register group obtained in the (i-1)-th round, and obtaining 2 based on the new DQ data signal. i The sum of the widths of the two eye diagrams, where the sum of the widths of each eye diagram is equal to the sum of the widths of the two adjacent eye diagrams. n-i The sum of the eye diagram widths corresponding to each phase clock signal; based on 2 i The eye diagram width and adjustment of the m*2th eye in the first DCA register group n-i The value of the DCA register for +1 phase clock signals is used to make the width of each eye diagram the same, where m takes values ​​from [1, 2] in sequence. i Odd numbers within the range of )

[0134] The nth round of adjusting the value of the first DCA register group includes: generating a new DQ data signal based on the optimal value of the first DCA register group obtained in the (n-1)th round of adjustment, and obtaining 2 based on the new DQ data signal. n Eye width; based on 2 n The eye diagram width is adjusted by changing the value of the DCA register of the (k+1)th phase clock signal in the first DCA register group to make each adjacent eye diagram width the same, where k takes values ​​from [1, 2] to [3]. n Odd numbers within the range of ).

[0135] The principle of adjusting the value of the first DCA register group in this embodiment is the same as that described above based on 2. n The principle of adjusting the value of the first DCA register group by adjusting the eye diagram width is similar, but the difference is that this embodiment can directly adjust the eye diagram width of multiple phases.

[0136] To better understand, the following explanation includes examples.

[0137] Example 3

[0138] Taking n=2 as an example, when adjusting the value of the DCA register of IBCLK_DQ, the data transmitted by the DQ data signal can be set to 1100 (or 0011) and 0011 (or 1100). Then, the DQS clock signal is used to sample it, which can obtain the eye diagram widths of phase 01 (the sum of the eye diagram widths of phase 0 and phase 1) and phase 23 (the sum of the eye diagram widths of phase 2 and phase 3). Then, the value of the DCA register of IBCLK_DQ is adjusted according to the eye diagram widths of phase 01 and phase 23. The schematic diagram is as follows. Figure 5 As shown, the specific process can be:

[0139] In the first step, set the data transmitted by the DQ data signal to 1100 (or 0011), sample the DQ data with the DQS clock signal, and determine whether the data returned at the r0 rising edge (odd cycle) of the DQS clock signal is 1 (or 0). Gradually delay the DQS clock signal to obtain the interval where the data returned at the r0 rising edge is 1 (or 0), which is the eye diagram width of phase01.

[0140] In the second step, set the data transmitted by the DQ data signal to 0011 (or 1100), sample the DQ data with the DQS clock signal, and determine whether the data returned at the r1 rising edge (even cycle) of the DQS clock signal is 1 (or 0). Gradually delay the DQS clock signal to obtain the interval where the data returned at the r1 rising edge is 1 (or 0), which is the eye diagram width of phase23.

[0141] In the third step, compare the eye diagram widths of phase01 and phase23:

[0142] 1. If phase01 > phase23, decrease the value of the DCA register of IBCLK_DQ. Then, based on the new DQ data signal, obtain the new eye diagram widths of phase01 and phase23 until phase01 <= phase23. The value of the DCA register when the absolute value of phase01 - phase23 is the smallest is the optimal value of the DCA register of IBCLK_DQ.

[0143] 2. If phase01 < phase23, increase the value of the DCA register of IBCLK_DQ. Then, based on the new DQ data signal, obtain the new eye diagram widths of phase01 and phase23 until phase01 >= phase23. The value of the DCA register when the absolute value of phase01 - phase23 is the smallest is the optimal value of the DCA register of IBCLK_DQ.

[0144] 3. If phase01 = phase23, there is no need to adjust the value of the DCA register of IBCLK_DQ (second). Here, equality means equality within a certain precision range.至此, the phase of IBCLK_DQ is at the optimal phase.

[0145] After optimizing the DCA register value of IBCLK_DQ, the DCA register values ​​of QCLK_DQ and QBCLK_DQ also need to be adjusted. When adjusting the QCLK_DQ DCA register value, the eye diagram widths of phase 0 and phase 1 need to be compared; this process is the same as step six in Example 1 above. When adjusting the QBCLK_DQ DCA register value, the eye diagram widths of phase 2 and phase 3 need to be compared; this process is the same as step seven in Example 1 above.

[0146] Example 4

[0147] Taking n=3 as an example, when adjusting the values ​​of the DCA registers for the 5th, 3rd, and 7th phase clock signals, the data transmitted by the DQ data signal can be set to a specific value. Then, the DQS clock signal is used to sample it, which yields the eye diagram widths of phases 0, 1, 2, and 3 (the sum of the eye diagram widths of phases 0, 1, 2, and 3) and phases 4, 5, 6, and 7 (the sum of the eye diagram widths of phases 4, 5, 6, and 7), as well as the eye diagram widths of phases 01, 23, 45, and 67 (the sum of the eye diagram widths of phases 4 and 5) and 67 (the sum of the eye diagram widths of phases 6 and 7). Then, the value of the DCA register for the 5th phase clock signal is adjusted according to the eye diagram widths of phases 0, 1, 2, 3, 4, 5, and 67; the value of the DCA register for the 3rd phase clock signal is adjusted according to phases 01 and 23; and the value of the DCA register for the 7th phase clock signal is adjusted according to the eye diagram widths of phases 45 and 67. In this process, the eye widths of phases 01, 23, 45, 67, and 7, as well as the eye widths of phases 01, 23, 45, and 67, can be directly obtained through sampling, instead of first obtaining the eye widths of each phase and then calculating the sum of the eye widths based on the eye widths of each phase. The specific process can be:

[0148] The first step is to set the DQ data signal transmission data to 11110000 (or 00001111), sample the DQ data with the DQS clock signal, and determine whether the data returned by the rising edge of the DQS clock signal r0 is 1 (or 0). By gradually delaying the DQS clock signal, the interval in which the data returned by the rising edge of r0 is 1 (or 0) can be obtained. This is the eye diagram width of phase0123 (that is, the width of the first eye diagram).

[0149] The second step is to set the DQ data signal to 00001111 (or 11110000), sample the DQ data with the DQS clock signal, and determine whether the data returned on the rising edge of the DQS clock signal r2 is 1 (or 0). By gradually delaying the DQS clock signal, the interval in which the data returned on the rising edge of r2 is 1 (or 0) can be obtained. This is the eye diagram width of phase4567 (that is, the second eye diagram width).

[0150] The third step is to compare the eye diagram widths of phase 0123 and phase 4567 to obtain the optimal value of the DCA register for the fifth phase clock signal.

[0151] The fourth step involves setting the DQ data signal transmission to 11001100 (or 00110011). The DQ data is sampled using the DQS clock signal. The system checks if the data returned at the rising edge of the DQS clock signal (r0) is 1 (or 0). By progressively delaying the DQS clock signal, the interval where the data returned at the rising edge of r0 is 1 (or 0) can be obtained; this is the eye diagram width for phase 01. Then, the system checks if the data returned at the rising edge of the DQS clock signal (r2) is 1 (or 0). By progressively delaying the DQS clock signal, the interval where the data returned at the rising edge of r2 is 1 (or 0) can be obtained; this is the eye diagram width for phase 45. Alternatively, the DQ data signal transmission can be set to 11000000 (or 00111111) and 00001100 (or 11110011) respectively, yielding the eye diagram widths for phase 01 and phase 45.

[0152] Step 5: Set the DQ data signal transmission data to 00110011 (or 11001100). Sample the DQ data using the DQS clock signal. Determine if the data returned at the rising edge of the DQS clock signal (r1) is 1 (or 0). Gradually delay the DQS clock signal to obtain the interval where the data returned at the rising edge of r1 is 1 (or 0). This is the eye diagram width for phase 23. Then, determine if the data returned at the rising edge of the DQS clock signal (r3) is 1 (or 0). Gradually delay the DQS clock signal to obtain the interval where the data returned at the rising edge of r3 is 1 (or 0). This is the eye diagram width for phase 67. Alternatively, in step 5, the DQ data signal transmission data can be set to 00110000 (or 11001111) and 00000011 (or 11111100) respectively to obtain the eye diagram widths for phase 23 and phase 67.

[0153] Step 6: Compare the eye diagram widths of phase 01 and phase 23 to obtain the optimal value of the DCA register for the third phase clock signal. Compare the eye diagram widths of phase 45 and phase 67 to obtain the optimal value of the DCA register for the seventh phase clock signal.

[0154] Step 7: Set the DQ data signal transmission to 10101010 (or 01010101). Sample the DQ data using the DQS clock signal. Determine if the data returned on the rising edge of the DQS clock signal (r0) is 1 (or 0). Gradually delay the DQS clock signal to obtain the interval where the data returned on the rising edge of r0 is 1 (or 0). This is the eye diagram width of phase 0. Then, obtain the interval where the data returned on the rising edge of r1 is 1 (or 0). This is the eye diagram width of phase 2. Then, obtain the interval where the data returned on the rising edge of r2 is 1 (or 0). This is the eye diagram width of phase 4. Finally, obtain the interval where the data returned on the rising edge of r3 is 1 (or 0). This is the eye diagram width of phase 6. In this step, the DQ data can also be set to 10000000, 00100000, 00001000, 00000010 to obtain the eye diagram widths of phase 0, phase 2, phase 4, and phase 6 respectively.

[0155] Step 8: Set the DQ data signal transmission to 01010101. Sample the DQ data using the DQS clock signal and determine if the f0 return data of the DQS clock signal is 1. Gradually delay the DQS clock signal to obtain the interval where the f0 return data is 1; this is the eye diagram width of phase 1. Then, obtain the interval where the f1 return data is 1; this is the eye diagram width of phase 3. Then, obtain the interval where the f2 return data is 1; this is the eye diagram width of phase 5. Then, obtain the interval where the f3 return data is 1; this is the eye diagram width of phase 7. In this step, the DQ data can also be set to 01000000, 00010000, 00000100, 00000001 to obtain the eye diagram widths of phases 1, 3, 5, and 7 respectively.

[0156] Step 9: Compare the eye diagram widths of phase 0 and phase 1 to obtain the optimal DCA for the second phase clock signal; compare the eye diagram widths of phase 2 and phase 3 to obtain the optimal DCA for the fourth phase clock signal; compare the eye diagram widths of phase 4 and phase 5 to obtain the optimal DCA for the sixth phase clock signal; and compare the eye diagram widths of phase 6 and phase 7 to obtain the optimal DCA for the eighth phase clock signal.

[0157] S2: Based on the optimal value of the first DCA register group obtained by adjustment, adjust the value of the second DCA register group, and generate the DQS clock signal based on the optimal value of the second DCA register group obtained by adjustment.

[0158] Specifically, by adjusting the values ​​of the second DCA register group, the duty cycle distortion of the DQS clock signal in the memory can be optimized, or the clock jitter and duty cycle distortion of the DQS clock signal can be optimized. The values ​​of the second DCA register group are phase-dependent with the second system clock signal in the memory, which is used to generate the DQS clock signal. The second system clock signal contains 2... n There are 1 phase clock signal, each with its own independent DCA register, where n is an integer greater than or equal to 1.

[0159] In one implementation, when adjusting the value of the second DCA register group, the value of the second DCA register group can be adjusted based on the value obtained from experiments or simulations. By adjusting the value of the second DCA register group, the phase of the second system clock signal can be made to reach the ideal phase. For example, taking a 4-phase system clock as an example, by adjusting the value of the second DCA register group, the phases of the four phase clock signals can be made to be close to 0°, 90°, 180°, and 270°, respectively. This can optimize the clock jitter and duty cycle distortion of the memory's DQS clock signal.

[0160] In one implementation, adjusting the second DCA register group (containing 2 n When adjusting the value of a DCA register, the following method can be used: For example, obtain the maximum eye diagram of correctly sampled data obtained by sampling the DQ data signal transmitted using the DQS clock signal, and take the value of the DCA register corresponding to the maximum eye diagram as the optimal value of the DCA register. This process involves adjusting the value of the DCA register multiple times. Each adjustment yields an eye diagram. After multiple adjustments, multiple eye diagrams can be obtained. The maximum eye diagram is then selected, and the value of the DCA register corresponding to the maximum eye diagram is taken as the optimal value of the DCA register. This completes the adjustment of the DCA register value. The optimal value of the second DCA register group is the value of the DCA register corresponding to the maximum eye diagram, which is the maximum eye diagram of correctly sampled data obtained by sampling the DQ data signal transmitted using the DQS clock signal.

[0161] For example, assuming the initial value of a DCA register is 0, a DQS clock signal can be generated based on this initial value. This DQS clock signal is then used to sample the data transmitted by the DQ data signal. By continuously delaying the DQS clock signal, an eye diagram width capable of sampling correct data can be obtained; that is, correct data can be sampled within this eye diagram width. Next, the initial value of the DCA register is adjusted, assuming it is 1. Based on the adjusted value of the DCA register, a new DQS clock signal can be generated. This new DQS clock signal is then used to sample the data transmitted by the DQ data signal. By continuously delaying the DQS clock signal, a new eye diagram width capable of sampling correct data can be obtained. This process is repeated to obtain multiple eye diagrams. Finally, the largest eye diagram is selected, which is the eye diagram with the largest eye diagram width.

[0162] For example, taking the adjustment of the DCA register value corresponding to the IBCLK_DQS phase clock signal in the above example as an example, the adjustment of the DCA register value can be done by increasing the value of the DCA register corresponding to the IBCLK_DQS phase clock signal. If the eye diagram increases, continue increasing the value of the DCA register corresponding to the IBCLK_DQS phase clock signal until the eye diagram decreases. Alternatively, the value of the DCA register corresponding to the phase clock signal can be decreased. If increasing the value of the DCA register corresponding to the IBCLK_DQS phase clock signal decreases the eye diagram, then return to the previous DCA register value, and then decrease the value of the DCA register corresponding to the IBCLK_DQS phase clock signal again. If the eye diagram also decreases at this time, then the value of the previous DCA register is the optimal value of the DCA register.

[0163] In one implementation, when n is an integer greater than or equal to 2, the process of adjusting the value of the second DCA register group can be as follows: Adjust the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group to obtain the optimal value of the DCA register corresponding to the first type of phase clock signal, thereby optimizing the clock jitter of the DQS clock signal; based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained from the adjustment, adjust the value of the DCA register corresponding to the second type of phase clock signal in the second DCA register group to obtain the optimal value of the DCA register corresponding to the second type of phase clock signal, thereby optimizing the duty cycle distortion of the DQS signal. Here, the first type of phase clock signal is a phase clock signal related to the clock jitter of the DQS clock signal. When n is 1, the process of adjusting the value of the second DCA register group can be as follows: Adjust the value of the DCA register corresponding to the second type of phase clock signal in the second DCA register group to optimize the duty cycle distortion of the DQS clock signal. Here, the second type of phase clock signal is a phase clock signal related to the duty cycle of the DQS clock signal.

[0164] In one implementation, the value of the DCA register corresponding to the first type of phase clock signal can be adjusted directly without adjusting the value of the DCA register corresponding to the second type of phase clock signal. This method, compared to first adjusting the value of the DCA register corresponding to the first type of phase clock signal and then adjusting the value of the DCA register corresponding to the second type of phase clock signal, requires more time for adjustment.

[0165] In one possible implementation, the process of adjusting the values ​​of the DCA registers corresponding to the first type of phase clock signal and the second type of phase clock signal in the second DCA register group can be: adjusting the values ​​of the DCA registers corresponding to the first type of phase clock signal and the second type of phase clock signal based on values ​​obtained from experiments or simulations.

[0166] In one possible implementation, the process of adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group is as follows: Adjust the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group to obtain the first maximum eye diagram of correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal; take the value of the DCA register corresponding to the first maximum eye diagram as the optimal value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group. In this implementation, the value of the DCA register corresponding to the first type of phase clock signal is adjusted multiple times. Each adjustment yields an eye diagram. After multiple adjustments, multiple eye diagrams are obtained. The maximum eye diagram is selected, and the value of the DCA register corresponding to the maximum eye diagram is taken as the optimal value of the DCA register corresponding to the first type of phase clock signal. This completes the adjustment of the value of the DCA register corresponding to the first type of phase clock signal.

[0167] For example, when adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group, the process of obtaining the first maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal involves n-1 rounds of adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group:

[0168] The first round of adjustments involves modifying the values ​​of the DCA registers corresponding to the first type of phase clock signal in the second DCA register group, including: adjusting the values ​​of the second... n-1 The value of the DCA register corresponding to the +1 phase clock signal is used to obtain the first maximum eye diagram of correctly sampled data obtained by sampling the DQ data signal transmitted using the DQS clock signal. After obtaining the first maximum eye diagram, the value of the DCA register corresponding to the first maximum eye diagram is the second... n-1 The optimal value of the DCA register corresponding to +1 phase clock signals.

[0169] i is sequentially selected from 2 to n-1. In the i-th round, the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group is adjusted, including: based on the optimal value of the second DCA register group obtained in the (i-1)-th round, the value of the m*2-th register in the second DCA register group is adjusted multiple times. n-i The value of the DCA register with +1 phase clock signal is used to obtain the first maximum eye diagram of the correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal, where m takes values ​​of [1, 2]. i Odd numbers within the range of ). Based on the optimal value of the second DCA register group obtained from the (i-1)th round of adjustment, the m*2th value in the second DCA register group is adjusted multiple times. n-iWhen the value of the DCA register of +1 phase clock signal is obtained, a new DQS clock signal will be generated based on the optimal value of the second DCA register group obtained in the (i-1)th round of adjustment. The first maximum eye diagram of the correctly sampled data will be obtained by sampling the data transmitted by the DQ data signal using the new DQS clock signal, and the value of the DCA register corresponding to the first maximum eye diagram will be taken as the optimal value.

[0170] In one implementation, the process of adjusting the value of the DCA register corresponding to the second type of phase clock signal in the second DCA register group based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment can be as follows: a new DQS clock signal is generated based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment; the value of the DCA register corresponding to the second type of phase clock signal is adjusted to obtain a second maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the new DQS clock signal; and the value of the DCA register corresponding to the second maximum eye diagram is taken as the optimal value of the DCA register corresponding to the second type of phase clock signal.

[0171] In one implementation, the process of adjusting the value of the DCA register corresponding to the second type of phase clock signal to obtain the second maximum eye diagram for sampling the data transmitted by the DQ data signal using the new DQS clock signal to obtain correctly sampled data includes: repeatedly adjusting the value of the DCA register of the (k+1)th phase clock signal in the second DCA register group to obtain the second eye diagram width for sampling the data transmitted by the DQ data signal using the new DQS clock signal to obtain correctly sampled data, wherein k sequentially takes values ​​[1, 2...]. n Odd numbers within the range of ).

[0172] Taking n=2 as an example, the process of adjusting the value of the DCA register corresponding to the first type of phase clock signal to obtain the first maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal can be as follows: adjust the value of the DCA register corresponding to the third phase clock signal (such as IBCLK_DQS mentioned above) multiple times, obtain the value of each DCA register, and then use two adjacent rising edges in the DQS clock signal to sample the data transmitted by the DQ data signal to obtain the first eye diagram of the correctly sampled data; and then select the first maximum eye diagram from the multiple obtained first eye diagrams.

[0173] Taking n=2 as an example, the process of adjusting the value of the DCA register corresponding to the second type of phase clock signal to obtain the second maximum eye diagram for sampling the data transmitted by the new DQ data signal using the new DQS clock signal to obtain the correct sampled data can be as follows: Adjust the value of the DCA register corresponding to the second phase clock signal to obtain the second maximum eye diagram for sampling the data transmitted by the new DQ data signal using the rising and falling edges of the even-numbered periods in the new DQS clock signal to obtain the correct sampled data; Adjust the value of the DCA register corresponding to the fourth phase clock signal to obtain the second maximum eye diagram for sampling the data transmitted by the new DQ data signal using the rising and falling edges of the odd-numbered periods in the new DQS clock signal to obtain the correct sampled data.

[0174] To better understand the above process, a specific example will be provided below.

[0175] Example 5

[0176] Taking the ICLK_DQS, QCLK_DQS, IBCLK_DQS, and QBCLK_DQS phase clock signals shown above as examples, Figure 6 This diagram illustrates a data mode for optimizing clock jitter. The DQ data is set to 1100 (or other values ​​such as 0011, 1010, or 0101). r0 and r1 are two rising edges of adjacent cycles of the DQS clock signal. The DQ data is sampled using the rising edges r0 and r1 of the DQS clock signal. The data sampled at the rising edges r0 and r1 are compared. If data 1 is sampled at the rising edge r0 and data 0 is sampled at the rising edge r1 (if the DQ data has other values, the data sampled at the rising edges r0 and r1 will also change; for example, if the DQ data is 1010, then data 1 is sampled at the rising edge r0 and data 1 at the rising edge r1), then the data is considered correct. The DQS clock signal is progressively delayed, and the transition point from the first sampled erroneous data to the first sampled correct data is recorded as the first delay. The transition point from the first sampled correct data to the first sampled erroneous data is recorded as the second delay. Based on the first and second delays, the eye diagram width can be obtained. The eye diagram width is determined by the width of the DQ data "1" and "0" and the clock periods r0 and r1 in the DQS clock signal. By progressively changing the value of the DCA register corresponding to the IBCLK_DQS phase clock signal, multiple eye diagram widths can be obtained. The value of the DCA register at the maximum eye diagram width is the optimal value of the DCA register. The process of adjusting the value of the DCA register corresponding to the IBCLK_DQS phase clock signal is as follows:

[0177] If the value of the DCA register of IBCLK_DQS is increased, and the eye diagram increases, then continue increasing the value of the DCA register of IBCLK_DQS until the eye diagram decreases; if the value of the DCA register of IBCLK_DQS is decreased, and the eye diagram increases, then continue decreasing the value of the DCA register of IBCLK_DQS until the eye diagram decreases; if the value of the DCA register of IBCLK_DQS is increased, and the eye diagram decreases, then return to the previous value of the DCA register of IBCLK_DQS, and then decrease the value of the DCA register of IBCLK_DQS again. If the eye diagram also decreases at this time, then the value of the previous DCA register is the optimal value of the DCA register.

[0178] After writing the value of the DCA register corresponding to the optimal IBCLK_DQS phase clock signal into the DCA register, set the DQ data to 1010 (or other values, such as 0101). r0 and f0 are the rising and falling edges of the even-numbered cycles of the DQS clock signal, and r1 and f1 are the rising and falling edges of the odd-numbered cycles of the DQS clock signal. Adjusting the phase of the QCLK_DQS phase clock signal (the value of the DCA register) adjusts the duty cycle of the even-numbered cycles, and adjusting the phase of the QBCLK_DQS phase clock signal (DCA) adjusts the duty cycle of the odd-numbered cycles. Sample the DQ data using the DQS clock signal, and compare the data sampled at the rising edge of r0 and the falling edge of f0. If data 1 is sampled at the rising edge of r0 and data 0 is sampled at the falling edge of f0 (if the DQ data is other values, the data sampled at the rising edge of r0 and the falling edge of f0 will also change), then the data is considered correct. Gradually delaying the DQS clock signal yields the eye diagram width for the even-numbered cycles. The eye diagram width depends on the duty cycle of the even-numbered cycles of the DQ data signal (or DQS clock signal). By gradually changing the value of the DCA register corresponding to the QCLK_DQS phase clock signal, the optimal value of the DCA register is the value of the QCLK_DQS phase clock signal at which the eye diagram width is maximized.

[0179] Similarly, for odd-period DQS clock signals and DQ data, compare the data sampled at the rising edge of r1 and the falling edge of f1. If data 1 is sampled at the rising edge of r1 and data 0 is sampled at the falling edge of f1, the data is considered correct. By progressively delaying the DQS clock signal, the eye diagram width for odd-periods can be obtained. The eye diagram width depends on the duty cycle of the odd-period DQ data signal (or DQS clock signal). By progressively changing the value of the DCA register corresponding to the QBCLK_DQS phase clock signal, the value of the DCA register at the point of maximum eye diagram width is the optimal value of the DCA register. The method for adjusting the values ​​of the DCA registers corresponding to the QCLK_DQS and QBCLK_DQS phase clock signals is the same as that for adjusting the value of the DCA register corresponding to the IBCLK_DQS phase clock signal.

[0180] The above adjustment process can be summarized as follows:

[0181]

[101] Set the initial value of the DCA register to 0. QCLK_DQS, IBCLK_DQS, and QBCLK_DQS each have their own independent DCA register.

[0182]

[102] Set the DQ data to 1100, and judge the DQ data sampled at the rising edges of r0 and r1. When the rising edge return value is 10, it is considered that the correct data has been sampled. Gradually delay the DQS clock signal, and the eye diagram width can be obtained according to the delay interval of the sampled correct data.

[0183]

[103] Gradually change the value of the DCA register of IBCLK_DQS, that is, adjust the phase of IBCLK_DQS, until the eye diagram is at its maximum. Write the value of the DCA register of IBCLK_DQS corresponding to the maximum eye diagram as the optimal value into the DCA register. At this point, the process of improving clock jitter is complete.

[0184]

[104] Set the DQ data to 1010, and determine the sampled data at the even-numbered rising edge r0 and falling edge f0 of the DQS clock signal. When the return value at the rising and falling edges is 10, it is considered that the correct data has been sampled. Gradually delay the DQS clock signal, and the eye diagram width can be obtained based on the delay interval of the sampled correct data.

[0185]

[105] Gradually change the value of the DCA register of QCLK_DQS, that is, adjust the phase of QCLK, until the eye diagram is at its maximum. Write the value of the DCA register of QCLK_DQS when the eye diagram is at its maximum as the optimal value into the DCA register. At this point, the duty cycle of even-numbered cycles is adjusted to the optimal value.

[0186]

[106] Set the DQ data to 1010, and judge the sampled data at the rising edge r1 and falling edge f1 of the odd-numbered period of DQS. When the return value of the rising and falling edges is 10, it is considered that the correct data has been sampled. Gradually delay the DQS clock signal, and the eye diagram width can be obtained according to the delay interval of the sampled correct data.

[0187]

[107] Change the value of the DCA register of QBCLK_DQS, that is, adjust the phase of QBCLK until the eye diagram is at its maximum. Write the value of the DCA register of QBCLK_DQS when the eye diagram is at its maximum as the optimal value into the DCA register. At this point, the duty cycle of the odd-numbered cycles is adjusted to the optimal value. The above

[104] ,

[105] ,

[106] , and

[107] can be done simultaneously, that is, the duty cycle adjustment of the even-numbered cycles and the odd-numbered cycles can be performed at the same time.

[0188] Example 6

[0189] Taking the generation of memory transfer signals using an 8-phase system clock as an example, each phase clock signal has its own DCA register. The adjustment process is as follows:

[0190]

[201] Set the initial value of the DCA register to 0. Each of the 2 to 8 phase clock signals has an independent DCA register.

[0191]

[202] Set the DQ data to 11110000 (or 00001111, 10001000, or 01110111), and determine the DQ data sampled at rising edge 0 and rising edge 4 of DQS. When the return value is 10, it is considered that the correct data has been sampled. Gradually delay the DQS clock signal, and the eye diagram width can be obtained based on the delay interval of the correctly sampled data.

[0192]

[203] Gradually change the value of the DCA register corresponding to the 5th phase clock signal until the eye diagram is at its maximum. Write the value of the DCA register when the eye diagram is at its maximum as the optimal value into the DCA register.

[0193]

[204] Set the DQ data to 11001100 (or other values, such as 00110011), and determine the sampled data at the rising edge 0 and rising edge 2 of the DQS clock signal. When the return value is 10, it is considered that the correct data has been sampled. Gradually delay the DQS clock signal, and the eye diagram width can be obtained based on the delay interval of the sampled correct data.

[0194]

[205] Gradually change the value of the DCA register corresponding to the third phase clock signal until the eye diagram is at its maximum. Write the value of the DCA register when the eye diagram is at its maximum as the optimal value into the DCA register.

[0195]

[206] Set the DQ data to 11001100 (or other values, such as 00110011), and determine the sampled data at the rising edge 4 and rising edge 6 of the DQS clock signal. When the return value is 10, it is considered that the correct data has been sampled. Gradually delay the DQS clock signal, and the eye diagram width can be obtained based on the delay interval of the sampled correct data.

[0196]

[207] Gradually change the value of the DCA register corresponding to the 7th phase clock signal until the eye diagram is at its maximum. Write the value of the DCA register at the maximum eye diagram as the optimal value into the DCA register. Steps

[204] to

[207] can be performed simultaneously.

[0197]

[208] Set the DQ data to 10101010 (or other values, such as 01010101), and determine the sampled data at the rising edge 0 and falling edge 1 of the DQS clock signal. When the return value is 10, it is considered that the correct data has been sampled. Gradually delay the DQS clock signal, and the eye diagram width can be obtained based on the delay interval of the sampled correct data.

[0198]

[209] Gradually change the value of the DCA register corresponding to the second phase clock signal until the eye diagram is at its maximum. Write the value of the DCA register when the eye diagram is at its maximum as the optimal value into the DCA register.

[0199]

[210] Set the DQ data to 10101010 (or other values, such as 01010101), and determine the sampled data at the rising edge 2 and falling edge 3 of the DQS clock signal. When the return value is 10, it is considered that the correct data has been sampled. Gradually delay the DQS clock signal, and the eye diagram width can be obtained based on the delay interval of the sampled correct data.

[0200]

[211] Gradually change the value of the DCA register corresponding to the fourth phase clock signal until the eye diagram is at its maximum. Write the value of the DCA register when the eye diagram is at its maximum as the optimal value into the DCA register.

[0201]

[212] Set the DQ data to 10101010 (or other values, such as 01010101), and judge the sampled data at the rising edge 4 and falling edge 5 of the DQS clock signal. When the return value is 10, it is considered that the correct data has been sampled. Gradually delay the DQS clock signal, and the eye diagram width can be obtained according to the delay interval of the sampled correct data.

[0202]

[213] Gradually change the value of the DCA register corresponding to the 6th phase clock signal until the eye diagram is at its maximum. Write the value of the DCA register when the eye diagram is at its maximum as the optimal value into the DCA register.

[0203]

[214] Set the DQ data to 10101010 (or other values, such as 01010101), and determine the sampled data at the rising edge 6 and falling edge 7 of the DQS clock signal. When the return value is 10, it is considered that the correct data has been sampled. Gradually delay the DQS clock signal, and the eye diagram width can be obtained based on the delay interval of the sampled correct data.

[0204]

[215] Gradually change the value of the DCA register corresponding to the 8th phase clock signal until the eye diagram is at its maximum. Write the value of the DCA register at the maximum eye diagram as the optimal value into the DCA register. Steps

[208] to

[215] can be performed simultaneously.

[0205] In one implementation, the first DCA register group and the second DCA register group may be built into the DDR memory. In this case, the DDR memory may include the first DCA register group, the second DCA register group, and a signal generation unit. The signal generation unit is configured to adjust the phase of the first system clock signal based on the value of the first DCA register group and generate the DQ data signal of the memory based on the first system clock signal; and to adjust the phase of the second system clock signal based on the value of the second DCA register group and generate the DQS clock signal of the memory based on the second system clock signal. That is, by modifying the value of the first DCA register group, the phase relationship between the first system clock signals can be changed, and the time of each phase of the DQ data signal generated by the first system clock signal can be further changed. Similarly, by modifying the value of the second DCA register group, the phase relationship between the second system clock signals can be changed, and the high-level time and low-level time of the DQS clock signal generated by the second system clock signal can be further changed.

[0206] The training process described above can be implemented by a memory controller. Based on the same inventive concept, this application also provides a memory controller, which can be a memory controller. The memory controller is connected to the memory via a DQS clock line and a DQ data line.

[0207] The memory controller includes a training engine configured to instruct the adjustment of the values ​​of a first DCA register group and a second DCA register group. If the first and second DCA register groups are embedded in the DDR memory, the training engine is configured to instruct the DDR memory to adjust the value of the first DCA register group to obtain the optimal value of the first DCA register group, thereby optimizing the duty cycle distortion of the DQ data signal in the memory, or optimizing the clock jitter and duty cycle distortion of the DQ data signal, or optimizing the clock jitter and duty cycle distortion of the transmission signal of the DDR memory. The value of the first DCA register group is phase-dependent with the first system clock signal in the memory, which is used to generate the DQ data signal. It is also configured to instruct the DDR memory to adjust the value of the second DCA register group based on the optimal value of the first DCA register group, to obtain the optimal value of the second DCA register group, in order to optimize the duty cycle distortion of the DQS clock signal in the memory, or optimize the clock jitter and duty cycle distortion of the DQS clock signal; wherein the value of the second DCA register group is phase-dependent with the second system clock signal in the memory, the second system clock signal being used to generate the DQS clock signal.

[0208] In one embodiment, the memory controller further includes: a measurement unit configured to acquire the eye diagram width of correctly sampled data obtained by sampling data transmitted using a DQ data signal (or a new DQ data signal) with a DQS clock signal (or a new DQS clock signal), and to acquire the maximum eye diagram width of correctly sampled data obtained by sampling data transmitted using a DQ data signal (or a new DQ data signal) with a DQS clock signal (or a new DQS clock signal). Accordingly, the training engine is further configured to instruct the memory to adjust the value of a first DCA register group based on the eye diagram width, and to instruct the memory to adjust the value of a second DCA register group based on the maximum eye diagram width.

[0209] The training engine is also configured to instruct the DDR memory to adjust the values ​​of the DCA registers corresponding to the first type-phase clock signals in the first DCA register group to optimize the clock jitter of the DQ data signal; to instruct the DDR memory to adjust the values ​​of the DCA registers corresponding to the second type-phase clock signals in the first DCA register group to optimize the duty cycle distortion of the DQ data signal; and to instruct the DDR memory to adjust the values ​​of the DCA registers corresponding to the first type-phase clock signals in the second DCA register group to optimize the clock jitter of the DQS clock signal; and to instruct the DDR memory to adjust the values ​​of the DCA registers corresponding to the second type-phase clock signals in the second DCA register group to optimize the duty cycle distortion of the DQS clock signal.

[0210] The training engine described above can be implemented using various suitable microprocessors, such as ARM (Advanced RISC Machines) / RISCCV (RISC-V Instruction Set Architecture), etc. The training engine can also be a hardware control circuit. The measurement unit can be a delay measurement circuit that records the first and second delays and calculates the eye diagram width accordingly.

[0211] The adjustment of the values ​​of the first DCA register group and the second DCA register group provided in the memory controller embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the memory controller embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0212] This application also provides an electronic device, which includes a DDR memory and the aforementioned memory controller. The memory controller is connected to the DDR memory via a DQS clock line and a DQ data line. The DDR memory includes a first DCA register group, a second DCA register group, and a signal generation unit. The signal generation unit is configured to adjust the phase of a first system clock signal based on the value of the first DCA register group and generate a DQ data signal for the memory based on the first system clock signal; and to adjust the phase of a second system clock signal based on the value of the second DCA register group and generate a DQS clock signal for the memory based on the second system clock signal.

[0213] The aforementioned electronic device 200 includes, but is not limited to, mobile phones, tablets, computers, servers, etc. In one embodiment, the structural block diagram of the aforementioned electronic device can be as follows: Figure 7 As shown. The electronic device 200 includes: a transceiver 210, a DDR memory 220, a communication bus 230, and a processor 240. The processor 240 may include a memory controller (such as a memory controller).

[0214] The transceiver 210, the DDR memory 220, and the processor 240 are electrically connected to each other directly or indirectly to realize data transmission or interaction.

[0215] Processor 240 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a microprocessor, etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, processor 240 can also be any conventional processor.

[0216] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0217] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for optimizing the transmission signals of a memory, characterized in that, include: The values ​​of the first DCA register group are adjusted, and the DQ data signal is generated based on the optimal values ​​obtained from the adjustment of the first DCA register group; wherein, the first DCA register group contains 2 n There are three DCA registers, where n is an integer greater than or equal to 2; the value of the first DCA register group is related to the phase of the first system clock signal in the memory, and the first system clock signal is used to generate the DQ data signal; Based on the optimal values ​​of the first DCA register group obtained through adjustment, the values ​​of the second DCA register group are adjusted, and a DQS clock signal is generated based on the optimal values ​​of the second DCA register group obtained through adjustment; wherein, the second DCA register group contains 2 n One DCA register; the value of the second DCA register group is related to the phase of the second system clock signal in the memory, the second system clock signal being used to generate the DQS clock signal; Among them, the DQS clock signal and the DQ data signal are the transmission signals between the memory and the memory controller.

2. The method according to claim 1, characterized in that, The first system clock signal includes 2 n Each phase clock signal has an independent DCA register; adjusting the values ​​of the first DCA register group includes: Adjust the value of the DCA register corresponding to the first type of phase clock signal in the first DCA register group to obtain the optimal value of the DCA register corresponding to the first type of phase clock signal, wherein the first type of phase clock signal is a phase clock signal related to the clock jitter of the DQ data signal; Based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment, the value of the DCA register corresponding to the second type of phase clock signal in the first DCA register group is adjusted to obtain the optimal value of the DCA register corresponding to the second type of phase clock signal, wherein the second type of phase clock signal is a phase clock signal related to the duty cycle of the DQ data signal.

3. The method according to claim 1, characterized in that, The first system clock signal includes 2 n Each phase clock signal has an independent DCA register; adjusting the values ​​of the first DCA register group includes: Adjust the value of the first DCA register group, and generate the DQ data signal based on the adjusted value of the first DCA register group; Obtain the correct sampled data by sampling the DQ data signal using the DQS clock signal. n Each eye diagram width represents the phase difference between the corresponding phase clock signal and the next phase clock signal; Based on 2 n The eye diagram width is adjusted to change the value of the first DCA register group so that the new DQ data signal is sampled using the DQS clock signal to obtain correctly sampled data. n Each eye diagram has the same width, and the new DQ data signal is generated based on the adjusted value of the first DCA register group.

4. The method according to claim 3, characterized in that, Based on 2 n Each eye diagram width adjusts the value of the first DCA register group, including: The process involves n rounds of adjusting the values ​​of the first DCA register group; wherein, the first round of adjusting the values ​​of the first DCA register group includes: Based on the first two n-1 Eye width and the last 2 n-1 The eye diagram width is adjusted, and the second eye diagram in the first DCA register group is adjusted. n-1 +1 phase clock signal value of DCA register, so that the first 2 n-1 The sum of the widths of each eye diagram and the last two n-1 The sum of the widths of all eye diagrams is the same; i takes values ​​from 2 to n-1 sequentially, and the i-th round of adjusting the value of the first DCA register group includes: Based on the optimal value of the first DCA register group obtained in the (i-1)th round of adjustment, a new DQ data signal is generated, and a new 2 is obtained based on the new DQ data signal. n Eye diagram width; based on the new 2 n The eye diagram width is adjusted in the m*2th register group of the first DCA register group. n-i The value of the DCA register is increased by 1 phase clock signal to make the sum of the widths of each eye diagram the same, and the sum of the widths of each eye diagram is 2 for adjacent eyes. n-i The sum of the widths of the eye diagrams, where m takes values ​​from [1, 2] to [3]. i Odd numbers within the range of ) The nth round of adjusting the value of the first DCA register group includes: Based on the optimal value of the first DCA register group obtained in the (n-1)th round of adjustment, a new DQ data signal is generated, and based on the new DQ data signal, a new 2 n Eye diagram width; based on the new 2 n Each eye diagram width is adjusted by changing the value of the DCA register of the (k+1)th phase clock signal in the first DCA register group to make each eye diagram width the same, where k takes values ​​from [1, 2] to [3]. n Odd numbers within the range of ).

5. The method according to claim 1, characterized in that, The first system clock signal includes 2 n Each phase clock signal has an independent DCA register; adjusting the values ​​of the first DCA register group includes: The process involves n rounds of adjusting the values ​​of the first DCA register group; wherein, the first round of adjusting the values ​​of the first DCA register group includes: Based on the width of the first eye diagram and the width of the second eye diagram, adjust the second register in the first DCA register group. n-1 +1 phase clock signal value of DCA register, so that the first 2 n-1 The sum of the eye diagram widths corresponding to each phase clock signal and the following 2 n-1 The sum of the eye diagram widths corresponding to each phase clock signal is the same, wherein the sum of the widths of the first eye diagram is equal to the sum of the widths of the previous two phase clock signals. n-1 The sum of the eye diagram widths corresponding to each phase clock signal, and the sum of the widths of the second eye diagram is the sum of the widths of the last two phase clock signals. n-1 The sum of the eye diagram widths corresponding to each phase clock signal, where each eye diagram width represents the phase difference between the corresponding phase clock signal and the next phase clock signal; i takes values ​​from 2 to n-1 sequentially, and the i-th round of adjusting the value of the first DCA register group includes: Based on the optimal value of the first DCA register group obtained in the (i-1)th round of adjustment, a new DQ data signal is generated, and based on the new DQ data signal, 2 is obtained. i The sum of the widths of the two eye diagrams, where the sum of the widths of each eye diagram is equal to the sum of the widths of the two adjacent eye diagrams. n-i The sum of the eye diagram widths corresponding to each phase clock signal; based on 2 i The eye diagram width and adjustment of the m*2th eye in the first DCA register group n-i The value of the DCA register for +1 phase clock signals is used to make the width of each eye diagram the same, where m takes values ​​from [1, 2] in sequence. i Odd numbers within the range of ) The nth round of adjusting the value of the first DCA register group includes: Based on the optimal value of the first DCA register group obtained in the (n-1)th round of adjustment, a new DQ data signal is generated, and based on the new DQ data signal, 2 is obtained. n Eye width; based on 2 n The eye diagram width is adjusted by changing the value of the DCA register of the (k+1)th phase clock signal in the first DCA register group to make each adjacent eye diagram width the same, where k takes values ​​from [1, 2] to [3]. n Odd numbers within the range of ).

6. The method according to any one of claims 1-5, characterized in that, The second system clock signal contains 2 n Each phase clock signal has an independent DCA register; adjusting the values ​​of the second DCA register group includes: Adjust the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group to obtain the optimal value of the DCA register corresponding to the first type of phase clock signal, wherein the first type of phase clock signal is a phase clock signal related to the clock jitter of the DQS clock signal; Based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment, the value of the DCA register corresponding to the second type of phase clock signal in the second DCA register group is adjusted to obtain the optimal value of the DCA register corresponding to the second type of phase clock signal, wherein the second type of phase clock signal is a phase clock signal related to the duty cycle of the DQS clock signal.

7. The method according to claim 6, characterized in that, Adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group includes: Adjust the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group to obtain the first maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal. The value of the DCA register corresponding to the first maximum eye diagram is taken as the optimal value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group.

8. The method according to claim 7, characterized in that, Adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group to obtain the first maximum eye diagram of correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal, including: This involves n-1 rounds of adjusting the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group; The first round of adjustments includes changing the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group, including: Multiple adjustments to the 2nd n-1 The value of the DCA register corresponding to +1 phase clock signal is used to obtain the first maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the DQS clock signal. i is sequentially selected from 2 to n-1. In the i-th round, the value of the DCA register corresponding to the first type of phase clock signal in the second DCA register group is adjusted, including: Based on the optimal value of the second DCA register group obtained in the (i-1)th round of adjustment, the m*2th value of the second DCA register group is adjusted multiple times. n-i The value of the DCA register with +1 phase clock signal is used to obtain the first maximum eye diagram of the correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal, where m takes values ​​of [1, 2]. i Odd numbers within the range of ).

9. The method according to claim 6, characterized in that, Based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained from the adjustment, the values ​​of the DCA registers corresponding to the second type of phase clock signal in the second DCA register group are adjusted, including: A new DQS clock signal is generated based on the optimal value of the DCA register corresponding to the first type of phase clock signal obtained by adjustment. Adjust the value of the DCA register corresponding to the second type of phase clock signal to obtain the second maximum eye diagram of the correctly sampled data by sampling the data transmitted by the DQ data signal using the new DQS clock signal. The value of the DCA register corresponding to the second maximum eye diagram is taken as the optimal value of the DCA register corresponding to the second type of phase clock signal.

10. The method according to claim 9, characterized in that, Adjust the value of the DCA register corresponding to the second type of phase clock signal to obtain the second maximum eye diagram of correctly sampled data by sampling the data transmitted by the DQ data signal using the new DQS clock signal, including: By repeatedly adjusting the value of the DCA register of the (k+1)th phase clock signal in the second DCA register group, the width of the second eye diagram is obtained by sampling the data transmitted by the DQ data signal using the new DQS clock signal to obtain the correct sampled data. Here, k takes values ​​in the range [1, 2]. n Odd numbers within the range of ).

11. A memory controller, characterized in that, The memory controller is connected to the memory via a DQS clock line and a DQ data line. The DQS clock line is used to transmit the DQS clock signal, and the DQ data line is used to transmit the DQ data signal. The memory controller includes: The training engine is configured to instruct the memory to adjust the values ​​of the first DCA register group to obtain the optimal values ​​of the first DCA register group; wherein the first DCA register group contains 2 n There are three DCA registers, where n is an integer greater than or equal to 2; the value of the first DCA register group is related to the phase of the first system clock signal in the memory, and the first system clock signal is used to generate the DQ data signal; The training engine is further configured to instruct the memory to adjust the values ​​of the second DCA register group based on the optimal values ​​of the first DCA register group, thereby obtaining the optimal values ​​of the second DCA register group; wherein the second DCA register group contains 2 n A DCA register; the value of the second DCA register group is related to the phase of the second system clock signal in the memory, which is used to generate the DQS clock signal.

12. The memory controller according to claim 11, characterized in that, The memory controller also includes: The measurement unit is configured to acquire the eye diagram width of correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal, and to acquire the maximum eye diagram width of correctly sampled data obtained by sampling the data transmitted by the DQ data signal using the DQS clock signal. The training engine is also configured to adjust the value of the first DCA register group based on the eye width indication memory, and to adjust the value of the second DCA register group based on the maximum eye width indication memory.

13. An electronic device, characterized in that, include: The memory and the memory controller as described in claim 11 or 12, wherein the memory controller is connected to the memory via a DQS clock line and a DQ data line, the DQS clock line being used to transmit a DQS clock signal and the DQ data line being used to transmit a DQ data signal; The memory includes a first DCA register group, a second DCA register group, and a signal generation unit. The signal generation unit is configured to adjust the phase of the first system clock signal based on the value of the first DCA register group, generate the DQ data signal based on the first system clock signal, adjust the phase of the second system clock signal based on the value of the second DCA register group, and generate the DQS clock signal based on the second system clock signal.

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