Semiconductor device and method of manufacturing the same
By using continuous laser annealing and pulsed laser annealing processes to process amorphous silicon structures in semiconductor devices to form polycrystalline silicon layers, the problem of low conversion efficiency of amorphous silicon is solved, and the performance of semiconductor devices is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-24
- Publication Date
- 2026-03-27
AI Technical Summary
In existing technologies, the conversion rate of amorphous silicon to polycrystalline silicon is low, resulting in poor quality of the polycrystalline silicon layer and affecting the performance of semiconductor devices.
The channel material layer and drain material layer of amorphous silicon structure are processed by continuous laser annealing and pulsed laser annealing to form the channel layer and drain of polycrystalline silicon structure.
This improved the conversion rate of amorphous silicon to polycrystalline silicon, enhanced the quality of the polycrystalline silicon layer, and thus improved the performance of semiconductor devices.
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Figure CN118692903B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor device and a preparation method thereof. BACKGROUND
[0002] Polysilicon has strong electric field effect mobility and low resistance advantages, and is widely used in semiconductor devices. In the traditional technology, for the polysilicon layer in the semiconductor device, the method of converting amorphous silicon into polysilicon is usually used to form the corresponding polysilicon layer.
[0003] However, the conversion rate of converting amorphous silicon into polysilicon is low at present, which leads to poor quality of the formed polysilicon layer. SUMMARY
[0004] Based on this, the embodiments of the present application provide a semiconductor device and a preparation method thereof, which can improve the quality of the polysilicon layer in the semiconductor device, and further improve the performance of the semiconductor device.
[0005] In order to achieve the above purpose, the preparation method of the semiconductor device provided by the embodiments of the present application comprises the following steps:
[0006] providing a substrate;
[0007] forming a source and a first isolation layer on the substrate in sequence;
[0008] forming a gate arranged in intervals on the first isolation layer;
[0009] forming a second isolation layer covering the gate;
[0010] forming a via hole penetrating through the second isolation layer, the gate and the first isolation layer 11 in sequence; the via hole exposes the surface of the source;
[0011] forming a channel material layer; the channel material layer covers the inner wall of the via hole and the surface of the source;
[0012] filling a third isolation layer and a drain material layer in the via hole in sequence;
[0013] performing a continuous laser annealing process and a pulse laser annealing process on the channel material layer and the drain material layer to form a channel layer and a drain;
[0014] Among them, the source, the channel layer and the drain have a polycrystalline structure.
[0015] In some embodiments of the present application, before performing the continuous laser annealing process and the pulse laser annealing process on the channel material layer and the drain material layer, the preparation method of the semiconductor device further comprises the following steps: forming an absorption layer or a reflection layer on the drain material layer.
[0016] In some embodiments of the present application, forming the absorption layer 51 on the drain material layer comprises the following steps:
[0017] forming a first insulating layer, a metal layer and a second insulating layer on the drain material layer in sequence.
[0018] In some embodiments of the present application, the first insulating layer and the second insulating layer are made of different materials.
[0019] In some embodiments of the present application, the first insulating layer is made of silicon nitride, and the second insulating layer is made of silicon oxide.
[0020] In some embodiments of the present application, forming the reflection layer on the drain material layer comprises the following steps:
[0021] forming a metal oxide layer and a third insulating layer on the drain material layer in sequence.
[0022] In some embodiments of the present application, the metal oxide layer is made of titanium dioxide, and the third insulating layer is made of silicon oxide.
[0023] In some embodiments of the present application, forming the via hole penetrating through the second isolation layer, the gate and the first isolation layer 11 in sequence comprises the following steps:
[0024] forming an initial via hole penetrating through the second isolation layer and the gate in sequence; the initial via hole exposes the surface of the first isolation layer;
[0025] forming a gate dielectric layer; the gate dielectric layer covers the inner wall of the initial via hole, and the surface of the second isolation layer 12;
[0026] forming a sacrificial layer covering the gate dielectric layer in shape;
[0027] etching the sacrificial layer, the gate dielectric layer and the first isolation layer in the initial via hole in sequence to form the via hole;
[0028] Before forming the channel material layer, the method for manufacturing the semiconductor device further comprises the following steps:
[0029] partially removing the sacrificial layer and the gate dielectric layer.
[0030] In some embodiments of the present application, after forming the channel layer and the drain, the method for manufacturing the semiconductor device further comprises the following steps:
[0031] removing the drain located on the surface of the channel material layer;
[0032] performing an annealing process;
[0033] forming a drain barrier layer and a drain metal layer on the drain in sequence;
[0034] forming a side wall covering the side wall of the drain barrier layer and the drain metal layer.
[0035] This invention also provides a semiconductor device, which is fabricated using the semiconductor device fabrication method described in the foregoing embodiments.
[0036] The semiconductor structure and its fabrication method provided in the embodiments of the present invention have, or at least have, the following advantages:
[0037] In this embodiment of the invention, after forming a via, a channel material layer is first formed on the inner wall of the via and the surface of the source electrode, and then a third isolation layer and a drain material layer are sequentially filled into the via. By performing continuous laser annealing and pulsed laser annealing processes on the channel material layer and drain material layer respectively, the amorphous silicon channel material layer and drain material layer are transformed into a polycrystalline silicon channel layer and drain electrode. Thus, compared with the traditional annealing process, this embodiment of the invention uses continuous laser annealing and pulsed laser annealing processes to process the amorphous silicon channel material layer and drain material layer, which can further improve the conversion rate of amorphous silicon to polycrystalline silicon. That is, it improves the conversion rate of amorphous silicon channel material layer and drain material layer to polycrystalline silicon channel layer and drain electrode, thereby improving the quality of polycrystalline silicon channel layer and drain electrode, and thus improving the performance of semiconductor devices. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Fig. 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to one embodiment;
[0040] Fig. 2 This is a flowchart illustrating the formation of a through-hole in a method for fabricating a semiconductor device according to one embodiment;
[0041] Fig. 3 This is a flowchart illustrating the formation of sidewalls in a method for fabricating a semiconductor device according to one embodiment;
[0042] Figs. 4 to 23 This is a schematic cross-sectional view of the structure obtained in different steps of a semiconductor device fabrication method provided in one embodiment.
[0043] Explanation of reference numerals in the attached figures:
[0044] 1-substrate, 10-medium layer, 101-connector, 102-barrier layer, 11-first isolation layer, 12-second isolation layer, 121-first part, 122-second part, 130-channel material layer, 13-channel layer, 140-third isolation material layer, 14-third isolation layer, 15-gate medium layer, 16-sacrificial layer, 17-side wall; 2-source, 21-source metal layer, 22-source barrier layer; 3-gate, 310-gate barrier material layer, 31-gate barrier layer; 4-drain, 40-drain material layer, 41-drain barrier layer, 42-drain metal layer; 51-absorbing layer, 511-first insulating layer, 512-metal layer, 513-second insulating layer, 52-reflective layer, 521-metal oxide layer, 522-third insulating layer; K10-initial via, K1-via. DETAILED DESCRIPTION
[0045] For the purpose of promoting an understanding of the application, the application will now be described in greater detail with reference to the drawings. Given in the drawings are embodiments of the application. However, the application can be realized in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It will be apparent, however, to one of ordinary skill in the art that the application can be practiced without these specific details.
[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0047] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.
[0048] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0049] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
[0050] Embodiments of the application are described herein with reference to the drawings, which show ideal embodiments (and intermediate structures) of the application. Variations to the shapes of the features illustrated in the drawings can occur because of, for example, manufacturing processes and / or tolerances. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result from, for example, manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implantation was performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.
[0051] Polysilicon has the advantages of strong electric field effect mobility and low resistance, and is widely used in semiconductor devices. For a polysilicon layer in a semiconductor device, a method of converting amorphous silicon into polysilicon is usually used to form a corresponding polysilicon layer. However, the conversion rate of converting amorphous silicon into polysilicon is low at present, resulting in poor quality of the formed polysilicon layer.
[0052] Based on this, the embodiments of the present application provide a semiconductor device and a preparation method thereof, which can improve the quality of the polysilicon layer in the semiconductor device, and further improve the performance of the semiconductor device.
[0053] Please refer to Fig. 1 The embodiments of the present application provide a preparation method of a semiconductor device, including steps S100-S800.
[0054] S100, providing a substrate.
[0055] S200, sequentially forming a source electrode and a first isolation layer on the substrate.
[0056] S300, forming a gate electrode arranged at intervals on the first isolation layer.
[0057] S400, forming a second isolation layer covering the gate electrode.
[0058] S500, forming a via hole penetrating through the second isolation layer, the gate electrode and the first isolation layer in sequence. The via hole exposes the surface of the source electrode.
[0059] S600, forming a channel material layer. The channel material layer covers the inner wall of the via hole and the surface of the source electrode.
[0060] S700, sequentially filling a third isolation layer and a drain material layer in the via hole.
[0061] S800, performing a continuous laser annealing process and a pulse laser annealing process on the channel material layer and the drain material layer to form a channel layer and a drain.
[0062] The source, the channel layer and the drain have a polycrystalline structure.
[0063] In the embodiment of the present application, after forming the via, the channel material layer is formed on the inner wall of the via and the surface of the source, and then the third isolation layer and the drain material layer are sequentially filled in the via. By performing the continuous laser annealing process and the pulse laser annealing process on the channel material layer and the drain material layer in sequence, the amorphous silicon structure of the channel material layer and the drain material layer is converted into the polycrystalline silicon structure of the channel layer and the drain. In this way, compared with the traditional annealing process, the continuous laser annealing process and the pulse laser annealing process are used to process the amorphous silicon structure of the channel material layer and the drain material layer in the embodiment of the present application, which can further improve the conversion rate of amorphous silicon to polycrystalline silicon, that is, improve the conversion rate of the amorphous silicon structure of the channel material layer and the drain material layer to the polycrystalline silicon structure of the channel layer and the drain, thereby improving the quality of the polycrystalline silicon structure of the channel layer and the drain, and further improving the performance of the semiconductor device.
[0064] In some embodiments, before the step S800 of performing the continuous laser annealing process and the pulse laser annealing process on the channel material layer and the drain material layer, the method for manufacturing the semiconductor device further comprises: forming an absorption layer or a reflective layer on the drain material layer.
[0065] In some embodiments, the step S750 is included in forming the absorption layer on the drain material layer.
[0066] S750, forming a first insulating layer, a metal layer and a second insulating layer which are sequentially stacked on the drain material layer.
[0067] In some embodiments, the materials of the first insulating layer and the second insulating layer are different.
[0068] In some embodiments, the material of the first insulating layer is silicon nitride, and the material of the second insulating layer is silicon oxide.
[0069] In some embodiments, the step S750' is included in forming the reflective layer on the drain material layer.
[0070] S750', forming a metal oxide layer and a third insulating layer which are sequentially stacked on the drain material layer.
[0071] In some embodiments, the material of the metal oxide layer includes titanium dioxide, and the material of the third insulating layer includes silicon oxide.
[0072] In some embodiments, please refer to Fig. 2The step S500 of forming the via hole penetrating through the second isolation layer, the gate and the first isolation layer in sequence comprises steps S510-S540.
[0073] S510, forming an initial via hole penetrating through the second isolation layer and the gate in sequence; the initial via hole exposes the surface of the first isolation layer.
[0074] S520, forming a gate dielectric layer; the gate dielectric layer covers the inner wall of the initial via hole and the surface of the second isolation layer.
[0075] S530, forming a sacrificial layer covering the gate dielectric layer in shape.
[0076] S540, etching the sacrificial layer, the gate dielectric layer and the first isolation layer in the initial via hole in sequence to form the via hole.
[0077] Before the step S600 of forming the channel material layer, the method for manufacturing the semiconductor device further comprises a step of partially removing the sacrificial layer and the gate dielectric layer.
[0078] In some embodiments, referring to Fig. 3 After the step S800 of forming the channel layer and the drain, the method for manufacturing the semiconductor device further comprises steps S910-S940.
[0079] S910, removing the drain located on the surface of the channel material layer;
[0080] S920, performing an annealing process;
[0081] S930, forming a drain barrier layer and a drain metal layer on the drain in sequence;
[0082] S940, forming a side wall covering the side wall of the drain barrier layer and the drain metal layer.
[0083] It should be understood that, although Figs. 1 to 3 the steps in the flowchart of the method are shown in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figs. 1 to 3 at least part of the steps in the method can comprise multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with other steps or steps or stages in other steps.
[0084] In order to more clearly illustrate the method for manufacturing the semiconductor device provided by the embodiments of the present application, the following will be combined with Figs. 4 to 23Some possible embodiments of the method for manufacturing the semiconductor structure are described in detail.
[0085] In step S100, referring to Fig. 4 , a substrate 1 is provided.
[0086] In some examples, the substrate 1 in the embodiments of the present application can be made of a semiconductor material, an insulating material, a conductive material, or any combination of the material types thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrate or II / VI semiconductor substrate. Alternatively, for example, the substrate 1 can be a layered substrate including a stack such as Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI), or a silicon-germanium-on-insulator, etc. A person skilled in the art can select the type of the substrate 1 according to the type of the transistor formed on the substrate 1, and thus the type of the substrate 1 should not limit the protection scope of the present application.
[0087] In some embodiments, after the step S100 of providing the substrate 1, the method for manufacturing the semiconductor device further includes: forming a dielectric layer 10 on the substrate 1; forming a connection hole in the dielectric layer 10; the connection hole penetrating through the dielectric layer 10; forming a connection member 102 covering the inner wall and the bottom surface of the connection hole; forming a barrier layer 101 filling the connection hole; the barrier layer 101 being electrically connected to the substrate 1 and the source 2.
[0088] In some examples, the material of the dielectric layer 10 includes but is not limited to a silicon organic compound. The material of the connection member 102 includes but is not limited to a metal nitride, for example, titanium nitride. The material of the barrier layer 101 includes but is not limited to a metal, for example, tungsten.
[0089] In step S200, referring to Fig. 4 , a source 2 and a first isolation layer 11 are sequentially formed on the substrate 1.
[0090] In some embodiments, the source 2 and the first isolation layer 11 extend along a first direction (for example, the X direction). Before forming the source 2 extending along the first direction (for example, the X direction) on the substrate 1, the method further includes: sequentially forming a source metal layer 21 and a source barrier layer 22 extending along the first direction (for example, the X direction) on the substrate 1.
[0091] In some examples, the material of the source 2 includes but is not limited to polysilicon. The material of the first isolation layer 11 includes but is not limited to a silicon organic compound. The material of the source metal layer 21 includes but is not limited to a metal, for example, tungsten. The material of the source barrier layer 22 includes but is not limited to titanium nitride.
[0092] In step S300, please refer to Fig. 4 and Fig. 5 Gates 3 are formed at intervals on the first isolation layer 11.
[0093] In some examples, forming a gate 3 spaced apart on the first isolation layer 11 includes: sequentially forming a gate barrier material layer 310 and a gate material layer 30 on the first isolation layer 11; and sequentially etching the gate material layer 30 and the gate barrier material layer 310 along a second direction (e.g., the Y direction) to form the gate 3 and the gate barrier layer 31.
[0094] In some examples, the material of gate 3 includes, but is not limited to, metals, such as tungsten. The material of gate barrier layer 31 includes, but is not limited to, titanium nitride.
[0095] In step S400, please refer to Fig. 6 and Fig. 7 A second isolation layer 12 is formed covering the gate 3.
[0096] In some embodiments, the second isolation layer 12 includes a first portion 121 and a second portion 122.
[0097] In some examples, forming a second isolation layer 12 covering the gate 3 includes: (See also) Fig. 6 A first portion 121 is formed on the first isolation layer 11; see also Fig. 7 The second part 122 is formed on the first part 121.
[0098] In some examples, the materials of the first part 121 and the second part 122 may be the same or different. For example, the material of the first part 121 includes, but is not limited to, oxides. The material of the second part 122 includes, but is not limited to, organosilicon compounds.
[0099] In step S510, please refer to Fig. 8 An initial via K10 is formed that sequentially penetrates the second isolation layer 12 and the gate 3; the initial via K10 exposes the surface of the first isolation layer 11.
[0100] In some examples, an etching process can be used to sequentially etch the second isolation layer 12 and the gate 3 along a second direction (e.g., the Y direction) to form an initial via K10.
[0101] In step S520, please refer to Fig. 9 A gate dielectric layer 15 is formed. The gate dielectric layer 15 covers the inner wall of the initial via K10 and the surface of the second isolation layer 12.
[0102] In some examples, a deposition process can be used to form the gate dielectric layer 15.
[0103] In some examples, the material of the gate dielectric layer 15 can include, but is not limited to, silicon nitride.
[0104] In step S530, please refer to Fig. 9 to form the sacrificial layer 16 which conforms to the gate dielectric layer 15.
[0105] In some examples, the deposition process can be used to form the sacrificial layer 16.
[0106] In some examples, the material of the sacrificial layer 16 can include, but is not limited to, amorphous silicon.
[0107] In step S540, please refer to Fig. 10 to etch the sacrificial layer 16, the gate dielectric layer 15 and the first isolation layer 11 in the initial via K10 in sequence to form the via K1.
[0108] In step S600, please refer to Fig. 10 and Fig. 11 to form the channel material layer 130. The channel material layer 130 covers the inner wall of the via K1 and the surface of the source 2.
[0109] In some examples, the material of the channel material layer 130 can include, but is not limited to, amorphous silicon.
[0110] In step S700, please refer to Figs. 12 to 14 to fill the third isolation layer 14 and the drain material layer 40 in the via K1 in sequence.
[0111] In some embodiments, filling the third isolation layer 14 and the drain material layer 40 in the via K1 in sequence includes:
[0112] Please refer to Fig. 12 to form the third isolation material layer 140 on the surface of the channel material layer 130, and the third isolation material layer 140 fills the via K1.
[0113] Please refer to Fig. 13 to partially remove the third isolation material layer 140 on the surface of the channel material layer and in the via K1 to form the third isolation layer 14. In some embodiments, the surface of the third isolation layer 14 is not lower than the surface of the gate 3.
[0114] Please refer to Fig. 14 to form the drain material layer 40 on the surface of the third isolation layer 14, and the drain material layer 40 also covers the surface of the channel material layer 130.
[0115] In some examples, the material of the third isolation layer 14 includes, but is not limited to, oxide. The material of the drain material layer 40 includes, but is not limited to, amorphous silicon.
[0116] In step S800, referring to Fig. 15 A continuous laser annealing process P1 is performed on the channel material layer 130 and the drain material layer 40, referring to Fig. 16 A pulse laser annealing process P2 is performed to form the channel layer 13 and the drain 4.
[0117] In some examples, the material of the channel layer 13 includes but is not limited to polysilicon. The material of the drain 4 includes but is not limited to polysilicon.
[0118] In the embodiments of the present application, compared with the conventional annealing process, the continuous laser annealing process and the pulse laser annealing process are used to process the channel material layer and the drain material layer of the amorphous silicon structure, which can further improve the conversion rate of the amorphous silicon into polysilicon, i.e., improve the conversion rate of the channel material layer and the drain material layer of the amorphous silicon structure into the channel layer and the drain of the polysilicon structure, thereby improving the quality of the channel layer and the drain of the polysilicon structure, and further improving the performance of the semiconductor device.
[0119] In some embodiments, before the step S800 of performing the continuous laser annealing process and the pulse laser annealing process on the channel material layer 130 and the drain material layer 40, the method for manufacturing the semiconductor device further includes: forming an absorption layer 51 or a reflective layer 52 on the drain material layer 40.
[0120] In the embodiments of the present application, the absorption layer 51 or the reflective layer 52 is formed on the drain material layer 40 before the continuous laser annealing process and the pulse laser annealing process are performed. In this way, the uniformity of the laser is improved, the activation efficiency of the laser is improved, and the conversion rate of the amorphous silicon into polysilicon is further improved.
[0121] Referring to Fig. 17 In some examples, forming the absorption layer 51 on the drain material layer 40 includes:
[0122] The first insulating layer 511, the metal layer 512 and the second insulating layer 513 are sequentially formed on the drain material layer 40.
[0123] For example, the materials of the first insulating layer 511 and the second insulating layer 513 are different.
[0124] For example, the material of the first insulating layer 511 is silicon nitride. The material of the second insulating layer 513 is silicon oxide.
[0125] For example, the material of the metal layer 512 can include but is not limited to metal, for example, tungsten.
[0126] Correspondingly, in some embodiments, in step S800, referring to Fig. 18The continuous laser annealing process P1 is performed on the channel material layer 130 and the drain material layer 40 by using the absorption layer 51. Please refer to Fig. 19 The continuous pulsed laser annealing process P2 is performed on the channel material layer 130 and the drain material layer 40 by using the absorption layer 51 to form the channel layer 13 and the drain 4.
[0127] Please refer to Fig. 20 In some examples, forming the reflection layer 52 on the drain material layer 40 comprises:
[0128] A metal oxide layer 521 and a third insulating layer 522 are formed on the drain material layer 40 in sequence.
[0129] For example, the material of the metal oxide layer 521 comprises titanium dioxide. The material of the third insulating layer 522 comprises silicon oxide.
[0130] Correspondingly, in some embodiments, in step S800, please refer to Fig. 21 The continuous laser annealing process P1 is performed on the channel material layer 130 and the drain material layer 40 by using the reflection layer 52. Please refer to Fig. 22 The continuous pulsed laser annealing process P2 is performed on the channel material layer 130 and the drain material layer 40 by using the reflection layer 52 to form the channel layer 13 and the drain 4.
[0131] In step S910, please refer to Fig. 23 The drain 4 located on the surface of the channel layer 13 is removed.
[0132] In some examples, the etching process can be used to remove the drain 4 located on the surface of the channel layer 13.
[0133] In step S920, please continue to refer to Fig. 23 The annealing process is performed.
[0134] In step S930, please continue to refer to Fig. 23 The drain blocking layer 41 and the drain metal layer 42 are formed on the drain 4 in sequence.
[0135] In some examples, the deposition process can be used to form the drain blocking layer 41 and the drain metal layer 42 in sequence.
[0136] In some examples, the material of the drain blocking layer 41 comprises but is not limited to titanium nitride. The material of the drain metal layer 42 comprises but is not limited to metal, such as tungsten.
[0137] In step S940, please continue to refer to Fig. 23 The side wall 17 covering the side wall of the drain blocking layer 41 and the drain metal layer 42 is formed.
[0138] In some examples, the material of the sidewall 17 includes, but is not limited to, silicon nitride.
[0139] The embodiment of the present application further provides a semiconductor device prepared by the preparation method of the semiconductor device.
[0140] In the embodiment of the present application, the semiconductor device adopts the above structure, and the technical effects that can be achieved by the structure are the same as the technical effects that can be achieved by the preparation method of the semiconductor device in the above embodiment, and thus will not be described here.
[0141] In the description of the specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example.
[0142] The technical features of the above embodiments can be combined arbitrarily, and in order to make the description simple, all possible combinations of the technical features of the above embodiments are not described, however, as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present application.
[0143] The above embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as the limitation of the patent application scope. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A source electrode and a first isolation layer are sequentially formed on the substrate; Gates are formed at intervals on the first isolation layer; A second isolation layer is formed covering the gate; A via is formed that sequentially penetrates the second isolation layer, the gate, and the first isolation layer; the via exposes the surface of the source electrode; A channel material layer is formed; the channel material layer covers the inner wall of the through hole and the surface of the source electrode; The via is sequentially filled with a third isolation layer and a drain material layer; The channel material layer and the drain material layer are subjected to a first annealing process and a second annealing process in sequence to form the channel layer and the drain electrode; wherein, the first annealing process is a continuous laser annealing process and the second annealing process is a pulsed laser annealing process; the source electrode, the channel layer and the drain electrode have a polycrystalline structure.
2. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A source electrode and a first isolation layer are sequentially formed on the substrate; Gates are formed at intervals on the first isolation layer; A second isolation layer is formed covering the gate; A via is formed that sequentially penetrates the second isolation layer, the gate, and the first isolation layer; the via exposes the surface of the source electrode; A channel material layer is formed; the channel material layer covers the inner wall of the through hole and the surface of the source electrode; The via is sequentially filled with a third isolation layer and a drain material layer; Continuous laser annealing and pulsed laser annealing processes are performed on the channel material layer and the drain material layer to form the channel layer and the drain electrode; The source electrode, the channel layer, and the drain electrode have polycrystalline structures. After forming the channel layer and drain electrode, the process further includes: Remove the drain electrode located on the surface of the channel material layer; Perform the annealing process; A drain barrier layer and a drain metal layer are sequentially formed on the drain electrode; A sidewall is formed that covers the drain barrier layer and the sidewall of the drain metal layer.
3. The method for fabricating a semiconductor device as described in claim 1 or 2, characterized in that, Before performing continuous laser annealing and pulsed laser annealing processes on the channel material layer and the drain material layer, the method further includes forming an absorption layer or a reflection layer on the drain material layer.
4. The method for fabricating a semiconductor device as described in claim 3, characterized in that, Forming an absorption layer on the drain material layer includes: A first insulating layer, a metal layer, and a second insulating layer are formed sequentially on the drain material layer.
5. The method for fabricating a semiconductor device as described in claim 4, characterized in that, The first insulating layer and the second insulating layer are made of different materials.
6. The method for fabricating a semiconductor device as described in claim 4, characterized in that, The first insulating layer is made of silicon nitride, and the second insulating layer is made of silicon oxide.
7. The method for fabricating a semiconductor device as described in claim 3, characterized in that, Forming a reflective layer on the drain material layer includes: A metal oxide layer and a third insulating layer are formed sequentially on the drain material layer.
8. The method for fabricating a semiconductor device as described in claim 7, characterized in that, The material of the metal oxide layer includes titanium dioxide; the material of the third insulating layer includes silicon oxide.
9. The method for fabricating a semiconductor device as described in claim 1 or 2, characterized in that, The via formed sequentially penetrating the second isolation layer, the gate, and the first isolation layer includes: An initial via is formed that sequentially penetrates the second isolation layer and the gate; the initial via exposes the surface of the first isolation layer; A gate dielectric layer is formed; the gate dielectric layer covers the inner wall of the initial via and the surface of the second isolation layer; Form a sacrificial layer that conformally covers the gate dielectric layer; The sacrificial layer, the gate dielectric layer, and the first isolation layer are sequentially etched within the initial via to form a via; Before forming the channel material layer, the method further includes: Partial removal of the sacrificial layer and the gate dielectric layer.
10. A semiconductor device, characterized in that, It is prepared by the method of preparing a semiconductor device as described in any one of claims 1 to 9.
Citation Information
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