Light emitting diode with improved soldering reliability and method of manufacturing the same

Abstract

This disclosure provides a light-emitting diode (LED) with improved soldering reliability and its fabrication method, belonging to the field of optoelectronic manufacturing technology. The LED includes a substrate, an epitaxial layer, a passivation layer, and a metal interconnect layer. The epitaxial layer and the metal interconnect layer are both located on the surface of the substrate, with the metal interconnect layer spaced apart from the epitaxial layer and distributed along the peripheral edge of the epitaxial layer. The passivation layer is located on the surface of the epitaxial layer away from the substrate, on the sidewalls of the epitaxial layer, in the gap between the metal interconnect layer and the epitaxial layer, and on the surface of the metal interconnect layer away from the substrate, with the passivation layer exposed on the sidewalls of the metal interconnect layer. Embodiments of this disclosure can improve the soldering stability of the LED pads and circuit board after soldering.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode with improved welding reliability and a method for its fabrication. Background Technology

[0002] Light-emitting diodes (LEDs) are highly influential new products in the optoelectronics industry. They are characterized by their small size, long lifespan, rich and colorful colors, and low energy consumption. They are widely used in lighting, displays, signal lights, backlights, toys, and other fields.

[0003] In related technologies, a light-emitting diode includes a substrate, an epitaxial layer, and pads. The epitaxial layer is located on the surface of the substrate, and the pads are located on the surface of the epitaxial layer away from the substrate.

[0004] However, the miniaturization of LEDs has led to mass production, resulting in smaller LED pads. During die bonding, the pads need to be fixed to the circuit board via reflow soldering. Due to the small size of the pads, the connection area between the pads and the circuit board after soldering is small, making the connection between the LED and the circuit board unstable. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) with improved welding reliability and its fabrication method, which can improve the welding stability of the LED pads and circuit board after soldering. The technical solution is as follows:

[0006] On one hand, this disclosure provides a light-emitting diode (LED) comprising: a substrate, an epitaxial layer, a passivation layer, and a metal interconnect layer. The epitaxial layer and the metal interconnect layer are both located on the surface of the substrate. The metal interconnect layer is arranged at intervals from the epitaxial layer and is distributed along the peripheral edge of the epitaxial layer. The passivation layer is located on the surface of the epitaxial layer away from the substrate, on the sidewall of the epitaxial layer, in the gap between the metal interconnect layer and the epitaxial layer, and on the surface of the metal interconnect layer away from the substrate. The passivation layer exposes the sidewall of the metal interconnect layer.

[0007] Optionally, the metal interconnect layer is strip-shaped and surrounds the epitaxial layer; or, the metal interconnect layer includes a plurality of metal blocks, which are spaced apart along the peripheral edge of the epitaxial layer.

[0008] Optionally, the orthographic projection of the metal block onto the substrate is a polygon, a circle, or an ellipse.

[0009] Optionally, the light-emitting diode further includes: a first pad and a second pad, the first pad and the second pad being arranged at intervals on the surface of the passivation layer away from the substrate, and the first pad and the second pad being electrically connected to semiconductor layers of different conductivity types of the epitaxial layer through vias; the metal interconnect layer includes a first portion and a second portion, the first portion surrounding at least a portion of the first pad, and the second portion surrounding at least a portion of the second pad, and both the first portion and the second portion being located outside the gap region between the first pad and the second pad in a direction parallel to the surface of the substrate.

[0010] Optionally, the width of the metal bonding layer is 2 μm to 10 μm.

[0011] Optionally, the metal interconnect layer comprises multiple layers of metal layers stacked sequentially, including a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

[0012] Optionally, the thickness of the metal layer is from 0.1 μm to 3 μm.

[0013] Optionally, the distance between the metal interconnect layer and the epitaxial layer is greater than or equal to 2 μm.

[0014] Optionally, the cross-section of the metal connection layer is a trapezoid, and the angle between the sidewall of the metal connection layer and the surface of the metal connection layer near the substrate is 10° to 50°.

[0015] On the other hand, embodiments of this disclosure also provide a method for fabricating a light-emitting diode, the method comprising: providing a substrate; forming an epitaxial layer and a metal interconnect layer on the substrate, the metal interconnect layer being spaced apart from the epitaxial layer and the metal interconnect layer being distributed along the peripheral edge of the epitaxial layer; forming a passivation layer, the passivation layer being located on the surface of the epitaxial layer away from the substrate, the sidewall of the epitaxial layer, the gap between the metal interconnect layer and the epitaxial layer, and the surface of the metal interconnect layer away from the substrate, the passivation layer exposing the sidewall of the metal interconnect layer.

[0016] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0017] The light-emitting diode (LED) provided in this embodiment has an epitaxial layer and a metal interconnect layer disposed on the surface of a substrate. The metal interconnect layer and the epitaxial layer are co-layered and spaced apart, meaning they are insulated from each other. The metal interconnect layer is distributed along the peripheral edge of the epitaxial layer to prevent electrical connection between the metal interconnect layer and other film layers in the LED, thus avoiding leakage and short circuits. A passivation layer covers the gap between the epitaxial layer, the metal interconnect layer, and the surface of the metal interconnect layer away from the substrate. Furthermore, the passivation layer exposes the sidewalls of the metal interconnect layer. This allows the LED to be fixed to a circuit board not only by soldering pads but also by the metal interconnect layer located at the peripheral edge of the epitaxial layer. This increases the soldering area between the LED and the circuit board, making the connection between the LED and the circuit board more reliable. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0020] Figure 2 This is a top view of a light-emitting diode provided in an embodiment of this disclosure;

[0021] Figure 3 This is a top view of a light-emitting diode provided in an embodiment of this disclosure;

[0022] Figure 4 This is a top view of a light-emitting diode provided in an embodiment of this disclosure;

[0023] Figure 5 This is a top view of a light-emitting diode provided in an embodiment of this disclosure;

[0024] Figure 6 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure.

[0025] The markings in the diagram are explained as follows:

[0026] 10. Substrate;

[0027] 20. Epitaxial layer; 21. First semiconductor layer; 22. Multiple quantum well layer; 23. Second semiconductor layer;

[0028] 30. Passivation layer;

[0029] 40. Metal bonding layer; 41. Metal block; 401. First part; 402. Second part;

[0030] 51. First pad; 52. Second pad;

[0031] 61. Current blocking layer; 62. Transparent conductive layer;

[0032] 71. First electrode; 72. Second electrode. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0034] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0035] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. For example... Figure 1 As shown, the light-emitting diode includes: a substrate 10, an epitaxial layer 20, a passivation layer 30 and a metal interconnect layer 40. The epitaxial layer 20 and the metal interconnect layer 40 are both located on the surface of the substrate 10, and the metal interconnect layer 40 and the epitaxial layer 20 are arranged at intervals.

[0036] Figure 2 This is a top view of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 As shown, the metal interconnect layer 40 is distributed along the peripheral edge of the epitaxial layer 20.

[0037] like Figure 1As shown, the passivation layer 30 is located on the surface of the epitaxial layer 20 away from the substrate 10, the sidewall of the epitaxial layer 20, the gap between the metal interconnect layer 40 and the epitaxial layer 20, and on the surface of the metal interconnect layer 40 away from the substrate 10, with the passivation layer 30 exposed on the sidewall of the metal interconnect layer 40.

[0038] The light-emitting diode provided in this embodiment has an epitaxial layer 20 and a metal interconnect layer 40 disposed on the surface of a substrate 10. The metal interconnect layer 40 and the epitaxial layer 20 are co-layered and spaced apart, meaning the metal interconnect layer 40 and the epitaxial layer 20 are insulated from each other. The metal interconnect layer 40 is distributed along the peripheral edge of the epitaxial layer 20 to prevent electrical connection between the metal interconnect layer 40 and other film structures in the light-emitting diode, thus avoiding leakage and short circuit problems. A passivation layer 30 covers the epitaxial layer 20, the gap between the metal interconnect layer 40 and the surface of the metal interconnect layer 40 away from the substrate 10. Furthermore, the passivation layer 30 exposes the sidewall of the metal interconnect layer 40, which means that when the light-emitting diode is soldered to the circuit board, in addition to being fixed to the circuit board by the solder pads, the light-emitting diode can also be fixed to the circuit board by the metal interconnect layer 40 located at the peripheral edge of the epitaxial layer 20. This increases the soldering area between the light-emitting diode and the circuit board, thereby making the connection between the light-emitting diode and the circuit board more reliable.

[0039] Optionally, such as Figure 2 As shown, the metal interconnect layer 40 includes a plurality of metal blocks 41, which are arranged at intervals along the peripheral edge of the epitaxial layer 20.

[0040] By setting the metal connection layer 40 as multiple metal blocks 41, the amount of metal material placed at the peripheral edge of the epitaxial layer 20 can be reduced, thereby reducing the possibility of leakage short circuit.

[0041] Optionally, the orthographic projection of the metal block 41 onto the substrate 10 is a polygon, a circle, or an ellipse.

[0042] For example, such as Figure 2 As shown, the metal block 41 can be a rectangular block. The spacing between adjacent metal blocks 41 can be less than or equal to one-tenth of the side length of the epitaxial layer 20 in the longitudinal direction.

[0043] For example, such as Figure 3 As shown, metal block 41 can be a rhombus-shaped block.

[0044] For example, such as Figure 4 As shown, metal block 41 can be an elliptical block.

[0045] Optionally, such as Figure 5 As shown, the metal interconnect layer 40 is strip-shaped and surrounds the epitaxial layer 20.

[0046] By setting the metal interconnect layer 40 as an elongated structure, more sidewalls of the metal interconnect layer 40 are exposed, which allows the metal interconnect layer 40 to have a larger area to be soldered and fixed to the circuit board, thereby improving the connection reliability between the light-emitting diode and the circuit board.

[0047] In this embodiment of the disclosure, the epitaxial layer 20 may include a first semiconductor layer 21, a multiple quantum well layer 22, and a second semiconductor layer 23 stacked sequentially.

[0048] Optionally, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0049] For example, the first semiconductor layer 21 is an n-type layer and the second semiconductor layer 23 is a p-type layer.

[0050] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0051] Optionally, the multi-quantum-well layer 22 includes alternating InGaN quantum-well layers and GaN quantum-barrier layers. Specifically, the multi-quantum-well layer 22 may include 3 to 8 alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0052] As an example, in an embodiment of this disclosure, the multi-quantum-well layer 22 includes five alternating periods of InGaN quantum-well layers and GaN quantum-barrier layers.

[0053] Optionally, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0054] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0055] Optionally, the surface of the second semiconductor layer 23 has a groove that exposes the first semiconductor layer 21.

[0056] Optionally, such as Figure 1 As shown, the light-emitting diode also includes a first pad 51 and a second pad 52, which are arranged at intervals on the surface of the passivation layer 30 away from the substrate 10.

[0057] The first pad 51 and the second pad 52 are electrically connected to semiconductor layers of different conductivity types in the epitaxial layer 20 through vias.

[0058] For example, the first pad 51 extends into the groove through a through-hole and is connected to the first semiconductor layer 21, and the second pad 52 is connected to the second semiconductor layer 23 through a through-hole.

[0059] like Figure 2 As shown, the metal interconnect layer 40 includes a first portion 401 and a second portion 402, the first portion 401 surrounding at least a portion of the first pad 51, and the second portion 402 surrounding at least a portion of the second pad 52.

[0060] For example, such as Figure 2 As shown, the first pad 51 is a rectangular block, and the first part 401 surrounds the three side walls of the first pad 51, that is, the first part 401 is distributed in the 270-degree surrounding area of ​​the first pad 51.

[0061] For example, such as Figure 2 As shown, the second pad 52 is a rectangular block, and the second part 402 surrounds the three sidewalls of the second pad 52, that is, the second part 402 is distributed in the 270-degree surrounding area of ​​the second pad 52.

[0062] In the direction parallel to the surface of the substrate 10, both the first portion 401 and the second portion 402 are located outside the gap region between the first pad 51 and the second pad 52.

[0063] In this embodiment, the first portion 401 does not extend beyond the opposite sidewalls of the first pad 51 and the second pad 52, and the second portion 402 also does not extend beyond the opposite sidewalls of the second pad 52 and the first pad 51. This prevents the metal interconnect layer 40 from being distributed between the first pad 51 and the second pad 52, avoiding the problem of the metal interconnect layer 40 overlapping the first pad 51 and the second pad 52 after soldering, thus preventing a short circuit between the first pad 51 and the second pad 52.

[0064] Optionally, such as Figure 2 As shown, the width of the metal interconnect layer 40 is 2 μm to 10 μm.

[0065] In this embodiment of the disclosure, the width of the metal interconnect layer 40 refers to the shortest length of the metal interconnect layer 40 in the direction parallel to the substrate 10.

[0066] By setting the width of the metal interconnect layer 40 within the above-mentioned range, it is possible to avoid the metal interconnect layer 40 being too wide, which would result in the gap between the metal interconnect layer 40 and the epitaxial layer 20 being too small, thus hindering the achievement of the insulation purpose between the metal interconnect layer 40 and the epitaxial layer 20.

[0067] For example, the width of the metal interconnect layer 40 is 5 μm.

[0068] Optionally, the metal interconnect layer 40 includes multiple layers of metal layers stacked sequentially, including a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

[0069] Specifically, the presence of Ti metal in the metal bonding layer 40 can improve the strength of the metal bonding layer 40; the presence of Al and Pt metals in the metal bonding layer 40 can improve the corrosion resistance of the metal bonding layer 40; the presence of Ni metal in the metal bonding layer 40 can increase the melting point of the metal bonding layer 40; and the presence of Au metal in the metal bonding layer 40 can make the metal bonding layer 40 more resistant to erosion.

[0070] For example, the metal interconnect layer 40 includes a Ti layer, an Al layer, a Pt layer, a Ni layer and an Au layer stacked sequentially.

[0071] Optionally, the thickness of the metal layer is from 0.1 μm to 3 μm.

[0072] For example, the thickness of the Ti layer is 2 μm; the thickness of the Al layer is 1 μm; the thickness of the Pt layer is 0.5 μm; the thickness of the Ni layer is 1.2 μm; and the thickness of the Au layer is 1.5 μm.

[0073] Optionally, the spacing between the metal interconnect layer 40 and the epitaxial layer 20 is greater than or equal to 2 μm.

[0074] By setting the spacing between the metal interconnect layer 40 and the epitaxial layer 20 within the aforementioned range, the metal interconnect layer 40 is prevented from being too close to the epitaxial layer 20, thereby increasing the risk of short circuit between the metal interconnect layer 40 and the epitaxial layer 20 and improving the reliability of the light-emitting diode.

[0075] For example, the distance between the metal interconnect layer 40 and the epitaxial layer 20 is 1 μm.

[0076] Optionally, the cross-section of the metal interconnect layer 40 is a trapezoid, and the angle between the sidewall of the metal interconnect layer 40 and the surface of the metal interconnect layer 40 near the substrate 10 is 10° to 50°.

[0077] The cross-section of the metal interconnect layer 40 refers to the cross-section perpendicular to the direction of the substrate 10.

[0078] By setting the cross-section of the metal interconnect layer 40 to a regular trapezoid and controlling the angle between the sidewall of the metal interconnect layer 40 and the surface of the metal interconnect layer 40 near the substrate 10 within the above range, the passivation layer 30 can be more easily covered on the metal interconnect layer 40. Furthermore, since the sidewall of the metal interconnect layer 40 is inclined, the passivation layer 30 covered on it is not easily scratched, thus preventing the passivation layer 30 from easily breaking.

[0079] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has high light transmittance, meaning it is a transparent substrate 10. Furthermore, sapphire material is relatively hard and has relatively stable chemical properties, giving the light-emitting diode good luminous effect and stability.

[0080] Optionally, such as Figure 1 As shown, the light-emitting diode further includes: a current blocking layer 61, a transparent conductive layer 62, a first electrode 71, and a second electrode 72. The current blocking layer 61 is located on the surface of the second semiconductor layer 23 of the epitaxial layer 20 away from the substrate 10, and the transparent conductive layer 62 is located on the surface of the second semiconductor layer 23 away from the substrate 10 and covers the current blocking layer 61.

[0081] like Figure 1 As shown, the second electrode 72 is located on the surface of the transparent conductive layer 62 and above the current blocking layer 61. This arrangement of the current blocking layer 61 below the second electrode 72 prevents current from being transmitted vertically downwards to the epitaxial layer 20, instead allowing the current to extend transversely through the transparent conductive layer 62 to various regions of the second semiconductor layer 23.

[0082] like Figure 1 As shown, the first electrode 71 is located in the groove and is electrically connected to the first semiconductor layer 21.

[0083] For example, the current blocking layer 61 may be a silicon oxide layer. Silicon oxide has good insulation properties and can effectively block the current in the second electrode 72 from being transmitted vertically downward to the epitaxial layer 20.

[0084] For example, the transparent conductive layer 62 can be an indium tin oxide (ITO) layer. Indium tin oxide layers have good transmittance and low resistivity. Using an indium tin oxide layer as the transparent conductive layer 62 allows more light to be transmitted from the transparent conductive layer 62, thus ensuring the light emission effect. At the same time, due to its low resistivity, it also facilitates carrier conduction and improves injection efficiency.

[0085] For example, the transparent conductive layer 62 can be an indium zinc oxide (IZO) layer. Indium zinc oxide layers have good transmittance and low resistivity. Using an indium zinc oxide layer as the transparent conductive layer 62 allows more light to be transmitted through it, thus ensuring good light emission. Simultaneously, due to its low resistivity, it also facilitates carrier conduction, improving injection efficiency.

[0086] As an example, the thickness of the transparent conductive layer 62 can be from 1,000 angstroms to 5,000 angstroms. For example, the thickness of the transparent conductive layer 62 is 2,000 angstroms.

[0087] Optionally, such as Figure 1 As shown, the passivation layer 30 is located on the surface of the second semiconductor layer 23 and covers the second electrode 72. The passivation layer 30 is also located in the groove and covers the first electrode 71.

[0088] The passivation layer 30 also has through holes that expose the first electrode 71 and the second electrode 72, respectively. The first pad 51 and the second pad 52 are located on the surface of the passivation layer 30 and are electrically connected to the first electrode 71 and the second electrode 72 through the through holes, respectively.

[0089] For example, the passivation layer 30 can be a distributed Bragg reflection (DBR layer), which includes multiple periodically alternating layers of SiO2 and TiO2. The number of periods in the DBR layer can be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0090] The thickness of the SiO2 layer in the DBR layer can be from 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer can be from 500 angstroms to 900 angstroms.

[0091] In addition to its passivation function, the DBR layer also reflects light emitted from the multi-quantum well layer 22 toward the DBR layer back to the substrate 10, thereby improving the light extraction effect.

[0092] Figure 6 This is a flowchart illustrating a method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. This method is used to fabricate... Figures 1 to 5 The light-emitting diode shown. For example... Figure 6 As shown, the preparation method includes:

[0093] S11: Provide a substrate.

[0094] S12: An epitaxial layer and a metal interconnect layer are formed on the substrate.

[0095] The metal bonding layer and the epitaxial layer are arranged alternately, with the metal bonding layer distributed along the peripheral edge of the epitaxial layer.

[0096] S13: Formation of a passivation layer.

[0097] The passivation layer is located on the surface of the epitaxial layer away from the substrate, the sidewall of the epitaxial layer, the gap between the metal interconnect layer and the epitaxial layer, and on the surface of the metal interconnect layer away from the substrate, with the passivation layer exposed on the sidewall of the metal interconnect layer.

[0098] The light-emitting diode (LED) fabricated using this method has an epitaxial layer and a metal interconnect layer disposed on the surface of a substrate. The metal interconnect layer and the epitaxial layer are co-layered and spaced apart, meaning they are insulated from each other. The metal interconnect layer is distributed along the peripheral edge of the epitaxial layer to prevent electrical connections between the metal interconnect layer and other film layers in the LED, thus avoiding leakage and short circuits. A passivation layer covers the gaps between the epitaxial layer, the metal interconnect layer, and the surface of the metal interconnect layer away from the substrate. Furthermore, the passivation layer exposes the sidewalls of the metal interconnect layer. This allows the LED to be fixed to the circuit board not only via solder pads but also via the metal interconnect layer located at the peripheral edge of the epitaxial layer. This increases the soldering area between the LED and the circuit board, resulting in a more reliable connection.

[0099] In step S11, the substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0100] As an example, in this embodiment of the disclosure, the substrate is a sapphire substrate. Sapphire substrates are a commonly used substrate, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a flat sapphire substrate.

[0101] The sapphire substrate can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. As an example, in this embodiment, the sapphire substrate is baked for 15 minutes.

[0102] Specifically, the baking temperature can be from 1000℃ to 1200℃, and the pressure inside the MOCVD reaction chamber during baking can be from 100mbar to 200mbar.

[0103] Step S12, growing an epitaxial layer on the substrate, may include: sequentially forming a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer on a sapphire substrate using MOCVD technology.

[0104] For example, the epitaxial layer includes an n-type GaN layer, a multiple quantum well layer and an n-type GaN layer stacked sequentially.

[0105] Optionally, the thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0106] The growth temperature of the n-type GaN layer can be from 1000℃ to 1100℃, and the growth pressure of the n-type GaN layer can be from 100 torr to 300 torr.

[0107] Optionally, the multi-quantum-well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0108] When growing multiple quantum well layers, the MOCVD reaction chamber pressure is controlled at 200 torr. When growing InGaN quantum well layers, the reaction chamber temperature is 760℃ to 780℃. When growing GaN quantum barrier layers, the reaction chamber temperature is 860℃ to 890℃.

[0109] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0110] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0111] Optionally, the thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0112] When growing p-type GaN layers, the growth pressure of p-type GaN layers can be from 200 Torr to 600 Torr, and the growth temperature of p-type GaN layers can be from 800℃ to 1000℃.

[0113] The epitaxial layer growth in step S13 may also include: etching the epitaxial layer to form a groove on the surface of the second semiconductor layer away from the substrate.

[0114] The etched grooves can be achieved through dry etching, or by using photolithography combined with wet etching, such as etching with a mixed solution of H3PO4 / H2SO4, or by using laser front scribing.

[0115] Optionally, the surface of the second semiconductor layer away from the substrate also has a groove exposing the first semiconductor layer, the groove being used to form a first electrode connected to the first semiconductor layer.

[0116] Before fabricating the metal interconnect layer, the process further includes: forming a current blocking layer on the surface of the second semiconductor layer; and forming a transparent conductive layer on the surface of the second semiconductor layer and the surface of the current blocking layer.

[0117] For example, the transparent conductive layer is an indium tin oxide layer or an indium zinc oxide layer.

[0118] For example, the thickness of the transparent conductive layer can be from 1,000 angstroms to 5,000 angstroms. For instance, the thickness of the transparent conductive layer is 2,000 angstroms.

[0119] In this embodiment of the disclosure, the metal interconnect layer may include two fabrication methods:

[0120] In the first preparation method, the metal interconnect layer can be prepared together with the first electrode and the second electrode. That is, the metal interconnect layer, the first electrode, and the second electrode are prepared in a single patterning process.

[0121] In the second preparation method, the metal interconnect layer can be prepared before or after the electrode preparation is completed. That is, the electrode and the metal interconnect layer are prepared using two patterning processes.

[0122] Taking the first fabrication method as an example, the fabrication process may include: fabricating a first electrode within a groove, connecting the first electrode to a first semiconductor layer; fabricating a second electrode on the surface of a transparent conductive layer, connecting the second electrode to the transparent conductive layer; and fabricating a metal interconnect layer on the surface of a substrate, controlling the spacing between the metal interconnect layer and the epitaxial layer, and distributing the metal interconnect layer along the peripheral edge of the epitaxial layer.

[0123] Step S13 may include forming a passivation layer on the surface of the second semiconductor layer, the surface of the transparent conductive layer, the surface of the first electrode, the surface of the second electrode, and within the groove.

[0124] The passivation layer can be a DBR layer, which comprises multiple periodically alternating layers of SiO2 and TiO2. The number of periods in the DBR layer can be between 20 and 50. For example, the number of periods in a DBR layer is 32.

[0125] The thickness of the SiO2 layer in the DBR layer can be from 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer can be from 500 angstroms to 900 angstroms.

[0126] After the passivation layer is formed, two through holes need to be etched on the surface of the passivation layer.

[0127] One through hole exposes the first electrode, and the other through hole exposes the second electrode.

[0128] After etching two vias on the passivation layer, the fabrication method further includes: fabricating a first pad and a second pad on the surface of the passivation layer.

[0129] The first pad is connected to the first electrode through a through hole, and the second pad is connected to the second electrode through another through hole.

[0130] For example, both the first pad and the second pad can be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer and an Au layer stacked sequentially.

[0131] In this embodiment of the disclosure, after fabricating the pads, the preparation method may further include: fabricating a protective layer on the surface of the passivation layer.

[0132] For example, in this embodiment of the disclosure, the protective layer may be a silicon oxide layer with a thickness of 2000 angstroms.

[0133] It should be noted that after a protective layer is grown on the surface of the passivation layer, photolithography can be used to etch through-holes that expose the pads on the surface of the protective layer to facilitate electrical connection.

[0134] Finally, the sapphire substrate can be stealth-cut and scratched, which can effectively reduce brightness loss. Then, the light-emitting diode is obtained through testing.

[0135] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes: a substrate (10), an epitaxial layer (20), a passivation layer (30), and a metal interconnect layer (40). The epitaxial layer (20) and the metal interconnect layer (40) are both located on the surface of the substrate (10). The metal interconnect layer (40) is arranged at intervals from the epitaxial layer (20). The metal interconnect layer (40) is distributed along the peripheral edge of the epitaxial layer (20). The passivation layer (30) is located on the surface of the epitaxial layer (20) away from the substrate (10), the sidewall of the epitaxial layer (20), the gap between the metal interconnect layer (40) and the epitaxial layer (20), and on the surface of the metal interconnect layer (40) away from the substrate (10), with the passivation layer (30) exposing the sidewall of the metal interconnect layer (40).

2. The light-emitting diode according to claim 1, characterized in that, The metal interconnect layer (40) is strip-shaped and surrounds the epitaxial layer (20); or, The metal bonding layer (40) includes a plurality of metal blocks (41), which are arranged at intervals along the peripheral edge of the epitaxial layer (20).

3. The light-emitting diode according to claim 2, characterized in that, The orthographic projection of the metal block (41) onto the substrate (10) is a polygon, a circle, or an ellipse.

4. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The light-emitting diode further includes a first pad (51) and a second pad (52), the first pad (51) and the second pad (52) being arranged at intervals on the surface of the passivation layer (30) away from the substrate (10), and the first pad (51) and the second pad (52) being electrically connected to semiconductor layers of different conductivity types of the epitaxial layer (20) through vias respectively. The metal interconnect layer (40) includes a first portion (401) and a second portion (402), the first portion (401) surrounding at least a portion of the first pad (51), and the second portion (402) surrounding at least a portion of the second pad (52). In a direction parallel to the surface of the substrate (10), both the first portion (401) and the second portion (402) are located outside the gap region between the first pad (51) and the second pad (52).

5. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The width of the metal bonding layer (40) is 2 μm to 10 μm.

6. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The metal interconnect layer (40) comprises multiple layers of metal layers stacked sequentially, including a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

7. The light-emitting diode according to claim 6, characterized in that, The thickness of the metal layer is from 0.1 μm to 3 μm.

8. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The distance between the metal interconnect layer (40) and the epitaxial layer (20) is greater than or equal to 2 μm.

9. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The cross-section of the metal connection layer (40) is a trapezoid, and the angle between the sidewall of the metal connection layer (40) and the surface of the metal connection layer (40) near the substrate (10) is 10° to 50°.

10. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: Provide a substrate; An epitaxial layer and a metal interconnect layer are formed on the substrate, wherein the metal interconnect layer is arranged at intervals from the epitaxial layer and is distributed along the peripheral edge of the epitaxial layer; A passivation layer is formed on the surface of the epitaxial layer away from the substrate, the sidewall of the epitaxial layer, the gap between the metal interconnect layer and the epitaxial layer, and the surface of the metal interconnect layer away from the substrate, wherein the passivation layer exposes the sidewall of the metal interconnect layer.

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