Capacitive load testing system, method, electronic device, storage medium and product

Abstract

The embodiment of the present invention provides a capacitive load test system, method, electronic device, storage medium and product, which relate to the field of computer technology. It includes a target test board and a board to be tested, the board to be tested includes a circuit protection element to be tested, the target test board includes a first load unit and a control unit, and the target test board and the board to be tested are connected; the first load unit is used to connect the target capacitive load to the circuit protection element to be tested; the control unit is used to connect the first load units one by one to the circuit protection element to be tested when it is determined that the power signal of the circuit protection element to be tested is normal, monitor the first power signal of the circuit protection element to be tested, record the target number of the first load units connected when the situation is normal, and determine the maximum capacitive load of the circuit protection element to be tested in the board to be tested according to the fixed-size target capacitive load and the target number. This embodiment improves the efficiency, accuracy and coverage of the test.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a capacitive load testing system, method, electronic equipment, storage medium and product. Background Art

[0002] As server performance continues to improve, power supply requirements are also increasing. In order to improve the safety and reliability of server power supply, EFuse (Electrically Programmable Fuse) design is added during the board design stage to protect the key core components of the server. EFuse mainly plays the role of switch and protection. When the power supply is working normally, EFuse is turned on to ensure the normal power supply demand of the back-end load; when the power supply is overcurrent and short-circuited, EFuse cuts off the circuit in time to achieve the protection function. It should be noted that the key core components in the server are usually the loads of EFuse, and these components will be designed with more capacitors to improve dynamic performance. In actual application, when the board is powered on, the EFuse enable is set high, and the metal oxide semiconductor field effect transistor inside the EFuse is instantly turned on. Due to the high capacitive load C of the component itself and I=C*ΔV / Δt, Inrush current is caused, which will trigger EFuse to start overcurrent protection, EFuse is turned off, and the board cannot be powered on normally.

[0003] In order to solve this problem, the EFuse capacitive load test is currently performed in advance to determine whether there is a problem with the EFuse design. The steps include: soldering a capacitor of the same capacitance value on the breadboard according to the capacitance design value of the adapter component itself, and then soldering the panel to the output end of the EFuse to be tested, and using an oscilloscope to measure the input and output voltage and current value of the EFuse. Power on the EFuse. If the input and output of the EFuse are normal, it proves that the design is feasible, and the design margin is determined based on the current value. If the EFuse has no output, the board failed to power on normally.

[0004] However, in the above method, since a server is equipped with many components and the same component needs to be adapted to multiple models, an EFuse design needs to be tested multiple times. In addition, during the capacitive load test, breadboard welding, board welding and oscilloscope waveform capture are required, resulting in a large waste of manpower and material resources and low test efficiency. In addition, operations such as breadboard welding, board welding and oscilloscope waveform capture all need to be performed manually, resulting in inaccurate test results. In addition, during the design and use of the server, changes in requirements will require the adaptation of some new components, and previous test results cannot evaluate their feasibility, resulting in low test result coverage. Summary of the invention

[0005] The embodiments of the present invention provide a capacitive load test system, method, electronic device, storage medium and product to solve the problems of low test efficiency, inaccurate test results and low test result coverage when performing capacitive load test on EFuse design. The specific technical solutions are as follows:

[0006] A first aspect of an embodiment of the present invention provides a capacitive load testing system, comprising a target test board and a board to be tested on a server, wherein the board to be tested comprises a circuit protection element to be tested; the target test board comprises a plurality of first load units and a control unit, the target test board is connected to the board to be tested, and the plurality of first load units are connected to the control unit;

[0007] The first load unit is used to connect target capacitive loads of different sizes to the circuit protection element to be tested;

[0008] The control unit is used to connect the first load units to the circuit protection element to be tested one by one when it is determined that the power signal of the circuit protection element to be tested is normal, monitor the first power signal of the circuit protection element to be tested after the first load units are connected to the circuit protection element to be tested, record the target number of the first load units connected when the first power signal is normal, and determine the maximum capacitive load that the circuit protection element to be tested in the board to be tested based on the fixed-size target capacitive load and the target number.

[0009] Optionally, the board to be tested also includes a test interface unit;

[0010] The target test board also includes a first interface unit and a display unit, wherein the first interface unit is connected to a plurality of first load units, the control unit is connected to the display unit, and the display unit is used to display the maximum capacitive load of the circuit protection element to be tested; the target test board is connected to the board to be tested through the first interface unit and the test interface unit;

[0011] The first interface unit includes a first power supply connector and a first signal connector;

[0012] The first load unit includes a switching circuit, a discharge circuit and a switch circuit, wherein the switch circuit is composed of a first circuit protection element, the switching circuit is composed of an electromagnetic relay and a target capacitive load of a fixed size, and the discharge circuit is composed of a target discharge resistor and a target semiconductor device;

[0013] The control unit includes a target integrated circuit;

[0014] The display unit includes light emitting diode indicator lights having the same number as the first load unit;

[0015] The test interface unit includes a second power supply connector and a second signal connector.

[0016] Optionally, establishing a connection between the target test board and the board to be tested through the first interface unit and the test interface unit includes:

[0017] Connecting the target power supply to the board to be tested through the second power supply connector;

[0018] Establishing a first connection between the first power supply connector and the second power supply connector;

[0019] The target power supply provides power to the target test board via the first connection;

[0020] Establishing a second connection through the first signal connector and the second signal connector;

[0021] The control unit monitors various signals of the target test board and the board to be tested through the second connection.

[0022] A second aspect of an embodiment of the present invention provides a capacitive load testing method, the method comprising:

[0023] When it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first load units of the target test board are connected to the circuit protection element to be tested one by one, wherein the first load units include a target capacitive load of a fixed size;

[0024] Monitoring, by a control unit of a target test board, a first power supply signal of the circuit protection element to be tested after the first load unit is connected to the circuit protection element to be tested;

[0025] When the control unit records the first power signal as normal, the target number of the first load units connected;

[0026] The maximum capacitive load that the circuit protection element to be tested in the board to be tested can withstand is determined according to the fixed-size target capacitive load and the target quantity.

[0027] Optionally, when it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first load units of the target test board are connected one by one to the circuit protection element to be tested, including:

[0028] Controlling the board to be tested to be powered on, and detecting the target power signal logic state of the circuit protection element to be tested in the board to be tested;

[0029] If the target power signal logic state is at a low level, it is determined that the power signal of the circuit protection element to be tested in the board to be tested is abnormal, and the light emitting diode indicator in the board to be tested is controlled to light up red to issue an early warning;

[0030] If the logic state of the first power signal is high, it is determined that the power signal of the circuit protection element to be tested in the board to be tested is normal, and several of the first load units of the target test board are connected to the board to be tested one by one.

[0031] Optionally, when it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first load units of the target test board are connected one by one to the circuit protection element to be tested, further comprising:

[0032] When it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first enable signal of the circuit protection element to be tested is controlled to be low level through the first control signal to ensure that the test environment is consistent with the actual application environment, wherein the circuit protection element is correspondingly turned off when the enable signal is low level, and the circuit protection element is correspondingly turned on when the enable signal is high level;

[0033] After waiting for a first preset time, randomly selecting a second load unit from the first load units of the target test board;

[0034] adjusting a second enable signal of the first circuit protection element in the second load unit to a high level;

[0035] By means of the high-level second enable signal, the electromagnetic relay in the second load unit is controlled to enter a target state, and the coil in the electromagnetic relay in the target state generates magnetism to attract the armature;

[0036] A target capacitive load of a fixed size in the second load unit is connected to the circuit protection element to be tested through the electromagnetic relay in the target state.

[0037] Optionally, after connecting the target capacitive load of a fixed size in the second load unit to the circuit protection element to be tested through the electromagnetic relay in the target state, the method further includes:

[0038] After waiting for a second preset time, adjusting the first enable signal of the circuit protection element to be tested to a high level;

[0039] Charging a target capacitive load of a fixed size in the second load unit through the circuit protection element to be tested which is at a high level, so that the target capacitive load of the fixed size is connected to the circuit protection element to be tested;

[0040] After determining that charging is completed, monitoring the first power signal of the circuit protection element to be tested.

[0041] Optionally, after monitoring the logic state of the second power supply signal of the circuit protection element to be tested, the method further includes:

[0042] If the first power signal of the circuit protection element to be tested is normal, the count in the control target register is increased by 1;

[0043] Control the first enable signal of the circuit protection element to be tested and the second enable signal of the first circuit protection element in the second load unit to be low level through the second control signal, and trigger the first semiconductor device in the second load unit to be turned on;

[0044] Through the turned-on first semiconductor device, the first discharge resistor is controlled to be connected to both ends of a target capacitive load of a fixed size for discharge, so that the current target capacitive load will not affect the next capacitive load test.

[0045] Optionally, when it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first load units of the target test board are connected one by one to the circuit protection element to be tested, further comprising:

[0046] After waiting for a third preset time, detecting whether the target capacitive load of the fixed size has been discharged;

[0047] If completed, continue to detect the second power supply signal of the circuit protection element to be tested;

[0048] When it is determined that the second power supply signal of the circuit protection element to be tested of the board to be tested on the server is normal, selecting second load units of increasing number from the first load units of the target test board and connecting them to the circuit protection element to be tested;

[0049] When it is determined that the second power signal of the circuit protection element to be tested is abnormal, the second load unit screening from the first load unit of the target test board is stopped.

[0050] Optionally, determining the maximum capacitive load of the circuit protection element to be tested in the board to be tested according to the fixed-size target capacitive load and the target quantity includes:

[0051] When it is determined that the target number is less than 1, determining that the maximum capacitive load of the circuit protection element to be tested in the board to be tested is less than a target capacitive load of a fixed size;

[0052] When it is determined that the target number is greater than or equal to 1, obtaining a product of the fixed-size target capacitive load and the target number;

[0053] The product is determined as the maximum capacitive load of the circuit protection element to be tested in the board to be tested.

[0054] Optionally, after recording, by the control unit, that the first power signal condition is normal and the target number of the first load units connected, the method further includes:

[0055] When it is determined that the target quantity is less than 1, a light emitting diode indicator light is controlled to flash green;

[0056] When it is determined that the target number is greater than or equal to 1, the light emitting diode indicator light of the target number is controlled to be always on green.

[0057] Optionally, before controlling a light emitting diode indicator to flash green when determining that the target quantity is less than 1, the method further includes:

[0058] In response to a first test input to the LED indicator lights by the user, controlling the plurality of LED indicator lights to flash green;

[0059] In response to a second test input to the LED indicator lights by the user, controlling the plurality of LED indicator lights to be constantly green;

[0060] In response to the user's third test input to the LED indicator lights, several LED indicator lights are controlled to light up in red.

[0061] A third aspect of an embodiment of the present invention provides a capacitive load testing device, the device comprising:

[0062] An access module is used to connect the first load units of the target test board to the circuit protection element to be tested one by one when it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, wherein the first load unit includes a target capacitive load of a fixed size;

[0063] A monitoring module, used for monitoring, through a control unit of a target test board, a first power supply signal of the circuit protection element to be tested after the first load unit is connected to the circuit protection element to be tested;

[0064] a recording module, configured to record, through the control unit, a target number of the first load units connected when the first power signal condition is normal;

[0065] The determination module is used to determine the maximum capacitive load that the circuit protection element to be tested in the board to be tested can withstand according to the target capacitive load of the fixed size and the target quantity.

[0066] A fourth aspect of an embodiment of the present invention provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the steps of the capacitive load testing method as described in the first aspect of the embodiment of the present invention are implemented.

[0067] A fifth aspect of an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the capacitive load testing method described in the first aspect of the embodiment of the present invention are implemented.

[0068] A sixth aspect of an embodiment of the present invention provides a computer program product, comprising a computer program / instructions, which, when executed by a processor, implement the steps of the capacitive load testing method as described in the first aspect of the embodiment of the present invention.

[0069] The embodiment of the present invention provides a capacitive load testing system, comprising a target test board and a board to be tested on a server, wherein the board to be tested comprises a circuit protection element to be tested; the target test board comprises a plurality of first load units and a control unit, the target test board is connected to the board to be tested, and the plurality of first load units are connected to the control unit; the first load units are used to connect target capacitive loads of different sizes to the circuit protection element to be tested, and the control unit is used to connect the first load units one by one to the circuit protection element to be tested when it is determined that the power supply signal of the circuit protection element to be tested is normal, and monitor the first power supply signal of the circuit protection element to be tested after the first load units are connected to the circuit protection element to be tested. When the first power supply signal condition is recorded as normal, the target number of the connected first load units is determined, and the maximum capacitive load of the circuit protection element to be tested in the board to be tested is determined according to the target capacitive load of a fixed size and the target number. In the embodiment of the present invention, a target test board including a plurality of first load units is provided, and the plurality of first load units are connected to the board to be tested one by one to determine the maximum capacitive load of the board to be tested. There is no need for manual welding and waveform capture operations, which greatly improves the test efficiency and accuracy. Moreover, the target test board can test different models of boards to be tested by controlling the number of the connected first load units, thereby improving the coverage of the capacitive load test. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0071] Figure 1 is a schematic diagram of a capacitive load testing system shown in an embodiment of the present invention;

[0072] Figure 2 is a circuit diagram of a target test board in a capacitive load test system shown in one embodiment of the present invention;

[0073] Figure 3 is a flow chart of steps of a capacitive load testing method shown in one embodiment of the present invention;

[0074] Figure 4 yes Figure 3 The flowchart of step 101 in a capacitive load testing method shown in one embodiment of the present invention;

[0075] Figure 5 is a flowchart of another capacitive load testing method according to an embodiment of the present invention;

[0076] Figure 6 is a structural block diagram of a capacitive load testing device provided by an embodiment of the present invention;

[0077] Figure 7 It is a schematic diagram of an electronic device shown in an embodiment of the present invention. DETAILED DESCRIPTION

[0078] To make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined and referenced with each other without contradiction.

[0079] With the rapid development of artificial intelligence, cloud computing and AI (Artificial Intelligence) technology, the design of servers is constantly being updated and optimized to adapt to higher-performance CPUs (Central Processing Units), GPUs (Graphics Processing Units) and high-precision chips. Power supply design is the key and core of server design. It is becoming increasingly important to strengthen the reliability and stability of power supply design. In the board design stage, EFuse design will be added to protect the key core components of the server. However, if the capacitive load of the component itself is too large, it will cause EFuse to be turned off and the board cannot be powered on normally. Therefore, a capacitive load test of EFuse (Electrically Programmable Fuse) is set to predict this problem in advance. The existing capacitive load test method is to solder a capacitor of the same capacitance on a breadboard based on the capacitance design value of the adapter component itself, and then solder the panel to the output end of the EFuse to be tested, power on the EFuse, and detect whether the EFuse input and output are normal, so as to determine whether there is a problem with the EFuse design.

[0080] However, the above settings require breadboard soldering, and different capacitors need to be soldered for different models, and multiple tests need to be performed, which wastes a lot of manpower and material resources and has low test efficiency. Manual soldering may also be affected by different test techniques and affect the test results. In addition, during the design and use of the server, changes in requirements will require the adaptation of some new components. Previous test results cannot evaluate their feasibility, and capacitive load tests need to be added again to verify the feasibility of adapting the changed components, resulting in low test coverage.

[0081] Therefore, the embodiment of the present invention provides a capacitive load testing system, such as Figure 1As shown, it includes a target test board and a board to be tested on a server, wherein the board to be tested includes a circuit protection element to be tested and a test interface unit; the target test board includes a first interface unit, a plurality of first load units, a control unit and a display unit, wherein the first interface unit is connected to the plurality of first load units, the plurality of first load units are connected to the control unit, the control unit is connected to the display unit, the first load unit is used to connect capacitive loads of different sizes to the circuit protection element to be tested, the control unit is used to monitor various signals of the target test board and the board to be tested, and control the first load unit to connect to the circuit protection element to be tested, and the display unit is used to display the maximum capacitive load that the circuit protection element to be tested can withstand; and a connection is established between the target test board and the board to be tested through the first interface unit and the test interface unit. Among them, the first interface unit includes a first power supply connector and a first signal connector; the first load unit includes a switching circuit, a discharge circuit and a switch circuit, the switch circuit is composed of a first circuit protection element, the switching circuit is composed of an electromagnetic relay and a target capacitive load of a fixed size, and the discharge circuit is composed of a target discharge resistor and a target semiconductor device; the control unit includes a target integrated circuit; the display unit includes light-emitting diode indicator lights that are the same in number as the first load unit; the test interface unit includes a second power supply connector and a second signal connector.

[0082] It should be noted that the first power supply connector and the second power supply connector can be an ATX connector designed according to actual current flow, the first signal connector and the second signal connector can be 2X10 sideband connectors, and the power status signal and enable signal of the circuit protection element to be tested (marked as the circuit protection element to be tested) on the board to be tested are all connected to the second signal connector. The working principle of the target test board is mainly to connect the first load units 0-9 to the output end of the board to be tested one by one through the control unit, until the added first load unit makes the circuit protection element to be tested on the board to be tested unable to start normally, thereby obtaining the maximum capacitive load of the circuit protection element to be tested, and informing the tester through the display unit.

[0083] When a connection is established between the target test board and the board to be tested through the first interface unit and the test interface unit, it includes a power supply connection and a signal connection. When the power supply is connected, the target power supply needs to be connected to the board to be tested through the second power supply connector first, and then the first power supply connector and the second power supply connector establish a first connection. At this time, the target power supply provides power to the target test board through the first connection. When the signal is connected, since the power status signal and the enable signal of the circuit protection element to be tested (marked as the circuit protection element to be tested) on the board to be tested are all connected to the second signal connector, after the second connection is established through the first signal connector and the second signal connector, the control unit can obtain the signal status of the circuit protection element to be tested on the board to be tested (such as the power status signal and the enable signal) through the second connection. In addition, since the control unit is connected to the first load unit, the control unit can obtain the signal status in the first load unit.

[0084] Specifically, the circuit diagram of the target test board is as follows Figure 2As shown, the target integrated circuit in the control unit can be a control unit (Complex Programmable Logic Device). The control unit is provided with PG0~9 and EN0~9 pins to obtain the PG signal and EN signal of EFuse0~9 in the first load unit respectively. A register is defined inside the control unit to record the number of groups that have completed the test. The initial register value is zero. Each time the power status signal of the circuit protection element to be tested is detected to be high, the register value is increased by one. When the power status signal of the circuit protection element to be tested is detected to be low, the control unit lights up the indicator light of the display unit according to the register value. The first interface unit includes a 2X6 ATX power supply connector J1 and a 2X10 The sideband signal connector J2, the first interface unit is connected to the test interface unit, so the target power supply (such as P3V3) on the board to be tested is led to the target test board to power the target integrated circuit and the first circuit protection element on the board. The target test board is equipped with 10 first load units, each of which is composed of a switching circuit, a discharge circuit and a switch circuit. Among them, the switching circuit is mainly composed of an electromagnetic relay and a fixed-size target capacitive load (which can be called capacitor C). Therefore, the target test board includes relays 0~9 (K0~9) and capacitors C0~9. Capacitor C is the capacitive load of the EFuse test. The capacitive load value is controlled by adjusting the number of capacitors C connected to the circuit protection element to be tested. The capacitance of each capacitor C is It is 470uF (this value can be adjusted according to the actual design situation). The electromagnetic relay mainly acts as a switch, which can quickly connect or disconnect the capacitor C. The switch circuit is composed of a first circuit protection element. The PG power supply status signal and EN enable signal of the first circuit protection element are connected to the control unit and operated under the control of the control unit. When the switch first circuit protection element is controlled to open, the output end is connected to the electromagnetic relay K. When the current flows through, the coil in the electromagnetic relay will generate magnetism, attract the armature, and instantly connect the capacitor C to the output end of the circuit protection element to be tested. When the switch first circuit protection element is controlled to be closed, the coil in the electromagnetic relay K will not generate magnetism, and the armature rebounds, instantly disconnecting the capacitor C from the output end of the circuit protection element to be tested. Because the first load units 0-9 are connected to the output end of the circuit protection element to be tested of the board to be tested one by one during the test, it is necessary to fully discharge the capacitor C of the previous group before the next group of tests, so that the next group of tests can reach the set maximum capacitive load state.Therefore, a discharge circuit is designed to fully discharge the capacitor C. The discharge circuit is mainly composed of a target discharge resistor R and a target semiconductor device (such as PMOSFET (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor). The gate of the PMOSFET is connected to the output end of the switching circuit EFuse. When a set of tests is completed, the first circuit protection element of the switching circuit is turned off. At this time, Vgs>Vth of the PMOSFET, the PMOSFET is turned on, and the target discharge resistor R is connected to both ends of the capacitor C to discharge the capacitor C. Therefore, the target discharge resistor R0~9 and PMOSFETQ0~9 are set. The display unit is mainly composed of 10 LED indicator lights. The control unit will control the lighting status of the indicator lights to inform the tester of the test results. The specific correspondence between the indicator light status and the test results is shown in Table 1.

[0085] Table 1: Correspondence between indicator light status and test results

[0086]

[0087] The 470uF in Table 1 refers to a fixed-size target capacitive load value, which can be adjusted according to actual conditions and is not specifically limited in the present invention.

[0088] The embodiment of the present invention provides a capacitive load testing system, comprising a target test board and a board to be tested on a server, wherein the board to be tested comprises a circuit protection element to be tested; the target test board comprises a plurality of first load units and a control unit, the target test board is connected to the board to be tested, and the plurality of first load units are connected to the control unit; the first load units are used to connect target capacitive loads of different sizes to the circuit protection element to be tested, and the control unit is used to connect the first load units one by one to the circuit protection element to be tested when it is determined that the power supply signal of the circuit protection element to be tested is normal, and monitor the first power supply signal of the circuit protection element to be tested after the first load units are connected to the circuit protection element to be tested. When the first power supply signal condition is recorded as normal, the target number of the connected first load units is determined, and the maximum capacitive load of the circuit protection element to be tested in the board to be tested is determined according to the target capacitive load of a fixed size and the target number. In the embodiment of the present invention, a target test board including a plurality of first load units is provided, and the plurality of first load units are connected to the board to be tested one by one to determine the maximum capacitive load of the board to be tested. There is no need for manual welding and waveform capture operations, which greatly improves the test efficiency and accuracy. Moreover, the target test board can test different models of boards to be tested by controlling the number of the connected first load units, thereby improving the coverage of the capacitive load test.

[0089] Based on the above configuration, the embodiment of the present invention further provides a capacitive load testing method, referring to Figure 3 , shows a flow chart of the steps of a capacitive load testing method provided by an embodiment of the present invention, the method may include:

[0090] Step 101, when it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first load units of the target test board are connected to the circuit protection element to be tested one by one, and the first load units include a target capacitive load of a fixed size.

[0091] The capacitive load test method of the embodiment of the present invention is applied to a capacitive load test system, which includes a target test board and a board to be tested on a server, the target test board is connected to the board to be tested through a cable, the board to be tested includes a circuit protection element to be tested, the target test board includes a plurality of first load units and a control unit, and the first load unit includes a target capacitive load of a fixed size. Before performing a capacitive load test, it is necessary to first determine whether the circuit protection element to be tested is normal. At this time, the board to be tested will be powered on to ensure that the board is in a working state, and then the target power supply signal logic state of the circuit protection element to be tested in the board to be tested will be detected. If it is a low level, it is considered that the circuit protection element to be tested in the board to be tested is abnormal. At this time, the light emitting diode (LED) indicator in the board to be tested is controlled to light up a red light to warn the operator of an abnormal situation. If it is a high level, it is considered that the circuit protection element to be tested in the board to be tested is normal. Next, the plurality of first load units of the target test board are connected to the board to be tested one by one, and further testing or operation is performed. The specific steps include:

[0092] Controlling the power-on of the board to be tested and detecting the target power signal logic state of the circuit protection element to be tested in the board to be tested;

[0093] If the target power signal logic state is at a low level, it is determined that the power signal of the circuit protection element to be tested in the board to be tested is abnormal, and the light emitting diode indicator in the board to be tested is controlled to light up red to issue an early warning;

[0094] If the first power signal is at a high level, it is determined that the power signal of the circuit protection element to be tested in the board to be tested is normal, and a plurality of the first load units of the target test board are connected to the board to be tested one by one.

[0095] The above steps ensure that after the board is powered on, the abnormal power signal in the circuit protection element to be tested can be discovered and handled in time, and the LED indicator can be used for early warning. At the same time, if the power signal in the circuit protection element to be tested is normal, the system can continue to perform subsequent load tests to ensure the normal operation and performance of the board.

[0096] By determining that the power supply signal of the circuit protection element to be tested is normal, it can be determined that the circuit protection element to be tested is normal. At this time, the first capacitive load test can be performed. Because in normal use, the board to be tested needs to be inserted into the server. At this time, the circuit protection element to be tested of the board to be tested is turned off, so the first enable signal of the circuit protection element to be tested is first pulled low to turn off the circuit protection element to be tested. After waiting for the first preset time, a load unit is selected from the first load unit, and the enable signal corresponding to the first circuit protection element therein is pulled high. The first circuit protection element is turned on, and the coil in the electromagnetic relay will generate magnetism to attract the armature, and instantly connect the target capacitive load of a fixed size to the circuit protection element to be tested.

[0097] Further, step 101, such as Figure 4 As shown:

[0098] Step 1011, when it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first enable signal of the circuit protection element to be tested is controlled to be low level through the first control signal to ensure that the test environment is consistent with the actual application environment, wherein the circuit protection element is correspondingly turned off when the enable signal is low level, and the circuit protection element is correspondingly turned on when the enable signal is high level.

[0099] Step 1012: After waiting for a first preset time, randomly select a second load unit from the first load units of the target test board.

[0100] Step 1013: adjust the second enable signal of the first circuit protection element in the second load unit to a high level.

[0101] Step 1014: Control the electromagnetic relay in the second load unit to enter a target state through a high-level second enable signal. The coil in the electromagnetic relay in the target state generates magnetism to attract the armature.

[0102] Step 1015: Connect a target capacitive load of a fixed size in the second load unit to the circuit protection element to be tested through the electromagnetic relay in the target state.

[0103] The above steps ensure that when the power signal is normal, the system can simulate the actual application environment and test the circuit protection components by randomly selecting the first load unit connected, adjusting the enable signal, controlling the electromagnetic relay, and connecting a fixed-size capacitive load. Such a test process helps to verify the performance and reliability of circuit protection components in actual applications.

[0104] It should be noted that when performing the first capacitive load test, a second load unit is randomly selected from the first load unit of the target test board. When performing the second capacitive load test, two second load units are randomly selected from the first load unit of the target test board. Similarly, when performing the Nth capacitive load test, N second load units (N≥1) are randomly selected from the first load unit of the target test board. Before performing the next set of tests, the target capacitive load connected to the previous set needs to be fully discharged so that the next set of tests can reach the set maximum capacitive load state. The number of capacitive load tests is determined according to the second power supply signal of the circuit protection element to be tested. If the second power supply signal can be a high level, the number of second load units tested can be increased. If it can only be a low level, the test is terminated. The specific steps include:

[0105] After waiting for a third preset time, detecting whether the target capacitive load of the fixed size has been discharged;

[0106] If completed, continue to detect the second power supply signal of the circuit protection element to be tested;

[0107] When it is determined that the second power supply signal of the circuit protection element to be tested of the board to be tested on the server is normal, selecting second load units of increasing number from the first load units of the target test board and connecting them to the circuit protection element to be tested;

[0108] When it is determined that the second power signal of the circuit protection element to be tested is abnormal, the second load unit screening from the first load unit of the target test board is stopped.

[0109] Step 102 : After the first load unit is connected to the circuit protection element to be tested, the control unit of the target test board monitors the first power signal of the circuit protection element to be tested.

[0110] In the embodiment of the present invention, after the first load unit is connected to the circuit protection element to be tested, the second preset time is waited, and the first enable signal of the circuit protection element to be tested is adjusted to a high level, so that the circuit protection element to be tested is turned on, and the target capacitive load is charged. At this time, the first power supply signal of the circuit protection element to be tested is detected. The specific steps include:

[0111] After waiting for a second preset time, adjusting the first enable signal of the circuit protection element to be tested to a high level;

[0112] Charging a target capacitive load of a fixed size in the second load unit through the circuit protection element to be tested which is at a high level, so that the target capacitive load of the fixed size is connected to the circuit protection element to be tested;

[0113] After determining that charging is completed, monitoring the first power signal of the circuit protection element to be tested.

[0114] It should be noted that the first power signal is used to determine whether the target capacitive load connected at this time exceeds the maximum capacitive load of the circuit protection element to be tested. If the first power signal is normal, it indicates that the target capacitive load connected at this time does not exceed the maximum capacitive load of the circuit protection element to be tested. At this time, the target register of the control unit is increased by 1, and the capacitance is continued to be increased for testing. When the next set of tests is performed, the first semiconductor device in the second load unit is discharged to prevent the current target capacitive load from affecting the next capacitive load test. The specific steps include:

[0115] If the first power signal of the circuit protection element to be tested is normal, the count in the control target register is increased by 1;

[0116] Control the first enable signal of the circuit protection element to be tested and the second enable signal of the first circuit protection element in the second load unit to be low level through the second control signal, and trigger the first semiconductor device in the second load unit to be turned on;

[0117] Through the turned-on first semiconductor device, the first discharge resistor is controlled to be connected to both ends of a target capacitive load of a fixed size for discharge, so that the current target capacitive load will not affect the next capacitive load test.

[0118] It should be noted that when the first semiconductor device in the second load unit is triggered to turn on, the specific steps include:

[0119] Presetting a discharge voltage threshold for the first semiconductor device;

[0120] Acquiring a target terminal voltage of the first semiconductor device when determining that the first enable signal of the circuit protection element to be tested and the second enable signal of the first circuit protection element in the second load unit are at a low level;

[0121] comparing the target terminal voltage with the discharge voltage threshold;

[0122] If the target terminal voltage is greater than the discharge voltage threshold, the first semiconductor device is controlled to be turned on.

[0123] Step 103: The control unit records the target number of connected first load units when the first power signal is normal.

[0124] In the embodiment of the present invention, when the first power signal is normal, the corresponding power signal logic state is high level, and when the first power signal is abnormal, the corresponding power signal logic state is low level. Because the first load units are connected to the circuit protection element to be tested one by one, and once the first power signal is abnormal, the first load units will stop being connected, so by recording the target number of the first load units connected when the first power signal is normal, the number of target capacitive loads that can be connected is determined.

[0125] Step 104, determining the maximum capacitive load that the circuit protection element to be tested in the board to be tested can withstand according to the fixed-size target capacitive load and the target quantity.

[0126] After determining the fixed size and target number of the target capacitive load connected to the circuit protection element to be tested in the embodiment of the present invention, the maximum capacitive load of the circuit protection element to be tested can be determined based on this, including two cases. One is that the target number is less than 1. At this time, it is considered that the maximum capacitive load is less than the fixed-size target capacitive load. At this time, if it is necessary to further determine the maximum capacitive load of the circuit protection element to be tested, it is necessary to adjust the fixed size of the target capacitive load in the target test board. The other is that the target number is greater than or equal to 1. At this time, the product of the fixed-size target capacitive load and the target number is used as the maximum capacitive load of the circuit protection element to be tested. The specific steps include:

[0127] When it is determined that the target number is less than 1, it is determined that the maximum capacitive load of the circuit protection element to be tested in the board to be tested is less than the target capacitive load of the fixed size;

[0128] When it is determined that the target quantity is greater than or equal to 1, a product of a fixed-size target capacitive load and the target quantity is obtained;

[0129] The product is determined as the maximum capacitive load that the circuit protection component under test in the board under test can withstand.

[0130] Through the above steps, the maximum capacitive load of the circuit protection component to be tested can be determined and calculated according to the target quantity, without the need for manual welding and waveform capture, which greatly improves the test efficiency and accuracy.

[0131] Correspondingly, when the maximum capacitive load is less than the fixed target capacitive load, one LED indicator light will be controlled to flash green. When the target number is greater than or equal to 1, the target number of LED indicators will be controlled to be always green. This will intuitively show the test results to the tester, which will help the operator quickly understand the test status of the circuit protection element. The specific steps include:

[0132] When it is determined that the target quantity is less than 1, a light emitting diode indicator light is controlled to flash green;

[0133] When it is determined that the target quantity is greater than or equal to 1, the light emitting diode indicator light controlling the target quantity is always on in green.

[0134] It should be noted that, when it is determined that the target quantity is less than 1, before controlling a light emitting diode indicator to flash green, the following steps are also included:

[0135] In response to a first test input to the LED indicator lights by the user, controlling the plurality of LED indicator lights to flash green;

[0136] In response to a second test input to the LED indicator lights by the user, controlling the plurality of LED indicator lights to be constantly green;

[0137] In response to the user's third test input to the LED indicator lights, several LED indicator lights are controlled to light up in red.

[0138] The above steps are used to test the status of the LED indicator light to avoid the test result being affected by problems of the LED indicator light itself.

[0139] For example, the above steps are as follows Figure 5As shown, the board to be tested and the target test board are connected through a cable, and the board to be tested is powered on, and the power signal of the circuit protection element to be tested is detected. If the control unit detects that the power signal of the circuit protection element to be tested is high, the control unit first pulls down the enable signal of the circuit protection element to be tested to turn off the circuit protection element to be tested; if the control unit detects that the power signal of the circuit protection element to be tested is low, the process is terminated, the control unit controls the indicator light to light red, and after 50ms, the enable signal of the first circuit protection element 0 is pulled high, the first circuit protection element 0 is turned on, the coil in the electromagnetic relay will generate magnetism, attract the armature, and instantly connect the capacitor C0 to the output end of the circuit protection element to be tested. After 100ms, the enable signal of the circuit protection element to be tested is pulled high, the circuit protection element to be tested is turned on, and the capacitor C0 is charged. If the control unit detects that the power signal of the circuit protection element to be tested is high, it proves that the circuit protection element to be tested can withstand a capacitive load of 470uF, and the internal register of the control unit is incremented by 1, and the capacitance is continued to be increased for testing; if the control unit detects that the power signal of the circuit protection element to be tested is low, the process is terminated, and the internal register value is 0 at this time. The control unit controls a flashing green light of the indicator light to inform the tester that the maximum capacitive load value of the circuit protection element to be tested is less than 470uF. The next set of tests is carried out to detect the high and low power signal of the circuit protection element to be tested. If it is high, the control unit first pulls down the enable signal of the circuit protection element to be tested and the first circuit protection element 0. At this time, the circuit protection element to be tested and the first circuit protection element 0 are both turned off, and the Vgs of PMOSFET Q1>Vth, PMOSFET Q1 is turned on, and the discharge resistor R0 is connected to both ends of capacitor C0 to discharge capacitor C0. After 50ms, capacitor C0 has completed discharging, and the control unit pulls up the enable signal of the first circuit protection element 0 and the first circuit protection element 1, and the first circuit protection element 0 and the first circuit protection element 1 are turned on. The coil in the electromagnetic relay will generate magnetism, attract the armature, and instantly connect capacitors C0 and C1 to the output end of the circuit protection element to be tested. After 100ms, the enable signal of the circuit protection element to be tested is pulled high, the circuit protection element to be tested is turned on, and capacitors C0 and C1 are charged.Detect the power signal of the circuit protection element to be tested. If the control unit detects that the power signal of the circuit protection element to be tested is high, it proves that the circuit protection element to be tested can withstand a capacitive load of 470uF*2. The internal register of the control unit is incremented by 1, and the capacitance is continued to be increased for testing. Pull down the enable signals of the first circuit protection element 0, the first circuit protection element 1, and the circuit protection element to be tested. After 50ms, pull up the enable signals of the first circuit protection element 0, the first circuit protection element 1, and the first circuit protection element 2. After 100ms, pull up the enable signal of the circuit protection element to be tested. If the control unit detects that the power signal of the circuit protection element to be tested is low, the process is terminated. At this time, the internal register value is 1, and the control unit controls the indicator light to be a constant green light, informing the tester that the maximum capacitive load value of the circuit protection element to be tested is 470uF. If the maximum capacitive load of the circuit protection element to be tested is large, the test steps will be repeated, and the capacitor C can be adjusted and modified according to the actual situation.

[0140] The embodiment of the present invention provides a capacitive load testing method. When it is determined that the power signal of a circuit protection element to be tested is normal, first load units are connected to the circuit protection element to be tested one by one in an increasing manner, the first power signal of the circuit protection element to be tested is monitored after the first load units are connected to the circuit protection element to be tested, the target number of connected first load units is recorded when the first power signal is normal, and the maximum capacitive load that the circuit protection element to be tested in the board to be tested is determined according to a fixed-size target capacitive load and a target number. In the embodiment of the present invention, a target test board including a plurality of first load units is provided, and the plurality of first load units are connected to the board to be tested one by one in an increasing manner, so as to determine the maximum capacitive load that the board to be tested can withstand, without the need for manual welding and waveform capture operations, thereby greatly improving the test efficiency and accuracy, and the target test board can test boards to be tested of different models by controlling the number of connected first load units, thereby improving the coverage of the capacitive load test.

[0141] Reference Figure 6 , shows a schematic diagram of the structure of a capacitive load testing device provided by an embodiment of the present invention, such as Figure 6 As shown, the device may include:

[0142] The access module 201 is used to connect the first load units of the target test board to the circuit protection element to be tested one by one when it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal. The first load unit includes a target capacitive load of a fixed size.

[0143] The monitoring module 202 is used to monitor, through the control unit of the target test board, the first power signal status of the circuit protection element to be tested after the first load unit is connected to the circuit protection element to be tested.

[0144] The recording module 203 is used to record, through the control unit, the target number of the connected first load units when the first power signal condition is normal.

[0145] The determination module 204 is used to determine the maximum capacitive load that the circuit protection element to be tested in the board to be tested can withstand according to the target capacitive load of the fixed size and the target quantity.

[0146] Optionally, the access module 201 specifically includes:

[0147] The first control submodule is used to control the power-on of the board to be tested and detect the target power signal logic state of the circuit protection element to be tested in the board to be tested.

[0148] The first determination submodule is used to determine that the power signal of the circuit protection element to be tested in the board to be tested is abnormal if the target power signal logic state is low level, and control the light emitting diode indicator in the board to be tested to light up red to issue an early warning.

[0149] The second determination submodule is used to determine that the power signal of the circuit protection element to be tested in the board to be tested is normal if the logic state of the first power signal is high, and to connect several first load units of the target test board to the board to be tested one by one.

[0150] The second control submodule is used to control the first enable signal of the circuit protection element to be tested to a low level through the first control signal when it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, so as to ensure that the test environment is consistent with the actual application environment, wherein the circuit protection element is correspondingly turned off when the enable signal is at a low level, and the circuit protection element is correspondingly turned on when the enable signal is at a high level.

[0151] The screening submodule is used to randomly screen out a second load unit from the first load unit of the target test board after waiting for a first preset time.

[0152] The first adjustment submodule is used to adjust the second enable signal of the first circuit protection element in the second load unit to a high level.

[0153] The third control submodule is used to control the electromagnetic relay in the second load unit to enter a target state through a high-level second enable signal, and the coil in the electromagnetic relay in the target state generates magnetism to attract the armature.

[0154] The access submodule is used to connect the target capacitive load of a fixed size in the second load unit to the circuit protection element to be tested through the electromagnetic relay in the target state.

[0155] Optionally, the monitoring module 202 specifically includes:

[0156] The second adjustment submodule is used to adjust the first enable signal of the circuit protection element to be tested to a high level after waiting for a second preset time.

[0157] The charging submodule is used to charge the target capacitive load of fixed size in the second load unit through the circuit protection element to be tested at a high level, so that the target capacitive load of fixed size is connected to the circuit protection element to be tested.

[0158] The monitoring submodule is used to monitor the first power supply signal of the circuit protection element to be tested after determining that the charging is completed.

[0159] Optionally, the capacitive load test device further comprises:

[0160] The first control module is used to control the count in the target register to increase by 1 if the first power signal of the circuit protection element to be tested is normal.

[0161] The second control module is used to control the first enable signal of the circuit protection element to be tested and the second enable signal of the first circuit protection element in the second load unit to be low level through the second control signal, and trigger the first semiconductor device in the second load unit to turn on.

[0162] The third control module is used to control the first discharge resistor to be connected to both ends of a target capacitive load of a fixed size through the turned-on first semiconductor device for discharge, so that the current target capacitive load will not affect the next capacitive load test.

[0163] Optionally, the access module 201 specifically includes:

[0164] The first detection submodule is used to detect whether the target capacitive load of a fixed size has been discharged after waiting for a third preset time.

[0165] The second detection submodule is used to continue detecting the second power supply signal status of the circuit protection element to be tested if the detection is completed.

[0166] The continued screening submodule is used to screen out second load units in increasing numbers from the first load units of the target test board and connect them to the circuit protection element to be tested when it is determined that the second power supply signal of the circuit protection element to be tested of the board to be tested on the server is normal.

[0167] The stop screening submodule is used to stop screening the second load unit from the first load unit of the target test board when it is determined that the second power supply signal of the circuit protection element to be tested is abnormal.

[0168] Optionally, the determination module 204 specifically includes:

[0169] The third determination submodule is used to determine, when it is determined that the target number is less than 1, that the maximum capacitive load of the circuit protection element to be tested in the board to be tested is less than a target capacitive load of a fixed size.

[0170] The acquisition submodule is used to acquire the product of the fixed-size target capacitive load and the target quantity when it is determined that the target quantity is greater than or equal to 1.

[0171] The fourth determining submodule is used to determine the product as the maximum capacitive load that the circuit protection element to be tested in the board to be tested can withstand.

[0172] The fourth control submodule is used to control a light emitting diode indicator to flash green when it is determined that the target quantity is less than 1.

[0173] The fifth control submodule is used to control the target number of light emitting diode indicators to be always green when it is determined that the target number is greater than or equal to 1.

[0174] Optionally, the capacitive load test device further comprises:

[0175] The fourth control module is used to control a plurality of light emitting diode indicator lights to flash green in response to a first test input to the light emitting diode indicator lights by a user.

[0176] The fifth control module is used to control a plurality of light emitting diode indicator lights to be always green in response to a second test input to the light emitting diode indicator lights by the user.

[0177] The sixth control module is used to control a plurality of light emitting diode indicator lights to light up red in response to a third test input to the light emitting diode indicator lights by the user.

[0178] The embodiment of the present invention provides a capacitive load testing method. When it is determined that the power signal of a circuit protection element to be tested is normal, first load units are connected to the circuit protection element to be tested one by one in an increasing manner, the first power signal of the circuit protection element to be tested is monitored after the first load units are connected to the circuit protection element to be tested, the target number of connected first load units is recorded when the first power signal is normal, and the maximum capacitive load that the circuit protection element to be tested in the board to be tested is determined according to a fixed-size target capacitive load and a target number. In the embodiment of the present invention, a target test board including a plurality of first load units is provided, and the plurality of first load units are connected to the board to be tested one by one in an increasing manner, so as to determine the maximum capacitive load that the board to be tested can withstand, without the need for manual welding and waveform capture operations, thereby greatly improving the test efficiency and accuracy, and the target test board can test boards to be tested of different models by controlling the number of connected first load units, thereby improving the coverage of the capacitive load test.

[0179] Based on the same inventive concept, another embodiment of the present invention provides an electronic device 300, such as Figure 7 shown. Figure 7 3 is a schematic diagram of an electronic device according to an embodiment of the present invention. The electronic device includes a processor 301, a memory 302, and a computer program stored in the memory 302 and executable on the processor 301. When the computer program is executed by the processor, the steps of the capacitive load test method according to any of the above embodiments of the present invention are implemented.

[0180] Based on the same inventive concept, another embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the capacitive load testing method described in any of the above embodiments of the present invention are implemented.

[0181] Based on the same inventive concept, another embodiment of the present invention provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps in the capacitive load testing method as described in any of the above embodiments of the present invention.

[0182] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0183] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, computer, server, air conditioner, or network equipment, etc.) to execute the methods described in each embodiment of the present invention.

[0184] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

[0185] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the embodiments of the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0186] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0187] In the embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0188] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0189] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0190] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the relevant technology or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, ROM, RAM, disk or optical disk, etc., which can store program code.

[0191] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A capacitive load testing system, characterized in that: It includes a target test board and a board to be tested on a server, wherein the board to be tested includes a circuit protection element to be tested; the target test board includes a plurality of first load units and a control unit, the target test board is connected to the board to be tested, and the plurality of first load units are connected to the control unit; The first load unit is used to connect target capacitive loads of different sizes to the circuit protection element to be tested; The control unit is used to connect the first load units to the circuit protection element to be tested one by one when it is determined that the power signal of the circuit protection element to be tested is normal, monitor the first power signal of the circuit protection element to be tested after the first load unit is connected to the circuit protection element to be tested, record the target number of the first load units connected when the first power signal is normal, and determine the maximum capacitive load that the circuit protection element to be tested in the board to be tested according to the fixed-size target capacitive load and the target number. The first load unit includes a switching circuit composed of an electromagnetic relay and a fixed-size target capacitive load. The fixed-size target capacitive load in the first load unit is connected to the circuit protection element to be tested through the electromagnetic relay in a target state. The target state refers to the state in which the electromagnetic relay is in a state where the coil generates magnetism and attracts the armature after the enable signal of the first circuit protection element in the first load unit is adjusted to a high level.

2. The capacitive load testing system according to claim 1, characterized in that: The board to be tested also includes a test interface unit; The target test board also includes a first interface unit and a display unit, wherein the first interface unit is connected to a plurality of first load units, the control unit is connected to the display unit, and the display unit is used to display the maximum capacitive load of the circuit protection element to be tested; the target test board is connected to the board to be tested through the first interface unit and the test interface unit; The first interface unit includes a first power supply connector and a first signal connector; The first load unit includes a switching circuit, a discharge circuit and a switch circuit, wherein the switch circuit is composed of a first circuit protection element, and the discharge circuit is composed of a target discharge resistor and a target semiconductor device; The control unit includes a target integrated circuit; The display unit includes light emitting diode indicator lights having the same number as the first load unit; The test interface unit includes a second power supply connector and a second signal connector.

3. The capacitive load testing system according to claim 2, characterized in that: The step of establishing a connection between the target test board and the board to be tested through the first interface unit and the test interface unit includes: Connecting the target power supply to the board to be tested through the second power supply connector; Establishing a first connection between the first power supply connector and the second power supply connector; The target power supply provides power to the target test board via the first connection; Establishing a second connection through the first signal connector and the second signal connector; The control unit monitors various signals of the target test board and the board to be tested through the second connection.

4. A capacitive load testing method, characterized in that: The method comprises: When it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first load units of the target test board are connected to the circuit protection element to be tested one by one, the first load units include a target capacitive load of a fixed size, and the target capacitive load of the fixed size in the first load unit is connected to the circuit protection element to be tested through an electromagnetic relay in a target state, and the target state refers to the state in which the electromagnetic relay is in a state where the coil generates magnetism and attracts the armature after the enable signal of the first circuit protection element in the first load unit is adjusted to a high level; Monitoring, by a control unit of a target test board, a first power supply signal of the circuit protection element to be tested after the first load unit is connected to the circuit protection element to be tested; When the control unit records the first power signal as normal, the target number of the first load units connected; The maximum capacitive load that the circuit protection element to be tested in the board to be tested can withstand is determined according to the fixed-size target capacitive load and the target quantity.

5. The capacitive load testing method according to claim 4, characterized in that: When it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first load units of the target test board are connected one by one to the circuit protection element to be tested, including: Controlling the board to be tested to be powered on, and detecting the target power signal logic state of the circuit protection element to be tested in the board to be tested; If the target power signal logic state is at a low level, it is determined that the power signal of the circuit protection element to be tested in the board to be tested is abnormal, and the light emitting diode indicator in the board to be tested is controlled to light up red to issue an early warning; If the logic state of the first power signal is high, it is determined that the power signal of the circuit protection element to be tested in the board to be tested is normal, and several of the first load units of the target test board are connected to the board to be tested one by one.

6. The capacitive load testing method according to claim 4, characterized in that: When it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first load units of the target test board are connected one by one to the circuit protection element to be tested, and further include: When it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first enable signal of the circuit protection element to be tested is controlled to be low level through the first control signal to ensure that the test environment is consistent with the actual application environment, wherein the circuit protection element is correspondingly turned off when the enable signal is low level, and the circuit protection element is correspondingly turned on when the enable signal is high level; After waiting for a first preset time, randomly selecting a second load unit from the first load units of the target test board; adjusting a second enable signal of the first circuit protection element in the second load unit to a high level; By means of the high-level second enable signal, the electromagnetic relay in the second load unit is controlled to enter a target state, and the coil in the electromagnetic relay in the target state generates magnetism to attract the armature; A target capacitive load of a fixed size in the second load unit is connected to the circuit protection element to be tested through the electromagnetic relay in the target state.

7. The capacitive load testing method according to claim 6, characterized in that: After the target capacitive load of a fixed size in the second load unit is connected to the circuit protection element to be tested through the electromagnetic relay in the target state, the method further includes: After waiting for a second preset time, adjusting the first enable signal of the circuit protection element to be tested to a high level; Charging a target capacitive load of a fixed size in the second load unit through the circuit protection element to be tested which is at a high level, so that the target capacitive load of the fixed size is connected to the circuit protection element to be tested; After determining that charging is completed, monitoring the first power signal of the circuit protection element to be tested.

8. The capacitive load testing method according to claim 7, characterized in that: After monitoring the logic state of the second power signal of the circuit protection element to be tested, the method further includes: If the first power signal of the circuit protection element to be tested is normal, the count in the control target register is increased by 1; Control the first enable signal of the circuit protection element to be tested and the second enable signal of the first circuit protection element in the second load unit to be low level through the second control signal, and trigger the first semiconductor device in the second load unit to be turned on; Through the turned-on first semiconductor device, the first discharge resistor is controlled to be connected to both ends of a target capacitive load of a fixed size for discharge, so that the current target capacitive load will not affect the next capacitive load test.

9. The capacitive load testing method according to claim 8, characterized in that: When it is determined that the power signal of the circuit protection element to be tested of the board to be tested on the server is normal, the first load units of the target test board are connected one by one to the circuit protection element to be tested, and further include: After waiting for a third preset time, detecting whether the target capacitive load of the fixed size has been discharged; If completed, continue to detect the second power supply signal of the circuit protection element to be tested; When it is determined that the second power supply signal of the circuit protection element to be tested of the board to be tested on the server is normal, selecting second load units of increasing number from the first load units of the target test board and connecting them to the circuit protection element to be tested; When it is determined that the second power signal of the circuit protection element to be tested is abnormal, the second load unit screening from the first load unit of the target test board is stopped.

10. The capacitive load testing method according to claim 4, characterized in that: The step of determining the maximum capacitive load of the circuit protection element to be tested in the board to be tested according to the fixed-size target capacitive load and the target quantity includes: When it is determined that the target number is less than 1, determining that the maximum capacitive load of the circuit protection element to be tested in the board to be tested is less than a target capacitive load of a fixed size; When it is determined that the target number is greater than or equal to 1, obtaining a product of the fixed-size target capacitive load and the target number; The product is determined as the maximum capacitive load of the circuit protection element to be tested in the board to be tested.

11. The capacitive load testing method according to claim 10, characterized in that: After the control unit records the target number of the first load units connected when the first power signal condition is normal, the method further includes: When it is determined that the target quantity is less than 1, a light emitting diode indicator light is controlled to flash green; When it is determined that the target number is greater than or equal to 1, the light emitting diode indicator light of the target number is controlled to be always on green.

12. The capacitive load testing method according to claim 11, characterized in that: Before controlling a light emitting diode indicator to flash green when determining that the target quantity is less than 1, the method further comprises: In response to a first test input to the LED indicator lights by the user, controlling the plurality of LED indicator lights to flash green; In response to a second test input to the LED indicator lights by the user, controlling the plurality of LED indicator lights to be constantly green; In response to the user's third test input to the LED indicator lights, several LED indicator lights are controlled to light up in red.

13. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the steps in the capacitive load testing method according to any one of claims 4 to 12 are implemented.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the capacitive load testing method according to any one of claims 4 to 12 are implemented.

15. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps in the capacitive load testing method according to any one of claims 4 to 12 are implemented.

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