A multi-rate structured QC-LDPC encoding method suitable for 3D NAND flash memory

Abstract

The application relates to the technical field of wireless communication and discloses a multi-code rate structured QC-LDPC encoding method suitable for 3D NAND flash memory, which comprises the following steps: constructing a base matrix based on a finite field; performing a mask operation on the base matrix; performing a hash operation and a cyclic permutation operation on the base matrix after the mask operation to obtain a first sub-matrix corresponding to information bits; designing a second sub-matrix corresponding to check bits; and splicing the first sub-matrix and the second sub-matrix into a check matrix; wherein the size of the check matrix is determined by a preset total number of compatible code rates and a preset highest code rate; and performing encoding on the check matrix to obtain a QC-LDPC code.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communications, and more particularly, to a multi-rate structured QC-LDPC encoding method suitable for 3D NAND flash memory. Background Art

[0002] For 3D TLC NAND flash memory, the accumulation of various noise factors makes RBER changes difficult to predict. Generally speaking, as the number of P / E cycles and retention time increases, the RBER of 3D NAND flash memory also increases. Currently, the construction of LDPC codewords for 3D NAND flash memory channel matching depends on the RBER of the 3D NAND flash memory. It is necessary to set an RBER threshold to match the appropriate LDPC codeword. When selecting the LDPC codeword rate, two factors must be considered: error correction capability and redundancy. In 3D NAND flash memory, when the code rate is high, the redundancy occupied by the parity bits is small, but the LDPC codeword's error correction capability is poor, which may lead to an increase in read retries. While lowering the LDPC codeword rate significantly improves error correction capability, the length of the parity bits also increases, which occupies more storage space in the 3D NAND flash memory. To further improve storage efficiency, high-rate LDPC codewords are typically used in new 3D NAND flash memory. As P / E cycles and retention time increase, it is necessary to switch to low-rate LDPC codewords to ensure ECC performance. However, existing LDPC codewords are not compatible with multiple code rates and cannot meet the demand for switching code rates according to actual needs. Summary of the Invention

[0003] In order to overcome the defect of the above-mentioned prior art that it is not compatible with multiple code rates, the present invention provides a multi-rate structured QC-LDPC encoding method suitable for 3D NAND flash memory that is compatible with several code rates.

[0004] In order to solve the above technical problems, the technical solutions of the present invention are as follows:

[0005] Construct basis matrices based on finite fields;

[0006] performing a mask operation on the basis matrix;

[0007] Performing hashing and cyclic permutation operations on the masked basis matrix to obtain a first submatrix corresponding to the information bit;

[0008] Design a second sub-matrix corresponding to the check bit;

[0009] Splice the first sub-matrix and the second sub-matrix into a check matrix; wherein the size of the check matrix is determined by the preset total number of compatible code rates and the preset highest code rate.

[0010] Encode the check matrix to obtain a QC-LDPC code.

[0011] The application further provides a multi-code rate structured QC-LDPC encoding system suitable for 3D NAND flash memory, which is used for realizing the multi-code rate structured QC-LDPC encoding method suitable for 3D NAND flash memory.

[0012] A base matrix construction module is used for constructing a base matrix based on a finite field;

[0013] A mask operation module is used for performing a mask operation on the base matrix;

[0014] A first sub-matrix generation module is used for performing a hash operation and a cyclic permutation operation on the base matrix after the mask operation to obtain a first sub-matrix corresponding to information bits;

[0015] A second sub-matrix generation module is used for designing a second sub-matrix corresponding to check bits;

[0016] A check matrix generation module is used for splicing the first sub-matrix and the second sub-matrix into a check matrix; wherein the size of the check matrix is determined by the preset total number of compatible code rates and the preset highest code rate;

[0017] An encoding module is used for encoding the check matrix to obtain a QC-LDPC code.

[0018] The application further provides a computer device, which comprises a memory and a processor, and the memory stores computer readable instructions; when the computer readable instructions are executed by the processor, the processor executes the steps of the multi-code rate structured QC-LDPC encoding method suitable for 3D NAND flash memory.

[0019] Compared with the prior art, the application has the following beneficial effects:

[0020] The first sub-matrix is constructed based on the base matrix, and the first sub-matrix and the second sub-matrix are spliced into a check matrix; wherein the size of the check matrix is determined by the preset total number of compatible code rates and the preset highest code rate; the size of the check matrix is adjusted through the preset total number of compatible code rates and the preset highest code rate, so that the purpose of compatible with several code rates is achieved, and the demand of switching code rates according to actual needs can be met. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1A flowchart of the multi-rate structured QC-LDPC encoding method suitable for 3D NAND flash memory proposed in Embodiment 1;

[0022] Figure 2 A flowchart of the algebraic construction of the base matrix proposed in Embodiment 1;

[0023] Figure 3 A schematic diagram of the mask matrix structure proposed in Embodiment 1;

[0024] Figure 4 A schematic diagram of the check matrix structure of the QC-LDPC code proposed in Embodiment 1;

[0025] Figure 5 A schematic diagram of the first simulation result proposed in Embodiment 2;

[0026] Figure 6 A schematic diagram of the second simulation result proposed in Embodiment 2;

[0027] Figure 7 A schematic diagram of the overall framework of a multi-rate structured QC-LDPC encoding system suitable for 3D NAND flash memory proposed in Embodiment 3. DETAILED DESCRIPTION

[0028] The accompanying drawings are only for illustrative purposes and should not be construed as limiting the present embodiment;

[0029] In order to better illustrate the present embodiment, some components in the drawings may be omitted, enlarged or reduced, and do not represent the actual size of the product;

[0030] It is understandable that some well-known structures and their descriptions in the drawings may be omitted for those skilled in the art.

[0031] The technical solutions of the present application will be further described below in conjunction with the drawings and embodiments.

[0032] Embodiment 1

[0033] The present embodiment proposes a multi-rate structured QC-LDPC encoding method suitable for 3D NAND flash memory, Figure 1 A flowchart of the multi-rate structured QC-LDPC encoding method suitable for 3D NAND flash memory proposed in the present embodiment;

[0034] The multi-rate structured QC-LDPC encoding method suitable for 3D NAND flash memory proposed in the present embodiment includes the following steps:

[0035] S1: constructing a base matrix based on a finite field;

[0036] S2: performing a mask operation on the base matrix;

[0037] S3: performing a hash operation and a cyclic permutation operation on the base matrix after the mask to obtain a first sub-matrix corresponding to the information bits;

[0038] S4: designing a second sub-matrix corresponding to the check bits;

[0039] S5: splicing the first sub-matrix and the second sub-matrix into a check matrix; wherein the size of the check matrix is determined by a preset total number of compatible code rates and a preset highest code rate;

[0040] S6: encoding the check matrix to obtain a QC-LDPC code.

[0041] In the specific implementation process, the first sub-matrix is constructed based on the base matrix, and the first sub-matrix and the second sub-matrix are spliced into a check matrix; wherein the size of the check matrix is determined by a preset total number of compatible code rates and a preset highest code rate; the size of the check matrix is adjusted through the preset total number of compatible code rates and the preset highest code rate, so as to achieve the purpose of compatibility of several code rates, and meet the demand of switching code rates according to actual needs.

[0042] In an optional embodiment, the expression of the base matrix comprises:

[0043]

[0044] or

[0045]

[0046] S1,S2∈GF(q)

[0047] In the formula, M base represents a base matrix; α m,n represents the element of the mth row and the nth column of M base , also represents the shift value of M base ; M b represents the total number of rows of M base ; N b represents the total number of columns of M base ; represents the mth element of set S1; represents the nth element of set S2; GF(q) represents a finite field of prime field; q represents a prime number; wherein α i is a primitive element of GF(q), α j is another primitive element of GF(q), there is no same element in set S1 and set S2; mod represents a modulus operator.

[0048] As an exemplary illustration, based on The constructed check matrix is better than the check matrix based on The check matrix constructed by the method has better performance.

[0049] As an exemplary illustration, Figure 2 A flow chart for constructing the base matrix by algebra is provided for the embodiment; Figure 2 A flow chart for constructing the base matrix by algebra is provided for the embodiment; Figure 2 The shift value matrix in the embodiment is the base matrix.

[0050] In an alternative embodiment, the step of performing a masking operation on the base matrix comprises:

[0051] The PEG-ACE algorithm is used to construct a masking matrix, and the masking matrix is used to perform a masking operation on the base matrix to obtain a masked base matrix H mask , H mask The expression of H x,y includes:

[0052]

[0053] Z = [Z x,y ]

[0054]

[0055] In the formula, Z represents the masking matrix; Z m,n represents the element in the xth row and yth column of Z; a b represents the element in the mth row and nth column of the base matrix.

[0056] In the alternative embodiment, in the construction of the check matrix of the QC-LDPC code, masking is a commonly used key technology, which is mainly used to process the constructed QC-LDPC code to make the check matrix have better structural characteristics and improve the decoding performance of the LDPC code. As an exemplary illustration, a known QC-LDPC check matrix has a size of M b (q-1)×N QC (q-1); the shift size of the CPM is L = q-1; and the density λ of the check matrix H QC is defined as the ratio of the non-zero elements to all elements in the matrix; the number of non-zero elements in the check matrix H Q is λ×M Q ×N QC . In order to make the check matrix H QC more sparse and reduce the possibility of short loops, some CPMs in the matrix H QCThere are β elements replaced by all-0 matrix, which corresponds to βL edges deleted in the Tanner graph; this can reduce short loops and increase the girth of the constructed parity check matrix; the shift value matrix H QC of the matrix after βL edges are deleted

[0057]

[0058] The mask operation can also be expressed in the form of Hadamard matrix multiplication; taking the mask operation on the base matrix M base as an example; matrix Z = [Z x,y ] is a binary matrix with the same size as the base matrix M base , which is M b ×N b ; such a matrix Z is called a mask matrix; the matrix H base after the mask operation on the matrix M mask can be expressed as:

[0059]

[0060] Wherein:

[0061]

[0062] The element value of the part of the base matrix M base replaced by the mask is -1, which corresponds to an all-0 matrix of size (q-1) × (q-1) after the hash operation; the remaining elements remain unchanged, which are the shift values of the CPM.

[0063] As an exemplary illustration, the construction of the mask matrix H mask uses the PEG-ACE algorithm; the English full name of PEG is Progressive Edge Growth, and the English full name of ACE is Approximate Cycle Extrinsic message degree; the loop in the Tanner graph will affect the performance of iterative decoding, and the shorter the loop, the greater the impact on the decoding performance; therefore, when constructing QC-LDPC codes, the girth should be as large as possible; the PEG algorithm is a greedy algorithm that maximizes the local loop length; this algorithm adds an edge to the existing Tanner graph each time, so that the new Tanner graph has the maximum girth; the ACE algorithm can reduce the small dimension distribution of the stopping set by increasing the ACE value, thereby improving the expansion of the cycle and thus improving the decoding performance; the PEG algorithm is very suitable for long QC-LDPC code words, and the ACE algorithm can eliminate loops with poor connectivity; PEG-ACE is an excellent mask construction algorithm; therefore, the QC-LDPC encoding method proposed in the present application adopts the PEG-ACE algorithm design;Figure 3 This is a schematic diagram of the mask matrix structure proposed in this embodiment. Figure 3 In, M base_J Represents the basis matrix, and the black box represents M base_J The shift value, the white box represents M base_J The element is -1; the size of the mask matrix is ​​designed according to different code rates, H mask_1 The box shows the maximum code rate mask matrix size, H mask_J The box shows the minimum code rate mask matrix size.

[0064] In an optional embodiment, the step of performing a hash operation and a cyclic permutation operation on the masked base matrix to obtain a first submatrix corresponding to the information bit includes:

[0065] Each element of the masked basis matrix is ​​replaced by the cyclic permutation matrix corresponding to each element to obtain a first submatrix corresponding to the information bit;

[0066] The total number of rows and columns of the circulant permutation matrix are both (q-1), where q represents the number corresponding to the finite field selected when constructing the basis matrix based on the finite field; when the element α in the mth row and nth column of the masked basis matrix is m,n When the value of α is 0, m,n The corresponding circulant permutation matrix is ​​the identity matrix; when α m,n When the value of is -1, the circulant permutation matrix is ​​an all-0 matrix; the total number of rows and columns of the first submatrix are M b (q-1) and (N b -M b )(q-1);M b Represents the total number of rows of the basis matrix; N b Represents the total number of columns in the basis matrix.

[0067] As an example, when the finite field is a prime field GF(q), q is a prime number; for the prime field GF(q), the circulant permutation matrix (CPM) C(α s ) is defined as (q-1)×(q-1), and (q-1) is defined as the shift size L of CPM; the basis matrix M base The value in is defined as the shift value of CPM; the unit CPM is defined as a unit matrix; each row in CPM is right-shifted according to the shift value; the elements in the base matrix are replaced with CPM; the replacement process is called a hash operation.

[0068] In an optional embodiment, the expression of the second submatrix includes:

[0069]

[0070] 1≤X≤MQ -2

[0071] Where H dp represents the second sub-matrix; M Q Indicates H dp The total number of rows, also referred to as H dp The total number of columns; hdp X,1 Indicates H dp The element in the X+1th row and 1st column of ; Indicates H dp The Mth Q The check digit corresponding to the column element.

[0072] As an example, since the LDPC codeword is a linear block code, there are two encoding methods: one is to encode the check matrix by a series of transformations to obtain a systematic generator matrix; the other is to directly encode the check matrix with a codable structure; this application uses (N Q ,K) codeword as an example, where N Q is the codeword length, K is the information bit length; the check matrix H QC The size is M Q ×N Q ; and assume that the check matrix H QC is a full rank matrix, that is, rank(H QC )=M=N Q -K; and only consider binary LDPC codewords; for the general check matrix H QC , H can be transformed into QC Converted to "system form", the system form H sys The expressions include:

[0073]

[0074] The check matrix H in the system form sys middle, Is a size M Q ×M Q The identity matrix; assuming that the information sequence is u={u0,u1,…,u K-1}, the codeword sequence is Where p is the check bit sequence, According to the LDPC check relation H sys ×c T (mod2) = 0, we can get the expression of the check bit sequence; at this time, the generator matrix of the system form of the codeword is G sys =[I K P T]; The above method is applicable to all LDPC code words, that is, it is also applicable to QC-LDPC code words; In order to simplify the check matrix H QC Perform column permutation and Gauss-Jordan elimination operations to directly convert the check matrix H QC Designed in the form of direct coding, namely H QC =[H ds H dp H in ] dp There are some special structures, such as: single diagonal structure, upper / lower triangular structure, dual diagonal structure; the basis of the variable code rate structured QC-LDPC coding method of the present application is to design a dual diagonal structure, and the second sub-matrix is ​​a dual diagonal structure; the dual-diagonal structure is generally used to design a variable code rate LDPC coding method. The basis of the coding method of the present application is to design a dual diagonal structure, wherein, in the matrix H dp In the first leftmost column, the Xth row must have an additional non-zero element hdp X,1 .

[0075] In an optional embodiment, the expression of the check matrix includes:

[0076]

[0077] 1≤X≤M Q -2

[0078] Where H QC represents the check matrix; M Q Indicates H QC The total number of rows; N Q Indicates H QC The total number of columns, also referred to as H QC The codeword length of the corresponding QC-LDPC code; K represents H QC The information bit length of the corresponding QC-LDPC code; H ds represents the first submatrix; H dp represents the second submatrix; s K-1 Indicates H ds The Kth column element of H ds The Kth information bit of ; Indicates H dp The Mth b Column elements, also represented by H dp The Mth b check digit; hds X,K-1 Indicates H ds The element in the X+1th row and Kth column of hdp X,K Indicates H QC The X+1th row and K+1th column element ofdp The element in the X+1th row and 1st column of ;

[0079] In an optional embodiment, the total number of preset compatible code rates is J, and the expression of J code rates compatible with the check matrix includes:

[0080]

[0081] Ji∈1,2,3,...,J

[0082]

[0083] K=N QJi -M QJi

[0084] N Q ∈N Q1 ,N Q2 ,…,N QJi ,…,N QJ

[0085]

[0086] M Q ∈M Q1 ,M Q2 ,…,M QJi ,…,M QJ

[0087] M QJi =Ji×L

[0088] L=q-1

[0089] Where M Q and N Q Respectively represent the total number of rows and columns of the check matrix; R Ji represents the i-th code rate compatible with the check matrix, J represents the total number of code rates compatible with the check matrix; R max Indicates the preset maximum bit rate; M QJi and N QJi Respectively represent R Ji The total number of rows and columns of the corresponding check matrix; K represents H QC The information bit length of the corresponding QC-LDPC code; q represents the number corresponding to the finite field selected when constructing the basis matrix based on the finite field.

[0090] As an example, Figure 4 Schematic diagram of the check matrix structure of the QC-LDPC code proposed in this embodiment; Figure 4 In the figure, the black box represents the CPM after shift transformation, and the white box represents the all-0 matrix; Figure 4 The matrix H inQC_J corresponds to H QC ; Figure 4 corresponds to H p_J corresponds to H QC corresponds to H dp ; Figure 4 corresponds to H k_J corresponds to H QC corresponds to H ds ; Figure 4 corresponds to H p The first column of H QC_1 represents the check matrix corresponding to the first code rate R1, H QC_2 represents the check matrix corresponding to the second code rate R2, H QC_3 represents the check matrix corresponding to the third code rate R3, and the LDPC code with a low code rate contains the LDPC code with a high code rate. The nested relationship has a low construction complexity and can ensure that the check matrix is a full rank matrix. Moreover, the check matrix constructed according to the above process does not have a 4-cycle.

[0091] As an example, R Ji is expressed as: a fraction with the information bit length as the numerator and the codeword length as the denominator. The information bit length is defined as K=N QJi -M QJi , and the information bit length needs to remain fixed during design and does not change with the code rate, that is, K is a constant. Therefore, to maximize the code rate, the codeword length should be minimized. Let N Q1 be the minimum codeword length, N QJi increases with the increase of Ji, and then, Because the check matrix is obtained by hashing and cyclic permutation of the base matrix, the number of rows of the check matrix is a positive integer multiple of the size of the cyclic permutation matrix, that is, M QJi = Ji x L; and N Q1 = K + M Q1 = K + L, and the solution is

[0092] Because K = N QJi -M QJi = N Q1 -M Q1 , so, The solution is, Therefore, the code rate R JiThe expression of the range of values of M and N is as follows: M ∈ M, N ∈ N, M = M(q-1), N = (N-M)(q-1); as an exemplary illustration, the compatible different code rates are related to the number of set code rates and the highest code rate; as an exemplary illustration, the highest code rate that can be achieved by the check matrix constructed by the method of the present application includes: 0.941, 0.914, 0.889, 0.865, 0.842, 0.8.

[0093] As an exemplary illustration, when the total number of rows and the total number of columns of the first sub-matrix are M b (q-1) and (N b -M b )(q-1) respectively, the range of values of M b and N b is as follows:

[0094] M b ∈M b1 ,M b2 ,…,M bJi ,…,M bJ ; N b ∈N b1 ,N b2 ,…,N bJi ,…,N bJ ;

[0095] wherein M bJi and N bJi respectively represent the total number of rows and the total number of columns of the base matrix corresponding to R Ji ;

[0096] Then, M QJi = M bJi (q-1), N QJi = (N bJi -M bJi )(q-1); in the process of implementation, the size of R max and J is determined first, the size of M max and N QJi can be calculated according to the size of R QJi and J, and then the size of M bJi and N bJi is obtained; in the case where the size of M bJi and N bJi is known, the QC-LDPC code corresponding to R Ji can be obtained by using the QC-LDPC encoding method proposed in the present application.

[0097] In an optional embodiment, the check matrix H QC is directly encoded into a QC-LDPC code, and the expression of the QC-LDPC code includes:

[0098]

[0099] wherein c represents a QC-LDPC code, c n represents an (n+1)th element of c, also represents a code word corresponding to an (n+1)th column element of the first sub-matrix; N b represents a total number of elements of c; p0 represents a first check bit of the second sub-matrix; K represents a total number of columns of the first sub-matrix; M b represents a total number of rows of H QC ; hds i,j represents an (i+1)th row and (j+1)th column element of the first sub-matrix; c j represents a (j+1)th element of c; mod represents a modulo operator; p m represents an (m+1)th check bit of the second sub-matrix; & represents and; hdp X,K represents an (X+1)th row and (K+1)th column element of H QC ; hds d represents an (X+1)th row and first column element of p.

[0100] As an example, all rows of the check matrix H QC are added to obtain a first check bit p0; the remaining check bits are calculated according to the check relation H QC ×c T = 0.

[0101] In this embodiment, the application can design a channel model based on 3D NAND flash channel measurement data by means of machine learning, and evaluate and analyze model parameters; around different stages of evolution of channel parameters, the channel error code characteristics are fitted to determine the code rate variation interval; under the constraint of the code rate variation interval, the structured QC-LDPC code word with code rate compatibility can be constructed based on the method of algebraic tool and mask; the basic idea is to use the row expansion method to first construct a high code rate mother code (a check matrix with a total number of rows M Q1 and a total number of columns N Q1 ), and then reduce the code rate by increasing the check bits; the difference from the traditional expansion method is that the newly constructed code word not only has relevance with the QC-LDPC code word of the mother code, but also has relevance between the QC-LDPC code words of other code rates constructed; in addition, using the algebraic tool to construct the check matrix can greatly reduce the encoding complexity; by using the influence of flash noise on the original error rate, QC-LDPC code words of different code rates are dynamically selected according to the characteristics of the flash channel; for low flash noise points, QC-LDPC code words with high code rate can be selected to save the storage space of the flash memory, and for high flash noise points, QC-LDPC encoding methods with low code rate can be selected to reduce the error rate of the flash memory.

[0102] Embodiment 2

[0103] This embodiment is based on the multi-rate structured QC-LDPC encoding method for 3D NAND flash memory proposed in Example 1, and proposes the following performance comparison example:

[0104] In this embodiment, the performance of the QC-LDPC codeword (MHR-SA-QC-LDPC codeword) of this application in a 3D TLC NAND flash memory channel is simulated and compared with the performance of the 3GPP 5GNR LDPC codeword. When operating at the optimal read voltage, the RBER and RFER of the 3D NAND TLC flash memory increase rapidly and eventually reach the critical error rate. We simulated the performance of the MHR-SA-QC-LDPC codeword under different data retention times under different P / E cycles (program / erase cycles) and retention time conditions. Figure 5 This is a schematic diagram of the first simulation result proposed in this embodiment. Figure 6 This is a schematic diagram of the second simulation result proposed in this embodiment. Figure 5 The BER (bit error rate) and FER (frame error rate) of LDPC codes with optimal RRV (read reference voltage) are demonstrated for MHR-SA-QC-LDPC codewords and 3GPP 5GNR LDPC codewords under the same P / E cycles = 6500 and different retention times. Figure 6The MHR-SA-QC-LDPC code word and the 3GPP 5GNR LDPC code word are shown in the same retention time = 2 months and different P / E cycles conditions, the BER and FER of the LDPC code with the optimal RRV (please indicate which part of the figure is the MHR-SA-QC-LDPC code word and which part is the 3GPP 5GNR LDPC code word), and the simulation results prove that the performance of the MHR-SA-QC-LDPC code word is better than that of the 5GNR LDPC code under the same P / E cycles and retention time; in the specific implementation process, the optimal read reference voltage is analyzed and predicted according to the RBER (raw bit error rate) under different P / E cycles and retention time to reduce the RBER, and then the MHR-SA-QC-LDPC code word with different code rates is selected to match the NAND flash channel. Through this method, the code rate switching threshold is set according to the BER. When the BER of the high code rate LDCP code word is higher than the code rate switching threshold, the LDPC code word with a lower code rate needs to be switched to ensure the ECC correction performance; the MHR-SA-QC-LDPC code word can automatically match the suitable code rate according to the BER of the NAND flash, reduce the occupation of the redundant space by the check bits, and has good error correction performance.

[0105] Embodiment 3

[0106] The embodiment provides a multi-rate structured QC-LDPC encoding system suitable for 3D NAND flash memory, which is used for implementing the multi-rate structured QC-LDPC encoding method suitable for 3D NAND flash memory.

[0107] Figure 7 The embodiment provides a multi-rate structured QC-LDPC encoding system suitable for 3D NAND flash memory, which is used for implementing the multi-rate structured QC-LDPC encoding method suitable for 3D NAND flash memory.

[0108] The multi-rate structured QC-LDPC encoding system suitable for 3D NAND flash memory comprises a base matrix construction module, a mask operation module, a first sub-matrix generation module and a second sub-matrix generation module.

[0109] The base matrix construction module is used for constructing a base matrix based on a finite field.

[0110] The mask operation module is used for performing a mask operation on the base matrix.

[0111] The first sub-matrix generation module is used for performing a hash operation and a cyclic permutation operation on the base matrix after the mask operation, to obtain a first sub-matrix corresponding to information bits.

[0112] The second sub-matrix generation module is used for designing a second sub-matrix corresponding to check bits.

[0113] The parity check matrix generating module is configured to splice the first sub-matrix and the second sub-matrix into a parity check matrix, wherein the size of the parity check matrix is determined by the preset total number of compatible code rates and the preset highest code rate.

[0114] The encoding module is configured to encode the parity check matrix to obtain a QC-LDPC code.

[0115] The embodiment provides a computer device, which comprises a memory and a processor, and the memory stores computer readable instructions, and the computer readable instructions are executed by the processor to make the processor execute the steps of the method for multi-code rate structured QC-LDPC encoding applicable to 3D NAND flash memory in embodiment 1.

[0116] It can be understood that the multi-code rate structured QC-LDPC encoding system and the computer device applicable to 3D NAND flash memory of the embodiment improve the method in embodiment 1, and the optional items in the above embodiment 1 are also applicable to the embodiment, so they will not be described here.

[0117] The same or similar reference signs correspond to the same or similar components;

[0118] The terms describing the positional relationship in the drawings are only used for exemplary illustration, and cannot be understood as a limitation on the embodiment;

[0119] Obviously, the above embodiments of the present application are only examples for clearly illustrating the present application, and are not intended to limit the implementation modes of the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the implementation modes need not and cannot be exhausted. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the claims of the present application.

Claims

1. A multi-rate structured QC-LDPC encoding method suitable for 3D NAND flash memory, characterized in that: The following steps are involved: Construct basis matrices based on finite fields; Performing a masking operation on the basis matrix, wherein a masking matrix is ​​constructed using a PEG-ACE algorithm, and the masking matrix is ​​used to perform a masking operation on the basis matrix to obtain a masked basis matrix; Performing hashing and cyclic permutation operations on the masked basis matrix to obtain a first submatrix corresponding to the information bit; Designing a second submatrix corresponding to the check bit, wherein the second submatrix has a dual diagonal structure; splicing the first submatrix and the second submatrix into a check matrix; wherein the size of the check matrix is ​​determined by a preset total number of compatible code rates and a preset maximum code rate; Encoding the check matrix to obtain a QC-LDPC code; The step of performing a hash operation and a cyclic permutation operation on the masked base matrix to obtain a first submatrix corresponding to the information bit includes: Each element of the masked basis matrix is ​​replaced by the cyclic permutation matrix corresponding to each element to obtain a first submatrix corresponding to the information bit; The total number of rows and columns of the circulant permutation matrix are , Indicates the number corresponding to the finite field selected when constructing the basis matrix based on the finite field; when the first m Rank n Elements of a column When the value of is 0, The corresponding circulant permutation matrix is ​​the identity matrix; when When the value of is -1, the circulant permutation matrix is ​​an all-0 matrix; the total number of rows and columns of the first submatrix are and ; Represents the total number of rows of the basis matrix; Indicates the total number of columns in the basis matrix.

2. The multi-rate structured QC-LDPC encoding method for 3D NAND flash memory according to claim 1, wherein: The expression of the basis matrix includes: ， or ； Where, represents the basis matrix; express No. m Rank n The elements of the column also represent The shift value of express The total number of rows, express The total number of columns; Representing a collection No. m elements; Representing a collection No. n elements; represents the finite field of prime numbers; represents a prime number; among them, for within A primitive element, for within Another primitive element, the set and collection There are no identical elements in Represents the modulo operator.

3. The multi-rate structured QC-LDPC encoding method for 3D NAND flash memory according to claim 1, wherein: The step of performing a mask operation on the basis matrix includes: The mask matrix is ​​constructed using the PEG-ACE algorithm, and the mask matrix is ​​used to perform a mask operation on the basis matrix to obtain the masked basis matrix. , The expressions include: Where, represents the mask matrix; express No. x Rank y Column elements; represents the basis matrix m Rank n Elements of a column.

4. The multi-rate structured QC-LDPC encoding method for 3D NAND flash memory according to claim 1, characterized in that: The expression of the second submatrix includes: Where, represents the second sub-matrix; express The total number of rows, also expressed as The total number of columns; express No. X +1 row and 1 column element; express No. The check digit corresponding to the column element.

5. The multi-rate structured QC-LDPC encoding method for 3D NAND flash memory according to claim 1, characterized in that: The expression of the check matrix includes: Where, represents the check matrix; express The total number of rows; express The total number of columns, also expressed as The codeword length of the corresponding QC-LDPC code; K express The information bit length of the corresponding QC-LDPC code; represents the first submatrix; represents the second sub-matrix; express No. K Column elements, also represented by No. K information bits; express No. Column elements, also represented by No. check digits; express No. X +1 line K Column elements; express No. X +1 line K +1 column element, also means No. X +1 row, 1 column element.

6. The multi-rate structured QC-LDPC encoding method for 3D NAND flash memory according to claim 1, characterized in that: The total number of preset compatible bit rates is J , the check matrix is ​​compatible with J The bitrate expressions include: Where, and Respectively represent the total number of rows and columns of the check matrix; Indicates that the check matrix is ​​compatible with Bit rate, J Indicates the total number of code rates compatible with the parity check matrix; Indicates the preset maximum bit rate; and Respectively The total number of rows and columns of the corresponding check matrix; K express The information bit length of the corresponding QC-LDPC code; The number corresponding to the finite field selected when constructing the basis matrix based on the finite field.

7. The multi-rate structured QC-LDPC encoding method for 3D NAND flash memory according to any one of claims 1 to 6, characterized in that: The step of encoding the check matrix includes: The check matrix Directly encode into a QC-LDPC code, the expression of the QC-LDPC code includes: Where, represents QC-LDPC code, express No. n +1 element, also represents the first submatrix n +1 column element corresponding to the code word; express The total number of elements; represents the first check bit of the second submatrix; Represents the total number of columns of the first submatrix; express The total number of rows; The first submatrix is ​​represented by i +1 line j +1 column element; express No. j +1 element; Represents the modulo operator; The second submatrix is ​​represented by m +1 check digit; Indicates and; express No. X +1 line K +1 column element, also means No. X +1 row, 1 column element.

8. A multi-rate structured QC-LDPC encoding system applicable to 3D NAND flash memory, for implementing the multi-rate structured QC-LDPC encoding method applicable to 3D NAND flash memory according to any one of claims 1 to 7, characterized in that: include: Basis matrix construction module, used to construct basis matrix based on finite field; A mask operation module, configured to perform a mask operation on the basis matrix; A first sub-matrix generation module is used to perform a hash operation and a cyclic permutation operation on the masked base matrix to obtain a first sub-matrix corresponding to the information bit; A second sub-matrix generation module, used for designing a second sub-matrix corresponding to the check bit; a check matrix generation module, configured to concatenate the first submatrix and the second submatrix into a check matrix; wherein the size of the check matrix is ​​determined by a preset total number of compatible code rates and a preset maximum code rate; The encoding module is used to encode the check matrix to obtain a QC-LDPC code.

9. A computer device comprising a memory and a processor, wherein the memory stores computer-readable instructions, wherein: When the computer-readable instructions are executed by the processor, the processor performs the steps of the multi-rate structured QC-LDPC encoding method applicable to 3D NAND flash memory as described in any one of claims 1 to 7.

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