Large-capacity storage package chip and data writing method

Abstract

The present application relates to the field of semiconductor manufacturing technology and provides a large-capacity storage package chip and a data writing method. The package chip includes: a control chip, N flash memory groups and N switching modules. The control chip includes N data channels, and each flash memory group includes M flash memories. Each data channel of the control chip is connected to a flash memory group. The control chip sends a switching signal to the corresponding switching module through the data channel, and the switching module switches the flash memory connected to the control chip in the flash memory group according to the switching signal. The control chip only communicates with one flash memory in the flash memory group at the same time. In the present application, the data channel is not connected to a single flash memory, but to a flash memory group. The flash memory connected to the control chip is continuously switched among the flash memories in the flash memory group through the switching module, which is equivalent to expanding the total capacity of the flash memory connected to the control chip. No additional data channels are required, and the cost is low.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a large-capacity storage package chip and a data writing method. Background Art

[0002] In the related art, the number of flash memories that can be connected to a control chip depends on the number of its data channels. When each data channel is connected to a flash memory, if you want to increase the storage capacity, you need to increase the number of data channels, but the cost of increasing data channels is high. Summary of the Invention

[0003] In response to the deficiencies in the prior art, the present application provides a large-capacity storage package chip and a data writing method, which are conducive to increasing the storage capacity of the packaged chip in a low-cost manner.

[0004] In order to solve the above problems, the present invention provides the following technical solutions:

[0005] In a first aspect, an embodiment of the present application provides a large-capacity storage package chip, the package chip including a control chip, N flash memory groups, and N switching modules, the control chip including N data channels, and each flash memory group including M flash memories; wherein N and M are both positive integers, and N is greater than or equal to 1, and M is greater than or equal to 2;

[0006] Each data channel of the control chip is connected to a flash memory group;

[0007] The control chip sends a switching signal to the corresponding switching module through the data channel, and the switching module switches the flash memory connected to the control chip in the flash memory group according to the switching signal; wherein, the control chip only communicates with one flash memory in the flash memory group at the same time.

[0008] In some embodiments, the switching module is a synchronous sequential circuit, and the switching signal is a clock signal;

[0009] The control chip sends a clock signal to the switching module through the data channel, and the switching module switches the flash memory in the flash memory group connected to the control chip according to the clock signal.

[0010] In some embodiments, the switching module switches the flash memory in the flash memory group connected to the control chip when the clock signal is at a rising edge.

[0011] In some embodiments, the switching module is a software module, and each data channel of the control chip is directly connected to each flash memory in the corresponding flash memory group.

[0012] In some embodiments, it is characterized in that the multiple flash memories in the flash memory group are stacked in a vertical direction.

[0013] In a second aspect, an embodiment of the present application provides a method for writing data to a large-capacity storage package chip based on the first aspect, the method comprising:

[0014] Sending a control signal to a switching module connected to the data channel, so that the switching module switches the flash memory connected to the control chip in the flash memory group according to the control signal;

[0015] The data to be written is written into the flash memory connected to the control chip.

[0016] In some embodiments, sending a control signal to a switching module connected to the data channel so that the switching module switches the flash memory in the flash memory group connected to the control chip according to the control signal includes:

[0017] Obtain the preset switching rules corresponding to the data channel;

[0018] When the preset switching rule is met, a control signal is sent to the switching module connected to the data channel, so that the switching module switches the flash memory connected to the control chip in the flash memory group according to the control signal.

[0019] In some embodiments, the preset switching rule includes whether the connection time of the flash memory connected to the control chip in the current channel reaches a preset time.

[0020] In some implementations, the preset switching rule includes whether power-on of the control chip is detected.

[0021] In some embodiments, sending a control signal to a switching module connected to the data channel so that the switching module switches the flash memory in the flash memory group connected to the control chip according to the control signal includes:

[0022] A clock signal of a preset period is sent to a switching module connected to the data channel, so that the switching module switches the flash memory connected to the control chip in the flash memory group when the clock signal changes from a falling edge to a rising edge.

[0023] The present application provides a large-capacity storage package chip and a data writing method. The package chip includes: a control chip, N flash memory groups, and N switching modules. The control chip includes N data channels, and each flash memory group includes M flash memories; wherein N and M are both positive integers, and N is greater than or equal to 1, and M is greater than or equal to 2; each data channel of the control chip is connected to a flash memory group; the control chip sends a switching signal to the corresponding switching module through the data channel, and the switching module switches the flash memory in the flash memory group connected to the control chip according to the switching signal; wherein the control chip only communicates with one flash memory in the flash memory group at the same time. In the present application, the data channel is not connected to a single flash memory, but to a flash memory group. The flash memory connected to the control chip is continuously switched among the flash memories in the flash memory group through the switching module, which is equivalent to expanding the total capacity of the flash memory connected to the control chip, and no additional data channels are required, which is low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a first structural diagram of a large-capacity storage package chip provided in an embodiment of the present application.

[0025] Figure 2 This is a second structural diagram of the large-capacity storage package chip provided in an embodiment of the present application.

[0026] Figure 3 This is a flow chart of a data writing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0029] See also Figure 1 , Figure 1 This is a first structural diagram of a large-capacity storage package chip provided by an embodiment of the present application. Figure 1As shown, the large-capacity storage package chip 1 includes: a control chip 10 , a first switching module 21 , a second switching module 22 , a first flash memory group 31 and a second flash memory group 32 .

[0030] Specifically, Figure 1 The switching module is not a software module, so each data channel or flash memory group corresponds to a switching module.

[0031] In some embodiments, the packaged chip 1 further includes a printed circuit board (PCB), and the control chip 10 , the switching module, and the flash memory group are all disposed on the printed circuit board (PCB).

[0032] Optionally, a central processing unit (CPU), namely a control chip, two double data rate synchronous dynamic random access memories (DDRSRAMs) and at least one flash memory group are provided in the printed circuit board.

[0033] Specifically, Figure 1 The system includes two switching modules, namely a first switching module 21 and a second switching module 22.

[0034] Specifically, Figure 1 The system includes two flash memory groups, namely a first flash memory group 31 and a second flash memory group 32. The first flash memory group 31 and the second flash memory group 32 each include two flash memories.

[0035] In some embodiments, the data channel referred to in the embodiments of the present application is a bus, such as a "Serial Peripheral Interface (SPI) bus", an "Inter-Integrated Circuit (I²C) bus", a "Quad SPI (QSPI) bus", a "Universal Serial Bus (USB)", a "Peripheral Component Interconnect express (PCIe)", etc. The bus defines the physical path, communication protocol and electrical specifications for data transmission between the control chip 10 and the flash memory.

[0036] Optionally, the control chip 10 includes a central processing unit (CPU) or a microcontroller (MCU).

[0037] Specifically, Figure 1 The control chip 10 includes a first data channel. The control chip 10 is connected to the first switching module 21 through the first data channel. The first switching module 21 is connected to the first flash memory group 31. The control chip 10 sends a switching signal to the first switching module 21 through the first data channel. The first switching module 21 switches the flash memory connected to the control chip 10 in the first flash memory group 31 according to the switching signal; wherein, the control chip only communicates with one flash memory in the first flash memory group 31 at the same time.

[0038] For example, when the first switching module 21 receives a switching signal, the first switching module 21 disconnects from the first flash memory 311 in the first flash memory group 31 and establishes a connection with the second flash memory 312 in the first flash memory group 31; when the first switching module 21 receives a switching signal again, the first switching module 21 disconnects from the second flash memory 312 in the first flash memory group 31 and establishes a connection with the first flash memory 311 in the first flash memory group 31, thereby writing data into the first flash memory 311 and the second flash memory 312 as needed, respectively, thereby expanding the storage capacity of the packaged chip.

[0039] Specifically, Figure 1 The control chip 10 includes a second data channel. The control chip 10 is connected to the second switching module 22 through the second data channel. The second switching module 22 is connected to the second flash memory group 32. The control chip 10 sends a switching signal to the second switching module 22 through the second data channel. The second switching module 22 switches the flash memory connected to the control chip 10 in the second flash memory group 32 according to the switching signal; wherein, the control chip only communicates with one flash memory in the second flash memory group 32 at the same time.

[0040] For example, when the second switching module 22 receives a switching signal, the second switching module 22 is disconnected from the third flash memory 321 in the second flash memory group 32, and is connected to the fourth flash memory 322 in the second flash memory group 32; when the second switching module 22 receives a switching signal again, the second switching module 22 is disconnected from the fourth flash memory 322 in the second flash memory group 32, and is connected to the third flash memory 321 in the second flash memory group 32, thereby writing data into the third flash memory 321 and the fourth flash memory 322 as needed, respectively, thereby expanding the storage capacity of the packaged chip.

[0041] It is understandable that the present application does not limit every data channel of the control chip 10 to be connected to the flash memory group 30. Some data channels of the control chip 10 may also be directly connected to a flash memory, for example Figure 1The control chip 10 may include eight data channels, the third to eighth data channels are directly connected to a flash memory, and only the first and second data channels are connected to the switching module to connect to the flash memory group. The number of flash memory groups can be selected according to needs and is not limited in this application.

[0042] In some embodiments, the packaged chip includes a control chip, N flash memory groups, and N switching modules. The control chip includes N data channels, and each of the flash memory groups includes M flash memories. Wherein, N and M are both positive integers, and N is greater than or equal to 1, and M is greater than or equal to 2.

[0043] Each data channel of the control chip is connected to a flash memory group;

[0044] The control chip sends a switching signal to the corresponding switching module through the data channel, and the switching module switches the flash memory connected to the control chip in the flash memory group according to the switching signal; wherein, the control chip only communicates with one flash memory in the flash memory group at the same time.

[0045] In some embodiments, the switching signal corresponds to a target flash memory, and the switching module switches the flash memory connected to the control chip in the flash memory group according to the switching signal, which means that the switching module disconnects the control chip from the current flash memory in the flash memory group and establishes a connection between the control chip and the target flash memory corresponding to the switching signal in the flash memory group.

[0046] In some embodiments, the switching module has a preset switching sequence. After receiving the switching information, the switching module switches the flash memory connected to the control chip according to the preset switching sequence.

[0047] In some embodiments, the switching module is a synchronous sequential circuit, and the switching signal is a clock signal;

[0048] The control chip sends a clock signal to the switching module through the data channel, and the switching module switches the flash memory in the flash memory group connected to the control chip according to the clock signal.

[0049] In some implementations, the switching module switches the flash memory in the flash memory group connected to the control chip when the clock signal is at a rising edge.

[0050] Please refer to Figure 2 , a second structural diagram of a large-capacity storage package chip provided in an embodiment of the present application. Figure 2 As shown, the packaged chip 1 includes: a main control chip 10 , a third switching module 23 and a third flash memory group 33 .

[0051] In some embodiments, the third switching module 23 is a synchronous sequential circuit, and the third switching module 23 includes three D flip-flops and a multiplexer.

[0052] Specifically, a D flip-flop is a digital logic circuit with memory functionality that can store one bit of binary information. It is the basic unit of sequential logic circuits and is widely used in digital systems and computers. The main features and functions of a D flip-flop include:

[0053] Memory function: The D flip-flop has two stable states, usually represented as 0 and 1, which can store data.

[0054] Data transmission: Under the action of the clock pulse, the D flip-flop will transmit the signal at its data input terminal (D) to the output terminal (Q), that is, the next state (next state) Qn+1 is equal to the current input D, that is, Qn+1 = D.

[0055] Edge triggered: Common D flip-flops are edge triggered, which means that the input data will be sampled and stored only at the rising or falling edge of the clock pulse (CP). This ensures that changes in the input signal during the high or low level of the clock pulse will not affect the output state, providing data stability.

[0056] State retention: When no new clock pulse arrives, the D flip-flop will keep the current output state unchanged, that is, it has the function of maintenance and memory.

[0057] Specifically, a multiplexer can perform signal routing control, allowing specific input signals to be selected and transmitted to the output based on the control signal. For example, in a communication system, different data streams can be selected for transmission based on demand, or in test and measurement equipment, different sensor signals can be switched for acquisition.

[0058] In some embodiments, the control chip 10 is connected to three D flip-flops, and is used to send a clock signal to each D flip-flop to control the 01 signal output by the D flip-flop. The multiplexer receives the 01 signal output by the three D flip-flops and switches the flash memory connected to the control chip 10 according to the signal.

[0059] Exemplarily, when the first D flip-flop outputs a 1 signal and the second and third D flip-flops output a 0 signal, the multiplexer controls the control chip 10 to be connected to the fifth flash memory; when the first and second D flip-flops output a 1 signal and the third D flip-flop outputs a 0 signal, the multiplexer controls the control chip 10 to be connected to the sixth flash memory; when the first, second, and third D flip-flops output a 1 signal, the multiplexer controls the control chip 10 to be connected to the seventh flash memory.

[0060] It is understandable that Figure 2It is only used to illustrate an optional structure when the switching module is a synchronous sequential circuit and should not be understood as a limitation to the present application.

[0061] In some embodiments, multiple flash memories in a flash memory group are stacked in a vertical direction, thereby preventing the flash memories from occupying too large an area and compressing the arrangement space of other devices.

[0062] In some embodiments, the switching module is a software module, and each data channel of the control chip is directly connected to each flash memory in the corresponding flash memory group.

[0063] Specifically, if the switching module is a software module, the number of switching modules is one, and the switching signal may include addressing information and load information, wherein the addressing information is used to uniquely identify a flash memory in the flash memory group, and the load information is the data that needs to be sent to the flash memory.

[0064] In some embodiments, the switching module is a software module in the control chip.

[0065] Please refer to Figure 3 , Figure 3 1 is a flow chart of a data writing method provided in an embodiment of the present application. The method 100 includes: steps 110 to 120.

[0066] Step 110: Send a control signal to the switching module connected to the data channel, so that the switching module switches the flash memory connected to the control chip in the flash memory group according to the control signal.

[0067] In some embodiments, the control chip communicates with only one flash memory in the flash memory group at a time, so the control signal causes the control chip to switch from connecting with the current flash memory to connecting with the target flash memory.

[0068] Step 120: Write the data to be written into a flash memory connected to the control chip.

[0069] By using the above method, data is written into different flash memories as required, thereby increasing storage capacity.

[0070] In some embodiments, step 120 includes the following steps.

[0071] (1) Obtain the preset switching rules corresponding to the data channel;

[0072] (2) When the preset switching rule is met, a control signal is sent to the switching module connected to the data channel, so that the switching module switches the flash memory in the flash memory group connected to the control chip according to the control signal.

[0073] In some embodiments, the preset switching rule includes whether the connection time of the flash memory connected to the control chip in the current channel reaches a preset time.

[0074] Optionally, the preset time corresponding to each flash memory is the same.

[0075] Through the above method, data can be written to different flash memories as needed. Because flash memories have a life limit of erase and write times, if data is always written to the same flash memory, the life of the flash memory will drop rapidly compared to other flash memories. Writing data to different flash memories based on time not only increases the storage capacity, but also balances the life of the flash memories in the flash memory group.

[0076] In some implementations, the preset switching rule includes whether power-on of the control chip is detected.

[0077] In this way, data is written to different flash memories each time the power is turned on, which not only expands the capacity but also makes data writing more regular, thereby reducing the difficulty and obstacles of subsequent data reading.

[0078] In some embodiments, a storage space for storing the number of power-on times is preset in each flash memory. When the control chip is powered on, the switching module switches the control chip to connect with the target flash memory. At this time, the control chip will first write the current number of power-on times in the power-on times storage space, for example, write 0x0001 to represent that the number of power-on times is 1, and then write the data.

[0079] When the data in the flash memory needs to be read subsequently, the control chip first determines the power-on count when the data to be read is written, and queries whether the power-on count storage space of the currently connected flash memory contains the power-on count. If not, a control signal is sent to the switching module to query the power-on count storage space of the next flash memory until the flash memory where the data was written is found and the data is read again.

[0080] By adopting the above method, it is not necessary to go through all the data in the flash memory one by one when reading data, thereby improving the data reading efficiency.

[0081] In some embodiments, step 120 includes the steps of: sending a clock signal of a preset period to a switching module connected to the data channel, so that the switching module switches the flash memory connected to the control chip in the flash memory group when the clock signal changes from a falling edge to a rising edge.

[0082] Optionally, the switching module may also switch the flash memory in the flash memory group connected to the control chip when the clock signal changes from a rising edge to a falling edge, and this application does not impose any limitation thereto.

[0083] In some embodiments, if the switching module includes a plurality of D flip-flops, the control chip needs to send a clock signal of a plurality of preset cycles to each D flip-flop.

[0084] In summary, the present application provides a large-capacity storage package chip and a data writing method, the package chip comprising: a control chip, N flash memory groups and N switching modules, the control chip comprising N data channels, each of the flash memory groups comprising M flash memories; wherein N and M are both positive integers, and N is greater than or equal to 1, and M is greater than or equal to 2; each data channel of the control chip is connected to a flash memory group; the control chip sends a switching signal to the corresponding switching module through the data channel, and the switching module switches the flash memory in the flash memory group connected to the control chip according to the switching signal; wherein the control chip communicates with only one flash memory in the flash memory group at the same time. In the present application, the data channel is not connected to a single flash memory, but to a flash memory group. The flash memory connected to the control chip is continuously switched among the flash memories in the flash memory group through the switching module, which is equivalent to expanding the total capacity of the flash memory connected to the control chip, and no additional data channels are required, which is low in cost.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A large-capacity storage package chip, characterized in that: The packaged chip includes a control chip, N flash memory groups, and N switching modules. The control chip includes N data channels, and each flash memory group includes M flash memories. Wherein, N and M are both positive integers, and N is greater than 1, and M is greater than or equal to 2. Each data channel of the control chip is connected to a flash memory group, and multiple flash memories in the flash memory group are stacked in a vertical direction; The control chip sends a switching signal to the corresponding switching module through the data channel, and the switching module switches the flash memory in the flash memory group connected to the control chip according to the switching signal; wherein, the control chip only communicates with one flash memory in the flash memory group at the same time, and the control chip obtains a preset switching rule corresponding to the data channel; when the preset switching rule is met, the control chip sends a control signal to the switching module connected to the data channel, so that the switching module switches the flash memory in the flash memory group connected to the control chip according to the control signal, and the preset switching rule includes whether the connection time of the flash memory connected to the control chip in the current channel reaches a preset time, whether the control chip is detected to be powered on, or switching the flash memory connected to the control chip according to a preset switching order; The switching module is a software module, and each data channel of the control chip is directly connected to each flash memory in the corresponding flash memory group; The switching signal corresponds to a target flash memory, and the switching module disconnects the control chip from the current flash memory in the flash memory group and establishes a connection between the control chip and the target flash memory corresponding to the switching signal in the flash memory group. The switching signal includes addressing information and load information. The addressing information is used to uniquely identify a flash memory in the flash memory group, and the load information is data that needs to be sent to the flash memory. A storage space for storing the number of power-on times is preset in each of the flash memories. When the control chip is powered on, the switching module switches the control chip to connect with the target flash memory. The control chip first writes the current number of power-on times into the power-on times storage space and then writes data. When it is necessary to read the data in the flash memory, the control chip first determines the power-on times when the data to be read is written, and queries whether the power-on times storage space of the currently connected flash memory contains the power-on times. If not, a control signal is sent to the switching module to query the power-on times storage space of the next flash memory, until the flash memory where the data is written is found and the data is read again.

2. The large-capacity storage package chip according to claim 1, characterized in that: The switching module is a synchronous timing circuit, and the switching signal is a clock signal; The control chip sends a clock signal to the switching module through the data channel, and the switching module switches the flash memory in the flash memory group connected to the control chip according to the clock signal.

3. The large-capacity storage package chip according to claim 2, characterized in that: The switching module switches the flash memory in the flash memory group connected to the control chip when the clock signal is at a rising edge.

4. The large-capacity storage package chip according to claim 1, characterized in that: The switching module is a software module, and each data channel of the control chip is directly connected to each flash memory in the corresponding flash memory group.

5. A method for writing data to a large-capacity storage package chip according to any one of claims 1 to 4, characterized in that: The method comprises: Sending a control signal to a switching module connected to the data channel, so that the switching module switches the flash memory connected to the control chip in the flash memory group according to the control signal; The data to be written is written into the flash memory connected to the control chip.

6. The method according to claim 5, characterized in that The sending of a control signal to the switching module connected to the data channel so that the switching module switches the flash memory connected to the control chip in the flash memory group according to the control signal includes: A clock signal of a preset period is sent to a switching module connected to the data channel, so that the switching module switches the flash memory connected to the control chip in the flash memory group when the clock signal changes from a falling edge to a rising edge.

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