Intelligent identification method and system for component structure based on semiconductor memory chip

Abstract

The present invention relates to the field of semiconductor technology, and discloses a method and system for intelligent identification of component structures based on semiconductor memory chips, the method comprising: collecting memory chip images of semiconductor memory chips; constructing a noise probability distribution model of the memory chip images, constructing a denoising function of the memory chip images, removing noise from the memory chip images, and obtaining denoised memory chip images; constructing an adaptive threshold segmentation model of structure identification training images, and using the adaptive threshold segmentation model to segment the structure identification training images to obtain segmented training images; constructing a deep learning network of the segmented training images, establishing a component structure identification model of the denoised memory chip images, analyzing the structural composition of the denoised memory chip images, identifying the abnormal coefficients of the structural composition, and constructing a component structure analysis report of the semiconductor memory chip. The present invention can improve the accuracy of identifying the component structures of semiconductor memory chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and system for intelligently identifying a component structure based on a semiconductor storage chip. Background Art

[0002] Intelligent identification of the composition structure of semiconductor memory chips uses computer vision and machine learning technology to automatically analyze the chip microstructure to achieve structural detection, classification and defect identification. The effects include improving production efficiency, reducing costs, improving product quality and reliability, while promoting technological innovation and achieving real-time monitoring of production lines and data-driven decision-making.

[0003] At present, the intelligent identification of the composition structure of semiconductor memory chips is mainly done by operators examining the chips with a microscope or using preset rules and template matching technology to identify the chip structure. This method is difficult to adapt to the diverse defect types and structural changes, making it impossible to identify a large number of defects in a timely manner, resulting in inaccurate identification of the composition structure of semiconductor memory chips. Summary of the invention

[0004] The present invention provides a method and system for intelligently identifying the component structure of a semiconductor memory chip, the main purpose of which is to improve the accuracy of identifying the component structure of a semiconductor memory chip.

[0005] To achieve the above-mentioned purpose, the present invention provides a method for intelligently identifying the composition structure of a semiconductor memory chip, comprising:

[0006] Determining a structural recognition requirement of a semiconductor storage chip, building a microscope cluster of the semiconductor storage chip based on the structural recognition requirement, and collecting a storage chip image of the semiconductor storage chip based on the microscope cluster;

[0007] Constructing a noise probability distribution model of the storage chip image, constructing a denoising function of the storage chip image based on the noise probability distribution model, and removing noise from the storage chip image based on the denoising function to obtain a denoised storage chip image;

[0008] Acquire a structure recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structure recognition training image, and segment the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image;

[0009] Constructing a deep learning network for the segmentation training image, wherein the deep learning network includes a CNN network, an RNN network, and a GAN network, using the CNN network to extract hierarchical features of the segmentation training image, using the RNN network to analyze the temporal relationship of the segmentation training image corresponding to the image structure, and using the GAN network to construct diversified training images of the segmentation training image;

[0010] A composition structure recognition model of the denoised storage chip image is established by utilizing the hierarchical features, the temporal relationship and the diversified training images. The structural composition of the denoised storage chip image is analyzed based on the composition structure recognition model to identify the abnormal coefficient of the structural composition. Based on the structural composition and the abnormal coefficient, a composition structure analysis report of the semiconductor storage chip is constructed.

[0011] Optionally, determining the structural identification requirement of the semiconductor storage chip includes:

[0012] Obtaining a design drawing of the semiconductor memory chip;

[0013] Based on the design drawings, identifying key structural elements of the semiconductor memory chip;

[0014] identifying structural element characteristics of the key structural elements;

[0015] Analyzing the recognition accuracy requirements of the semiconductor storage chip based on the structural element characteristics;

[0016] Based on the recognition accuracy requirement, a structural recognition requirement of the semiconductor storage chip is determined.

[0017] Optionally, the step of constructing a microscope cluster of the semiconductor storage chip based on the structure recognition requirement includes:

[0018] Based on the structure recognition requirement, determining microscope indicators of the semiconductor memory chip, wherein the microscope indicators include resolution, magnification, and imaging speed;

[0019] constructing a microscope layout of the semiconductor memory chip based on the design drawings corresponding to the structural recognition requirements;

[0020] Based on the microscope indicator, configuring a target microscope of a layout node corresponding to the microscope layout;

[0021] Constructing a data transmission network for the target microscope;

[0022] Calibrate the target microscope through the data transmission network to obtain a calibrated microscope;

[0023] constructing an initial microscope cluster of the calibration microscopes;

[0024] analyzing a synergy coefficient of the initial microscope cluster;

[0025] When the synergy coefficient meets a preset synergy threshold, the initial microscope cluster is used as a microscope cluster.

[0026] Optionally, analyzing the synergy coefficient of the initial microscope cluster comprises:

[0027] Performing operation simulation on the initial microscope cluster to obtain simulation results;

[0028] Dividing the simulation results into normal operation results and abnormal operation results;

[0029] Based on the normal operation results, analyzing the image quality, data transmission efficiency and system response time of the operation simulation performed by the initial microscope cluster;

[0030] Based on the abnormal operation result, determining the fault recovery parameter and maintainability coefficient of the initial microscope cluster;

[0031] Based on the image quality, the data transmission efficiency, the system response time, the fault recovery parameter and the maintainability coefficient, the synergy coefficient of the initial microscope cluster is calculated using the following formula:

[0032]

[0033] in represents the synergy coefficient of the initial microscope cluster, Indicates image quality, Indicates the data transmission efficiency, Indicates the system response time. Indicates the fault recovery parameter corresponding to the fault detection speed, Indicates the fault recovery parameter corresponding to the fault response time. Indicates the fault recovery parameters corresponding to the fault processing time. Indicates the fault recovery parameters corresponding to the fault reconstruction time. Represents the maintainability factor.

[0034] Optionally, constructing the noise probability distribution model of the storage chip image includes:

[0035] Determining a suitable environment for noise analysis of the storage chip image;

[0036] Preprocessing the storage chip image through the noise analysis suitable environment to obtain a processed storage chip image;

[0037] Identifying the noise type of the processed storage chip image;

[0038] Based on the noise type, analyzing the noise intensity of the processed storage chip image;

[0039] Based on the noise intensity, a noise probability distribution model for processing the storage chip image is constructed.

[0040] Optionally, constructing a noise probability distribution model of the storage chip image based on the noise intensity includes:

[0041] Based on the noise intensity, determining a noise intensity mean and a noise intensity standard deviation of the processed storage chip image;

[0042] Based on the noise intensity, the noise intensity mean and the noise intensity standard deviation, the noise probability function of the processed storage chip image is constructed using the following formula:

[0043]

[0044] in, represents the noise probability function, represents the noise intensity of the processed storage chip image, represents the standard deviation of the noise intensity of the processed storage chip image, represents the mean noise intensity of the processed storage chip image, represents the base of natural logarithms, Indicates the noise intensity Close to the mean noise intensity the extent of;

[0045] Based on the noise probability function, a noise probability distribution model of the storage chip image is constructed.

[0046] Optionally, the segmenting the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image includes:

[0047] Analyzing the HOG map of the structure recognition training image;

[0048] Based on the HOG map, identifying training image features of the structure recognition training image;

[0049] Based on the training image features, using the adaptive threshold segmentation model, determining the segmentation threshold of the pixel points corresponding to the structure recognition training image;

[0050] The structure recognition training image is segmented based on the segmentation threshold to obtain the segmented training image.

[0051] Optionally, the extracting hierarchical features of the segmented training image using the CNN network includes:

[0052] Standardizing the segmentation training image to obtain a standard segmentation training image;

[0053] Determine the CNN network architecture of the standard segmentation training image;

[0054] Using the standard segmentation training image to train the CNN network architecture to obtain a training CNN network;

[0055] Identifying the prediction loss of the trained CNN network;

[0056] Based on the prediction loss, the weight of the training CNN network is adjusted using a preset back-propagation algorithm to obtain a target CNN network;

[0057] The hierarchical features of the segmented training image are extracted based on the target CNN network, wherein the hierarchical features include low-level features and high-level features.

[0058] Optionally, the using the RNN network to analyze the temporal relationship between the segmented training images and the corresponding image structures includes:

[0059] Serializing the segmented training images to obtain sequence training images;

[0060] Using the standard segmentation training image to train the RNN network architecture to obtain a training RNN network;

[0061] When the performance of the training RNN network meets a preset performance threshold, using the training RNN network as a target RNN network;

[0062] Based on the target RNN network, the hidden state and time step output of the sequence training image are analyzed using the following formula:

[0063]

[0064]

[0065] in, Represents the time step The hidden state of represents the sequence training images, Represents the time step The hidden state of represents an LSTM (Long Short-Term Memory) or GRU (Gated Recurrent Unit) neural network unit, Represents the time step The time step output is represents a fully connected layer, which contains multiple neurons, each of which is connected to every neuron in the input layer;

[0066] Based on the hidden state and time step output, the temporal relationship between the sequence training images and the corresponding image structures is analyzed.

[0067] In order to solve the above problems, the present invention also provides a composition structure intelligent recognition system based on a semiconductor storage chip, the system comprising:

[0068] A storage chip image acquisition module, used to determine the structural recognition requirements of the semiconductor storage chip, build a microscope cluster of the semiconductor storage chip based on the structural recognition requirements, and acquire a storage chip image of the semiconductor storage chip based on the microscope cluster;

[0069] A chip image noise removal module is used to construct a noise probability distribution model of the storage chip image, construct a denoising function of the storage chip image based on the noise probability distribution model, and remove noise from the storage chip image based on the denoising function to obtain a denoised storage chip image;

[0070] A training image segmentation module, used to obtain a structure recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structure recognition training image, and segment the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image;

[0071] A segmentation training image analysis module, used to construct a deep learning network for the segmentation training image, wherein the deep learning network includes a CNN network, an RNN network and a GAN network, the CNN network is used to extract the hierarchical features of the segmentation training image, the RNN network is used to analyze the temporal relationship of the segmentation training image corresponding to the image structure, and the GAN network is used to construct a diversified training image of the segmentation training image;

[0072] The composition structure analysis module is used to establish a composition structure recognition model of the denoised storage chip image by using the hierarchical features, the temporal relationship and the diversified training images, analyze the structural composition of the denoised storage chip image based on the composition structure recognition model, identify the abnormal coefficient of the structural composition, and construct a composition structure analysis report of the semiconductor storage chip based on the structural composition and the abnormal coefficient.

[0073] Based on the structural recognition requirement, the present invention constructs a microscope cluster of the semiconductor memory chip to monitor the structural image of the semiconductor memory chip and provide a basis for subsequent structural analysis; optionally, based on the microscope cluster, the present invention collects the memory chip image of the semiconductor memory chip to improve the basic image for the subsequent microstructure analysis of the chip; the present invention constructs a noise probability distribution model of the memory chip image to provide a basis for the subsequent image denoising algorithm design, thereby improving the reliability of image noise removal; based on the noise probability distribution model, the present invention constructs a denoising function of the memory chip image to remove noise in the image, improve image quality and the accuracy of subsequent analysis, and the present invention uses the adaptive threshold segmentation model to The structure recognition training image is segmented, and the segmented training image obtained can be used to train and optimize the structure recognition model to improve production efficiency and product quality. The present invention uses the RNN network to analyze the temporal relationship of the image structure corresponding to the segmented training image to capture the time dependency in the image sequence, thereby improving the accuracy and reliability of chip structure composition recognition. Finally, the present invention analyzes the structural composition of the denoised storage chip image based on the composition structure recognition model to better understand the working principle and performance characteristics of the storage chip, thereby better identifying the composition structure of the storage chip and based on the structural composition and the abnormal coefficient, constructing the composition structure analysis report of the semiconductor storage chip can better understand the working principle and performance characteristics of the storage chip. Therefore, the present invention can improve the accuracy of the composition structure recognition of semiconductor storage chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 1 A schematic diagram of a flow chart of a method for intelligently identifying a component structure of a semiconductor memory chip provided by an embodiment of the present invention;

[0075] Figure 2 A functional module diagram of a composition structure intelligent identification system based on a semiconductor memory chip provided by an embodiment of the present invention;

[0076] Figure 3 A schematic diagram of the structure of an electronic device of a composition structure intelligent identification system based on a semiconductor memory chip provided by an embodiment of the present invention;

[0077] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0078] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0079] The embodiment of the present application provides a method for intelligently identifying a composition structure based on a semiconductor storage chip. The execution subject of the method for intelligently identifying a composition structure based on a semiconductor storage chip includes but is not limited to at least one of the electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided in the embodiment of the present application. In other words, the method for intelligently identifying a composition structure based on a semiconductor storage chip can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc. The server can be an independent server, or it can be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), and big data and artificial intelligence platforms.

[0080] Reference Figure 1 FIG. 1 is a flow chart of a method for intelligently identifying a component structure of a semiconductor memory chip according to an embodiment of the present invention. In this embodiment, the method for intelligently identifying a component structure of a semiconductor memory chip comprises:

[0081] S1. Determine a structural recognition requirement of a semiconductor storage chip, build a microscope cluster of the semiconductor storage chip based on the structural recognition requirement, and collect a storage chip image of the semiconductor storage chip based on the microscope cluster.

[0082] The present invention can provide a basis for constructing a subsequent identification method by determining the structural identification requirements of a semiconductor storage chip.

[0083] In detail, the determining of the structural identification requirements of the semiconductor storage chip includes:

[0084] Obtaining a design drawing of the semiconductor memory chip;

[0085] Based on the design drawings, identifying key structural elements of the semiconductor memory chip;

[0086] identifying structural element characteristics of the key structural elements;

[0087] Analyzing the recognition accuracy requirements of the semiconductor storage chip based on the structural element characteristics;

[0088] Based on the recognition accuracy requirement, a structural recognition requirement of the semiconductor storage chip is determined.

[0089] Among them, the design drawing refers to the detailed design blueprint of the semiconductor memory chip, which usually exists in electronic form and contains all the design details of the chip, such as circuit layout, device size, connection method, etc. The key structural elements refer to the parts of the design drawings that are crucial to the function of the chip, which include but are not limited to storage units, circuit layout, registers, logic gates and other electronic components. The structural element characteristics refer to the physical and electrical characteristics of the key structural elements, which may include size, shape, material and other characteristics. The recognition accuracy requirement refers to the level of accuracy that the structure recognition system must achieve in order to ensure the function and performance of the chip, such as spatial resolution, feature accuracy, false detection and missed detection rate, etc. The structure recognition requirement refers to the specific requirements for the semiconductor memory chip structure recognition system, such as the list of structural elements, the recognition accuracy of structural elements, the abnormal recognition of the structure, etc.

[0090] Furthermore, the structural element features for identifying the key structural elements may be extracted by edge detection.

[0091] Based on the structural recognition requirement, the present invention constructs a microscope cluster of the semiconductor memory chip to monitor the structural image of the semiconductor memory chip and provide a basis for subsequent structural analysis. The microscope cluster refers to an integrated microscope system, including scanning electron microscopes, transmission electron microscopes, atomic force microscopes, optical microscopes and other microscopes.

[0092] In detail, the construction of the microscope cluster of the semiconductor storage chip based on the structure recognition requirement includes:

[0093] Based on the structure recognition requirement, determining microscope indicators of the semiconductor memory chip, wherein the microscope indicators include resolution, magnification, and imaging speed;

[0094] constructing a microscope layout of the semiconductor memory chip based on the design drawings corresponding to the structural recognition requirements;

[0095] Based on the microscope indicator, configuring a target microscope of a layout node corresponding to the microscope layout;

[0096] Constructing a data transmission network for the target microscope;

[0097] Calibrate the target microscope through the data transmission network to obtain a calibrated microscope;

[0098] constructing an initial microscope cluster of the calibration microscopes;

[0099] analyzing a synergy coefficient of the initial microscope cluster;

[0100] When the synergy coefficient meets a preset synergy threshold, the initial microscope cluster is used as a microscope cluster.

[0101] Among them, the resolution refers to the minimum detail size that a microscope can clearly display, usually in nanometers (nm); the magnification refers to the magnification factor of the microscope, which affects the size of the observed details; the imaging speed refers to the speed at which a microscope generates images, usually in frames per second (fps); the microscope layout refers to the physical arrangement and configuration of microscopes in a microscope cluster, including the distance between them, the angle between each other, and the relative position to the sample; the target microscope is the microscope selected for use in the cluster based on structure recognition requirements and microscope indicators; the data transmission network refers to a network connecting microscopes and subsequent processing systems (such as image analysis software) to ensure rapid transmission of image data; the calibrated microscope refers to a microscope that is calibrated through a data transmission network to ensure the accuracy and consistency of its output images; the initial microscope cluster refers to a collection of microscopes configured according to the microscope layout and the target microscope, used for initial analysis and testing; the synergy coefficient refers to the degree of collaborative work between the microscopes in the initial microscope cluster and with the subsequent processing system.

[0102] Furthermore, the construction of the data transmission network of the target microscope can be achieved through communication protocol technology.

[0103] Further, the analyzing the synergy coefficient of the initial microscope cluster includes:

[0104] Performing operation simulation on the initial microscope cluster to obtain simulation results;

[0105] Dividing the simulation results into normal operation results and abnormal operation results;

[0106] Based on the normal operation results, analyzing the image quality, data transmission efficiency and system response time of the operation simulation performed by the initial microscope cluster;

[0107] Based on the abnormal operation result, determining the fault recovery parameter and maintainability coefficient of the initial microscope cluster;

[0108] Based on the image quality, the data transmission efficiency, the system response time, the fault recovery parameter and the maintainability coefficient, the synergy coefficient of the initial microscope cluster is calculated using the following formula:

[0109]

[0110] in represents the synergy coefficient of the initial microscope cluster, Indicates image quality, Indicates the data transmission efficiency, Indicates the system response time. Indicates the fault recovery parameter corresponding to the fault detection speed, Indicates the fault recovery parameter corresponding to the fault response time. Indicates the fault recovery parameters corresponding to the fault processing time. Indicates the fault recovery parameters corresponding to the fault reconstruction time. Represents the maintainability factor.

[0111] Among them, the simulation result refers to the simulated operation of the microscope cluster by simulating the actual operating environment to predict its performance in actual production. The normal operation result refers to the operation result without any fault or abnormality during the simulation process, which reflects the performance of the microscope cluster under normal circumstances. The abnormal operation result refers to the operation result of a fault or abnormality that occurred during the simulation process. The image quality refers to the comprehensive quality of the image output by the microscope cluster. The data transmission efficiency refers to the transmission speed and stability of data from the microscope cluster to the subsequent processing system. The system response time refers to the response speed of the microscope cluster to operating instructions. The maintainability coefficient refers to the difficulty of maintaining and upgrading the microscope cluster. The fault detection speed refers to the speed at which the system detects a fault and issues an alarm. The fault response time refers to the time from fault detection to the start of action. The fault handling time refers to the time from the start of fault handling to the restoration of normal operation. The fault reconstruction time refers to the time from the completion of fault handling to the complete restoration of system normal operation.

[0112] The present invention is based on the microscope cluster, and collecting the memory chip image of the semiconductor memory chip can provide a basic image for the subsequent microstructure analysis of the chip. In detail, the memory chip image refers to an image obtained by performing high-resolution imaging of the semiconductor memory chip by the microscope cluster.

[0113] S2. Construct a noise probability distribution model of the storage chip image, construct a denoising function of the storage chip image based on the noise probability distribution model, and remove noise from the storage chip image based on the denoising function to obtain a denoised storage chip image.

[0114] The noise probability distribution model of the storage chip image constructed by the present invention can provide a basis for the subsequent image denoising algorithm design, thereby improving the reliability of image noise removal.

[0115] In detail, the step of constructing the noise probability distribution model of the storage chip image includes:

[0116] Determining a suitable environment for noise analysis of the storage chip image;

[0117] Preprocessing the storage chip image through the noise analysis suitable environment to obtain a processed storage chip image;

[0118] Identifying the noise type of the processed storage chip image;

[0119] Based on the noise type, analyzing the noise intensity of the processed storage chip image;

[0120] Based on the noise intensity, a noise probability distribution model for processing the storage chip image is constructed.

[0121] Among them, the suitable environment for noise analysis refers to providing stable and consistent environmental conditions for the storage chip image during the noise analysis process so as to accurately identify and analyze the noise. The processing of the storage chip image refers to preprocessing the original storage chip image to improve the image quality and facilitate noise analysis and subsequent processing. Preprocessing may include steps such as adjusting brightness, contrast, filtering and denoising. The noise type refers to the type of noise present in the storage chip image, such as Gaussian noise, salt and pepper noise, impulse noise, etc. The noise intensity refers to the intensity or density of the noise, which is usually quantified by the mean and standard deviation of the noise. The noise probability distribution model refers to a probability distribution model constructed to accurately describe the noise characteristics in the storage chip image.

[0122] Furthermore, constructing a noise probability distribution model of the storage chip image based on the noise intensity includes:

[0123] Based on the noise intensity, determining a noise intensity mean and a noise intensity standard deviation of the processed storage chip image;

[0124] Based on the noise intensity, the noise intensity mean and the noise intensity standard deviation, the noise probability function of the processed storage chip image is constructed using the following formula:

[0125]

[0126] in, represents the noise probability function, represents the noise intensity of the processed storage chip image, represents the standard deviation of the noise intensity of the processed storage chip image, represents the mean noise intensity of the processed storage chip image, represents the base of natural logarithms, Indicates the noise intensity Close to the mean noise intensity the extent of;

[0127] Based on the noise probability function, a noise probability distribution model of the storage chip image is constructed.

[0128] The present invention constructs a denoising function for the storage chip image based on the noise probability distribution model to remove the noise in the image, thereby improving the image quality and the accuracy of subsequent analysis. The model parameters refer to designing an algorithm or method that can estimate the noise in the storage chip image based on the parameters of the noise probability distribution model (such as mean, variance, etc.), and subtract the noise from the original image to obtain a denoised image.

[0129] It should be explained that the denoised memory chip image refers to the memory chip image obtained after being processed by the denoising function. In detail, the denoising of the memory chip image based on the denoising function refers to estimating the noise value of each pixel point through the denoising function and subtracting the noise value from the original image to obtain the denoised image.

[0130] S3, obtaining a structure recognition training image of the semiconductor memory chip, constructing an adaptive threshold segmentation model for the structure recognition training image, and using the adaptive threshold segmentation model to segment the structure recognition training image to obtain a segmented training image.

[0131] It should be explained that the structural recognition training images refer to images containing key structural features of memory chips. These images are used to train the structural recognition model so that it can accurately identify and classify different parts of the memory chip, such as storage cells, circuit connections, defects, etc. The structural recognition training images are usually obtained by: laboratory collection, production site collection, historical data, simulation generation, etc.

[0132] In detail, the adaptive threshold segmentation model refers to a model that can automatically adjust the segmentation threshold according to image features, and the model can adaptively segment the training image of the memory chip to accurately identify and classify the different parts of the memory chip. The steps of constructing the adaptive threshold segmentation model include: designing the model architecture, training the model architecture using the labeled structure recognition training image, evaluating the performance of the segmentation model after training, adjusting the model structure and parameters according to the evaluation results, iterative optimization, and finally integrating the trained adaptive threshold segmentation model into the production environment. Through these steps, an adaptive threshold segmentation model can be constructed for structural recognition and classification of memory chip images.

[0133] The present invention utilizes the adaptive threshold segmentation model to segment the structure recognition training image, and the obtained segmented training image can be used to train and optimize the structure recognition model, thereby improving production efficiency and product quality.

[0134] In detail, the step of segmenting the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image includes:

[0135] Analyzing the HOG map of the structure recognition training image;

[0136] Based on the HOG map, identifying training image features of the structure recognition training image;

[0137] Based on the training image features, using the adaptive threshold segmentation model, determining the segmentation threshold of the pixel points corresponding to the structure recognition training image;

[0138] The structure recognition training image is segmented based on the segmentation threshold to obtain the segmented training image.

[0139] Among them, the HOG map calculates the gradient direction and intensity of each pixel in the image, and statistics the histogram of the gradient values ​​in these directions. The training image features refer to the features extracted from the structure recognition training image, which can be used for training and recognition models. The segmentation threshold refers to the threshold used to determine whether a pixel belongs to a segmentation area in the adaptive threshold segmentation model. The segmented training image refers to the image obtained after segmenting the structure recognition training image through the adaptive threshold segmentation model.

[0140] Furthermore, the identification of the training image features of the structure recognition training image based on the HOG map can be performed based on a statistical method (such as feature selection), a model-based method (such as regularization technology) or a visualization-based method (such as visual analysis of features) to perform feature evaluation to obtain feature evaluation results, and based on the evaluation results, the most useful features are selected to obtain the training image features. This can be achieved by retaining the first n features, using a feature selection algorithm (such as recursive feature elimination, model-based feature selection, etc.) or combining multiple strategies.

[0141] S4. Construct a deep learning network for the segmentation training image, wherein the deep learning network includes a CNN network, an RNN network and a GAN network, use the CNN network to extract hierarchical features of the segmentation training image, use the RNN network to analyze the temporal relationship of the segmentation training image corresponding to the image structure, and use the GAN network to construct diversified training images of the segmentation training image.

[0142] It should be explained that the CNN network refers to a deep learning network specifically used to process image data. It extracts local features of the image through convolutional layers and reduces the size of feature maps through pooling layers, thereby reducing computational complexity. The RNN network refers to a deep learning network that can process sequence data. It maintains internal states through cyclic units, allowing the model to process sequence data of any length. The GAN network refers to a generative model consisting of two neural networks: a generator and a discriminator. The generator tries to generate images that are as realistic as possible, while the discriminator tries to distinguish between generated images and real images.

[0143] In detail, the step of extracting the hierarchical features of the segmented training image using the CNN network includes:

[0144] Standardizing the segmentation training image to obtain a standard segmentation training image;

[0145] Determine the CNN network architecture of the standard segmentation training image;

[0146] Using the standard segmentation training image to train the CNN network architecture to obtain a training CNN network;

[0147] Identifying the prediction loss of the trained CNN network;

[0148] Based on the prediction loss, the weight of the training CNN network is adjusted using a preset back-propagation algorithm to obtain a target CNN network;

[0149] The hierarchical features of the segmented training image are extracted based on the target CNN network, wherein the hierarchical features include low-level features and high-level features.

[0150] The standard segmentation training image refers to a segmentation training image that has been standardized. Standardization usually includes normalization processing, which scales the pixel values ​​of the image to a specific range, such as between 0 and 1, to reduce the differences between different images and make network training more stable and efficient. The CNN network architecture refers to the hierarchical structure of CNN, including convolutional layers, pooling layers, fully connected layers, etc. The design of the network architecture will affect the learning ability and performance of the network. The training CNN network refers to the process of training the CNN network using a segmentation training image data set. The prediction loss refers to the difference between the prediction result of the network and the actual label. The back propagation algorithm refers to a method for calculating the gradient of the network weight and adjusting the network weight accordingly. The target CNN network refers to the optimized network obtained after adjusting the weight through the back propagation algorithm. The bottom-level features refer to the features extracted by the early convolutional layers of the CNN network, which usually reflect the low-level visual information of the image, such as edges, textures, etc. The high-level features refer to the features extracted by the later convolutional layers of the CNN network, which usually reflect the high-level visual information of the image, such as objects, categories, etc.

[0151] Furthermore, the identification of the prediction loss of the trained CNN network can be achieved through a loss function, and the loss function is used to quantify the accuracy of the prediction. Commonly used loss functions include cross entropy loss, mean square error and other functions.

[0152] The present invention utilizes the RNN network to analyze the temporal relationship between the segmented training images and the corresponding image structures, thereby capturing the temporal dependency in the image sequence, thereby improving the accuracy and reliability of chip structure composition recognition.

[0153] In detail, the using of the RNN network to analyze the temporal relationship of the segmented training image corresponding to the image structure includes:

[0154] Serializing the segmented training images to obtain sequence training images;

[0155] Using the standard segmentation training image to train the RNN network architecture to obtain a training RNN network;

[0156] When the performance of the training RNN network meets a preset performance threshold, using the training RNN network as a target RNN network;

[0157] Based on the target RNN network, the hidden state and time step output of the sequence training image are analyzed using the following formula:

[0158]

[0159]

[0160] in, Represents the time step The hidden state of represents the sequence training images, Represents the time step The hidden state of represents an LSTM (Long Short-Term Memory) or GRU (Gated Recurrent Unit) neural network unit, Represents the time step The time step output is represents a fully connected layer, which contains multiple neurons, each of which is connected to every neuron in the input layer;

[0161] Based on the hidden state and time step output, the temporal relationship between the sequence training images and the corresponding image structures is analyzed.

[0162] Among them, the sequence training image refers to a sequence formed by arranging the segmentation training images in chronological order. These images can represent the state of the chip at different time points or under different conditions. The training RNN network refers to a network that uses the segmentation training image sequence to train the RNN network. The performance threshold refers to a preset performance indicator used to determine whether the performance of the training RNN network reaches the expected level. When the performance of the training RNN network reaches or exceeds this threshold, it can be considered effective and used as the target RNN network. The target RNN network refers to the optimized network obtained through the training process. The weights of this network are adjusted to better adapt to the training data and improve the accuracy of prediction. The hidden state is an internal state maintained by the RNN network at time step t when processing sequence data. It contains information from all previous time steps and affects the output of the current time step. The time step output refers to the output of the RNN network at time step t, which is usually determined by the input of the current time step and the hidden state of the previous time step. The image structure refers to the chip structure in the segmentation training image, including storage units, circuit connections, defects and other structures. The timing relationship refers to the relationship between the changes in the image structure over time. The Both units are designed to process and remember long-term dependencies in long sequences, and they are better able to handle time spans in sequence data than traditional RNN units. LSTM unit: The LSTM unit contains three gates (input gate, forget gate, and output gate) and cell states, which work together to control the flow and storage of information. GRU unit: The GRU unit is a simpler RNN unit that merges the forget gate and input gate in the LSTM unit into one gate and shares a hidden state, which makes the GRU more efficient in some cases. The fully connected layer is usually used in the RNN network to transform the hidden state of the last time step of the sequence into the final output, or to merge the hidden state information of multiple time steps.

[0163] Furthermore, the temporal relationship of the image structure corresponding to the sequence training image is analyzed based on the hidden state and the time step output, including: the hidden state is an internal state maintained by the RNN network at time step t when processing sequence data. It contains the information of all previous time steps and affects the output of the current time step. In this way, the hidden state can integrate contextual information to help the network understand the temporal relationship in the sequence. The time step output is the output of the RNN network at time step t, which is usually determined by the input of the current time step and the hidden state of the previous time step. By analyzing the time step output, the structural changes of the image at different time points in the sequence can be understood, thereby modeling the temporal relationship. By analyzing the hidden state and the time step output, the trend and pattern of the image structure over time can be understood, which helps to understand the dynamic behavior of the chip at different production stages or under different environmental conditions.

[0164] Optionally, the GAN network is used to construct diversified training images of the segmentation training images. The diversified training images refer to new images generated by the GAN network that are similar to the original segmentation training images but have different features. These images can be used to expand the training data set and improve the generalization and robustness of the model. In detail, the GAN network consists of two main parts: a generator and a discriminator. The generator is responsible for generating new images, while the discriminator is responsible for judging whether the input image is generated by the generator or a real segmentation training image. During the training process, the generator continuously improves its ability to generate images, while the discriminator continuously improves its ability to judge between real and generated images.

[0165] S5. Utilize the hierarchical features, the temporal relationship and the diversified training images to establish a composition structure recognition model of the denoised storage chip image, analyze the structural composition of the denoised storage chip image based on the composition structure recognition model, identify the abnormal coefficient of the structural composition, and construct a composition structure analysis report of the semiconductor storage chip based on the structural composition and the abnormal coefficient.

[0166] By using the hierarchical features, the temporal relationship and the diversified training images, the composition structure recognition model of the denoised memory chip image is established, which can accurately identify the key structures in the memory chip, such as storage units, circuit connections, etc., thereby improving production efficiency and product quality. In detail, the composition structure recognition model means a model that can identify and classify different parts in the memory chip. By using the hierarchical features, the temporal relationship and the diversified training images to build a model training set, the model is trained using the constructed model training set, and by adjusting the model parameters, the model can accurately identify the key structures in the memory chip.

[0167] The present invention analyzes the structural composition of the denoised memory chip image based on the composition structure recognition model to better understand the working principle and performance characteristics of the memory chip, thereby better identifying the composition structure of the memory chip.

[0168] In detail, the structural composition of the denoised memory chip image is analyzed based on the composition structure recognition model, and the denoised memory chip image can be provided as input to the composition structure recognition model, and the composition structure recognition model outputs the structural composition of the denoised memory chip image by analyzing the denoised memory chip image, wherein the structural composition includes storage units, circuit layout, key connections, defect detection, performance indicators and other contents.

[0169] The present invention can analyze the structural composition of the denoised memory chip image and identify potential abnormalities by identifying the abnormal coefficient of the structural composition. The abnormal coefficient refers to the degree of abnormality in the structural composition. In detail, the abnormal coefficient can be analyzed by comparing with a preset standard structural composition. The standard structural composition includes the layout, connection mode, defect limitation and other contents of the storage unit.

[0170] Finally, based on the structural composition and the abnormal coefficient, the present invention constructs a composition structure analysis report of the semiconductor memory chip to better understand the working principle and performance characteristics of the memory chip. Among them, the composition structure analysis report refers to a detailed description of the results of analyzing the structural composition of the semiconductor memory chip by technical means, including analysis methods, structural composition analysis, abnormality detection and evaluation, etc.

[0171] Based on the structural recognition requirement, the present invention constructs a microscope cluster of the semiconductor memory chip to monitor the structural image of the semiconductor memory chip and provide a basis for subsequent structural analysis; optionally, based on the microscope cluster, the present invention collects the memory chip image of the semiconductor memory chip to improve the basic image for the subsequent microstructure analysis of the chip; the present invention constructs a noise probability distribution model of the memory chip image to provide a basis for the subsequent image denoising algorithm design, thereby improving the reliability of image noise removal; based on the noise probability distribution model, the present invention constructs a denoising function of the memory chip image to remove noise in the image, improve image quality and the accuracy of subsequent analysis, and the present invention uses the adaptive threshold segmentation model to The structure recognition training image is segmented, and the segmented training image obtained can be used to train and optimize the structure recognition model to improve production efficiency and product quality. The present invention uses the RNN network to analyze the temporal relationship of the image structure corresponding to the segmented training image to capture the time dependency in the image sequence, thereby improving the accuracy and reliability of chip structure composition recognition. Finally, the present invention analyzes the structural composition of the denoised storage chip image based on the composition structure recognition model to better understand the working principle and performance characteristics of the storage chip, thereby better identifying the composition structure of the storage chip and based on the structural composition and the abnormal coefficient, constructing the composition structure analysis report of the semiconductor storage chip can better understand the working principle and performance characteristics of the storage chip. Therefore, the present invention can improve the accuracy of the composition structure recognition of semiconductor storage chips.

[0172] like Figure 2 1 is a functional module diagram of a semiconductor memory chip-based intelligent identification system for component structures provided in one embodiment of the present invention.

[0173] The semiconductor memory chip-based intelligent identification system 200 of the present invention can be installed in an electronic device. According to the functions to be implemented, the semiconductor memory chip-based intelligent identification system 200 of the composition structure can include a storage chip image acquisition module 201, a chip image noise removal module 202, a training image segmentation module 203, a segmented training image analysis module 204 and a composition structure analysis module 205. The module of the present invention can also be called a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0174] In this embodiment, the functions of each module / unit are as follows:

[0175] The storage chip image acquisition module 201 is used to determine the structural recognition requirements of the semiconductor storage chip, build a microscope cluster of the semiconductor storage chip based on the structural recognition requirements, and acquire the storage chip image of the semiconductor storage chip based on the microscope cluster;

[0176] The chip image noise removal module 202 is used to construct a noise probability distribution model of the storage chip image, construct a denoising function of the storage chip image based on the noise probability distribution model, and remove noise from the storage chip image based on the denoising function to obtain a denoised storage chip image;

[0177] The training image segmentation module 203 is used to obtain the structure recognition training image of the semiconductor memory chip, build an adaptive threshold segmentation model for the structure recognition training image, and segment the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image;

[0178] The segmentation training image analysis module 204 is used to construct a deep learning network for the segmentation training image, wherein the deep learning network includes a CNN network, an RNN network and a GAN network, the CNN network is used to extract the hierarchical features of the segmentation training image, the RNN network is used to analyze the temporal relationship of the segmentation training image corresponding to the image structure, and the GAN network is used to construct a diversified training image of the segmentation training image;

[0179] The composition structure analysis module 205 is used to establish a composition structure recognition model of the denoised storage chip image by using the hierarchical features, the temporal relationship and the diversified training images, analyze the structural composition of the denoised storage chip image based on the composition structure recognition model, identify the abnormal coefficient of the structural composition, and construct a composition structure analysis report of the semiconductor storage chip based on the structural composition and the abnormal coefficient.

[0180] In detail, each module described in the semiconductor memory chip-based component structure intelligent identification system 200 described in the embodiment of the present invention adopts the same technical means as the semiconductor memory chip-based component structure intelligent identification method described in the accompanying drawings when used, and can produce the same technical effects, which will not be repeated here.

[0181] An embodiment of the present invention provides an electronic device for implementing a method for intelligently identifying a component structure based on a semiconductor memory chip.

[0182] See also Figure 3As shown, the electronic device may include a processor 30, a memory 31, a communication bus 32 and a communication interface 33, and may also include a computer program stored in the memory 31 and executable on the processor 30, such as a program for intelligent identification of the composition structure based on a semiconductor memory chip.

[0183] In some embodiments, the processor may be composed of an integrated circuit, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and a combination of various control chips, etc. The processor is the control core (Control Unit) of the electronic device, and uses various interfaces and lines to connect various components of the entire electronic device, and executes various functions and processes data of the electronic device by running or executing programs or modules stored in the memory (for example, executing a composition structure intelligent recognition program based on a semiconductor memory chip, etc.), and calling data stored in the memory.

[0184] The memory includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a mobile hard disk, a multimedia card, a card-type memory (for example, SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. In some embodiments, the memory may be an internal storage unit of an electronic device, such as a mobile hard disk of the electronic device. In other embodiments, the memory may also be an external storage device of an electronic device, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device. Further, the memory may also include both an internal storage unit of the electronic device and an external storage device. The memory can be used not only to store application software and various types of data installed in the electronic device, such as the code of the intelligent recognition program based on the composition structure of the semiconductor memory chip, but also to temporarily store data that has been output or is to be output.

[0185] The communication bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. The bus is configured to realize connection and communication between the memory and at least one processor, etc.

[0186] The communication interface is used for communication between the above-mentioned electronic device and other devices, including a network interface and a user interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device and other electronic devices. The user interface may be a display (Display), an input unit (such as a keyboard (Keyboard)), and optionally, the user interface may also be a standard wired interface, a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, and an OLED (Organic Light-Emitting Diode, organic light-emitting diode) touch device, etc. Among them, the display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device and to display a visual user interface.

[0187] For example, although not shown, the electronic device may also include a power source (such as a battery) for supplying power to various components. Preferably, the power source may be logically connected to the at least one processor through a power management system, so that the power management system can realize functions such as charging management, discharging management, and power consumption management. The power source may also include any components such as one or more DC or AC power sources, recharging systems, power failure detection circuits, power converters or inverters, and power status indicators. The electronic device may also include a variety of sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be repeated here.

[0188] It should be understood that the embodiment is for illustration only and the scope of the patent application is not limited to this structure.

[0189] The semiconductor memory chip-based composition structure intelligent recognition program stored in the memory of the electronic device is a combination of multiple instructions. When running in the processor, it can achieve:

[0190] Determining a structural recognition requirement of a semiconductor storage chip, building a microscope cluster of the semiconductor storage chip based on the structural recognition requirement, and collecting a storage chip image of the semiconductor storage chip based on the microscope cluster;

[0191] Constructing a noise probability distribution model of the storage chip image, constructing a denoising function of the storage chip image based on the noise probability distribution model, and removing noise from the storage chip image based on the denoising function to obtain a denoised storage chip image;

[0192] Acquire a structure recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structure recognition training image, and segment the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image;

[0193] Constructing a deep learning network for the segmentation training image, wherein the deep learning network includes a CNN network, an RNN network, and a GAN network, using the CNN network to extract hierarchical features of the segmentation training image, using the RNN network to analyze the temporal relationship of the segmentation training image corresponding to the image structure, and using the GAN network to construct diversified training images of the segmentation training image;

[0194] A composition structure recognition model of the denoised storage chip image is established by utilizing the hierarchical features, the temporal relationship and the diversified training images. The structural composition of the denoised storage chip image is analyzed based on the composition structure recognition model to identify the abnormal coefficient of the structural composition. Based on the structural composition and the abnormal coefficient, a composition structure analysis report of the semiconductor storage chip is constructed.

[0195] Specifically, the specific implementation method of the processor for the above instructions can refer to the description of the relevant steps in the corresponding embodiment of the accompanying drawings, which will not be repeated here.

[0196] Furthermore, if the module / unit integrated in the electronic device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium can include: any entity or system that can carry the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, and a read-only memory (ROM).

[0197] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor of an electronic device, the computer program can implement:

[0198] Determining a structural recognition requirement of a semiconductor storage chip, building a microscope cluster of the semiconductor storage chip based on the structural recognition requirement, and collecting a storage chip image of the semiconductor storage chip based on the microscope cluster;

[0199] Constructing a noise probability distribution model of the storage chip image, constructing a denoising function of the storage chip image based on the noise probability distribution model, and removing noise from the storage chip image based on the denoising function to obtain a denoised storage chip image;

[0200] Acquire a structure recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structure recognition training image, and segment the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image;

[0201] Constructing a deep learning network for the segmentation training image, wherein the deep learning network includes a CNN network, an RNN network, and a GAN network, using the CNN network to extract hierarchical features of the segmentation training image, using the RNN network to analyze the temporal relationship of the segmentation training image corresponding to the image structure, and using the GAN network to construct diversified training images of the segmentation training image;

[0202] A composition structure recognition model of the denoised storage chip image is established by utilizing the hierarchical features, the temporal relationship and the diversified training images. The structural composition of the denoised storage chip image is analyzed based on the composition structure recognition model to identify the abnormal coefficient of the structural composition. Based on the structural composition and the abnormal coefficient, a composition structure analysis report of the semiconductor storage chip is constructed.

[0203] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation.

[0204] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0205] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0206] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0207] Therefore, no matter from which point of view, the embodiments should be regarded as illustrative and non-restrictive, and the scope of the present invention is limited by the appended claims rather than the above description, so it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any attached figure mark in the claims should not be regarded as limiting the claims involved.

[0208] The embodiments of the present application can acquire and process relevant data based on artificial intelligence technology. Artificial Intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results.

[0209] In addition, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or systems stated in a system claim can also be implemented by one unit or system through software or hardware. The words first, second, etc. are used to indicate names, and do not indicate any particular order.

[0210] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for intelligently identifying the composition structure of a semiconductor memory chip, characterized in that: The method comprises: Determining a structural recognition requirement of a semiconductor storage chip, building a microscope cluster of the semiconductor storage chip based on the structural recognition requirement, and collecting a storage chip image of the semiconductor storage chip based on the microscope cluster; Constructing a noise probability distribution model of the storage chip image, constructing a denoising function of the storage chip image based on the noise probability distribution model, and removing noise from the storage chip image based on the denoising function to obtain a denoised storage chip image; Acquire a structure recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structure recognition training image, and segment the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image; Constructing a deep learning network for the segmentation training image, wherein the deep learning network includes a CNN network, an RNN network, and a GAN network, using the CNN network to extract hierarchical features of the segmentation training image, using the RNN network to analyze the temporal relationship of the segmentation training image corresponding to the image structure, and using the GAN network to construct diversified training images of the segmentation training image; A composition structure recognition model of the denoised storage chip image is established by utilizing the hierarchical features, the temporal relationship and the diversified training images. The structural composition of the denoised storage chip image is analyzed based on the composition structure recognition model to identify the abnormal coefficient of the structural composition. Based on the structural composition and the abnormal coefficient, a composition structure analysis report of the semiconductor storage chip is constructed.

2. The method for intelligently identifying the composition structure of a semiconductor memory chip according to claim 1, characterized in that: The determining of the structural identification requirements of the semiconductor storage chip includes: Obtaining a design drawing of the semiconductor memory chip; Based on the design drawings, identifying key structural elements of the semiconductor memory chip; identifying structural element characteristics of the key structural elements; Analyzing the recognition accuracy requirements of the semiconductor storage chip based on the structural element characteristics; Based on the recognition accuracy requirement, a structural recognition requirement of the semiconductor storage chip is determined.

3. The method for intelligently identifying the composition structure of a semiconductor memory chip according to claim 1, characterized in that: The step of constructing a microscope cluster of the semiconductor storage chip based on the structure recognition requirement includes: Based on the structure recognition requirement, determining microscope indicators of the semiconductor memory chip, wherein the microscope indicators include resolution, magnification, and imaging speed; Constructing a microscope layout of the semiconductor memory chip based on the design drawings corresponding to the structural recognition requirements; Based on the microscope indicator, configuring a target microscope of a layout node corresponding to the microscope layout; Constructing a data transmission network for the target microscope; Calibrate the target microscope through the data transmission network to obtain a calibrated microscope; constructing an initial microscope cluster of the calibration microscopes; analyzing a synergy coefficient of the initial microscope cluster; When the synergy coefficient meets a preset synergy threshold, the initial microscope cluster is used as a microscope cluster.

4. The method for intelligently identifying the composition structure based on a semiconductor memory chip according to claim 3, characterized in that: The analyzing the synergy coefficient of the initial microscope cluster comprises: Performing operation simulation on the initial microscope cluster to obtain simulation results; Dividing the simulation results into normal operation results and abnormal operation results; Based on the normal operation results, analyzing the image quality, data transmission efficiency and system response time of the operation simulation performed by the initial microscope cluster; Based on the abnormal operation result, determining the fault recovery parameter and maintainability coefficient of the initial microscope cluster; Based on the image quality, the data transmission efficiency, the system response time, the fault recovery parameter and the maintainability coefficient, the synergy coefficient of the initial microscope cluster is calculated using the following formula: in represents the synergy coefficient of the initial microscope cluster, Indicates image quality, Indicates the data transmission efficiency, Indicates the system response time. Indicates the fault recovery parameter corresponding to the fault detection speed, Indicates the fault recovery parameter corresponding to the fault response time. Indicates the fault recovery parameters corresponding to the fault processing time. Indicates the fault recovery parameters corresponding to the fault reconstruction time. Represents the maintainability factor.

5. The method for intelligently identifying the composition structure based on a semiconductor memory chip according to claim 1, characterized in that: The step of constructing the noise probability distribution model of the storage chip image includes: Determining a suitable environment for noise analysis of the storage chip image; Preprocessing the storage chip image through the noise analysis suitable environment to obtain a processed storage chip image; Identifying the noise type of the processed storage chip image; Based on the noise type, analyzing the noise intensity of the processed storage chip image; Based on the noise intensity, a noise probability distribution model for processing the storage chip image is constructed.

6. The method for intelligently identifying the composition structure based on a semiconductor memory chip according to claim 5, characterized in that: The step of constructing a noise probability distribution model for processing the storage chip image based on the noise intensity includes: Based on the noise intensity, determining a noise intensity mean and a noise intensity standard deviation of the processed storage chip image; Based on the noise intensity, the noise intensity mean and the noise intensity standard deviation, the noise probability function of the processed storage chip image is constructed using the following formula: in, represents the noise probability function, represents the noise intensity of the processed storage chip image, represents the standard deviation of the noise intensity of the processed storage chip image, represents the mean noise intensity of the processed storage chip image, represents the base of natural logarithms, Indicates the noise intensity Close to the mean noise intensity the extent of; Based on the noise probability function, a noise probability distribution model for processing the storage chip image is constructed.

7. The method for intelligently identifying the composition structure based on a semiconductor memory chip according to claim 1, characterized in that: The step of segmenting the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image includes: Analyzing the HOG map of the structure recognition training image; Based on the HOG map, identifying training image features of the structure recognition training image; Based on the training image features, using the adaptive threshold segmentation model, determining the segmentation threshold of the pixel points corresponding to the structure recognition training image; The structure recognition training image is segmented based on the segmentation threshold to obtain the segmented training image.

8. The method for intelligently identifying the composition structure based on a semiconductor memory chip according to claim 1, characterized in that: The step of extracting hierarchical features of the segmented training image using the CNN network comprises: Standardizing the segmentation training image to obtain a standard segmentation training image; Determine the CNN network architecture of the standard segmentation training image; Using the standard segmentation training image to train the CNN network architecture to obtain a training CNN network; Identifying the prediction loss of the trained CNN network; Based on the prediction loss, the weight of the training CNN network is adjusted using a preset back-propagation algorithm to obtain a target CNN network; The hierarchical features of the segmented training image are extracted based on the target CNN network, wherein the hierarchical features include low-level features and high-level features.

9. The method for intelligently identifying the composition structure of a semiconductor memory chip according to claim 1, characterized in that: The using the RNN network to analyze the temporal relationship of the segmented training image corresponding to the image structure includes: Serializing the segmented training images to obtain sequence training images; Using the sequence training images to train the RNN network architecture to obtain a training RNN network; When the performance of the training RNN network meets a preset performance threshold, using the training RNN network as a target RNN network; Based on the target RNN network, the hidden state and time step output of the sequence training image are analyzed using the following formula: in, Represents the time step The hidden state of represents the sequence training images, Represents the time step The hidden state of Represents LSTM long short-term memory or GRU gated recurrent unit neural network unit, Represents the time step The time step output is represents a fully connected layer, which contains multiple neurons, each of which is connected to every neuron in the input layer; Based on the hidden state and time step output, the temporal relationship between the sequence training images and the corresponding image structures is analyzed.

10. A composition structure intelligent recognition system based on semiconductor memory chip, characterized in that: A system for executing a method for intelligently identifying a component structure based on a semiconductor memory chip as claimed in any one of claims 1 to 9, the system comprising: A storage chip image acquisition module, used to determine the structural recognition requirements of the semiconductor storage chip, build a microscope cluster of the semiconductor storage chip based on the structural recognition requirements, and acquire a storage chip image of the semiconductor storage chip based on the microscope cluster; A chip image noise removal module is used to construct a noise probability distribution model of the storage chip image, construct a denoising function of the storage chip image based on the noise probability distribution model, and remove noise from the storage chip image based on the denoising function to obtain a denoised storage chip image; A training image segmentation module, used to obtain a structure recognition training image of the semiconductor memory chip, construct an adaptive threshold segmentation model for the structure recognition training image, and segment the structure recognition training image using the adaptive threshold segmentation model to obtain a segmented training image; A segmentation training image analysis module, used to construct a deep learning network for the segmentation training image, wherein the deep learning network includes a CNN network, an RNN network and a GAN network, the CNN network is used to extract the hierarchical features of the segmentation training image, the RNN network is used to analyze the temporal relationship of the segmentation training image corresponding to the image structure, and the GAN network is used to construct a diversified training image of the segmentation training image; The composition structure analysis module is used to establish a composition structure recognition model of the denoised storage chip image by using the hierarchical features, the temporal relationship and the diversified training images, analyze the structural composition of the denoised storage chip image based on the composition structure recognition model, identify the abnormal coefficient of the structural composition, and construct a composition structure analysis report of the semiconductor storage chip based on the structural composition and the abnormal coefficient.

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