Read and write control method, system, device, medium and program product for storage chip

Abstract

The present disclosure provides a method, system, device, medium and program product for read-write control of a storage chip, the method comprising: generating a first check code corresponding to first data; writing the first data and the first check code to a target address of the storage chip; reading second data and the second check code from the target address; generating a third check code corresponding to the second data; and performing read-write control on the storage chip based on the second check code and the third check code. The present disclosure reads the second data and the second check code in the target address of the storage chip, generates a third check code according to the second data, and finally performs read-write control on the storage chip according to the second check code and the third check code, thereby realizing the function of self-checking and error correction of the storage chip, and ensuring the reliability of the data stored in the storage chip.

Description

Technical Field

[0001] The present disclosure relates to the technical field of memory chip testing, and in particular to a read / write control method, system, device, medium and program product of a memory chip. Background Art

[0002] Currently, for storage chips such as EEPROM (Electrically Erasable Programmable read only memory) and Nor Flash (a non-volatile flash memory technology), it is necessary to test the entire storage array of the storage chip during design verification, finished product testing, sample introduction testing, reliability testing, and failure analysis testing.

[0003] The current functional design of the storage chip read-write system is as follows: the read-write system operating software sets up a data cache area to map the data in the storage chip. The write operation fills the data to be written into the corresponding address of the data cache area, and then writes all the data in the data cache area (including the data that needs to be newly written and the data that has been successfully written into the storage chip) into the full array of the storage chip. The read operation reads out the full array data of the storage chip and presents it in the data cache area of ​​the read-write system operating software. Figure 1 The figure shows the data buffer interface diagram of the 24C02 series EEPROM storage chip corresponding to the read-write system operating software.

[0004] The data verification function of the current system is to compare the data in the data cache area of ​​the operating software with the data stored in the read chip. It cannot realize the self-verification and error correction function of the storage chip. The data transmission of the storage chip is easily disturbed, causing data failure, so the reliability of the data stored in the storage chip cannot be guaranteed. Summary of the invention

[0005] The technical problem to be solved by the present invention is to overcome the defects in the prior art of comparing the data in the operating software data cache area with the data stored in the read chip for data verification, which cannot realize the self-verification and error correction function of the storage chip, and cannot ensure the reliability of the data stored in the storage chip. A method, system, device, medium and program product for reading and writing control of a storage chip are provided.

[0006] The present invention solves the above technical problems through the following technical solutions:

[0007] The present disclosure provides a read-write control method for a memory chip, the read-write control method comprising:

[0008] Generate a first check code corresponding to the first data;

[0009] Writing the first data and the first check code into a target address of a storage chip;

[0010] Reading second data and a second check code from the target address;

[0011] generating a third check code corresponding to the second data;

[0012] Based on the second check code and the third check code, read and write control is performed on the storage chip.

[0013] Preferably, the step of performing read and write control on the storage chip based on the second check code and the third check code comprises:

[0014] Performing an XOR operation on the second check code and the third check code to obtain a fourth check code;

[0015] Based on the fourth check code, read and write control is performed on the storage chip.

[0016] Preferably, the step of performing read and write control on the storage chip based on the fourth check code comprises:

[0017] In response to the fourth check code being the first preset value, determining that the reading and writing process of the storage chip is correct;

[0018] In response to the fourth check code not being the first preset value, it is determined that a read / write process of the memory chip is erroneous.

[0019] Preferably, after the step of determining that a read / write process of the storage chip is wrong in response to the fourth check code not being the first preset value, the method further comprises:

[0020] In response to the fourth check code being greater than a second preset value, determining that the target address is wrong, and writing the first data into a new target address;

[0021] In response to the fourth verification code being not greater than the second preset value, modifying the target data based on the fourth verification code, and determining a write strategy for the storage chip based on the modified target data;

[0022] The target data includes the second data and the second check code.

[0023] Preferably, the step of modifying the target data based on the fourth check code comprises:

[0024] Based on the fourth check code and the preset mapping relationship, obtaining a target storage bit;

[0025] Wherein, the preset mapping relationship is used to characterize the mapping relationship between the preset check code and the preset storage bit;

[0026] Based on the target storage bit, modify the target data;

[0027] and / or,

[0028] The step of determining the write strategy of the storage chip based on the modified target data comprises:

[0029] extracting third data and a fifth check code from the modified target data;

[0030] generating a sixth check code corresponding to the third data;

[0031] Based on the fifth check code and the sixth check code, a seventh check code is obtained;

[0032] In response to the seventh check code being the first preset value, writing the modified target data to the target address;

[0033] In response to the seventh check code not being the first preset value, it is determined that the target address is erroneous, and the first data is written into a new target address.

[0034] Preferably, the first check code, the third check code and the sixth check code are all Hamming codes.

[0035] The present disclosure also provides a read-write control system for a storage chip, the read-write control system comprising:

[0036] A first check code generation module, used to generate a first check code corresponding to the first data;

[0037] A data writing module, used for writing the first data and the first check code into a target address of a storage chip;

[0038] A data reading module, used for reading second data and a second check code from the target address;

[0039] A second check code generation module, used to generate a third check code corresponding to the second data;

[0040] A read / write control module is used to perform read / write control on the storage chip based on the second check code and the third check code.

[0041] Preferably, the read-write control module includes:

[0042] an XOR operation unit, configured to perform an XOR operation on the second check code and the third check code to obtain a fourth check code;

[0043] A read / write control unit is used to perform read / write control on the storage chip based on the fourth check code.

[0044] Preferably, the read-write control unit comprises:

[0045] A first response subunit, configured to determine that the reading and writing process of the storage chip is correct in response to the fourth check code being a first preset value;

[0046] The second response subunit is used to determine that a read / write process of the storage chip is wrong in response to the fourth check code not being the first preset value.

[0047] Preferably, the read-write control unit further includes:

[0048] a third response subunit, configured to determine that the target address is wrong in response to the fourth check code being greater than a second preset value, and write the first data into a new target address;

[0049] a fourth response subunit, configured to modify the target data based on the fourth check code in response to the fourth check code being not greater than the second preset value, and determine a write strategy for the storage chip based on the modified target data;

[0050] The target data includes the second data and the second check code.

[0051] Preferably, the fourth response subunit is further used to obtain a target storage bit based on the fourth check code and a preset mapping relationship;

[0052] The preset mapping relationship is used to represent the mapping relationship between the preset check code and the preset storage bit;

[0053] Based on the target storage bit, modify the target data;

[0054] and / or,

[0055] The fourth response subunit is further used to extract third data and a fifth check code from the modified target data;

[0056] generating a sixth check code corresponding to the third data;

[0057] Based on the fifth check code and the sixth check code, a seventh check code is obtained;

[0058] In response to the seventh check code being the first preset value, writing the modified target data to the target address;

[0059] In response to the seventh check code not being the first preset value, it is determined that the target address is erroneous, and the first data is written into a new target address.

[0060] Preferably, the first check code, the third check code and the sixth check code are all Hamming codes.

[0061] The present disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and used to run on the processor, and the processor implements the above-mentioned read and write control method of the storage chip when executing the computer program.

[0062] The present disclosure also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the read-write control method of the storage chip described above is implemented.

[0063] The present disclosure also provides a computer program product, including a computer program, which implements the read and write control method of the storage chip as described above when executed by a processor.

[0064] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0065] The positive and progressive effects of this disclosure are:

[0066] The present invention reads the second data and the second check code in the target address of the storage chip, generates a third check code according to the second data, and finally controls the reading and writing of the storage chip according to the second check code and the third check code, thereby realizing the self-checking and error correction function of the storage chip and ensuring the reliability of the data stored in the storage chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 A schematic diagram of the data buffer interface of the EEPROM storage chip corresponding to the read-write system operating software of the prior art;

[0068] Figure 2 This is a flow chart of the read-write control method of the memory chip according to Embodiment 1 of the present disclosure;

[0069] Figure 3 This is a flowchart of step S5 in the read / write control method of a memory chip according to Embodiment 2 of the present disclosure;

[0070] Figure 4 This is a flow chart of a read-write control method for a memory chip according to Embodiment 2 of the present disclosure;

[0071] Figure 5 This is a flowchart of step S524 in the read / write control method of a memory chip according to Embodiment 2 of the present disclosure;

[0072] Figure 6 A specific example diagram of the read-write control method of the memory chip according to Embodiment 2 of the present disclosure;

[0073] Figure 7 This is a module schematic diagram of a read-write control system of a memory chip according to Embodiment 3 of the present disclosure;

[0074] Figure 8 This is a module schematic diagram of a read-write control system of a memory chip according to Embodiment 4 of the present disclosure;

[0075] Fig. 9 This is a schematic diagram of the structure of an electronic device according to Embodiment 5 of the present disclosure. DETAILED DESCRIPTION

[0076] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0077] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0078] In the embodiments of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0079] Example 1

[0080] This embodiment provides a read-write control method for a memory chip, such as Figure 2 As shown, the read-write control method includes:

[0081] S1. Generate a first check code corresponding to the first data;

[0082] S2, writing the first data and the first check code to the target address of the storage chip;

[0083] S3, reading second data and a second check code from the target address;

[0084] S4, generating a third check code corresponding to the second data;

[0085] S5. Based on the second check code and the third check code, read and write control is performed on the storage chip.

[0086] Specifically, the first data is user data. Before writing the user data to the target address of the storage chip, a first check code corresponding to the user data is generated. The first check code is an ECC (Error Checking and Correcting) check code, such as a Hamming code. Both the user data and the first check code are written to the target address of the storage chip. Then the second data and the second check code are read from the target address of the storage chip. The second check code is recorded as wECC. The corresponding third check code is calculated and generated based on the read second data. The third check code is recorded as rECC. Finally, error detection and error correction are performed based on the comparison between the read second check code and the generated third check code to control the read and write of the storage chip. If the comparison results of the second check code and the third check code are consistent, it is judged that the data is read and written correctly; otherwise, an error occurs in the written or read data.

[0087] The memory chip includes a memory chip such as EEPROM, Nor Flash, etc. The memory chip can be used to store user data and check codes, and can also be used as the execution subject of the read-write control method of this embodiment. The user data and check codes stored in the memory chip are in binary form and stored in the form of multiple address bits.

[0088] In this embodiment, by reading the second data and the second check code in the target address of the storage chip, generating a third check code based on the second data, and finally performing read and write control on the storage chip based on the second check code and the third check code, the storage chip write and read self-checking and error correction function is realized, thereby ensuring the reliability of data stored in the storage chip.

[0089] Example 2

[0090] This embodiment provides a read-write control method for a storage chip, which is a further improvement on Embodiment 1.

[0091] In one feasible solution, Figure 3 As shown, step S5 includes:

[0092] S51, performing an XOR operation on the second check code and the third check code to obtain a fourth check code;

[0093] S52: Based on the fourth check code, read and write control is performed on the storage chip.

[0094] Specifically, the second check code and the third check code are subjected to a bitwise XOR operation, and the result obtained is binary data, and the binary data is converted into decimal data, which is the fourth check code.

[0095] In this solution, the fourth check code is obtained by performing an XOR operation on the second check code and the third check code, and then the storage chip is read and written controlled, which improves the convenience and flexibility of comparing the second check code and the third check code.

[0096] In one feasible solution, Figure 4 As shown, step S52 includes:

[0097] S521, in response to the fourth check code being the first preset value, determining that the reading and writing process of the storage chip is correct;

[0098] S522: In response to the fourth check code not being the first preset value, determining that a read / write process of the storage chip is erroneous.

[0099] Specifically, the first preset value may be 0.

[0100] In this solution, by judging whether the fourth check code is the first preset value, it is determined whether the reading and writing process of the storage chip is correct or incorrect, thereby realizing error detection of the reading and writing process of the storage chip and improving the accuracy and reliability of the storage data of the storage chip.

[0101] In an implementable solution, after step S522, the method further includes:

[0102] S523, in response to the fourth check code being greater than the second preset value, determining that the target address is wrong, and writing the first data into a new target address;

[0103] S524, in response to the fourth verification code being not greater than the second preset value, modifying the target data based on the fourth verification code, and determining a write strategy for the storage chip based on the modified target data;

[0104] The target data includes second data and a second check code.

[0105] Specifically, the second preset value is determined according to the number of bits of the first data and the number of bits of the check code, and the sum of the number of bits of the first data and the number of bits of the check code can be used as the second preset value. For example, if the first data is 32 bits (bit) and the check code is 6 bits, then the second preset value is 38. The number of bits of the first data, the number of bits of the check code, and the second preset value can be set or adjusted according to actual conditions, and this is just an example.

[0106] When the fourth check code is greater than the second preset value, it indicates that the second data or the second check code has more than one bit error, and the target address is wrong, which means that the target address storing user data is prone to data errors. The user can choose whether to enable the address "overwrite" function according to needs. The address "overwrite" function automatically changes the write address of this group of user data to the new target address (Naddr). At the same time, the host computer sets a flag bit. Subsequent operations on this group of addresses with data errors will automatically change to the new target address (Naddr).

[0107] When the fourth check code is not greater than the second preset value, it indicates that a single bit error occurs in the second data or the second check code, and the target address is correct. A single bit error occurs in the user data stored at the target address, and the target data can be modified according to the specific value of the fourth check code, and the write strategy of the storage chip is determined according to the modified target data.

[0108] In this solution, by judging the size relationship between the fourth check code and the second preset value, it is determined whether the target address is available, thereby ensuring the accuracy and reliability of the data stored in the memory chip.

[0109] In one feasible solution, Figure 5 As shown, step S524 includes:

[0110] S5241. Obtain a target storage bit based on the fourth check code and a preset mapping relationship;

[0111] The preset mapping relationship is used to represent the mapping relationship between the preset check code and the preset storage bit;

[0112] S5242. Modify the target data based on the target storage bit.

[0113] Specifically, the fourth check code is compared with the preset verification code in the preset mapping relationship, and the preset storage bit corresponding to the preset verification code consistent with the fourth check code is the target storage bit, and the target storage bit is the bit where the target data has an error. For example, the preset mapping relationship includes 38 groups of corresponding relationships between preset verification codes and preset storage bits, that is, 32 preset verification codes correspond to 32 bits of the second data, and 6 preset verification codes correspond to 6 bits of the second check code. Therefore, the specific bit where the target data has an error, that is, the error bit, can be determined according to the target verification code. The modified target data can be obtained by inverting the stored value in the error bit (Eaddr).

[0114] In this solution, the target storage bit is obtained according to the fourth check code and the preset mapping relationship, and then the target data is modified and corrected according to the target storage bit, thereby ensuring the accuracy and reliability of user data modification.

[0115] In an implementable solution, step S524 further includes:

[0116] S5243, extracting the third data and the fifth check code from the modified target data;

[0117] S5244. Generate a sixth check code corresponding to the third data;

[0118] S5245. Obtain a seventh check code based on the fifth check code and the sixth check code;

[0119] S5246, in response to the seventh check code being the first preset value, writing the modified target data to the target address;

[0120] S5247: In response to the seventh check code not being the first preset value, determining that the target address is wrong, and writing the first data into a new target address.

[0121] Specifically, for the modified target data, the third data and the fifth check code are extracted, the sixth check code is generated according to the third data, the fifth check code and the sixth correction code are subjected to a bitwise XOR operation to obtain the seventh check code, and the seventh check code is compared with the first preset value to determine whether the modified target data is correct. If the seventh check code is consistent with the first preset value, the modified target data is correct, and the corresponding user data in the modified target data is written into the target address of the storage chip; if the seventh check code is inconsistent with the first preset value, it indicates that there is still an error in the modified target data, and the address "overwrite" function is enabled. The address "overwrite" function automatically replaces the write address of this group of user data with the new target address (Naddr), and the host computer sets the flag bit at the same time. The address of this group with data errors will be automatically replaced with the new target address (Naddr) when it is operated later.

[0122] In this solution, the accuracy and reliability of the data stored in the memory chip are ensured by comparing the modified target data with a verification code to detect errors.

[0123] In an implementable solution, the first check code, the third check code and the sixth check code are all Hamming codes.

[0124] In this solution, Hamming codes are generated to implement error detection and correction in the reading and writing process of the memory chip, thereby ensuring the accuracy and reliability of the check code and improving the accuracy and reliability of the data stored in the memory chip.

[0125] In addition, the read-write control method of this embodiment supports communication protocols such as I2C (bidirectional two-wire synchronous serial bus) communication protocol, SPI (Serial Peripheral Interfac, serial peripheral interface) communication protocol, Microwire (a four-wire serial interface) communication protocol, etc.; supports various functional operations described in the memory chip specification sheet such as byte write mode, page write mode, sector erase, and sector write of the memory chip, and can implement full-function testing according to the memory chip specification sheet, with simple and flexible operation; supports USB Type-C (a USB interface appearance standard; USB, Universal Serial Bus, universal serial bus) communication interface; no external power supply is required when used in online mode, and supports 0V~5.5V adjustable voltage to power the memory chip; the memory chip model can also be selected according to actual needs.

[0126] The corresponding operation software interface in online mode supports users to select functions according to their needs. For example, if you select byte write mode, you only need to enter the start address, end address and data of the memory chip to be written; if you select page write mode, you only need to enter the start page, end page and data to be written. Byte write operation covers the functional test of memory chips to a greater extent and improves the flexibility of operation. It provides multiple modes of functional test for users to choose, which improves the flexibility of operation and the richness of test content.

[0127] All write and read operations only operate on the storage area that the user is concerned about, and will not operate other irrelevant storage areas, which greatly reduces data transmission failures caused by communication interference or other factors, and greatly reduces test time and improves test efficiency.

[0128] It is also possible to add an aging test function for a specific area of ​​the memory chip. Specifically, according to actual needs, a repeated write-read verification test with error detection and correction is performed on a specific area of ​​the memory chip, and the total number of erase and write times and the number of data verification errors are recorded. When the total number of erase and write recorded is not less than the reference total number of erase and write times, it indicates that the number of read and write times of the memory chip reaches the reference standard; when the total number of erase and write recorded is less than the reference total number of erase and write times, it indicates that the number of read and write times of the memory chip does not reach the reference standard. When the total number of erase and write recorded reaches the preset total number of erase and write times, and the number of data verification errors recorded is not greater than the reference verification error number, it indicates that the read and write accuracy of the memory chip reaches the reference standard; when the total number of erase and write recorded reaches the preset total number of erase and write times, and the number of data verification errors recorded is greater than the reference verification error number, it indicates that the read and write accuracy of the memory chip does not reach the reference standard.

[0129] The write and read frequency of the memory chip can be adjusted. Specifically, according to the actual frequency requirement, the delay between the host computer program instructions is adjusted to achieve the adjustment of the memory chip clock frequency.

[0130] More MCU (Microcontroller Unit) IO (InputOutput) ports can be configured for communication according to actual needs to achieve simultaneous writing and reading of multiple storage chips.

[0131] The read-write control method can be displayed on an application interface in online mode, and the content of the application interface can be adjusted according to actual needs, so that a variety of simple operations on the storage chip can be implemented without changing the hardware design.

[0132] The working principle of the read-write control method of the memory chip of this embodiment is explained below with reference to specific examples. Figure 6 As shown:

[0133] Input user data (wDATA), which is 32 bits (bits) of data, corresponding to storage bits 0-31. Calculate and generate the ECC check code (wECC) of the user data, which is 6 bits of data, corresponding to storage bits 32-37. Add 0 to the upper two bits of the check code, that is, add 0 to bits 38 and 39. Write the user data and the ECC check code to the address "addr" of the EEPROM storage chip, totaling 40 bits of data, that is, 5 bytes of data. Read out the 5-byte data of the address "addr" of the EEPROM storage chip, and take out bits 32-37 and bits 0-31 of the data respectively. Calculate and generate the ECC check code (rECC) corresponding to the taken out bits 0-31, rECC is 6 bits of data. Perform a bitwise XOR operation on the taken out bits 32-37 and rECC, convert the operation result into decimal data, and determine whether the decimal data is 0. If the decimal data is 0, it indicates that the data read and write of the storage chip are consistent, and the read and write control process ends; if the decimal data is not 0, it is determined whether the decimal data is greater than 38. If the decimal data is greater than 38, the flag bit is set, the address "addr" is invalidated, and a new address "Naddr" is generated. The address "Naddr" is automatically incremented by judging the flag bit. When the host computer inputs the address "addr", it is equivalent to operating the address "Naddr" of the EEPROM. For example, addr=0x0000, after checking the corresponding flag bit, input the address "addr" again, that is, input addr+0x1000, Naddr=addr+0x1000. Re-entering user data to the address "addr" is equivalent to writing data to the address "Naddr". If the decimal data is not greater than 38, the storage value of the storage bit corresponding to the decimal data is inverted, that is, 1 becomes 0, 0 becomes 1, and a new set of 5-byte data is generated. Take out bits 32-37 and bits 0-31 of the new 5-byte data respectively. Calculate and generate the ECC check code (cECC) corresponding to bits 0-31 taken out. cECC is 6-bit data. Perform bitwise XOR operation on bits 32-37 taken out and cECC, convert the operation result into decimal data, and determine whether the decimal data is 0. If the decimal data is 0, it indicates that the new 5-byte data is correct, and bits 0-31 are used as user data; if the decimal data is not 0, execute the steps of setting the flag bit, invalidating the address "addr", and generating a new address "Naddr".

[0134] In this embodiment, by reading the second data and the second check code in the target address of the storage chip, generating a third check code based on the second data, and finally performing read and write control on the storage chip based on the second check code and the third check code, the storage chip write and read self-checking and error correction function is realized, thereby ensuring the reliability of data stored in the storage chip.

[0135] Example 3

[0136] This embodiment provides a read-write control system for a storage chip, such as Figure 7 As shown, the read-write control system includes:

[0137] A first check code generating module 1, used to generate a first check code corresponding to the first data;

[0138] A data writing module 2, used for writing the first data and the first check code into the target address of the storage chip;

[0139] A data reading module 3, used for reading second data and a second check code from a target address;

[0140] A second check code generating module 4, used to generate a third check code corresponding to the second data;

[0141] The read / write control module 5 is used to perform read / write control on the storage chip based on the second check code and the third check code.

[0142] In this embodiment, by reading the second data and the second check code in the target address of the storage chip, generating a third check code based on the second data, and finally performing read and write control on the storage chip based on the second check code and the third check code, the storage chip write and read self-checking and error correction function is realized, thereby ensuring the reliability of data stored in the storage chip.

[0143] Example 4

[0144] This embodiment provides a read / write control system for a storage chip, which is a further improvement on the third embodiment.

[0145] In one feasible solution, Figure 8 As shown, the read-write control module 5 includes:

[0146] An XOR operation unit 51 is used to perform an XOR operation on the second check code and the third check code to obtain a fourth check code;

[0147] The read / write control unit 52 is used to perform read / write control on the storage chip based on the fourth check code.

[0148] In one practicable solution, the read-write control unit 52 includes:

[0149] A first response subunit 521, configured to determine that the reading and writing process of the storage chip is correct in response to the fourth check code being a first preset value;

[0150] The second response subunit 522 is used to determine that a read / write process of the storage chip is wrong in response to the fourth check code not being the first preset value.

[0151] In an practicable solution, the read-write control unit 52 further includes:

[0152] A third response subunit 523, configured to determine that the target address is wrong in response to the fourth check code being greater than the second preset value, and write the first data into a new target address;

[0153] A fourth response subunit 524, configured to modify the target data based on the fourth check code in response to the fourth check code being not greater than the second preset value, and determine a write strategy for the storage chip based on the modified target data;

[0154] The target data includes second data and a second check code.

[0155] In an implementable solution, the fourth response subunit 524 is further used to obtain a target storage bit based on the fourth check code and a preset mapping relationship;

[0156] The preset mapping relationship is used to represent the mapping relationship between the preset check code and the preset storage bit;

[0157] Based on the target storage bit, the target data is modified.

[0158] In an implementable solution, the fourth response subunit 524 is further used to extract the third data and the fifth check code from the modified target data;

[0159] generating a sixth check code corresponding to the third data;

[0160] Based on the fifth check code and the sixth check code, a seventh check code is obtained;

[0161] In response to the seventh check code being the first preset value, writing the modified target data to the target address;

[0162] In response to the seventh check code not being the first preset value, it is determined that the target address is wrong, and the first data is written into a new target address.

[0163] In an implementable solution, the first check code, the third check code and the sixth check code are all Hamming codes.

[0164] In this embodiment, by reading the second data and the second check code in the target address of the storage chip, generating a third check code based on the second data, and finally performing read and write control on the storage chip based on the second check code and the third check code, the storage chip write and read self-checking and error correction function is realized, thereby ensuring the reliability of data stored in the storage chip.

[0165] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0166] Example 5

[0167] Fig. 9 This is a structural schematic diagram of an electronic device shown in an example embodiment of the present disclosure, the electronic device includes a memory, a processor, and a computer program stored in the memory and used to run on the processor, and when the processor executes the computer program, the read and write control method of the storage chip described in any of the above embodiments is implemented. Fig. 9 The electronic device 90 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0168] like Fig. 9 As shown, the electronic device 90 may be in the form of a general-purpose computing device, for example, it may be a server device. The components of the electronic device 90 may include, but are not limited to: at least one processor 91, at least one memory 92, and a bus 93 connecting different system components (including the memory 92 and the processor 91).

[0169] The bus 93 includes a data bus, an address bus, and a control bus.

[0170] The memory 92 may include a volatile memory, such as a random access memory (RAM) 921 and / or a cache memory 922 , and may further include a read only memory (ROM) 923 .

[0171] The memory 92 may also include a program tool 925 (or utility) having a set (at least one) of program modules 924, such program modules 924 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0172] The processor 91 executes various functional applications and data processing by running the computer program stored in the memory 92, such as the read and write control method of the memory chip provided in any of the above embodiments.

[0173] The electronic device 90 may also communicate with one or more external devices 94 (e.g., keyboards, pointing devices, etc.). Such communication may be performed via an input / output (I / O) interface 95. Furthermore, the electronic device 90 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 96. As shown, the network adapter 96 communicates with other modules of the electronic device 90 via a bus 93. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 90, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.

[0174] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0175] Example 6

[0176] The embodiments of the present disclosure further provide a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the read-write control method of the storage chip provided in any of the above embodiments is implemented.

[0177] The readable storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.

[0178] Example 7

[0179] The embodiments of the present disclosure further provide a computer program product, including a computer program, which, when executed by a processor, implements any of the above-mentioned methods for controlling the read and write of a storage chip.

[0180] Among them, the program code for executing the computer program product of the present disclosure can be written in any combination of one or more programming languages, and the program code can be executed completely on the user device, partially on the user device, as an independent software package, partially on the user device and partially on a remote device, or completely on the remote device.

[0181] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A read-write control method for a storage chip, characterized in that: The read-write control method comprises: Generate a first check code corresponding to the first data; Writing the first data and the first check code into a target address of a storage chip; Reading second data and a second check code from the target address; generating a third check code corresponding to the second data; Based on the second check code and the third check code, read and write control is performed on the storage chip.

2. The read-write control method of a memory chip according to claim 1, characterized in that: The step of performing read and write control on the storage chip based on the second check code and the third check code comprises: Performing an XOR operation on the second check code and the third check code to obtain a fourth check code; Based on the fourth check code, read and write control is performed on the storage chip.

3. The read-write control method of a memory chip according to claim 2, characterized in that: The step of performing read and write control on the storage chip based on the fourth check code comprises: In response to the fourth check code being the first preset value, determining that the reading and writing process of the storage chip is correct; In response to the fourth check code not being the first preset value, it is determined that a read / write process of the memory chip is erroneous.

4. The read-write control method of a memory chip according to claim 3, characterized in that: After the step of determining that a read / write process of the storage chip is wrong in response to the fourth check code not being the first preset value, the method further includes: In response to the fourth check code being greater than a second preset value, determining that the target address is wrong, and writing the first data into a new target address; In response to the fourth verification code being not greater than the second preset value, modifying the target data based on the fourth verification code, and determining a write strategy for the storage chip based on the modified target data; The target data includes the second data and the second check code.

5. The read-write control method of a memory chip as claimed in claim 4, characterized in that: The step of modifying the target data based on the fourth check code comprises: Based on the fourth check code and the preset mapping relationship, obtaining a target storage bit; The preset mapping relationship is used to represent the mapping relationship between the preset check code and the preset storage bit; Based on the target storage bit, modify the target data; and / or, The step of determining the write strategy of the storage chip based on the modified target data comprises: extracting third data and a fifth check code from the modified target data; generating a sixth check code corresponding to the third data; Based on the fifth check code and the sixth check code, a seventh check code is obtained; In response to the seventh check code being the first preset value, writing the modified target data to the target address; In response to the seventh check code not being the first preset value, it is determined that the target address is erroneous, and the first data is written into a new target address.

6. The method for controlling the read and write of a memory chip according to claim 5, wherein: The first check code, the third check code and the sixth check code are all Hamming codes.

7. A read-write control system for a storage chip, characterized in that: The read-write control system comprises: A first check code generation module, used to generate a first check code corresponding to the first data; A data writing module, used for writing the first data and the first check code into a target address of a storage chip; A data reading module, used for reading second data and a second check code from the target address; A second check code generation module, used to generate a third check code corresponding to the second data; A read / write control module is used to perform read / write control on the storage chip based on the second check code and the third check code.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and used to run on the processor, characterized in that: When the processor executes the computer program, the read and write control method of the memory chip according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the read-write control method of the memory chip according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the read and write control method of the storage chip as described in any one of claims 1 to 6 is implemented.

Images