Peripheral drive circuit modules, display screen components and electronic equipment

Abstract

The present application provides a peripheral drive circuit module, a display screen assembly and an electronic device. The peripheral drive circuit module includes a timing control circuit and a data drive integrated circuit; the timing control circuit includes: an encoding subcircuit for encoding and processing parallel first grayscale data and preset encoding data to obtain first encoding data; wherein the number of consecutive identical digits in the first grayscale data is a first number, and the number of consecutive identical digits in the first encoding data is a second number, wherein the second number is less than the first number; a first conversion subcircuit for converting the first encoding data into serial and differential second encoding data; the data drive integrated circuit includes: a first data receiving subcircuit for converting the second encoding data into parallel third encoding data; and a decoding subcircuit for decoding and processing the third encoding data and preset decoding data to obtain second grayscale data, wherein the second grayscale data is used to drive the display panel.

Description

Technical Field

[0001] The present application relates to the display field, and in particular to a peripheral driving circuit module, a display screen assembly and an electronic device. Background Art

[0002] Organic light emitting diode (OLED) display panels are widely used due to their advantages such as low power consumption, fast response speed, and wide viewing angle. Improving the resolution and grayscale depth of OLED display panels is an important development direction of OLED display panels. However, the improvement of resolution and grayscale depth will lead to an increase in data transmission rate, which will bring about electromagnetic interference (EMI) problems. Summary of the invention

[0003] In a first aspect, an embodiment of the present application provides a peripheral driving circuit module, characterized in that the peripheral driving circuit module includes a timing control circuit and a data driving integrated circuit;

[0004] The timing control circuit comprises:

[0005] an encoding subcircuit, configured to encode the parallel first grayscale data and the preset encoding data to obtain the first encoding data; wherein the number of consecutive identical digits in the first grayscale data is a first number, and the number of consecutive identical digits in the first encoding data is a second number, wherein the second number is smaller than the first number; and

[0006] a first conversion subcircuit, electrically connected to the encoding subcircuit, and configured to convert the first encoded data into serial and differential second encoded data;

[0007] The data driving integrated circuit comprises:

[0008] a first data receiving subcircuit, electrically connected to the first conversion subcircuit, and configured to convert the second coded data into parallel third coded data; and

[0009] The decoding subcircuit is electrically connected to the first data receiving subcircuit, and is used for decoding the third encoded data and the preset decoded data to obtain second grayscale data, wherein the second grayscale data is used for driving the display panel.

[0010] In a second aspect, an embodiment of the present application provides a display screen assembly, the display screen assembly comprising:

[0011] display panel; and

[0012] As described in the first aspect, the peripheral driving circuit module is used to drive the display panel.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, wherein the electronic device includes the display screen assembly as described in the second aspect.

[0014] In summary, the peripheral driving circuit module provided in the embodiment of the present application uses the encoding subunit to encode the first grayscale data and the preset encoding data to obtain the first encoding data; the number of consecutive identical digits in the first encoding data is less than the number of consecutive identical digits in the first grayscale data, thereby reducing the number of consecutive identical digits, and thus reducing EMI. Therefore, when the peripheral driving circuit module is applied to a display screen assembly and an electronic device, the EMI risk of the display screen assembly and the EMI risk of the electronic device can be reduced. The display screen assembly and the electronic device comply with the EMI standards of the corresponding country or region, or comply with the international EMI standards, thereby ensuring the safety of the display screen assembly and the electronic device, ensuring the health of the user, and improving the safety of product use. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the implementation will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 A schematic diagram of a plurality of consecutive identical numbers in the related art;

[0017] Figure 2 A schematic diagram of a differential circuit provided in one embodiment;

[0018] Figure 3 A circuit block diagram of a peripheral driving circuit module provided in one embodiment of the present application;

[0019] Figure 4 A schematic diagram of an encoding subcircuit and a decoding subcircuit provided in one embodiment;

[0020] Figure 5 Schematic diagram of a peripheral driving circuit module provided for two implementation modes;

[0021] Figure 6 is the truth table for XOR and XOR;

[0022] Figure 7 A schematic diagram of data sent by a timing control circuit of a peripheral driving circuit module and data received by a data driving integrated circuit in the related art;

[0023] Figure 8A schematic diagram of data sent by a timing control circuit of a peripheral driving circuit module and data received by a data driving integrated circuit provided in an embodiment of the present application;

[0024] Fig. 9 A schematic diagram of a timing control circuit provided in one embodiment of the present application;

[0025] Fig.10 A schematic diagram of a data driver integrated circuit provided in one embodiment of the present application;

[0026] Fig.11 A circuit block diagram of a peripheral driving circuit module provided in another embodiment of the present application;

[0027] Fig.12 A schematic diagram of a timing control circuit provided in another embodiment;

[0028] Fig.13 A schematic diagram of a timing control circuit provided in yet another embodiment;

[0029] Fig.14 A schematic diagram of a data driver integrated circuit provided in one embodiment;

[0030] Fig.15 A schematic diagram of a data driver integrated circuit provided in one embodiment;

[0031] Fig.16 A schematic diagram of a display screen assembly provided in one embodiment of the present application;

[0032] Fig.17 A schematic diagram of an electronic device provided in accordance with an embodiment of the present application.

[0033] Description of main component numbers:

[0034] Electronic device 1, display screen assembly 10, housing 30, display panel 300;

[0035] Peripheral driving circuit module 100, timing control circuit 110, data driving integrated circuit 130;

[0036] Coding subcircuit 111, first convolution unit 1111, coding unit 1112, first input terminal 111a, second input terminal 111b, first output terminal 111c;

[0037] A first conversion sub-circuit 112, a second data receiving sub-circuit 113, a core processor unit 114, and a first sub-memory 115;

[0038] A first data receiving subcircuit 131, a decoding subcircuit 132, a second convolution unit 1321, a decoding unit 1322, a third input terminal 132a, a fourth input terminal 132b, and a second output terminal 132c;

[0039] A digital-to-analog converter 133, a second conversion sub-circuit 134, a second sub-memory 135, a memory 150, and a system-on-chip 160;

[0040] Differential circuit 70, transmitting module 710, first switch Q1, second switch Q2, third switch Q3, fourth switch Q4, first signal terminal P1, second signal terminal P2;

[0041] Receiving module 730 , resistor R, receiver 731 . DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0044] Reference to "embodiment" or "implementation" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment or implementation may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] An embodiment of the present application provides a peripheral driving circuit module 100 and a display screen assembly 10 (see Fig.16 ) and electronic equipment 1 (see Fig.17 Before introducing the peripheral driving circuit module 100, the display screen assembly 10 and the electronic device 1 provided in one embodiment of the present application, the relevant background knowledge is first introduced.

[0046] Once electromagnetic interference (EMI) exceeds the acceptable limit for humans, it will cause harm to human health. For electronic devices 1, electromagnetic interference will damage the operating performance of electronic devices 1, or bring about obvious disaster consequences, and even damage the original sensitive components.

[0047] Based on the above reasons, each country or region has certain standards for electromagnetic interference. For example, international standards: IEC 61000-4-x series standards, domestic standards: GB / T 17626.x series standards; industrial standards: EN 55032 / 55035, CISPR 32 / 35, FCC Part 15, MIL-STD-461, MIL-STD-464, etc. The electromagnetic interference of electronic equipment 1 must comply with the standards for electromagnetic interference in the corresponding country or region.

[0048] High-frequency digital signal transmission is all carried out as "0" or "1"; if there are too many consecutive "0"s, or too many consecutive "1"s, the energy will accumulate seriously, causing EMI to exceed the standard.

[0049] See also Figure 1 , Figure 1 Schematic diagram of multiple consecutive identical numbers in the related art. Figure 1 (a) in the figure shows a series of identical digits “0”. Figure 1 (b) in the figure shows multiple consecutive identical numbers "1".

[0050] For high-frequency digital signal transmission, it is all carried out as "0" or "1". For hardware circuits, differential circuits 70 are generally used to transmit in the form of split pairs. Figure 2 , Figure 2A schematic diagram of a differential circuit provided in an embodiment. In this embodiment, the differential circuit 70 includes a transmitter module 710 (Transmitter) and a receiving module 730. The transmitter module 710 includes four switches, which are named as a first switch Q1, a second switch Q2, a third switch Q3 and a fourth switch Q4. The gate of the first switch Q1 is used to receive a first control signal (A is not, and is marked with a short horizontal line on the top of A in the figure), and the first end of the first switch Q1 is used to electrically connect to the first signal terminal P1, wherein the first signal terminal P1 is used to load the first signal VDD. The gate of the second switch Q2 unit is used to receive a second control signal (A), wherein the second control signal is a signal with opposite polarity to the first control signal; the first end of the second switch Q2 is electrically connected to the first end of the first switch Q1. The gate of the third switch Q3 is used to receive the second control signal (A), the first end of the third switch Q3 is electrically connected to the second end of the first switch Q1, and the second end of the third switch Q3 is used to electrically connect to the second signal terminal P2, wherein the second signal terminal P2 is used to load the second signal VSS. The gate of the fourth switch Q4 is used to receive the first control signal (A not), the first end of the fourth switch Q4 is electrically connected to the second end of the second switch Q2, and the second end of the fourth switch Q4 is electrically connected to the second end of the third switch Q3. In one embodiment, the first end is a source and the second end is a drain. In another embodiment, the first end is a drain and the second end is a source. The receiving module 730 includes a receiver 731 (Receiver) and a resistor R. The positive electrode of the receiver 731 is electrically connected to the second end of the second switch Q2 unit, and the negative electrode of the receiver 731 is electrically connected to the second end of the first switch Q1 unit. One end of the resistor R is electrically connected to the positive electrode of the receiver 731, and the other end of the resistor R is electrically connected to the negative electrode of the receiver 731.

[0051] When the first control signal is at a low level and the second control signal is at a high level, the first switch Q1 and the fourth switch Q4 are both closed, and the second switch Q2 and the third switch Q3 are both opened. At this time, the current path is: first signal terminal P1 - second switch Q2 - resistor R - third switch Q3 - second signal terminal P2. If the voltage of the resistor R received by the receiver 731 is high at the top and low at the bottom, it is data "1". Otherwise, it is data "0".

[0052] It can be seen that data "1" and data "0" are only related to the current direction of the resistor R, and have no direct relationship with the voltage at the transmitting end. The reason for EMI is that when transmitting digital signals, multiple consecutive identical digital "0"s or multiple consecutive identical digital "1"s appear. Correspondingly, when transmitting analog signals, the voltage on the transmission line maintains a voltage signal for a long time.

[0053] The following is a detailed description of a peripheral drive circuit module provided in the embodiment of the present application. Figure 3 , Figure 3 The circuit block diagram of the peripheral driving circuit module provided in one embodiment of the present application. The peripheral driving circuit module 100 includes a timing control circuit 110 (TCON) and a data driver integrated circuit 130 (Driver IC). The timing control circuit 110 includes an encoding subcircuit 111 and a first conversion subcircuit 112 (Data Transimitter). The encoding subcircuit 111 is used to encode the parallel first grayscale data and the preset encoding data to obtain the first encoded data; wherein the number of consecutive identical digits in the first grayscale data is the first number, and the number of consecutive identical digits in the first encoded data is the second number, wherein the second number is less than the first number. The first conversion subcircuit 112 is electrically connected to the encoding subcircuit 111, and is used to convert the first encoded data into serial and differential second encoded data. The data driver integrated circuit 130 includes a first data receiving subcircuit 131 (Data Receiver) and a decoding subcircuit 132. The first data receiving subcircuit 131 is electrically connected to the first conversion subcircuit 112, and is used to convert the second encoded data into parallel third encoded data. The decoding subcircuit 132 is electrically connected to the first data receiving subcircuit 131 , and is used to decode the third encoded data and the preset decoded data to obtain second grayscale data, wherein the second grayscale data is used to drive the display panel 300 .

[0054] The encoding subunit is used to encode the parallel first grayscale data and the preset encoding data to obtain the first encoding data, the number of consecutive identical digits in the first grayscale data is the first number, and the number of consecutive identical digits in the first encoding data is the second number, wherein the second number is smaller than the first number. It can be seen that the number of consecutive identical digits in the first grayscale data is relatively large, and after being processed by the encoding subunit, the number of consecutive identical digits in the obtained first encoding data is relatively small.

[0055] It should be noted that the consecutive identical numbers can be consecutive identical "1"s or consecutive identical "0". For example, in one embodiment, in the first grayscale data, the number of consecutive identical numbers is 16; in the first coded data, the number of consecutive identical numbers is 2. It can be understood that in the first grayscale data, the number of consecutive identical numbers can also be other data; in the first coded data, the number of consecutive identical numbers can also be other data, which is not limited here, as long as the second data is smaller than the first number.

[0056] As can be seen from the previous introduction, the reason for EMI is that when transmitting digital signals, multiple consecutive identical numbers "0" or multiple consecutive identical numbers "1" appear. Correspondingly, when transmitting analog signals, the voltage on the transmission line maintains a voltage signal for a long time. The peripheral drive circuit module provided in the embodiment of the present application uses a coding subunit to encode the first grayscale data and the preset coding data to obtain the first coding data; the number of consecutive identical numbers in the first coding data is less than the number of consecutive identical numbers in the first grayscale data, thereby reducing the number of consecutive identical numbers, thereby reducing EMI.

[0057] The first conversion subcircuit 112 converts the first coded data into serial and differential second coded data, which facilitates data transmission between the timing control circuit 110 and the data driving integrated circuit 130, reduces the bit error rate, and improves the accuracy of data transmission.

[0058] The first data receiving subcircuit 131 converts the second coded data into parallel third coded data to facilitate the subsequent data processing by the decoding subcircuit 132 .

[0059] The decoding subcircuit 132 is electrically connected to the first data receiving subcircuit 131, and is used to decode the third encoded data and the preset decoded data to obtain the second grayscale data. It should be noted that the decoding process performed by the decoding subcircuit 132 is the reverse process of the encoding process performed by the encoding subcircuit 111. The second grayscale data is the same as the first grayscale data. The encoding subcircuit 111 and the decoding subcircuit 132 will be described in detail later.

[0060] The second grayscale data is used to drive the display panel 300, including directly driving the display panel 300 with the second grayscale data, and indirectly driving the display panel 300 with the second grayscale data. The second grayscale data indirectly drives the display panel 300, that is, after processing the second grayscale data, the processed data is used to drive the display panel 300.

[0061] In summary, the peripheral driving circuit module provided in the embodiment of the present application uses the encoding subunit to encode the first grayscale data and the preset encoding data to obtain the first encoding data; the number of consecutive identical digits in the first encoding data is less than the number of consecutive identical digits in the first grayscale data, thereby reducing the number of consecutive identical digits, and thus reducing EMI. Therefore, when the peripheral driving circuit module is applied to the display screen assembly 10 and the electronic device 1, the EMI risk of the display screen assembly 10 and the EMI risk of the electronic device 1 can be reduced. The display screen assembly 10 and the electronic device 1 comply with the EMI standards of the corresponding country or region, or comply with the international EMI standards, to ensure the safety of the display screen assembly 10 and the electronic device 1, to ensure the health of the user, and to improve the safety of product use.

[0062] See also Figure 4 , Figure 4 The following is a schematic diagram of an encoding subcircuit and a decoding subcircuit provided in one embodiment. Figure 4 (a) is a schematic diagram of an encoding subcircuit provided in one embodiment; Figure 4 (b) is a schematic diagram of a decoding subcircuit provided by an embodiment. Figure 4 In (a), the encoding subcircuit 111 includes a first convolution unit 1111 and an encoding unit 1112. The first convolution unit 1111 stores the preset encoding data. The encoding unit 1112 includes a first input terminal 111a, a second input terminal 111b and a first output terminal 111c, the first input terminal 111a is used to receive the first grayscale data, the second input terminal 111b is electrically connected to the first convolution unit 1111, and the encoding unit 1112 is used to encode the first grayscale data and the preset encoding data to obtain the first encoding data.

[0063] The encoding subcircuit 111 includes a first convolution unit 1111 and an encoding unit 1112. The first convolution unit 1111 stores the preset encoding data. The encoding unit 1112 encodes the first grayscale data and the preset encoding data to obtain first encoding data. The number of consecutive identical digits in the first encoding data is less than the number of consecutive identical digits in the first grayscale data, thereby reducing the number of consecutive identical digits, thereby reducing EMI.

[0064] See also Figure 4In (b), the decoding subcircuit 132 includes a second convolution unit 1321 and a decoding unit 1322. The second convolution unit 1321 stores the preset decoded data. The decoding unit 1322 has a third input terminal 132a, a fourth input terminal 132b and a second output terminal 132c, the third input terminal 132a is used to receive the third encoded data, the fourth input terminal 132b is electrically connected to the second convolution unit 1321, and the decoding unit 1322 decodes the third encoded data and the decoded data to obtain the second grayscale data.

[0065] The decoding subcircuit 132 includes a second convolution unit 1321 and a decoding unit 1322. The second convolution unit 1321 stores the preset decoding data. The decoding unit 1322 decodes the third encoded data and the decoding data to obtain the second grayscale data. The second grayscale data is the same as the first grayscale data to ensure the correctness of the data finally output to the display panel 300.

[0066] For further information, see Figure 5 and Figure 6 , Figure 5 Schematic diagram of a peripheral driving circuit module provided for two implementation modes; Figure 6 is the truth table of XOR and XOR. Figure 5 In the implementation shown in (a), the encoding unit 1112 includes an XOR gate, and the decoding unit 1322 includes an XOR gate. Figure 5 In the implementation shown in (b), the encoding unit 1112 includes an XOR gate, and the decoding unit 1322 includes an XNOR gate. Figure 6 It is the truth table of XOR and XNOR, where A and B represent two data at the input end respectively.

[0067] Please also read Figure 7 and Figure 8 , Figure 7 A schematic diagram of data sent by a timing control circuit of a peripheral driving circuit module and data received by a data driving integrated circuit in the related art; Figure 8 A schematic diagram of data sent by a timing control circuit of a peripheral driving circuit module and data received by a data driving integrated circuit provided in an embodiment of the present application. Figure 8 (a) is a schematic diagram of data processing by the timing control circuit of the peripheral drive circuit module (see the part in the dotted box) and a schematic diagram of data processing by the data drive integrated circuit (see the part in the solid box); Figure 8 (b) in Figure 8 (a) is a schematic diagram of data processing by the timing control circuit; Figure 8(c) in Figure 8 (a) is a schematic diagram of the processing of data by the data driver integrated circuit. It should be noted that Figure 8 In the data processing, the encoding unit 1112 includes an XOR gate and an XNOR gate, and the decoding unit 1322 includes an XNOR gate. Figure 7 and Figure 8 In the example, the first grayscale data is 2-bit data, and the first grayscale data is "111111111; 11111111". Figure 7 In the related art shown in the figure, the data sent by the timing controller is "111111111; 11111111", and the data received by the data driver integrated circuit 130 is also "11111111; 11111111". It can be seen that when the data is transmitted between the timing control circuit 110 and the data driver circuit, it is transmitted as "11111111; 11111111", which includes 16 consecutive "1". Figure 8 In, see Figure 8 In the portion framed by the dotted line, the coded data stored in the first convolution unit 1111 is "01110110; 11011011", then, the first coded data output by the coding subcircuit 111 (which is an XOR gate) is "10001001; 00100100", which shows that after being processed by the coding subcircuit 111, the number of consecutive adjacent "1"s in the output first coded data is zero, and the number of consecutive adjacent "0"s is three. It can be seen that the number of consecutive identical digits (3) in the first coded data obtained after being processed by the first convolution unit 1111 and the coding unit 1112 in the coding subcircuit 111 is less than the number of consecutive identical digits (16) in the first grayscale data. Therefore, the number of consecutive identical digits in the first coded data is less than the number of consecutive identical digits in the first grayscale data, thereby reducing the number of consecutive identical digits, and thus reducing EMI.

[0068] Further, see Figure 8In the part framed by the solid line, the data received by the decoding subcircuit 132 is "10001001; 00100100". The decoded data in the second convolution unit 1321 is opposite to the encoded data of the first convolution unit 1111, that is, when the encoded data is the number "0", the decoded data is the number "1"; correspondingly, when the encoded data is the number "1", the decoded data is the number "0". Then, the encoded data stored in the first convolution unit 1111 is "01110110; 1101 1011", and the decoded data in the second convolution unit 1321 is "10001001; 00100100". Therefore, after being decoded by the decoding subcircuit 132, the second grayscale data obtained is "11111111; 11111111". It can be seen that the second grayscale data is equal to the first grayscale data, and the first grayscale data is not changed. In other words, the peripheral driving circuit module provided in the embodiment of the present application can ensure the consistency between the first grayscale data received by the timing control circuit 110 and the second grayscale data output by the data driving circuit.

[0069] It should be noted that, in one embodiment, the preset coding data has no pattern (in other words, the preset coding data is random). Then, when the coding sub-circuit 111 uses the first grayscale data and the preset coding data for coding processing, it avoids the appearance of more continuous numbers "1" in the obtained first coding data, and avoids the appearance of more continuous numbers "0" in the obtained first coding data, thereby reducing EMI during data transmission between the timing control circuit 110 and the data driving circuit.

[0070] In addition, the preset coding data is relatively complex. Optionally, the preset coding data is unique. In this way, when the first grayscale data and the preset coding data are used for encoding processing, it is possible to further avoid the appearance of more consecutive numbers "1" in the obtained first coding data, and further avoid the appearance of more consecutive numbers "0" in the obtained first coding data, thereby reducing EMI during data transmission between the timing control circuit 110 and the data driving circuit.

[0071] Optionally, in one embodiment, the preset coding data can be compiled, wherein the compilation method can be defined by the user.

[0072] Furthermore, the preset decoded data is completely opposite to the data in the preset encoded data, thereby ensuring the consistency of the second grayscale data obtained after encoding and decoding the first grayscale data.

[0073] Furthermore, the data quantity of the preset encoded data in the first convolution unit 1111 is less than or equal to the resolution of the display panel 300 driven by the peripheral driving circuit module.

[0074] For example, when the resolution of the display panel 300 is 3840*1920, the data amount of the preset coded data is less than or equal to 3840*1920. In other words, the data amount of the preset coded data is at most 3840*1920. In one embodiment, the data amount of the preset coded data is one-to-one or one-to-many with the resolution of the display panel 300.

[0075] When the data volume of the preset encoding data is one-to-one with the resolution of the display panel 300 , it is easier to encode the first grayscale data according to the preset encoding data.

[0076] When the amount of the preset coded data and the resolution of the display panel 300 are one-to-many, the amount of the preset coded data is relatively small, and encoding the first grayscale data according to the preset coded data is still relatively easy to process.

[0077] The data quantity of the preset coded data is related to the resolution of the display panel 300 driven by the peripheral driving circuit module 100. In this embodiment, the data quantity of the preset coded data in the first convolution unit 1111 is less than or equal to the resolution of the display panel 300 driven by the peripheral driving circuit module 100, thereby ensuring the consistency of the second grayscale data with the first grayscale data.

[0078] Since the preset decoded data is opposite to the preset coded data, and since the preset coded data is irregular, the preset decoded data is also irregular. Furthermore, the data quantity of the preset decoded data is less than or equal to the resolution of the display panel 300 driven by the peripheral driving circuit module.

[0079] For example, when the resolution of the display panel 300 is 3840*1920, the data amount of the preset decoded data is less than or equal to 3840*1920. In other words, the data amount of the preset decoded data is at most 3840*1920. In one embodiment, the data amount of the preset decoded data is one-to-one or one-to-many with the resolution of the display panel 300.

[0080] The data quantity of the preset decoded data is related to the resolution of the display panel 300 driven by the peripheral driving circuit module. In this embodiment, the data quantity of the preset decoded data in the second convolution unit 1321 is less than or equal to the resolution of the display panel 300 driven by the peripheral driving circuit module, thereby ensuring the consistency of the second grayscale data with the first grayscale data.

[0081] See also Fig. 9 , Fig. 9 Schematic diagram of a timing control circuit provided in one embodiment of the present application. In this embodiment, the timing control circuit 110 further includes a first sub-memory 115. The first sub-memory 115 is used to store the preset coded data. The encoding sub-circuit 111 is electrically connected to the first sub-memory 115, and is used to read the preset coded data in the first sub-memory 115.

[0082] In this embodiment, the timing control circuit 110 further includes a first sub-memory 115 , which stores the preset coding data, thereby facilitating the coding sub-circuit 111 to read the preset coding data, so that the timing control circuit 110 operates faster.

[0083] See also Fig.10 , Fig.10 Schematic diagram of a data driver integrated circuit provided in one embodiment of the present application. In this embodiment, the data driver integrated circuit 130 further includes a second sub-memory 135. The second sub-memory 135 is used to store the preset decoded data. The decoding sub-circuit 132 is electrically connected to the second sub-memory 135, and is used to read the preset decoded data in the second sub-memory 135.

[0084] In this embodiment, the data driver integrated circuit 130 further includes a second sub-memory 135, and the second sub-memory 135 stores the preset decoding data, so that the decoding sub-circuit 132 can exclusively use the preset decoding data, so that the data driver integrated circuit 130 can operate faster.

[0085] See also Fig.11 , Fig.11A circuit block diagram of a peripheral drive circuit module provided in another embodiment of the present application. In this embodiment, the peripheral drive circuit module further includes a memory 150. The memory 150 may be, but is not limited to, a flash memory. The memory 150 stores the preset coded data and the preset decoded data. The timing control circuit 110 and the data driver integrated circuit 130 are electrically connected to the memory 150 respectively, and the encoding subcircuit 111 of the timing control circuit 110 is used to call the preset coded data from the memory 150, and the decoding subcircuit 132 of the data driver integrated circuit 130 is used to call the preset decoded data from the memory 150.

[0086] See also Fig.12 , Fig.12 Schematic diagram of a timing control circuit provided in another embodiment. The timing control circuit 110 further includes a second data receiving subcircuit 113 (Data Receiver). The second data receiving subcircuit 113 is used to convert serial first original grayscale data into parallel second original grayscale data, wherein the first grayscale data is obtained from the second original grayscale data.

[0087] In this embodiment, the timing control circuit 110 also includes a second data receiving sub-circuit 113 which can be combined with the peripheral driving circuit module provided in any of the previous embodiments. In the schematic diagram of this embodiment, the timing control circuit 110 also includes a second data receiving sub-circuit 113 which is combined with the peripheral driving circuit module 100 provided in the previous embodiment as an example.

[0088] The second data receiving subcircuit 113 is used to convert serial first original grayscale data into parallel second original grayscale data, so as to facilitate other components in the timing control circuit 110 (such as the encoding subcircuit 111) to process the first grayscale data obtained according to the second original grayscale data.

[0089] The first grayscale data is obtained from the second original grayscale data, including: the first grayscale data is the second original grayscale data; or the second original grayscale data is processed to obtain the first grayscale data.

[0090] In one implementation, the second data receiving sub-circuit 113 is electrically connected to a system on chip (SOC) 160 to receive the first original grayscale data output by the SOC 160 .

[0091] See also Fig.13 , Fig.13A schematic diagram of a timing control circuit provided in another embodiment. The timing control circuit 110 further includes a second data receiving subcircuit 113 (Data Receiver). The second data receiving subcircuit 113 is used to convert serial first original grayscale data into parallel second original grayscale data, wherein the first grayscale data is obtained from the second original grayscale data.

[0092] Furthermore, the timing control circuit 110 further includes a core processor unit 114. The core processor unit 114 is electrically connected to the second data receiving subcircuit 113 and the encoding subunit 111, and is used to correct the second original grayscale data to obtain the first grayscale data.

[0093] The core processor unit 114 is used to correct the second original grayscale data so as to achieve a better display effect when driving the display panel 300. For example, the core processor unit 114 is used to correct the second original grayscale data to reduce or even eliminate abnormal highlights or abnormal black spots.

[0094] See also Fig.14 , Fig.14 Schematic diagram of a data driver integrated circuit provided in one embodiment. The data driver integrated circuit 130 further includes a digital-to-analog converter (DAC) 133. The digital-to-analog converter 133 is electrically connected to the decoding subcircuit 132, and is used to perform digital-to-analog conversion on the second grayscale data to obtain third grayscale data, wherein the second grayscale data is in a digital format and the third grayscale data is in an analog format.

[0095] The data driver integrated circuit 130 further includes a digital-to-analog converter 133 which can be combined with the peripheral driver circuit module 100 provided in any of the previous embodiments. In this embodiment, the data driver integrated circuit 130 further includes a digital-to-analog converter 133 which can be combined with the peripheral driver circuit module 100 provided in any of the previous embodiments is used as an example for illustration, which is understandable and should not be construed as limiting the embodiments of the present application.

[0096] The digital-to-analog converter 133 is electrically connected to the decoding subcircuit 132 , and is used for receiving the second grayscale data in a digital format and performing digital-to-analog conversion on the second grayscale data to obtain third grayscale data in an analog format.

[0097] The third grayscale data in analog format converted by the digital-to-analog converter 133 conforms to the format required by the display panel 300 for display, so as to drive the display panel 300 to operate.

[0098] See also Fig.15 , Fig.15 Schematic diagram of a data driver integrated circuit provided in one embodiment. The data driver integrated circuit 130 further includes a digital-to-analog converter 133. The digital-to-analog converter 133 is electrically connected to the decoding subcircuit 132 and is used to perform digital-to-analog conversion on the second grayscale data to obtain third grayscale data, wherein the second grayscale data is in a digital format and the third grayscale data is in an analog format.

[0099] Furthermore, the data driver integrated circuit 130 further includes a second conversion subcircuit 134. The second conversion subcircuit 134 is electrically connected to the digital-to-analog converter 133, and is used to process the third grayscale data to obtain fourth grayscale data, wherein the driving current of the fourth grayscale data is greater than the driving current of the third grayscale data.

[0100] For example, the driving current of the third grayscale data is 500mA, and the driving current of the fourth grayscale data is 1000mA, so that the driving capability of the peripheral driving circuit module is increased, and when the peripheral driving circuit module drives the display panel 300, the display surface has a better display quality. In one embodiment, the second conversion sub-circuit 134 may include an operational amplifier (OP) or a buffer.

[0101] In summary, the peripheral driving circuit module 100 provided in the embodiment of the present application is applicable to data transmission between two circuits using differential form. For example, it is also applicable to data transmission between the system-level chip 160 and the timing control circuit 110. The system-level chip 160 also includes an encoding subcircuit 111, and accordingly, the timing control circuit 110 also includes a decoding subcircuit 132 corresponding to the encoding subcircuit 111 in the system-level chip 160. In this way, EMI during data transmission between the system-level chip 160 and the timing control circuit 110 can be reduced.

[0102] In addition, the peripheral driving circuit module 100 provided in one embodiment of the present application can ensure that the data of the timing control circuit 110 in the peripheral driving circuit module 100 remains unchanged during the logic operation; ensure that the data of the data driving integrated circuit 130 remains unchanged during the operation; the timing control circuit 110 includes a first convolution unit 1111, which performs a convolution calculation; the data driving integrated circuit 130 includes a second convolution unit 1321, which performs a deconvolution calculation. The preset coded data stored in the first convolution unit 1111 can be relatively complex display screen data. The preset decoded data stored in the second convolution unit 1321 is opposite to the preset coded data.

[0103] The peripheral driving circuit module 100 provided in the embodiment of the present application can ensure that when transmitting digital signals, there will not be multiple consecutive identical numbers "0" and there will not be multiple consecutive identical numbers "1", thereby reducing EMI risks.

[0104] See also Fig.16 , Fig.16 Schematic diagram of a display screen assembly provided in one embodiment of the present application. The display screen assembly 10 includes a display panel 300 and a peripheral drive circuit module 100, and the peripheral drive circuit module is used to drive the display panel 300. The peripheral drive circuit module 100 is described in any of the previous embodiments, and will not be described again here. The display panel 300 may be, but is not limited to, an organic light emitting diode (OLED) display panel 300.

[0105] The display screen assembly 10 provided in the embodiment of the present application includes a peripheral drive circuit module 100, and the first grayscale data and the preset coding data are encoded by the coding subunit to obtain the first coding data; the number of consecutive identical digits in the first coding data is less than the number of consecutive identical digits in the first grayscale data, thereby reducing the number of consecutive identical digits, thereby reducing EMI. Therefore, the EMI risk of the display screen assembly 10 applied by the peripheral drive circuit module 100 is low. The display screen assembly 10 complies with the EMI standards of the corresponding country or region, or complies with the international EMI standards, thereby ensuring the safety of the display screen assembly 10, ensuring the health of the user, and improving the safety of product use.

[0106] An embodiment of the present application also provides an electronic device 1. The electronic device 1 may be, but is not limited to, a mobile phone, a tablet computer, etc. Fig.17 , Fig.17 This is a schematic diagram of an electronic device provided in one embodiment of the present application. The electronic device 1 includes a display screen assembly 10 as described in any of the above embodiments. Please refer to the above description of the display screen assembly 10, which will not be repeated here.

[0107] In summary, the embodiment of the present application provides an electronic device 1 including a display screen assembly 10, the display screen assembly 10 includes a peripheral driving circuit module, and the first grayscale data and the preset coding data are encoded by the encoding subunit to obtain the first coding data; the number of consecutive identical digits in the first coding data is less than the number of consecutive identical digits in the first grayscale data, thereby reducing the number of consecutive identical digits, and thus reducing EMI. Therefore, the EMI risk of the electronic device 1 can be reduced. The electronic device 1 is made to comply with the EMI standards of the corresponding country or region, or comply with the international EMI standards, to ensure the safety of the electronic device 1, to ensure the health of the user, and to improve the safety of product use.

[0108] In one embodiment, the electronic device 1 further includes a housing 30, and the housing 30 is used to carry the display panel 300. It is understandable that in other embodiments, the electronic device 1 may not include the housing 30. The embodiments of the present application do not limit whether the electronic device 1 includes the housing 30.

[0109] It should be noted that the examples and descriptions of the types of electronic devices 1 mentioned above are merely introductions to one application scenario of the display screen assembly 10 and should not be understood as limitations on the display screen assembly 10 provided in the embodiments of the present application.

[0110] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application, and these improvements and modifications are also regarded as the scope of protection of the present application.

Claims

1. A peripheral driving circuit module, characterized in that: The peripheral driving circuit module includes a timing control circuit and a data driving integrated circuit; The timing control circuit comprises: an encoding subcircuit, configured to encode the parallel first grayscale data and the preset encoding data to obtain the first encoding data; wherein the number of consecutive identical digits in the first grayscale data is a first number, and the number of consecutive identical digits in the first encoding data is a second number, wherein the second number is smaller than the first number; and a first conversion subcircuit, electrically connected to the encoding subcircuit, and configured to convert the first encoded data into serial and differential second encoded data; The data driving integrated circuit comprises: a first data receiving subcircuit, electrically connected to the first conversion subcircuit, and configured to convert the second coded data into parallel third coded data; and a decoding subcircuit, electrically connected to the first data receiving subcircuit, and configured to decode the third encoded data and the preset decoded data to obtain second grayscale data, wherein the second grayscale data is used to drive the display panel; Wherein, the encoding subcircuit comprises: a first convolution unit, wherein the first convolution unit stores the preset coded data; and The encoding unit includes a first input terminal, a second input terminal and a first output terminal, the first input terminal is used to receive the first grayscale data, the second input terminal is electrically connected to the first convolution unit, and the encoding unit is used to encode the first grayscale data and the preset encoding data to obtain the first encoding data.

2. The peripheral driving circuit module according to claim 1, wherein: The decoding subcircuit comprises: a second convolution unit, wherein the second convolution unit stores the preset decoding data; and A decoding unit, wherein the decoding unit has a third input terminal, a fourth input terminal and a second output terminal, the third input terminal is used to receive the third encoded data, the fourth input terminal is electrically connected to the second convolution unit, and the decoding unit decodes the third encoded data and the decoded data to obtain the second grayscale data.

3. The peripheral driving circuit module according to claim 2, characterized in that: The encoding unit includes an XOR gate, and the decoding unit includes an XNOR gate; Alternatively, the encoding unit includes an XOR gate, and the decoding unit includes an XOR gate.

4. The peripheral driving circuit module according to any one of claims 1 to 3, characterized in that: The timing control circuit also includes: The second data receiving sub-circuit is used to convert the serial first original grayscale data into parallel second original grayscale data, wherein the first grayscale data is obtained from the second original grayscale data.

5. The peripheral driving circuit module according to claim 4, characterized in that: The timing control circuit also includes: A core processor unit is electrically connected to the second data receiving subcircuit and the encoding subcircuit, and is used for correcting the second original grayscale data to obtain the first grayscale data.

6. The peripheral driving circuit module according to any one of claims 1 to 3, characterized in that: The data driver integrated circuit further includes: A digital-to-analog converter is electrically connected to the decoding subcircuit and is used for performing digital-to-analog conversion on the second grayscale data to obtain third grayscale data, wherein the second grayscale data is in a digital format and the third grayscale data is in an analog format.

7. The peripheral driving circuit module according to claim 6, characterized in that: The data driver integrated circuit further includes: The second conversion sub-circuit is electrically connected to the digital-to-analog converter, and is used for processing the third grayscale data to obtain fourth grayscale data, wherein a driving current of the fourth grayscale data is greater than a driving current of the third grayscale data.

8. A display screen assembly, characterized in that: The display screen assembly comprises: display panel; and The peripheral driving circuit module according to any one of claims 1 to 7, wherein the peripheral driving circuit module is used to drive the display panel.

9. An electronic device, characterized in that: The electronic device comprises the display screen assembly as claimed in claim 8.

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