A method for determining through silicon via etching parameters, through silicon via forming method and etching equipment

Abstract

The present invention discloses a method for determining through silicon via etching parameters, a method for forming a through silicon via and an etching device. The parameter determination method comprises forming a first through silicon via of a target depth with a first etching parameter and obtaining a first morphology and a first similarity between the first morphology and a preset morphology; when the first similarity is outside a threshold range, determining a first abnormal depth range of the first morphology, and determining a first etching depth corresponding to a first abnormal inflection point of the first morphology within the first abnormal depth range based on a dichotomy method; when etching to the first etching depth with the first etching parameter, adjusting the first etching parameter to a second etching parameter, and etching to the target depth with the second etching parameter and obtaining a second morphology; until the similarity between the acquired morphology and the preset morphology is within the threshold range, obtaining a total etching parameter capable of forming a through silicon via of a target depth corresponding to the preset morphology, and the total etching parameter is beneficial to improving the verticality and consistency of the through silicon via.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for determining silicon via etching parameters, a method for forming silicon vias, and an etching apparatus. Background Technology

[0002] As Moore's Law gradually approaches its physical limits, the field of advanced 3D packaging has largely adopted vertical interconnect structures using through-silicon vias (TSVs) to create vertical conductive paths with high aspect ratios, thereby increasing the system's integration density and enabling high-performance and low-power 3D systems.

[0003] As the TSV etching depth continues to increase and the types of patterns become more diverse, it becomes increasingly difficult to maintain the verticality of the bottom morphology of the via and the consistency of etching depth for patterns of different sizes. Summary of the Invention

[0004] This invention provides a method for determining silicon via etching parameters, a method for forming silicon vias, and an etching apparatus to solve the problems of verticality and consistency of silicon via morphology in related technologies.

[0005] To address the above problems, a first aspect of the present invention provides a method for determining etching parameters of through-silicon vias (TSVs), comprising the following steps:

[0006] During the formation of the first through-silicon via (TSV), a first TSV of a target depth is formed on the silicon wafer using a first etching parameter, and a first morphology of the first TSV is obtained.

[0007] Obtain the first similarity between the first morphology and the preset morphology; when the first similarity is outside the threshold range, determine the first abnormal depth range of the first morphology, and determine the first etching depth corresponding to the first abnormal inflection point of the first morphology within the first abnormal depth range based on the binary search method.

[0008] During the formation of the second through-silicon via (TSV), when etching to the first etching depth using the first etching parameters, the first etching parameters are adjusted to the second etching parameters, and etching is performed to the target depth using the second etching parameters to form the second TSV and obtain the second morphology of the second TSV.

[0009] Obtain the second similarity between the second morphology and the preset morphology; when the second similarity is outside the threshold range, determine the second abnormal depth range of the second morphology, and determine the second etching depth corresponding to the second abnormal inflection point of the second morphology within the second abnormal depth range based on the bisection method;

[0010] Repeating this process sequentially, during the formation of the i-th through-silicon via, etching is performed to the first etching depth using the first etching parameter, and then to the second etching depth using the second etching parameter. When etching is performed to the (i-1)-th etching depth using the (i-1)-th etching parameter, the (i-1)-th etching parameter is adjusted to the i-th etching parameter, and etching is performed to the target depth using the i-th etching parameter to form the i-th through-silicon via, and the i-th morphology of the i-th through-silicon via is obtained.

[0011] Until the similarity between the i-th morphology and the preset morphology is within a threshold range, the total etching parameters for forming a through-silicon via at the target depth corresponding to the preset morphology are obtained, where i is an integer greater than 1, and the total etching parameters include the first etching parameters to the i-th etching parameters.

[0012] Optionally, when the first similarity is outside the threshold range, determining the first abnormal depth range of the first morphology, and determining the first etching depth corresponding to the first abnormal inflection point of the first morphology within the first abnormal depth range based on a binary search method includes:

[0013] A silicon via of a first preset depth is etched on a silicon wafer using a first etching parameter to obtain the morphology of the silicon via at the first preset depth. The first abnormal depth range is from a first depth to a second depth, and the first preset depth is the sum of half of the first abnormal depth range and the first depth.

[0014] When the similarity between the morphology of the via at the first preset depth and the preset morphology of the via at the first preset depth is outside the threshold range, the via at the second preset depth is etched on the silicon wafer using the first etching parameters to obtain the morphology of the via at the second preset depth; wherein, the second preset depth is the difference between the first preset depth and one-quarter of the first abnormal depth range;

[0015] When the similarity between the morphology of the through-silicon via at the first preset depth and the preset morphology of the through-silicon via at the first preset depth is within a threshold range, the second preset depth is the sum of the first preset depth and one-quarter of the first abnormal depth range.

[0016] This process is repeated until the critical depth at which the similarity between the first morphology and the preset morphology is within a threshold range is determined along the etching direction, and the critical depth is taken as the first etching depth corresponding to the first abnormal inflection point.

[0017] Optionally, during the formation of the second through-silicon via, when etching to the first etching depth using the first etching parameters, adjusting the first etching parameters to the second etching parameters includes:

[0018] When the size of the through-silicon via at the target depth in the first morphology is smaller than the size of the through-silicon via at the first etching depth in the preset morphology, the ratio of the amount of etching gas to the amount of passivation gas in the second etching parameter is greater than the ratio of the amount of etching gas to the amount of passivation gas in the first etching parameter.

[0019] When the size of the through-silicon via at the target depth in the first morphology is greater than the size of the through-silicon via at the first etching depth in the preset morphology, the ratio of the amount of etching gas to the amount of passivation gas in the second etching parameters is less than the ratio of the amount of etching gas to the amount of passivation gas in the first etching parameters.

[0020] Optionally, during the formation of the second through-silicon via, when etching to the first etching depth using the first etching parameters, adjusting the first etching parameters to the second etching parameters includes:

[0021] When the size of the through-silicon via at the target depth in the first morphology is smaller than the size of the through-silicon via at the first etching depth in the preset morphology, the ratio of etching time to passivation time in the second etching parameters is greater than the ratio of etching time to passivation time in the first etching parameters.

[0022] When the size of the through-silicon via at the target depth in the first morphology is greater than the size of the through-silicon via at the first etching depth in the preset morphology, the ratio of etching time to passivation time in the second etching parameters is less than the ratio of etching time to passivation time in the first etching parameters.

[0023] Optionally, during the formation of the second through-silicon via, when etching to the first etching depth using the first etching parameters, adjusting the first etching parameters to the second etching parameters includes:

[0024] When the size of the through-silicon via at the target depth in the first morphology is smaller than the size of the through-silicon via at the first etching depth in the preset morphology, the distance between the silicon wafer adsorption disk and the plasma generator in the second etching parameters is greater than the distance between the silicon wafer adsorption disk and the plasma generator in the first etching parameters.

[0025] When the size of the through-silicon via at the target depth in the first morphology is greater than the size of the through-silicon via at the first etching depth in the preset morphology, the distance between the silicon wafer adsorption disk and the plasma generator in the second etching parameters is less than the distance between the silicon wafer adsorption disk and the plasma generator in the first etching parameters.

[0026] Optionally, obtaining the first similarity between the first morphology and the preset morphology includes:

[0027] The inclination or overlap between the sidewall of the first through-silicon via corresponding to the first morphology and the sidewall of the preset through-silicon via corresponding to the preset morphology is obtained as the first similarity.

[0028] When the tilt is within a preset range, or when the overlap is within a preset range, the first similarity is within a threshold range;

[0029] When the tilt is not within the preset range, and the overlap is not within the preset range, the first similarity is outside the threshold range.

[0030] To address the above problems, a second aspect of the present invention provides a method for forming through-silicon vias (TSVs), comprising:

[0031] Provide the silicon substrate to be etched;

[0032] The total etching stage of the through-silicon via (TSV) to be formed is obtained by using the total etching parameters determined by the TSV etching parameter determination method described in any embodiment of the present invention;

[0033] In the overall etching stage, the Bosch process of etching and passivation deposition is used cyclically to etch the silicon substrate to be etched, forming through-silicon vias at the target depth.

[0034] Optionally, in the etching parameters, the etching temperature range is 10℃-60℃, the etching chamber pressure is 1mtorr-100mtorr, the etching source RF power is 100-3000W, and the etching bias RF power is 10-500W.

[0035] Optionally, after forming the through-silicon via at the target depth, the method further includes:

[0036] The through-silicon vias at the target depth are cleaned at a temperature of 10°C to 300°C, and the cleaning reaction gases include at least SF6, O2, or N2.

[0037] To address the aforementioned problems, a third aspect of the present invention provides an etching apparatus for performing the silicon via etching parameter determination method described in any embodiment of the present invention, or the silicon via formation method described in any embodiment of the present invention.

[0038] According to embodiments of the present invention, a method for determining etching parameters for through-silicon vias (TSVs), a method for forming TSVs, and an etching apparatus are provided. The etching parameter determination method includes, during a first TSV formation process, forming a first TSV at a target depth on a silicon wafer using first etching parameters and acquiring a first morphology of the first TSV; acquiring a first similarity between the first morphology and a preset morphology; when the first similarity is outside a threshold range, determining a first abnormal depth range of the first morphology, and determining a first etching depth corresponding to a first abnormal inflection point of the first morphology within the first abnormal depth range based on a bisection method; during a second TSV formation process, when etching to a first etching depth using the first etching parameters, adjusting the first etching parameters to second etching parameters, and etching to a target depth using the second etching parameters to form a second TSV, and acquiring a second morphology of the second TSV; acquiring a second similarity between the second morphology and a preset morphology. When the second similarity is outside the threshold range, the second abnormal depth range of the second morphology is determined, and the second etching depth corresponding to the second abnormal inflection point of the second morphology is determined within the second abnormal depth range based on the bisection method; this process is repeated sequentially. During the formation of the i-th through-silicon via, etching is performed to the first etching depth using the first etching parameter, and to the second etching depth using the second etching parameter. When etching is performed to the i-1-th etching depth using the i-1-th etching parameter, the i-1-th etching parameter is adjusted to the i-th etching parameter, and etching is performed to the target depth using the i-th etching parameter to form the i-th through-silicon via, and the i-th morphology of the i-th through-silicon via is obtained; until the i-th similarity between the i-th morphology and the preset morphology is within the threshold range, the total etching parameters that can form the target depth of the preset morphology through-silicon via are obtained, where i is an integer greater than 1, and the total etching parameters include the first etching parameter to the i-th etching parameter. Therefore, after forming a through-silicon via (TSV) at the target depth, it can be compared with a preset morphology to determine the abnormal depth range of the current TSV. Then, within the abnormal depth range, the etching depth corresponding to the inflection point is determined, and the etching parameters are adjusted when etching to that etching depth in the next etching process until the final TSV morphology is close to or the same as the preset morphology. The etching parameters adjusted for verticality at each inflection point are used as the TSV etching parameters. In subsequent etching processes, etching is performed using these TSV etching parameters to obtain TSVs that are close to or the same as the preset morphology, thereby improving the verticality and consistency of the TSV.

[0039] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description.

[0040] The present invention has the following advantages: by continuously adjusting the etching parameters through the through-silicon via (TSV) etching parameter determination method, the total etching parameters that can maintain the verticality and consistency of the TSV morphology are determined. In subsequent etching processes, TSVs with good verticality and consistency can be obtained without frequent adjustment of the etching parameters. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart of the method for determining silicon via etching parameters proposed in an embodiment of the present invention;

[0043] Figure 2 The morphology of the through-silicon via (TSV) is obtained during the process of determining the etching parameters of the TSV proposed in this embodiment of the invention.

[0044] Figure 3 This is a flowchart of the bisection method for determining the etching parameters of through-silicon vias (TSVs) proposed in this embodiment of the invention.

[0045] Figure 4 This is a structural diagram corresponding to the bisection method of the through-silicon via etching parameter determination method proposed in this embodiment of the invention;

[0046] Figure 5 This is a flowchart of the through-silicon via (TSV) formation method proposed in an embodiment of the present invention;

[0047] Figure 6 This is a schematic diagram of a through-silicon via electron scanning microscope formed in related technologies;

[0048] Figure 7 This is a schematic diagram of a through-silicon via electron scanning microscope formed according to an embodiment of the present invention;

[0049] Figure 8 This is a schematic diagram of the etching device structure proposed in an embodiment of the present invention. Detailed Implementation

[0050] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0051] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0052] In related technologies, through-silicon vias (TSVs) are typically formed on silicon wafers using the Bosch process. However, due to the narrow etching window in the Bosch process, adjustments are often not made during etching, or a coarse adjustment method is used. When using a coarse adjustment method, such as fixed-step adjustment, adjustments may be made at depths where adjustments are needed (e.g., poor perpendicularity) but not at depths where adjustments are unnecessary (e.g., good perpendicularity). Consequently, the methods in related technologies are not only time-consuming and costly to adjust, but also result in poor perpendicularity and consistency of the etched TSVs. Therefore, the TSV etching parameter determination method proposed in this invention can predetermine the etching parameters for TSVs with the same morphology as a preset shape, and can pinpoint each inflection point for parameter adjustment. In practical applications, the etching parameters determined by this method can be directly used for etching, which helps improve the perpendicularity and consistency of the TSVs.

[0053] Figure 1 This is a flowchart of the method for determining silicon via etching parameters proposed in an embodiment of the present invention. Figure 1 As shown, the method for determining the etching parameters of a through-silicon via (TSV) includes the following steps:

[0054] S101, during the formation of the first through-silicon via, a first through-silicon via of a target depth is formed on the silicon wafer using the first etching parameters, and the first morphology of the first through-silicon via is obtained.

[0055] The target depth can be set according to requirements. The first etching parameters include etching gas volume, passivation gas volume, etching time, passivation time, etching temperature, etching chamber pressure, etching source RF power, etching bias RF power, and the distance between the silicon wafer adsorption disk and the plasma generator. The first etching parameter can be understood as a preset etching parameter, under which theoretically, a through-silicon via (TSV) with the same morphology as the preset can be obtained. This preset etching parameter is generally an empirical value. Because it becomes increasingly difficult for ions to enter and exit the trench as the etching depth increases during actual etching, the etching parameters may need to change (mostly non-linearly), and the morphology of the TSV formed according to the preset etching parameters may not meet the preset morphology requirements. In related technologies, even with linear control (fixed step size) of the preset etching parameter changes, ideal results are still not achieved.

[0056] Therefore, in step S101, a first through-silicon via (TSV) of the target depth is first formed using the first etching parameter. The first etching parameter can be kept constant, or it can be gradually varied with a fixed step size. In steps S102-S104, the preset etching parameter, i.e., the first etching parameter, is modified or changed.

[0057] S102, obtain the first similarity between the first morphology and the preset morphology; when the first similarity is outside the threshold range, determine the first abnormal depth range of the first morphology, and determine the first etching depth corresponding to the first abnormal inflection point of the first morphology within the first abnormal depth range based on the binary method.

[0058] After the first through-silicon via (TSV) is formed, it can be sliced ​​and its initial morphology obtained using an electron microscope, and then compared with the desired pre-defined morphology. The pre-defined morphology can be generated using simulation software.

[0059] In one embodiment, the first similarity between a first morphology and a preset morphology can be reflected by the perpendicularity of the hole walls in the first morphology. Generally, the perpendicularity of the preset morphology is 90°, and the perpendicularity of the hole walls in the first morphology can be measured. For example, if the target depth is 80 μm, then the perpendicularity of the hole walls is 80° between 0 and 80 μm, and the threshold range can be 0-1°. Therefore, it can be seen that the first similarity between the first morphology and the preset morphology exceeds the threshold range and is outside the threshold range. Conversely, if the perpendicularity of the hole walls is 89.3° between 0 and 80 μm, then the first similarity between the first morphology and the preset morphology does not exceed the threshold range and is within the threshold range.

[0060] In another embodiment, similarity can be calculated between two shapes: 1 for complete overlap, 0.5 for partial overlap, and 0 for no overlap. The threshold range can then be set to 0.9-1.

[0061] When the first similarity is determined to be outside the threshold range, the verticality of the hole wall is generally acceptable during the initial etching. An inflection point will suddenly appear at a certain location, allowing a rough indication of the inflection point's location range in the morphology. This inflection point's location range is taken as the first abnormal depth range of the first morphology. Then, a bisection method is used to determine the precise location of the first inflection point within the first abnormal depth range. For example, if the first abnormal depth range is 60-70 μm, a bisection method can be used to determine the first etching depth corresponding to the first inflection point within the 60-70 μm range.

[0062] S103, during the formation of the second through-silicon via (TSV), when etching to the first etching depth using the first etching parameters, the first etching parameters are adjusted to the second etching parameters, and etching is performed to the target depth using the second etching parameters to form the second TSV, and the second morphology of the second TSV is obtained. A second similarity score is obtained between the second morphology and a preset morphology; when the second similarity score is outside a threshold range, a second abnormal depth range of the second morphology is determined, and based on a bisection method, the second etching depth corresponding to the second abnormal inflection point of the second morphology is determined within the second abnormal depth range.

[0063] Specifically, when the similarity between the first morphology of the first through-silicon via (TSV) and the preset morphology is outside a threshold range, and the first etching depth corresponding to the first inflection point is found through step S102, a second TSV can be formed on the silicon wafer at a different location than the first TSV. When etching to the first etching depth using the first etching parameters, the etching parameters are adjusted to change the perpendicularity corresponding to the first inflection point. After forming the second TSV, a slice analysis can be performed to obtain the second morphology of the second TSV. By comparing the second morphology with the preset morphology, the appropriateness of the adjusted etching parameters can be verified. When the similarity between the second morphology and the preset morphology is within a threshold range, it indicates that the adjusted second etching parameters are reasonable. At this point, the first and second etching parameters can be used as the total etching parameters.

[0064] When the similarity between the second morphology and the preset morphology is outside the threshold range, it indicates that the adjusted second etching parameters are unreasonable. One possibility is that the verticality at the first inflection point is still problematic, and another possibility is that the verticality at the first inflection point has been corrected, but new inflection points appear at other locations between the first etching depth and the target depth.

[0065] If the verticality at the first inflection point within the first abnormal depth range remains problematic, the second etching parameters need to be fine-tuned. For example, if the abnormal portion in the first via is narrower at the top and wider at the bottom, and the adjusted abnormal portion of the second via is wider at the top and narrower at the bottom, it indicates that the second etching parameters have been over-adjusted and need to be adjusted back towards the portion closer to the first etching parameters. If the abnormal portion in the first via is narrower at the top and wider at the bottom, and the adjusted abnormal portion of the first via remains narrower at the top and wider at the bottom, but with a reduced amplitude, it indicates that the second etching parameters have been under-adjusted and need to be adjusted towards the portion farther from the first etching parameters.

[0066] If the verticality at the first inflection point within the first abnormal depth range has been corrected, and a new inflection point appears, it is necessary to determine the second abnormal depth range and then redetermine the second etching depth corresponding to the second inflection point. Repeat steps S102 and S103.

[0067] The above can be understood as follows: when the second similarity between the second morphology and the preset morphology is outside the threshold range, a second anomaly depth range is determined, and a second etching depth corresponding to the second anomaly inflection point of the second morphology is determined within the second anomaly depth range based on a bisection method. If the first etching depth and the second etching depth are the same, then at the first etching depth, the first etching parameter is adjusted to the second etching parameter (adjusted relative to the previous second etching parameter). If the first etching depth and the second etching depth are different, then at the first etching depth, the first etching parameter is adjusted to the second etching parameter, and at the second etching depth, the second etching parameter is adjusted to the third etching parameter, and so on. At this time, the first etching parameter, the second etching parameter corrected for the first anomaly inflection point, and the third etching parameter corrected for the second anomaly inflection point can be used as the total etching parameters.

[0068] S104, repeating sequentially, during the formation of the i-th through-silicon via, etching to the first etching depth with the first etching parameter, etching to the second etching depth with the second etching parameter, when etching to the (i-1)-th etching depth with the (i-1)-th etching parameter, adjusting the (i-1)-th etching parameter to the i-th etching parameter, and etching to the target depth with the i-th etching parameter to form the i-th through-silicon via, and obtaining the i-th morphology of the i-th through-silicon via; until the i-th similarity between the i-th morphology and the preset morphology is within the threshold range, the total etching parameters that can form the through-silicon via at the target depth corresponding to the preset morphology are obtained, where i is an integer greater than 1, and the total etching parameters include the first etching parameter to the i-th etching parameter.

[0069] Therefore, when the adjusted etching parameters ensure that the similarity between the current via morphology and the preset morphology is within a threshold range, this set of etching parameters is used as the etching parameters for the via at the target depth corresponding to the preset morphology. In other words, by saving the etching parameters at each inflection point, and then etching again according to the saved parameters, a via with the preset morphology can be obtained. This improves the perpendicularity of the via and enhances the accuracy of the etching process.

[0070] Optionally, in S102, when the first similarity is outside the threshold range, determining the first abnormal depth range of the first morphology, and determining the first etching depth corresponding to the first abnormal inflection point of the first morphology within the first abnormal depth range based on the binary method includes:

[0071] S1021, Etch a silicon via at a first preset depth on the silicon wafer using the first etching parameters to obtain the morphology of the silicon via at the first preset depth, wherein the first abnormal depth range is from the first depth to the second depth, and the first preset depth is the sum of half of the first abnormal depth range and the first depth;

[0072] S1022, when the similarity between the morphology of the through-silicon via at the first preset depth and the preset morphology of the through-silicon via at the first preset depth is outside the threshold range, the through-silicon via at the second preset depth is etched on the silicon wafer with the first etching parameters to obtain the morphology of the through-silicon via at the second preset depth; wherein, the second preset depth is the difference between the first preset depth and one-quarter of the first abnormal depth range.

[0073] S1023, when the similarity between the morphology of the through-silicon via at the first preset depth and the preset morphology of the through-silicon via at the first preset depth is within a threshold range, the second preset depth is the sum of the first preset depth and one-quarter of the range of the first abnormal depth.

[0074] S1024, repeat in sequence, until the critical depth of the similarity between the first morphology and the preset morphology is determined to be within the threshold range along the etching direction, and the critical depth is taken as the first etching depth corresponding to the first abnormal inflection point.

[0075] Understandable, Figure 2 The morphology of the through-silicon via (TSV) is obtained during the process of determining the etching parameters of the TSV proposed in this embodiment of the invention. Figure 2 In the middle (a), the morphology is the preset shape. Figure 2 (b) Figure 2 In the diagram (e), other morphologies that differ from the preset morphology are defined during the etching parameter determination process. This step uses the first morphology as an example for explanation. If the i-th morphology in other steps requires bisection analysis, please refer to the description in this step.

[0076] by Figure 2(d) in the figure represents the first morphological example, i.e., formed in step S101. Figure 2 In (d), the depth range of the first anomaly is 60μm-70μm obtained by slicing. Figure 3 This is a flowchart of the bisection method for determining silicon via etching parameters according to an embodiment of the present invention. Figure 4 This is a structural diagram corresponding to the bisection method for determining silicon via etching parameters proposed in this embodiment of the invention. (Reference) Figure 3 and Figure 4 As shown, after determining the first abnormal depth range, a first preset depth (65μm) can be etched at another location on the silicon wafer, i.e., 60 + (70 - 60) / 2 = 65μm. If the similarity between the morphology obtained at 65μm in S1021 and the preset morphology is outside the threshold range, it indicates that there is a first inflection point between 60μm and 65μm. Then, in S1022, a second preset depth (62.5μm) can be etched at another location on the silicon wafer, i.e., 65 - (70 - 60) / 4 = 62.5μm, and the binary division continues. If the similarity between the morphology obtained at 65μm in S1021 and the preset morphology is within the threshold range, it indicates that there is no first inflection point between 60μm and 65μm. Then, in S1023, a second preset depth (67.5μm) can be etched at another location on the silicon wafer, i.e., 65 + (70 - 60) / 4 = 67.5μm.

[0077] Similarly, after S1022, if the similarity between the obtained 62.5μm morphology and the preset morphology is outside the threshold range, it indicates that there is a first inflection point between 60μm and 62.5μm. Then, in the next etching, the preset depth is set to 61.25μm and kept approaching until the first etching depth corresponding to the first inflection point is found.

[0078] After S1023, if the similarity between the obtained 67.5μm morphology and the preset morphology is within the threshold range, it indicates that there is a first inflection point between 65-67.5μm. Then, in the next etching, the preset depth is set to 66.25μm and kept approaching until the first etching depth corresponding to the first inflection point is found.

[0079] After determining the first etching depth, the critical depth at which the similarity between the first morphology and the preset morphology is within the threshold range is found, and the first etching parameter can be adjusted to the second etching parameter at that point.

[0080] like Figure 2 For example, (e) can be referred to in the description of (d) above. Figure 2 Examples (b) and (c) are extreme cases, where the depth of the anomaly can range from 0 to 80 μm, with the inflection point at 0 μm.

[0081] Optionally, during the formation of the second through-silicon via, when etching to the first etching depth using the first etching parameters, adjusting the first etching parameters to the second etching parameters includes:

[0082] When the size of the through-silicon via at the target depth in the first morphology is smaller than the size of the through-silicon via at the first etching depth in the preset morphology, the ratio of the amount of etching gas to the amount of passivation gas in the second etching parameters is greater than the ratio of the amount of etching gas to the amount of passivation gas in the first etching parameters.

[0083] When the size of the through-silicon via at the target depth in the first morphology is greater than the size of the through-silicon via at the first etching depth in the preset morphology, the ratio of the amount of etching gas to the amount of passivation gas in the second etching parameters is less than the ratio of the amount of etching gas to the amount of passivation gas in the first etching parameters.

[0084] Understandably, after determining the critical depth of the first morphology, the via size at the target depth in the first morphology is compared with the via size at the first etching depth in the preset morphology. If the via size at the first etching depth in the preset morphology is larger than the via size at the target depth in the first morphology, it indicates that the amount of etching gas in the first etching parameters of the first morphology is insufficient and / or the amount of passivation gas is excessive. Therefore, the amount of etching gas can be increased and / or the amount of passivation gas can be decreased, i.e., the ratio of etching gas amount to passivation gas amount can be increased.

[0085] Conversely, after determining the critical depth of the first morphology, the via size at the target depth in the first morphology is compared with the via size at the first etching depth in the preset morphology. If the via size at the first etching depth in the preset morphology is smaller than the via size at the target depth in the first morphology, it indicates that the amount of etching gas in the first etching parameters of the first morphology is excessive and / or the amount of passivation gas is insufficient. Therefore, the amount of etching gas can be reduced and / or the amount of passivation gas can be increased, i.e., the ratio of etching gas to passivation gas can be reduced.

[0086] The etching gas may include at least SF6, and the passivation gas may include at least C4F8.

[0087] Optionally, during the formation of the second through-silicon via, when etching to the first etching depth using the first etching parameters, adjusting the first etching parameters to the second etching parameters includes:

[0088] When the size of the through-silicon via at the target depth in the first morphology is smaller than the size of the through-silicon via at the first etching depth in the preset morphology, the ratio of etching time to passivation time in the second etching parameters is greater than the ratio of etching time to passivation time in the first etching parameters.

[0089] When the size of the through-silicon via at the target depth in the first morphology is greater than the size of the through-silicon via at the first etching depth in the preset morphology, the ratio of etching time to passivation time in the second etching parameters is less than the ratio of etching time to passivation time in the first etching parameters.

[0090] Understandably, after determining the critical depth of the first morphology, the via size at the target depth in the first morphology is compared with the via size at the first etching depth in the preset morphology. If the via size at the first etching depth in the preset morphology is larger than the via size at the target depth in the first morphology, it indicates that the etching time in the first etching parameters of the first morphology is insufficient and / or the passivation time is excessive. Therefore, the etching time can be increased and / or the passivation time can be decreased, i.e., the ratio of etching time to passivation time can be increased.

[0091] Conversely, after determining the critical depth of the first morphology, the via size at the target depth in the first morphology is compared with the via size at the first etching depth in the preset morphology. If the via size at the first etching depth in the preset morphology is smaller than the via size at the target depth in the first morphology, it indicates that the etching time in the first etching parameters of the first morphology is excessive and / or the passivation time is insufficient. Therefore, the etching time can be reduced and / or the passivation time increased, i.e., the ratio of etching time to passivation time can be reduced.

[0092] In one embodiment, the ratio of etching gas to passivation gas can be adjusted first. If the ratio of etching gas to passivation gas has reached the etching process window limit, the verticality of the morphology can be improved by adjusting the ratio of etching time to passivation time.

[0093] Optionally, during the formation of the second through-silicon via, when etching to the first etching depth using the first etching parameters, adjusting the first etching parameters to the second etching parameters includes:

[0094] When the size of the silicon via at the target depth in the first morphology is smaller than the size of the silicon via at the first etching depth in the preset morphology, the distance between the silicon wafer adsorption disk and the plasma generator in the second etching parameters is greater than the distance between the silicon wafer adsorption disk and the plasma generator in the first etching parameters.

[0095] When the size of the through-silicon via at the target depth in the first morphology is greater than the size of the through-silicon via at the first etching depth in the preset morphology, the distance between the silicon wafer adsorption disk and the plasma generator in the second etching parameters is less than the distance between the silicon wafer adsorption disk and the plasma generator in the first etching parameters.

[0096] Understandably, after determining the critical depth of the first morphology, the size of the through-silicon via (TSV) at the target depth in the first morphology is compared with the size of the TSV at the first etching depth in the preset morphology. If the size of the TSV at the first etching depth in the preset morphology is larger than the size of the TSV at the target depth in the first morphology, it indicates that the distance between the plasma generator and the silicon wafer adsorption disk may be too large, and the distance can be reduced.

[0097] Conversely, after determining the critical depth of the first morphology, the size of the through-silicon via at the target depth in the first morphology is compared with the size of the through-silicon via at the first etching depth in the preset morphology. If the size of the through-silicon via at the first etching depth in the preset morphology is smaller than the size of the through-silicon via at the target depth in the first morphology, it indicates that the distance between the plasma generator and the silicon wafer adsorption disk may be too small, and the distance can be increased.

[0098] In one embodiment, the ratio of etching gas to passivation gas can be adjusted first. If this ratio already reaches the etching process window limit, the verticality of the morphology can be improved by adjusting the ratio of etching time to passivation time. If the ratio of etching time to passivation time also reaches the etching process window limit, the verticality can be improved by adjusting the distance between the plasma generator and the silicon wafer adsorption pad. The distance between the plasma generator and the silicon wafer adsorption pad can be adjusted within the range of 1-100 mm.

[0099] Optionally, obtaining the first similarity between the first morphology and the preset morphology includes:

[0100] The inclination or overlap between the sidewall of the first through-silicon via corresponding to the first morphology and the sidewall of the preset through-silicon via corresponding to the preset morphology is obtained as the first similarity.

[0101] When the tilt is within a preset range, or the overlap is within a preset range, the first similarity is within a threshold range;

[0102] When the tilt is not within the preset range, and the overlap is not within the preset range, the first similarity is outside the threshold range.

[0103] In other words, the initial similarity between the first morphology and the preset morphology can be reflected by the perpendicularity of the hole wall in the first morphology. Generally, the perpendicularity of the preset morphology is 90°, and the perpendicularity of the hole wall in the first morphology can be measured. For example, if the target depth is 80 μm, then the perpendicularity of the hole wall is 80° between 0 and 80 μm, and the threshold range can be 0-1°. Therefore, it can be seen that the initial similarity between the first morphology and the preset morphology exceeds the threshold range and is outside the threshold range. Conversely, if the perpendicularity of the hole wall is 89.3° between 0 and 80 μm, then the initial similarity between the first morphology and the preset morphology does not exceed the threshold range and is within the threshold range.

[0104] Alternatively, similarity can be calculated between two morphologies. A perfect overlap is recorded as 1, a partial overlap as 0.5, and no overlap as 0. A threshold range of 0.9-1 can then be set. When the overlap is within the range of 0.9-1, the first similarity between the first morphology and the preset morphology does not exceed the threshold range; when the overlap is outside the range of 0.9-1, the first similarity between the first morphology and the preset morphology exceeds the threshold range.

[0105] Therefore, the through-silicon via (TSV) etching parameter determination method proposed in this invention can obtain TSVs with a preset morphology. During subsequent etching, the etching parameters can be progressively adjusted at each inflection point, improving the perpendicularity of the TSVs and the precision of parameter control in forming them.

[0106] Figure 5 This is a flowchart of the through-silicon via (TSV) formation method proposed in an embodiment of the present invention. Figure 5 As shown, the method for forming a through-silicon via includes:

[0107] S201 provides the silicon substrate to be etched.

[0108] In this embodiment, the silicon substrate to be etched can be single-crystal silicon, such as an n-type single-crystal silicon substrate or a p-type single-crystal silicon substrate. Other semiconductor components, such as capacitors, resistors, or integrated circuits, can also be integrated on this silicon substrate.

[0109] Before etching, a mask layer needs to be formed on the silicon substrate. This mask layer can be one or more of the following stacked structures: photoresist, hard mask, bottom anti-reflective layer, and top anti-reflective layer.

[0110] S202, using the total etching parameters determined by the silicon via etching parameter determination method of any embodiment of the present invention, obtain the total etching stage of the silicon via to be formed at the target depth.

[0111] If the determined total etching parameters include two parameters, namely a first etching parameter and a second etching parameter, meaning there is only one inflection point and only one change in etching parameters is needed, then etching is performed using the first etching parameter before the first abnormal inflection point, and the second etching parameter is used after the first abnormal inflection point. This can also be understood as the total etching stage being divided into a first stage and a second stage.

[0112] In S203, the Bosch process of etching and passivation deposition is used in a cycle during the overall etching stage to etch the silicon substrate to be etched, forming through-silicon vias of the target depth.

[0113] The etching gas includes at least SF6, and the passivation gas includes at least C4F6. The etching gas is used to etch the silicon substrate to form through-silicon vias (TSVs), and the passivation gas is used to generate polymers during the etching process, which adhere to the sidewalls of the TSVs to protect their sidewall morphology. During the etching process, the etching and passivation processes are performed alternately. In the first stage, the etching and passivation processes are performed alternately. In the second stage, the etching and passivation processes are performed alternately.

[0114] The first and second etching parameters include the aforementioned etching gas quantity, etching time, passivation gas quantity, passivation time, and the distance between the silicon wafer adsorption pad and the plasma generator. They also include etching temperature, etching chamber pressure, etching source RF power, and etching bias RF power. The etching temperature, etching chamber pressure, etching source RF power, and etching bias RF power in the first and second etching parameters can remain consistent. For example, the etching temperature range is 10℃-60℃, the etching chamber pressure is 1mtorr-100mtorr, the etching source RF power is 100-3000W, and the etching bias RF power is 10-500W (further, it can be 10-200W). At least some of the etching gas quantity, etching time, passivation gas quantity, passivation time, and the distance between the silicon wafer adsorption pad and the plasma generator may differ, determined according to the aforementioned method for determining through-silicon via (TSV) etching parameters.

[0115] Optionally, after forming the through-silicon via at the target depth, the method further includes:

[0116] The through-silicon vias at the target depth are cleaned at a temperature of 10℃-300℃, or more specifically, 10℃-200℃. The cleaning reaction gases include at least SF6, O2, or N2.

[0117] This step cleans the protective layer previously passivated and formed on the walls of the through-silicon via (TSV). Then, by removing the mask layer from the silicon substrate surface, a TSV with good verticality can be obtained.

[0118] Figure 6This is a schematic diagram of a through-silicon via electron scanning microscope formed in related technologies; Figure 7 This is a schematic diagram of a through-silicon via electron scanning microscope formed according to an embodiment of the present invention. From... Figure 6 and Figure 7 As can be seen, the verticality of the through-silicon via has been significantly improved after optimization. Specifically, Figure 7 The amount of etching gas SF6 in the middle is compared to Figure 6 The amount of SF6 etching gas in the sample has increased.

[0119] This invention provides an etching apparatus for performing the silicon via etching parameter determination method of any embodiment of this invention, or the silicon via formation method of any embodiment of this invention.

[0120] Figure 8 This is a schematic diagram of the etching equipment structure proposed in an embodiment of the present invention. Figure 8 As shown, the etching apparatus may include a gas inlet device 100, a reaction chamber 101, a silicon wafer to be etched 102, a plasma generator 103, a silicon wafer adsorption disk 104, a drive unit 105, and a chamber outlet 106. The drive unit 105 is capable of moving the silicon wafer adsorption disk 104 up and down. The plasma generator 103 can be a radio frequency device. In other examples, the etching apparatus may also be used upside down.

[0121] Therefore, this invention employs a dichotomy method to determine the critical point of morphology change, better utilizing the ramp (gradual adjustment of etching parameters) function to significantly improve the verticality of the etched morphology. The method of moving the ESC (wafer adsorption disk) upwards allows ions and neutral ions to better enter and exit the trench, promoting etching while reducing sidewall damage from the ion beam. This greatly mitigates the loading effect caused by pattern differences, reduces the depth loading effect between vias of different sizes, improves etching consistency, and ensures device stability. This method has universal applicability and remains applicable to different CD patterns (through-silicon via sizes), significantly increasing the Bosch etching process window. It also improves the aspect ratio of the through-silicon vias.

[0122] In summary, according to the embodiments of the present invention, the method for determining etching parameters of through-silicon vias (TSVs), the method for forming TSVs, and the etching apparatus include the following steps: During the formation of a first TSV, a first TSV of a target depth is formed on a silicon wafer using first etching parameters, and a first morphology of the first TSV is obtained; a first similarity is obtained between the first morphology and a preset morphology; when the first similarity is outside a threshold range, a first abnormal depth range of the first morphology is determined, and a first etching depth corresponding to a first abnormal inflection point of the first morphology is determined within the first abnormal depth range based on a bisection method; During the formation of a second TSV, when etching to a first etching depth using the first etching parameters, the first etching parameters are adjusted to second etching parameters, and etching to a target depth using the second etching parameters is performed to form a second TSV, and a second morphology of the second TSV is obtained; a first similarity is obtained between the second morphology and the preset morphology. Two similarities are used; when the second similarity is outside the threshold range, the second abnormal depth range of the second morphology is determined, and the second etching depth corresponding to the second abnormal inflection point of the second morphology is determined within the second abnormal depth range based on the binary method; this process is repeated sequentially. During the formation of the i-th through-silicon via, etching is performed to the first etching depth with the first etching parameter, and then to the second etching depth with the second etching parameter. When etching is performed to the (i-1)-th etching depth with the (i-1)-th etching parameter, the (i-1)-th etching parameter is adjusted to the i-th etching parameter, and etching is performed to the target depth with the i-th etching parameter to form the i-th through-silicon via, and the i-th morphology of the i-th through-silicon via is obtained; until the i-th similarity between the i-th morphology and the preset morphology is within the threshold range, the total etching parameters that can form the target depth of the preset morphology through-silicon via are obtained, where i is an integer greater than 1, and the total etching parameters include the first etching parameter to the i-th etching parameter. Therefore, after forming a through-silicon via (TSV) at the target depth, it can be compared with a preset morphology to determine the abnormal depth range of the current TSV. Then, within the abnormal depth range, the etching depth corresponding to the inflection point is determined, and the etching parameters are adjusted when etching to that etching depth in the next etching process until the final TSV morphology is close to or the same as the preset morphology. The etching parameters adjusted for verticality at each inflection point are used as the TSV etching parameters. In subsequent etching processes, etching is performed using these TSV etching parameters to obtain TSVs that are close to or the same as the preset morphology, thereby improving the verticality and consistency of the TSV.

[0123] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0124] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for determining through silicon via etching parameters, characterized in that: The following steps are involved: During the first through silicon via formation process, a first through silicon via of a target depth is formed on a silicon wafer using a first etching parameter, and a first morphology of the first through silicon via is obtained; Obtaining a first similarity between the first shape and a preset shape; When the first similarity is outside a threshold range, determining a first abnormal depth range of the first morphology, and determining a first etching depth corresponding to a first abnormal inflection point of the first morphology within the first abnormal depth range based on a dichotomy method; During the formation of the second through silicon via, when etching to the first etching depth with the first etching parameter, adjusting the first etching parameter to a second etching parameter, and etching to the target depth with the second etching parameter to form a second through silicon via, and obtaining a second morphology of the second through silicon via; Obtaining a second similarity between the second shape and a preset shape; When the second similarity is outside the threshold range, determining a second abnormal depth range of the second morphology, and determining a second etching depth corresponding to a second abnormal inflection point of the second morphology within the second abnormal depth range based on a dichotomy method; Repeating successively, in the process of forming the i-th through silicon via, etching to the first etching depth with the first etching parameter, etching to the second etching depth with the second etching parameter, when etching to the i-1th etching depth with the i-1th etching parameter, adjusting the i-1th etching parameter to the i-th etching parameter, and etching to the target depth with the i-th etching parameter to form the i-th through silicon via, and obtaining the i-th morphology of the i-th through silicon via; Until the i-th similarity between the i-th morphology and the preset morphology is within a threshold range, a total etching parameter capable of forming a silicon through hole of a target depth corresponding to the preset morphology is obtained, wherein i is an integer greater than 1, and the total etching parameter includes the first etching parameter to the i-th etching parameter.

2. The method for determining through silicon via etching parameters according to claim 1, characterized in that: When the first similarity is outside a threshold range, determining a first abnormal depth range of the first morphology, and determining a first etching depth corresponding to a first abnormal inflection point of the first morphology within the first abnormal depth range based on a dichotomy method includes: Etching a through silicon via of a first preset depth on a silicon wafer using a first etching parameter to obtain a morphology of the through silicon via of the first preset depth, wherein the first abnormal depth range is from a first depth to a second depth, and the first preset depth is a sum of half of the first abnormal depth range and the first depth; When the similarity between the morphology of the through silicon via of the first preset depth and the preset morphology of the through silicon via corresponding to the first preset depth is outside the threshold range, etching the through silicon via of the second preset depth on the silicon wafer with the first etching parameter to obtain the morphology of the through silicon via of the second preset depth; wherein the second preset depth is the difference between the first preset depth and one quarter of the first abnormal depth range; When the similarity between the morphology of the through silicon via at the first preset depth and the preset morphology of the through silicon via corresponding to the first preset depth is within a threshold range, the second preset depth is the sum of the first preset depth and one quarter of the first abnormal depth range; The process is repeated successively until a critical depth at which the similarity between the first morphology and the preset morphology is within a threshold range is determined along the etching direction, and the critical depth is used as the first etching depth corresponding to the first abnormal inflection point.

3. The method for determining through silicon via etching parameters according to claim 1, characterized in that: During the second through silicon via formation process, when etching to the first etching depth with the first etching parameter, adjusting the first etching parameter to a second etching parameter includes: When the size of the through silicon via at the target depth in the first morphology is smaller than the size of the through silicon via at the first etching depth in the preset morphology, the ratio of the etching gas amount to the passivation gas amount in the second etching parameter is greater than the ratio of the etching gas amount to the passivation gas amount in the first etching parameter; When the size of the silicon via at the target depth in the first morphology is larger than the size of the silicon via at the first etching depth in the preset morphology, the ratio of the etching gas amount to the passivation gas amount in the second etching parameter is smaller than the ratio of the etching gas amount to the passivation gas amount in the first etching parameter.

4. The method for determining through silicon via etching parameters according to claim 1, characterized in that: During the second through silicon via formation process, when etching to the first etching depth with the first etching parameter, adjusting the first etching parameter to a second etching parameter includes: When the size of the through silicon via at the target depth in the first morphology is smaller than the size of the through silicon via at the first etching depth in the preset morphology, the ratio of the etching time to the passivation time in the second etching parameter is greater than the ratio of the etching time to the passivation time in the first etching parameter; When the size of the silicon via at the target depth in the first morphology is larger than the size of the silicon via at the first etching depth in the preset morphology, the ratio of the etching time to the passivation time in the second etching parameters is smaller than the ratio of the etching time to the passivation time in the first etching parameters.

5. The method for determining through silicon via etching parameters according to claim 1, characterized in that: During the second through silicon via formation process, when etching to the first etching depth with the first etching parameter, adjusting the first etching parameter to a second etching parameter includes: When the size of the through silicon via at the target depth in the first morphology is smaller than the size of the through silicon via at the first etching depth in the preset morphology, the distance between the silicon wafer adsorption disk and the plasma generator in the second etching parameter is larger than the distance between the silicon wafer adsorption disk and the plasma generator in the first etching parameter; When the size of the silicon via at the target depth in the first morphology is larger than the size of the silicon via at the first etching depth in the preset morphology, the distance between the silicon wafer adsorption disk and the plasma generator in the second etching parameters is smaller than the distance between the silicon wafer adsorption disk and the plasma generator in the first etching parameters.

6. The method for determining through silicon via etching parameters according to claim 1, characterized in that: Acquiring a first similarity between the first shape and a preset shape includes: Acquire, as the first similarity, an inclination or overlap between a sidewall of a first through silicon via corresponding to the first morphology and a sidewall of a preset through silicon via corresponding to the preset morphology; When the inclination is within a preset degree range, or the overlap is within a preset value range, the first similarity is within a threshold range; When the inclination is not within a preset degree range, and the overlap is not within a preset value range, the first similarity is outside a threshold range.

7. A method for forming a through silicon via, characterized in that: include: Providing a silicon substrate to be etched; Obtaining a total etching stage of a through silicon via of a target depth to be formed by using the total etching parameters determined by the through silicon via etching parameter determination method according to any one of claims 1 to 6; In the total etching stage, the silicon substrate to be etched is etched by cyclically adopting the Bosch process of etching and passivation deposition to form a through silicon via of the target depth.

8. The through silicon via forming method according to claim 7, characterized in that: Among the total etching parameters, the etching temperature range is 10° C.-60° C., the etching chamber pressure is 1 mtorr-100 mtorr, the etching source RF power is 100-3000W, and the etching bias RF power is 10-500W.

9. The method for forming a through silicon via according to claim 7, wherein: After forming the through silicon via of the target depth, the method further comprises: A cleaning step is performed on the through silicon via of the target depth. In the cleaning step, the cleaning temperature is 10° C.-300° C., and the cleaning reaction gas includes at least SF6, O2 or N2.

10. An etching device, characterized in that: Used to execute the method for determining through silicon via etching parameters as described in any one of claims 1-6, or the method for forming a through silicon via as described in any one of claims 7-9.

Images