DC-coupled source follower based analog front end

Abstract

The present application relates to the technical field of integrated circuits, and discloses an analog front end based on a source follower of DC coupling, including a first analog front end buffer, which includes: a pair of differential input transistors, each gate is coupled to a pair of differential input signals through a level conversion unit, and the level conversion unit includes a resistor and a capacitor connected in parallel; a pair of output resistors are coupled in series between the sources of the pair of differential input transistors; an operational amplifier, two input terminals are respectively coupled to the node between the pair of output resistors and the common mode reference voltage; a pair of feedback transistors, the drains are respectively coupled to the gates of the pair of differential input transistors and their corresponding level conversion units, and the sources are both coupled to the output terminals of the operational amplifier; a pair of differential output transistors, the drains are respectively connected to the sources of the corresponding differential input transistors and output a pair of differential output signals, and the gates are coupled to the first bias voltage through a high frequency filter unit. The common mode voltage, swing, and gain of the analog front end of the present application are all adjustable.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an analog front end based on a DC-coupled source follower. Background Art

[0002] The Analog Front End (AFE) is a system or subsystem containing analog circuits that is specifically designed to receive and process signals from sensors or other analog signal sources, and then convert these signals into a form suitable for subsequent digital processing. AFE often plays a vital role in applications such as data acquisition, wireless communications, audio processing, and biomedical equipment.

[0003] Source Follower (SF), also known as Common Drain Amplifier, is a basic circuit configuration of Field Effect Transistor (FET). In this configuration, the input signal is applied to the gate, the output signal is taken from the source, and the drain is usually connected to the power supply voltage (for N-type MOSFET) or to the ground (for P-type MOSFET). The characteristics of this circuit are that it has high input impedance, low output impedance and unity gain (gain close to 1), so it does not significantly amplify the signal.

[0004] In analog electronic circuits, source followers are used for buffering and voltage following in analog front ends. Conventional source followers have different common-mode voltages between input and output and are not adjustable. Summary of the invention

[0005] The purpose of the present application is to provide an analog front end based on a DC-coupled source follower, and to propose an analog front end with adjustable common-mode voltage, swing, and gain.

[0006] The present application discloses an analog front end based on a DC-coupled source follower, including a first analog front end buffer, wherein the first analog front end buffer includes:

[0007] A pair of differential input transistors, wherein the gates of the pair of differential input transistors are respectively coupled to a pair of differential input signals through a level conversion unit, wherein the level conversion unit includes a resistor and a capacitor connected in parallel;

[0008] a pair of output resistors coupled in series between sources of the pair of differential input transistors;

[0009] an operational amplifier, wherein two input terminals of the operational amplifier are respectively coupled to a node between the pair of output resistors and a common mode reference voltage;

[0010] a pair of feedback transistors, wherein drains of the pair of feedback transistors are respectively coupled between gates of the pair of differential input transistors and corresponding level conversion units, and sources of the pair of feedback transistors are both coupled to an output terminal of the operational amplifier; and

[0011] A pair of differential output transistors, wherein the gates of the pair of differential output transistors are coupled to a first bias voltage, the drains of the pair of differential output transistors are respectively connected to the sources of the corresponding differential input transistors and output a pair of differential output signals.

[0012] In a preferred embodiment, the first analog front-end buffer further includes:

[0013] a first comparator, wherein two input terminals of the first comparator are respectively coupled to a node between the pair of output resistors and the common mode reference voltage;

[0014] a seventh transistor, wherein a drain and a gate of the seventh transistor are connected to a gate of one of the pair of feedback transistors to form a current mirror; and

[0015] a first digital-to-analog converter, the first digital-to-analog converter being connected to the drain and the gate of the seventh transistor and configured to output a control signal to the first digital-to-analog converter according to a comparison result of the first comparator;

[0016] Wherein, the output of the seventh transistor and the output of the operational amplifier are selectively turned on.

[0017] In a preferred embodiment, the first analog front-end buffer further includes:

[0018] a second comparator, wherein two input terminals of the second comparator are respectively coupled to the pair of differential output signals;

[0019] a second digital-to-analog converter, wherein the second digital-to-analog converter receives a comparison result of the second comparator;

[0020] The eighth to eleventh transistors, the drain of the eighth transistor is coupled to the gate of one of the pair of differential input transistors, the gate of the eighth transistor, and the gate and drain of the ninth transistor are coupled to the second digital-to-analog converter; the drain of the tenth transistor is coupled to the gate of the other of the pair of differential input transistors, the gate of the tenth transistor, and the gate and drain of the eleventh transistor are coupled to the second digital-to-analog converter.

[0021] In a preferred embodiment, the first analog front-end buffer further includes:

[0022] A first adjustable resistor is coupled between the gates of the pair of differential input transistors and is used to adjust the gain of the low-frequency signal.

[0023] In a preferred embodiment, the first analog front-end buffer further includes:

[0024] A second adjustable resistor is coupled between the pair of differential output signals and is used to adjust the gain of the low-frequency and high-frequency signals.

[0025] In a preferred embodiment, the first analog front-end buffer further includes:

[0026] a pair of high-frequency feedback branches, the pair of high-frequency feedback branches are respectively coupled to the gates of the pair of differential output transistors, and are respectively coupled to a pair of differential input signals in opposite phases through source followers;

[0027] The pair of high-frequency feedback branches each include a resistor and a capacitor, wherein the capacitor is connected in series between the gate of the corresponding differential output transistor and the corresponding source follower, one end of the resistor is coupled to the capacitor of the gate of the corresponding differential output transistor, and the other end is coupled to the first bias voltage.

[0028] In a preferred embodiment, a calibration path is further included, and the calibration path includes:

[0029] A pair of flip-flops, wherein the data ends of the pair of flip-flops respectively receive a pair of complementary pseudo-random signals, and the clock ends of the pair of flip-flops respectively receive a pair of differential clock signals;

[0030] a pair of multiplexers, the pair of multiplexers receiving the outputs of the pair of flip-flops and a pair of differential clock signals respectively;

[0031] a pre-driver, the pre-driver receiving the outputs of the pair of multiplexers respectively;

[0032] a second analog front-end buffer, wherein the second analog front-end buffer receives a pair of differential signals output by the pre-driver respectively;

[0033] A slope control switch is provided, wherein the slope control switch receives a pair of differential signals output by the second analog front-end buffer respectively.

[0034] In a preferred example, the pre-driver includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor; wherein,

[0035] The gate of the twelfth transistor and the gate of the fourteenth transistor are respectively connected to a second bias voltage;

[0036] The gate of the thirteenth transistor and the gate of the fifteenth transistor receive the outputs of the pair of multiplexers respectively;

[0037] The drain of the twelfth transistor is connected to the source of the thirteenth transistor, and the drain of the thirteenth transistor is connected to the source of the fifteenth transistor.

[0038] In a preferred example, a third adjustable resistor is coupled between the output terminals of the pre-driver.

[0039] Compared with the prior art, the main differences and effects of this application are:

[0040] 1. Support a wider input common-mode voltage range. Due to the existence of DC coupling, the input common mode of the source follower is raised by the level converter. Different input common-mode voltages can be supported by changing the design of the level converter.

[0041] 2. It has a more stable and adjustable output common-mode voltage. The output common-mode of the traditional source follower is determined by the input common-mode voltage and the threshold voltage of the transistor, and will fluctuate with changes in process parameters. The present application has a common-mode feedback loop that accurately sets the output common-mode voltage, so that the common-mode voltage is only determined by the reference voltage of the common-mode feedback loop, and has nothing to do with the input common-mode voltage and process parameters.

[0042] 3. There is a gain difference between the DC path of resistor coupling and the AC path of capacitor coupling.

[0043] The first adjustable resistor is introduced to adjust the gain of the DC coupling path, thereby eliminating the gain difference between DC and AC.

[0044] 4. Introduce a current analog-to-digital converter to compensate the DC offset voltage of the buffer by injecting a differential current into the output of the level converter.

[0045] 5. Compensate the high-frequency signal through the high-frequency feedback branch, thereby improving the linearity and gain of the high-frequency signal input.

[0046] The specification of the present application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of the present application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, and the solution of A+B+C+E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic diagram of the structure of an analog front-end buffer according to an embodiment of the present application.

[0048] Figure 2 It is a schematic diagram of the structure of a calibration path according to one embodiment of the present application. DETAILED DESCRIPTION

[0049] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0050] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0051] One embodiment of the present application relates to an analog front end based on a DC-coupled source follower, the structure of which is as follows: Figure 1As shown, the structure includes a first analog front end (AFE) buffer 101, and the first analog front end buffer 101 includes: a pair of differential input transistors M1, M2, a pair of output resistors R1, R2, an operational amplifier OP, a pair of feedback transistors M5, M6, and a pair of differential output transistors M3, M4. The pair of differential input transistors M1, M2 respectively receive a pair of differential input signals vinp, vinn, and the drains of the pair of differential output transistors M3, M4 are used as the output of the analog front end buffer 101, and output a pair of differential output signals vop, von. The pair of differential input transistors M1, M2 and the pair of differential output transistors M3, M4 each constitute a source follower (SF), specifically, the input transistor M1 and the output transistor M3 constitute a source follower, and the input transistor M2 and the output transistor M4 constitute another source follower. The operational amplifier OP and the pair of feedback transistors M5, M6 constitute a common mode feedback loop (CMFB), and the inputs of the differential input transistors M1, M2 are respectively adjusted according to the outputs of the source followers.

[0052] The gates of a pair of differential input transistors M1 and M2 are respectively coupled to a pair of differential input signals vinp and vinn through level conversion units 103 and 104, and the level conversion units 103 and 104 include resistors and capacitors connected in parallel. A pair of output resistors R1 and R2 are coupled in series between the sources of a pair of differential input transistors M1 and M2. The drains of a pair of differential output transistors M3 and M4 are respectively connected to the sources of the corresponding differential input transistors M1 and M2 and output a pair of differential output signals vop and von. The gate of the differential input transistor M1 is coupled to the differential input signal vinp through the level conversion unit 103, and the level conversion unit 103 includes a resistor R3 and a capacitor C1 connected in parallel. The output resistor R1 is coupled in series between the sources of the differential input transistor M1. The gate of the differential output transistor M3 is coupled to the first bias voltage vb, and the drain of the differential output transistor M3 is connected to the source of the corresponding differential input transistor M1 and outputs the differential output signal vop. The gate of the differential input transistor M2 is coupled to the differential input signal vinn through the level conversion unit 104, and the level conversion unit 104 includes a resistor R4 and a capacitor C2 connected in parallel. The output resistor R2 is coupled in series between the source of the differential input transistor M2. The gate of the differential output transistor M4 is coupled to the first bias voltage vb, and the drain of the differential output transistor M4 is connected to the source of the corresponding differential input transistor M2 and outputs the differential output signal von.

[0053] The two input terminals of the operational amplifier OP are respectively coupled to the node between a pair of output resistors R1 and R2 and the common mode reference voltage vcmvef. The drains of a pair of feedback transistors M5 and M6 are respectively coupled between the gates of a pair of differential input transistors M1 and M2 and their corresponding level conversion units 103 and 104, and the gates of the pair of feedback transistors M5 and M6 are both coupled to the output terminal of the operational amplifier OP. The drain of the feedback transistor M5 is coupled between the gate of the differential input transistor M1 and its corresponding level conversion unit 103, and the gate of the feedback transistor M5 is coupled to the output terminal of the operational amplifier OP. The drain of the feedback transistor M6 is coupled between the gate of the differential input transistor M2 and its corresponding level conversion unit 104, and the gate of the feedback transistor M6 is coupled to the output terminal of the operational amplifier OP.

[0054] The operational amplifier OP compares the common-mode voltage outcm of the source follower (i.e., the voltage between R1 and R2) with the common-mode reference voltage vcmvef, and outputs corresponding voltages to the gates of the feedback transistors M5 and M6 according to the comparison result, and controls the switching of the feedback transistors M5 and M6, so that the feedback transistor M5 adjusts the gate voltage lsp of the input transistor M1 according to the output of the source follower, and the feedback transistor M6 adjusts the gate voltage lsn of the input transistor M2 according to the output of the source follower, thereby achieving the purpose of adjusting the common-mode voltage outcm.

[0055] In one embodiment, the first analog front-end buffer 101 further includes a first comparator 105, a seventh transistor M7, and a first digital-to-analog converter (VCM control IDAC) 106. The two input terminals of the first comparator 105 are respectively coupled to the node between a pair of output resistors R1 and R2 and the common-mode reference voltage vcmvef. The drain and gate of the seventh transistor M7 are connected to the gate of one of a pair of feedback transistors M5 and M6 to form a current mirror. For example, the drain and gate of the seventh transistor M7 are connected to the gate of the feedback transistor M5 to form a current mirror. The first digital-to-analog converter 106 is connected to the drain and gate of the seventh transistor M7, and is used to output a control signal vcm_dig to the first digital-to-analog converter 106 according to the comparison result of the first comparator 105.

[0056] In one embodiment, the first DAC 106 is a 7-bit DAC.

[0057] The first comparator 105 determines the magnitude of the common mode voltage outcm and the common mode reference voltage vcmvef, and generates a comparison result, which can be stored in a register. The first digital-to-analog converter 106 can read the comparison result, generate a control voltage to the gate of the seventh transistor M7 and the feedback transistor M5, and control the drain voltage lsp of the feedback transistor M5, so as to adjust the common mode voltage outcm.

[0058] In addition, a first switch S1 is connected between the output of the operational amplifier 102 and the gates of the feedback transistors M5 and M6. A second switch S2 is connected between the drain and gate of the seventh transistor M7 and the gate of the feedback transistor M5. The seventh transistor M7 and the output of the operational amplifier 102 are selectively turned on. In other words, the first switch S1 and the second switch S2 are selectively closed.

[0059] In one embodiment, the first analog front-end buffer 101 further includes a second comparator 107, a second digital-to-analog converter (offset control IDAC) 108, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. Two input terminals of the second comparator 107 are respectively coupled to a pair of differential output signals vop and von. The second digital-to-analog converter 108 receives the comparison result of the second comparator 107. The drain of the eighth transistor M8 is coupled to the gate of one of the pair of differential input transistors M1 and M2, and the gate of the eighth transistor M8 and the gate and drain of the ninth transistor M9 are coupled to the second digital-to-analog converter 108. The drain of the tenth transistor M10 is coupled to the gate of the other of the pair of differential input transistors M1 and M2, and the gate of the tenth transistor M10 and the gate and drain of the eleventh transistor M11 are coupled to the second digital-to-analog converter 108.

[0060] In one embodiment, the second DAC 108 is an 8-bit DAC.

[0061] The second comparator 107 determines the magnitude of the differential output signals vop and von, and generates a comparison result, which can be stored in a register. The second digital-to-analog converter 108 can read the comparison result to generate a control voltage to the gates of the eighth transistor M8 and the tenth transistor M10, and inject different currents into the eighth transistor M8 and the tenth transistor M10, thereby respectively controlling the drain voltage lsp of the feedback transistor M5 and the drain voltage lsn of the feedback transistor M6, so as to adjust the mismatch of the DC part of the differential output signals vop and von.

[0062] It should be understood that the second digital-to-analog converter 108 , the eighth transistor M8 , the ninth transistor M9 , the tenth transistor M10 , and the eleventh transistor M11 work simultaneously with the common-mode feedback loop CMFB.

[0063] In one embodiment, the first analog front-end buffer 101 further includes a first adjustable resistor R6, which is coupled between the gates of a pair of differential input transistors M1 and M2 and is used to adjust the gain of the low-frequency signal. For example, the gain control range is -1 to -0.3 dB.

[0064] In one embodiment, the first analog front-end buffer 101 further includes a second adjustable resistor R7, which is coupled between a pair of differential output signals M3 and M4 and is used to adjust the gain of the low-frequency and high-frequency signals. For example, the gain control range is -6 to -2 dB.

[0065] In one embodiment, the first analog front-end buffer 101 further includes a pair of high-frequency feedback branches 109 and 110, which are respectively coupled to the gates of a pair of differential output transistors M3 and M4, and are respectively coupled to a pair of inverted differential input signals vinp and vinn through source followers 111 and 112. The pair of high-frequency feedback branches 109 and 110 each include a resistor and a capacitor, the capacitor is connected in series between the gate of the corresponding differential output transistor and the corresponding source follower, one end of the resistor is coupled to the capacitor between the gate of the corresponding differential output transistor, and the other end is coupled to the first bias voltage vb. Specifically, the high-frequency feedback branch 109 includes a resistor R8 and a capacitor C3, one end of the resistor R8 is coupled to the first bias voltage vb, and the other end is coupled to the gate of the output transistor M2 and one end of the capacitor C3, the other end of the capacitor C3 is coupled to the output end of the source follower 111, and the input end of the source follower 111 is coupled to the differential input signal vinn. The high-frequency feedback branch 110 includes a resistor R9 and a capacitor C4, one end of the resistor R9 is coupled to the first bias voltage vb, the other end is coupled to the gate of the output transistor M4 and one end of the capacitor C4, the other end of the capacitor C4 is coupled to the output end of the source follower 112, and the input end of the source follower 112 is coupled to the differential input signal vinp. The resistor R9 and the capacitor C4, as well as the resistor R8 and the capacitor C3, respectively form passive high-pass filters.

[0066] The bandwidth of the voltage buffer can be increased through the high-frequency feedback branch without consuming extra power. The linearity of the buffer can be improved when a high-frequency signal is input, and the problem of large signal current limitation of the traditional buffer can be overcome through the AC coupling capacitor.

[0067] The proposed front-end circuit consists of a DC and AC coupled level converter. The output of the level converter is connected to an NMOS based source follower. The gate of the NMOS current source is connected to the input through a high pass filter. The low frequency components of the signal are suppressed, so it has no effect on the low frequency performance of the source follower, and the high frequency components can pass through, thus compensating for the high frequency gain loss of the source follower. The common mode feedback loop CMFB is used to set the AFE output common mode. The feedback point is the gate of the level converter PMOS current source. The CMFB loop can also be disconnected and the common mode voltage of the AFE is adjusted by a 7-bit current digital-to-analog converter. In addition, an 8-bit differential IDAC is used to eliminate the AFE offset. The level converter uses a 4-bit resistor array (adjustable resistor R6) to control the DC gain. The source follower output has a 3-bit resistor array (adjustable resistor R7) to control the gain.

[0068] In one embodiment, the analog front end further includes a calibration path 113, which includes: a pair of triggers 114, 115, a pair of multiplexers 116, 117, a pre-driver 118, a second analog front end buffer 119, a slope control switch 120, such as Figure 2 It should be noted that the structure of the second analog front-end buffer 119 is the same as that of the first analog front-end buffer 101, and in order to avoid repetition, it is not described here. When the calibration path 113 is turned on, the first analog front-end buffer 101 is turned off, and when the calibration path 113 is turned off, the first analog front-end buffer 101 is turned on.

[0069] The data terminals of a pair of flip-flops 114 and 115 receive a pair of complementary pseudo-random signals PN and PNb (such as Figure 2 As shown, the pseudo-random signals PN and PNb received by the two triggers are opposite, for example, one is 1 and the other is 0), and the clock ends receive a pair of differential clock signals Ckref and Ckrefb respectively. A pair of multiplexers 116 and 117 receive the outputs of a pair of triggers 114 and 115 and a pair of differential clock signals Ckref and Ckrefb respectively. The pre-driver 108 receives the outputs vip and vin of a pair of multiplexers 116 and 117 respectively, and outputs a pair of differential signals dacp and dacn. The second analog front-end buffer 119 receives a pair of differential signals dacp and dacn output by the pre-driver 118 respectively, and outputs corresponding differential signals vop' and von'. The slope control switch 120 receives a pair of differential signals output by the second analog front-end buffer 119 respectively. The slope control switch 120 is connected to the output of the first analog front-end buffer respectively.

[0070] Specifically, the data terminal of the flip-flop 114 receives the pseudo-random signal PN, the clock terminal receives the clock signal Ckref, the output terminal is connected to one input terminal of the multiplexer 116, the other input terminal of the multiplexer 116 is connected to the clock signal Ckref, and the output terminal of the multiplexer 116 is connected to the pre-driver 118. The multiplexer 116 selects the pseudo-random signal PN or the clock signal Ckref according to the calibration clock pattern selection signal (Cal clock pattern selection). The data terminal of the flip-flop 115 receives the pseudo-random signal PNb, the clock terminal receives the clock signal Ckrefb, the output terminal is connected to one input terminal of the multiplexer 117, the other input terminal of the multiplexer 117 is connected to the clock signal Ckrefb, and the output terminal of the multiplexer 117 is connected to the pre-driver 118. The multiplexer 117 selects the pseudo-random signal PNb or the clock signal Ckrefb according to the calibration clock pattern selection signal (Cal clock pattern selection).

[0071] In one embodiment, the pre-driver 118 includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15. The gate of the twelfth transistor M12 and the gate of the fourteenth transistor M14 are respectively connected to the second bias voltage vb'. The gate of the thirteenth transistor M13 and the gate of the fifteenth transistor M15 receive the output of a pair of multiplexers 116 and 117 respectively. The drain of the twelfth transistor M12 is connected to the source of the thirteenth transistor M13, and the drain of the thirteenth transistor M13 is connected to the source of the fifteenth transistor M15.

[0072] Specifically, the output vip of the multiplexer 116 is connected to the gate of the fifteenth transistor M15, and the output vin of the multiplexer 117 is connected to the gate of the thirteenth transistor M13.

[0073] In one embodiment, the slope control switch 120 includes two groups of PMOS transistor arrays, wherein the gates of the PMOS transistors in one group of the PMOS transistor arrays are all connected to the output vop' of the AFE buffer 119, the drains are all connected to the output vop of the AFE buffer 101, and the gates are all connected to the control signal; and the gates of the PMOS transistors in the other group of the PMOS transistor arrays are all connected to the output von' of the AFE buffer 119, the drains are all connected to the output von of the AFE buffer 101, and the gates are all connected to the control signal.

[0074] It should be understood that each group of PMOS transistor arrays includes a plurality of PMOS transistors connected in parallel. The on-resistance of the switch can be changed by controlling the number of transistors turned on in a group of PMOS transistor arrays. The more transistors turned on, the smaller the on-resistance, the stronger the overcurrent capability, and the greater the signal slope, and vice versa.

[0075] The working process of the calibration circuit is as follows: CKref and CKrefb form a set of differential CMOS clock signals, which directly drive the pre-driver 118 after passing through the multiplexer 116. The pre-driver can complete the functions of amplitude adjustment and common-mode level shifting, thereby driving the AFE buffer. The output of the AFE buffer is connected to the output of the signal path through a set of slope control switches. When the calibration circuit is working, the output of the signal path is in a high-impedance state.

[0076] In one embodiment, a third adjustable resistor R10 is coupled between the output terminals of the pre-driver 118 , and the gain control range is -7 to -1 dB.

[0077] The proposed AFE is used to drive a high-speed, medium-resolution time-interleaved SAR ADC. Therefore, the clock path is connected to the AFE output for interleaving error calibration. The calibration path includes the input multiplexer, pre-driver, AFE buffer, and slope control switch. The pre-driver also has a 4-bit gain control resistor array for adjusting the swing.

[0078] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0079] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0080] This specification includes combinations of the various embodiments described herein. Individual references to an embodiment (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0081] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

Claims

1. An analog front end based on a DC-coupled source follower, characterized in that: A first analog front end buffer is included, wherein the first analog front end buffer includes: A pair of differential input transistors, wherein the gates of the pair of differential input transistors are respectively coupled to a pair of differential input signals through a level conversion unit, wherein the level conversion unit includes a resistor and a capacitor connected in parallel; a pair of output resistors coupled in series between sources of the pair of differential input transistors; an operational amplifier, wherein two input terminals of the operational amplifier are respectively coupled to a node between the pair of output resistors and a common mode reference voltage; a pair of feedback transistors, wherein drains of the pair of feedback transistors are respectively coupled between gates of the pair of differential input transistors and corresponding level conversion units, and gates of the pair of feedback transistors are both coupled to an output terminal of the operational amplifier; a pair of differential output transistors, wherein the gates of the pair of differential output transistors are coupled to a first bias voltage, the drains of the pair of differential output transistors are respectively connected to the sources of the corresponding differential input transistors and output a pair of differential output signals; a first comparator, wherein two input terminals of the first comparator are respectively coupled to a node between the pair of output resistors and the common mode reference voltage; a seventh transistor, wherein a drain and a gate of the seventh transistor are connected to a gate of one of the pair of feedback transistors to form a current mirror; and a first digital-to-analog converter, the first digital-to-analog converter being connected to the drain and the gate of the seventh transistor and configured to output a control signal to the first digital-to-analog converter according to a comparison result of the first comparator; Wherein, the output of the seventh transistor and the output of the operational amplifier are selectively turned on.

2. The analog front end according to claim 1, characterized in that: The first analog front end buffer further comprises: a second comparator, wherein two input terminals of the second comparator are respectively coupled to the pair of differential output signals; a second digital-to-analog converter, wherein the second digital-to-analog converter receives a comparison result of the second comparator; The eighth to eleventh transistors, the drain of the eighth transistor is coupled to the gate of one of the pair of differential input transistors, the gate of the eighth transistor, and the gate and drain of the ninth transistor are coupled to the second digital-to-analog converter; the drain of the tenth transistor is coupled to the gate of the other of the pair of differential input transistors, the gate of the tenth transistor, and the gate and drain of the eleventh transistor are coupled to the second digital-to-analog converter.

3. The analog front end according to claim 1, characterized in that: The first analog front end buffer further comprises: A first adjustable resistor is coupled between the gates of the pair of differential input transistors and is used to adjust the gain of the low-frequency signal.

4. The analog front end according to claim 1, characterized in that: The first analog front end buffer further comprises: A second adjustable resistor is coupled between the pair of differential output signals and is used to adjust the gain of the low-frequency and high-frequency signals.

5. The analog front end according to claim 1, characterized in that: The first analog front end buffer further comprises: a pair of high-frequency feedback branches, the pair of high-frequency feedback branches are respectively coupled to the gates of the pair of differential output transistors, and are respectively coupled to a pair of differential input signals in opposite phases through source followers; The pair of high-frequency feedback branches each include a resistor and a capacitor, wherein the capacitor is connected in series between the gate of the corresponding differential output transistor and the corresponding source follower, one end of the resistor is coupled to the capacitor of the gate of the corresponding differential output transistor, and the other end is coupled to the first bias voltage.

6. The analog front end according to claim 1, characterized in that: Also included is a calibration path, the calibration path comprising: A pair of flip-flops, wherein the data ends of the pair of flip-flops respectively receive a pair of complementary pseudo-random signals, and the clock ends of the pair of flip-flops respectively receive a pair of differential clock signals; a pair of multiplexers, the pair of multiplexers receiving the outputs of the pair of flip-flops and a pair of differential clock signals respectively; a pre-driver, the pre-driver receiving the outputs of the pair of multiplexers respectively; a second analog front-end buffer, wherein the second analog front-end buffer receives a pair of differential signals output by the pre-driver respectively; A slope control switch is provided, wherein the slope control switch receives a pair of differential signals output by the second analog front-end buffer respectively.

7. The analog front end according to claim 6, characterized in that: The pre-driver includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor; wherein, The gate of the twelfth transistor and the gate of the fourteenth transistor are respectively connected to a second bias voltage; The gate of the thirteenth transistor and the gate of the fifteenth transistor receive the outputs of the pair of multiplexers respectively; The drain of the twelfth transistor is connected to the source of the thirteenth transistor, and the drain of the thirteenth transistor is connected to the source of the fifteenth transistor.

8. The analog front end according to claim 6, characterized in that: A third adjustable resistor is coupled between the output ends of the pre-driver.

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