A high-precision comparator with dynamic bias for SAR ADC

Abstract

The present invention belongs to the field of integrated circuit technology, and specifically relates to a high-precision comparator with dynamic bias for SAR ADC. The comparator of the present invention is composed of a preamplifier with dynamic bias, a fast comparator, and a latch. The preamplifier is used to amplify the input signal to reduce comparator error and reduce the impact of the kickback noise of the latch comparator on the ADC; the fast comparator is used to quickly compare the amplified signal, and the latch latches the comparison result. The dynamic bias circuit in the preamplifier is composed of two control switches and a tail current MOS transistor. When the SAR ADC performs high data bit judgment, the preamplifier is controlled to connect to an additional tail current to speed up the conversion time; when the SAR ADC performs low data bit judgment, the additional tail current is not connected to reduce comparator noise. Compared with traditional comparators, the comparator of the present invention can effectively improve the speed of the SAR ADC without losing the accuracy of the SAR ADC.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-precision comparator with dynamic bias for SAR ADC. Background Art

[0002] The successive approximation analog-to-digital converter (SAR ADC) is a device that converts analog signals into digital signals. It is the most common type of analog-to-digital converter and one of the indispensable modules in integrated circuit design. In the analog-to-digital converter, the comparator plays a vital role as a key component. The commonly used SAR ADC architecture is as follows: Figure 1 As shown in the figure, SAR ADCs are widely used in electronic systems due to their highly digital architecture, low power consumption, high energy efficiency, and virtually no latency. These applications include, but are not limited to, those requiring medium-to-high resolution and medium-to-high conversion rates, such as measurement, communications, healthcare, and industrial control. In these fields, SAR ADC performance metrics such as accuracy, speed, and power consumption have a significant impact on overall system performance. As one of the core modules of a SAR ADC, the performance of the comparator directly determines its performance in these applications.

[0003] The noise contribution of traditional high-speed, high-precision SAR ADCs primarily comes from the comparator. As the comparator's speed increases, its noise also increases. Therefore, achieving both high speed and high precision becomes a bottleneck in the comparator. Therefore, high-speed, high-precision comparators have been a hot topic and a challenge in current research. Summary of the Invention

[0004] In view of this, an object of the present invention is to provide a comparator with dynamic bias that can improve the speed of a SAR ADC without sacrificing the accuracy of the SAR ADC.

[0005] The comparator proposed in this invention incorporates a comparator dynamic biasing technique, which improves the speed of the SAR ADC without losing accuracy. Figure 2 As shown, a controllable tail current tube M2 is connected in parallel to the tail current tube M1 of the comparator, and the switch of M2 is controlled by the control signals S1 and S1b.

[0006] The high-precision comparator with dynamic bias for SAR ADC proposed by the present invention has a circuit structure as follows: Figure 2 As shown, it mainly includes three parts: pre-amplifier, fast comparator and latch; among them:

[0007] The pre-amplifier is used to amplify the input signal to reduce comparator error and reduce the impact of the kickback noise of the latch comparator on the ADC;

[0008] The preamplifier includes a dynamic bias circuit to provide an additional controllable tail current path; the preamplifier also includes an indication signal S1 / S1b to determine whether the SAR ADC is in a high / low data bit.

[0009] The fast comparator is used to quickly compare the amplified signal; the fast comparator includes a positive feedback path and a reset function;

[0010] The latch is used to latch the comparison result; the latch includes latching and resetting functions.

[0011] Further:

[0012] In the pre-amplifier, M1 and M2 are tail current MOS tubes, MOS tubes M3 and M4 are main amplifier tubes, MOS tubes M5 / M6 / M7 / M8 constitute the amplifier load, and MOS tubes M6 and M7 constitute a positive feedback path.

[0013] The dynamic bias circuit is composed of two switches S1 and S1b and a MOS transistor M2, wherein S1 and S1b are two opposite digital control signals, and the MOS transistor M2 introduces an additional tail current path.

[0014] In the preamplifier, when the SAR ADC is in the high data bit determination phase, indication signal S1 = 1 and S1b = 0; when the SAR ADC is in the low data bit determination phase, indication signal S1 = 0 and S1b = 1. Indication signals S1 and S1b jointly control M2 to determine whether to apply additional tail current. When S1 = 1 and S1b = 0, the preamplifier tail current doubles, increasing the SAR ADC speed. When S1 = 0 and S1b = 1, the preamplifier tail current remains unchanged, and the SAR ADC speed remains unchanged.

[0015] The fast comparator includes a clock CK signal and a positive feedback path consisting of four MOS transistors M12, M13, M15, and M16. MOS transistors M10 and M11 are main amplifiers, MOS transistor M9 is used for clock-controlled tail current, and MOS transistors M14 and M17 are two reset transistors.

[0016] When CK = 1, the fast comparator is reset; when CK = 0, the fast comparator operates normally. When the fast comparator operates normally, the positive feedback path formed by M12 / M13 / M15 / M16 can speed up the comparison speed.

[0017] The latch is composed of a NAND gate and a NOT gate, wherein CKb and CK are inverted signals. When CKb=1, the latch receives data; when CKb=0, the latch latches data.

[0018] Specific principle: When the SAR ADC performs high-bit conversion, S1 is turned on, S1b is turned off, and M2 is connected to the circuit, so that the operating current of the comparator preamplifier is doubled to speed up the working speed of the comparator; when the SAR ADC performs low-bit conversion, S1 is turned off, S1b is turned on, and M2 is turned off, so that the operating current of the comparator preamplifier returns to normal value to reduce the noise of the comparator. Through the above two processes, compared with the traditional SAR ADC, the high-speed conversion speed is accelerated, and the high-bit conversion time occupies most of the entire conversion time, thus greatly speeding up the conversion time of the SAR ADC; while the low-bit conversion accuracy remains unchanged compared with the traditional SAR ADC. The final accuracy of the entire SAR ADC is mainly determined by the low-bit conversion accuracy. Therefore, the introduction of this method speeds up the conversion speed without losing accuracy.

[0019] Among them, S1 and S1b are opposite signals, and S1 can be triggered by a high-bit conversion end signal.

[0020] The technical features and beneficial effects of the present invention are as follows:

[0021] Compared with traditional comparators, the comparator with dynamic bias of the present invention, when used in a SAR ADC, can increase the speed of the ADC without sacrificing accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of the traditional high-speed, low-power SAR ADC structure.

[0023] Figure 2 The diagram is a circuit diagram of a high-precision comparator with dynamic bias for SAR ADC according to the present invention. DETAILED DESCRIPTION

[0024] like Figure 2 As shown in FIG, the high-precision comparator of the present invention comprises three parts: a pre-amplifier, a fast comparator and a latch.

[0025] In the preamplifier, VB1 is the tail current bias voltage, VIP and VIN are the preamplifier's differential outputs, and S1 and S1b control whether M2's tail current is connected. Two switches (S1 and S1b) and a MOSFET M2 form a dynamic bias circuit. M1 and M2 are tail current MOSFETs, M3 and M4 are the main amplifier transistors, M5 / M6 / M7 / M8 form the amplifier load, and M6 and M7 form the positive feedback path. This preamplifier amplifies the differential input signal. When the SAR ADC is in the high data bit detection phase, the indication signal S1 = 1 and S1b = 0. At this time, M2 is turned on, doubling the preamplifier's tail current and increasing its speed. When the SAR ADC is in the low data bit detection phase, the indication signal S1 = 0 and S1b = 1. At this time, M2 is turned off, and the preamplifier's tail current and speed remain unchanged.

[0026] The fast comparator includes the clock CK signal and a positive feedback path formed by M12, M13, M15, and M16. When CK = 1, the fast comparator is reset; when CK = 0, the fast comparator operates normally. When the fast comparator operates normally, the positive feedback path formed by M12, M13, M15, and M16 accelerates the comparison speed. M10 and M11 are the main amplifiers, MOS transistor M9 is used for the tail current of clock control, and MOS transistors M14 and M17 are the two reset transistors.

[0027] In the latch, CKb and CK are inverted signals. When CKb=1, the latch receives data; when CKb=0, the latch latches data.

[0028] In the present invention, a comparator dynamic bias technology is introduced to achieve ADC speed improvement without losing accuracy. Specifically, a controllable tail current tube M2 is connected in parallel to the tail current tube M1 of the comparator, and the switch of M2 is controlled by the S1 and S1b control signals. When the SAR ADC performs high-bit conversion, S1 is turned on, S1b is turned off, and M2 is connected to the circuit, so that the operating current of the comparator preamplifier is doubled to speed up the working speed of the comparator; when the SAR ADC performs low-bit conversion, S1 is turned off, S1b is turned on, and the M2 tube is turned off, so that the operating current of the comparator preamplifier returns to a normal value to reduce the noise of the comparator. Through the above two processes, compared with the traditional SAR ADC, the speed of high-speed conversion is accelerated, and the high-bit conversion time occupies most of the entire conversion time, thereby greatly speeding up the conversion time of the SAR ADC; while the low-bit conversion accuracy remains unchanged compared to the traditional SAR ADC, the final accuracy of the entire SAR ADC is mainly determined by the low-bit conversion accuracy, and the conversion speed is accelerated without losing accuracy.

Claims

1. A high-precision comparator with dynamic bias for SAR ADC, characterized in that: A comparator dynamic bias is added, that is, a controllable tail current tube M2 is connected in parallel to the tail current tube M1 of the comparator. The switch of the tail current tube M2 is controlled by the indication signals S1 and S1b. Specifically, it includes three parts: pre-amplifier, fast comparator and latch. Among them: The preamplifier is used to amplify the input signal; the preamplifier includes a dynamic bias circuit to provide an additional controllable tail current path; the preamplifier also includes an indication signal S1 / S1b for determining whether the SAR ADC is in a high / low data bit; The fast comparator is used to quickly compare the amplified signal; the fast comparator includes a positive feedback path and a reset function; The latch is used to latch the comparison result; the latch includes latch and reset functions; In the pre-amplifier, the two MOS tubes M3 and M4 are the main amplifier tubes of the amplifier, the four MOS tubes M5, M6, M7, and M8 constitute the amplifier load, and the two MOS tubes M6 and M7 constitute a positive feedback path; The dynamic bias circuit is composed of a MOS transistor M2 and two indication signals S1 and S1b for controlling its switch, wherein S1 and S1b are two opposite digital control signals, and the MOS transistor M2 introduces an additional tail current path; Among them, the switch corresponding to the indication signal S1 has one end connected to the tail current bias voltage VB1 and the other end connected to the gate of the tail current tube M2; the switch corresponding to the indication signal S1b has one end connected to the ground GND and the other end connected to the gate of the tail current tube M2; the gate of the tail current tube M1 is connected to the tail current bias voltage VB1, the drain of the tail current tube M1 is connected to the source of the MOS tube M3 and the MOS tube M4, and the source of the tail current tube M1 is grounded GND; the drain of the tail current tube M2 is connected to the source of the MOS tube M3 and the MOS tube M4, and the source of the tail current tube M2 is grounded GND.

2. The high-precision comparator according to claim 1, wherein: In the preamplifier, when the SAR ADC is in the high data bit judgment stage, the indication signal S1=1 and S1b=0; when the SAR ADC is in the low data bit judgment stage, the indication signal S1=0 and S1b=1; the indication signals S1 and S1b jointly control M2 to determine whether to connect additional tail current; when S1=1 and S1b=0, the preamplifier tail current is doubled and the SAR ADC speed is increased; when S1=0 and S1b=1, the preamplifier tail current remains unchanged and the SAR ADC speed remains unchanged.

3. The high-precision comparator according to claim 1, wherein: The fast comparator includes a clock CK signal and a positive feedback path composed of four MOS tubes M12, M13, M15, and M16. In the fast comparator, MOS tubes M10 and M11 are main amplifier tubes, MOS tube M9 is a clock-controlled tail current, and MOS tubes M14 and M17 are two reset tubes.

4. The high-precision comparator according to claim 3, characterized in that: When CK=1, the fast comparator is reset; when CK=0, the fast comparator works normally; when the fast comparator works normally, the positive feedback path composed of four MOS tubes M12, M13, M15, and M16 can speed up the comparison speed.

5. The high-precision comparator according to claim 1, wherein: The latch is composed of a NAND gate and a NOT gate, and CKb and CK are inverted signals. When CKb=1, the latch receives data; when CKb=0, the latch latches data.

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