Chip structure and memory

Abstract

The chip structure and the memory provided by the present disclosure relate to the technical field of semiconductor packaging. The chip structure comprises at least one pad unit, and the pad unit comprises a plurality of power pads and a plurality of command data pads. The plurality of power pads are arranged at equal intervals in a predetermined direction in a first area close to a storage array unit. The plurality of command data pads are arranged at equal intervals in the predetermined direction, and the plurality of power pads are closer to the storage array unit than the plurality of command data pads. The command data pads and the power pads are arranged alternately in the predetermined direction. The distance between the center point of each command data pad and the center point of the adjacent power pad in the predetermined direction is less than a preset threshold. The distance between each command data pad and the adjacent power pad in the predetermined direction is set to be less than the preset threshold, so that the area occupied by each two adjacent pads is reduced, and the number of pads that can be configured in a small-size chip is increased.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, a chip structure and a memory. BACKGROUND

[0002] In the related art, a pad unit is arranged at a middle position of a chip in a packaging process of the chip. The pad unit usually has two rows of pads arranged uniformly. However, with the development of technology, the size of the chip is getting smaller and smaller, and the space for accommodating the pad unit at the middle position of the chip is also getting smaller and smaller. In the related art, the number of pads arranged in the chip with a smaller and smaller size is reduced by arranging two rows of pads uniformly at the middle position of the chip, and the number of pads that can be arranged in a small-size pad is also small. SUMMARY

[0003] The chip structure and the memory provided by the embodiments of the present disclosure can increase the number of pads that can be arranged in a small-size chip.

[0004] The technical solution of the present disclosure is implemented as follows:

[0005] The chip structure provided by the embodiments of the present disclosure includes at least one pad unit, the pad unit includes a plurality of power pads and a plurality of command data pads, a plurality of power pads are arranged equidistantly along a predetermined direction at a first region close to the storage array unit, a plurality of command data pads are arranged equidistantly along the predetermined direction, and a plurality of power pads are closer to the storage array unit than a plurality of command data pads. The command data pads and the power pads are arranged alternately in the predetermined direction. The distance between the center point of each command data pad and the center point of the adjacent power pad in the predetermined direction is less than a preset threshold.

[0006] In the above solution, the at least one pad unit includes a middle pad unit, the storage array unit includes a first storage array unit and a second storage array unit arranged at intervals, the plurality of power pads includes a plurality of first power pads and a plurality of second power pads, the plurality of command data pads includes a plurality of first command data pads and a plurality of second command data pads, and the middle pad unit is arranged between the first storage array unit and the second storage array unit.

[0007] The plurality of first power pads are arranged equidistantly along the predetermined direction at a first sub-region close to the first storage array unit.

[0008] The plurality of second power pads are arranged equidistantly along the predetermined direction at a second sub-region close to the second storage array unit.

[0009] The first command data pads are arranged at intervals along the predetermined direction between the first power pads and the second power pads and close to the first memory array unit.

[0010] The second command data pads are arranged at intervals along the predetermined direction between the first power pads and the second power pads and close to the second memory array unit.

[0011] The first command data pads and the first power pads are staggered along the predetermined direction, and the distance between the center point of the first command data pad and the center point of the adjacent first power pad along the predetermined direction is less than the preset threshold value; the second command data pads and the second power pads are staggered along the predetermined direction, and the distance between the center point of the second command data pad and the center point of the adjacent second power pad along the predetermined direction is less than the preset threshold value.

[0012] In the above scheme, the first command data pads include a plurality of first command pads and a plurality of first data pads; the second command data pads include a plurality of second command pads and a plurality of second data pads; the first command pads are arranged at intervals along the predetermined direction in a third sub-region, the first data pads are arranged at intervals along the predetermined direction in a fourth sub-region, and the third sub-region and the fourth sub-region are arranged at intervals along the predetermined direction; the second command pads are arranged at intervals along the predetermined direction in a fifth sub-region, the second data pads are arranged at intervals along the predetermined direction in a sixth sub-region, and the fifth sub-region and the sixth sub-region are arranged at intervals along the predetermined direction.

[0013] In the above scheme, the first power pads include a plurality of first power supply pads and a plurality of first ground pads, and the second power pads include a plurality of second power supply pads and a plurality of second ground pads; the first power supply pads and the first ground pads are arranged at intervals in two seventh sub-regions, and the two seventh sub-regions are arranged at intervals along the predetermined direction; the second power supply pads and the second ground pads are arranged at intervals in two eighth sub-regions, and the two eighth sub-regions are arranged at intervals along the predetermined direction.

[0014] In the above scheme, the first command data pads include a plurality of first command pads and a plurality of first data pads, and the second command data pads include a plurality of second command pads and a plurality of second data pads; the first command pads and the first data pads are arranged between the first power pads and the second power pads and close to the first memory array unit; and the second command pads and the second data pads are arranged between the first power pads and the second power pads and close to the second memory array unit.

[0015] In the above scheme, the first power pads include a plurality of first power supply pads and a plurality of first ground pads, and the second power pads include a plurality of second power supply pads and a plurality of second ground pads; the first power supply pads and the first ground pads are arranged in the first sub-region; and the second power supply pads and the second ground pads are arranged in the second sub-region.

[0016] In the above scheme, the power pads and the command data pads are arranged on a substrate in the pad unit, and a projection of the command data pads on the substrate is smaller than a projection of the power pads on the substrate.

[0017] In the above scheme, the region where the memory array unit is located includes four sides; when there are two pad units, the two pad units are arranged at the periphery of two opposite sides of the four sides, or the two pad units are arranged at the periphery of two adjacent sides of the four sides.

[0018] In the above scheme, the command data pads are connected to corresponding interfaces in the memory array unit through first wires arranged on the pad unit; the power pads are connected to corresponding interfaces in the memory array unit through second wires arranged on the pad unit; and the resistance of the first wires is smaller than that of the second wires.

[0019] In the above scheme, the command data pads include a first aluminum base, a first copper column, a first cap and a first bump arranged in sequence on a substrate of the pad unit; and the power pads include a second aluminum base, a second copper column, a second cap and a second bump arranged in sequence on the substrate of the pad unit; in the above scheme, the height of the second copper column is greater than the height of the first copper column, and the height of the second bump is smaller than the height of the first bump.

[0020] The embodiments of the present disclosure further provide a memory including the chip structure as described above.

[0021] In the above scheme, the memory is a dynamic random access memory (DRAM).

[0022] It can be seen that the chip structure provided by the embodiment of the present disclosure comprises: at least one pad unit, the pad unit comprising: a plurality of power pads and a plurality of command data pads; the plurality of power pads are arranged equidistantly along a predetermined direction in a first area close to the storage array unit; the plurality of command data pads are arranged equidistantly along the predetermined direction, and the plurality of power pads are closer to the storage array unit than the plurality of command data pads; wherein, the command data pads and the power pads are arranged alternately in the predetermined direction; the distance between the center point of each command data pad and the center point of the adjacent power pad in the predetermined direction is less than a preset threshold. In the present disclosure, by arranging the command data pads and the power pads alternately, the command data pads can be transmitted to the storage array unit through the gap between the two adjacent power pads, which ensures that the signal transmission between each pad and the storage array unit is not affected. Moreover, by arranging the distance between each command data pad and the adjacent power pad in the predetermined direction to be less than the preset threshold, the area occupied by each two adjacent pads is reduced. In this way, more pads can be accommodated in the limited size of the chip, and compared with the way of arranging two rows of uniformly arranged pads in the middle of the chip in the related art, the number of pads that can be configured in the small size chip is increased. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 Structure diagram of the chip structure provided by the embodiment of the present disclosure Figure 1 ;

[0024] Figure 2 Structure diagram of the chip structure provided by the embodiment of the present disclosure Figure 2 ;

[0025] Figure 3 Structure diagram of the chip structure provided by the embodiment of the present disclosure Figure 3 ;

[0026] Figure 4 Structure diagram of the chip structure provided by the embodiment of the present disclosure Figure 4 ;

[0027] Figure 5 Structure diagram of the chip structure provided by the embodiment of the present disclosure Figure 5 ;

[0028] Figure 6 Structure diagram of the chip structure provided by the embodiment of the present disclosure Figure 6 ;

[0029] Figure 7 Structure diagram of the chip structure provided by the embodiment of the present disclosure Figure 7 ;

[0030] Figure 8 Structure diagram of chip structure provided by an embodiment of the present disclosure Figure 8

[0031] Figure 9 Structure diagram of chip structure provided by an embodiment of the present disclosure Figure 9

[0032] Figure 10 Structure diagram of chip structure provided by an embodiment of the present disclosure Figure 10

[0033] Figure 11 Structure diagram of chip structure provided by an embodiment of the present disclosure Figure 10 one

[0034] Figure 12 Structure diagram of chip structure provided by an embodiment of the present disclosure Figure 10 two

[0035] Figure 13 Structure diagram of chip structure provided by an embodiment of the present disclosure Figure 10 three

[0036] Figure 14 Structure diagram of pad structure provided by an embodiment of the present disclosure

[0037] Figure 15 Structure diagram of memory provided by an embodiment of the present disclosure DETAILED DESCRIPTION

[0038] In order to make the purpose, technical scheme and advantages of the present disclosure clearer, the technical scheme of the present disclosure is further described in detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present disclosure.

[0039] In the following description, “some embodiments” are described, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.

[0040] If the description of “first / second” appears in the invention document, the following description is added, in the following description, the term “first\second\third” only distinguishes similar objects, and does not represent a specific order of the objects, and it can be understood that “first\second\third” can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0041] ​​​​​​Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the disclosure.

[0042] Please refer to Figure 1 , Figure 1 The structural diagram of the chip structure provided by the embodiments of the disclosure Figure 1 .

[0043] Please refer to Figure 1 , Figure 2 In some embodiments, the storage array unit 10 is connected to one pad unit 20, and in other embodiments, the storage array unit 10 can also be connected to other pad units 20. The embodiments of the disclosure provide a chip structure 70, which includes at least one pad unit 20, and the pad unit 20 includes a plurality of power pads 21 and a plurality of command data pads 22. The plurality of power pads 21 are arranged equidistantly along a predetermined direction in a first region 30 close to the storage array unit 10. The plurality of command data pads 22 are arranged equidistantly along a predetermined direction, and the plurality of power pads 21 are closer to the storage array unit 10 than the plurality of command data pads 22. Wherein, the command data pads 22 and the power pads 21 are arranged alternately in the predetermined direction. The distance between the center point of each command data pad 22 and the center point of the adjacent power pad 21 in the predetermined direction is less than a preset threshold. The distance between the center point of each command data pad 22 and the center point of any one of the adjacent power pads 21 in the predetermined direction is less than a preset threshold.

[0044] Wherein, the preset threshold is a distance threshold set in advance. In some embodiments, the preset threshold can be any one of 20um, 30um, 50um, 60um and 70um.

[0045] In combination with Figure 1 , the region where the storage array unit 10 is located can include four sides (the first side 101, the second side 102, the third side 103 and the fourth side 104), and any one side of the storage array unit 10 can be connected to the pad unit. In some other embodiments, the internal region 105 of the storage array unit 10 can also be provided with the pad unit. Wherein, the internal region 105 can be located at the middle position of the storage array unit 10.

[0046] In combination with Figure 1The power pads 21 are pads for providing power to corresponding interfaces in the memory array unit 10. The command data pads 22 are pads for receiving or sending address commands, data signals. The plurality of power pads 21 are arranged equidistantly in a predetermined direction near the first area 30 of the memory array unit 10, so as to reduce the distance between the power pads 21 and the memory array unit 10, so that the power pads 21 provide power to the memory array unit 10, the transmission distance of the electrical signals is reduced, and the loss of the electrical signals is also reduced accordingly.

[0047] The chip includes the pad unit 20 and the memory array unit 10. The pad unit 20 is a basic constituent unit of the surface mount assembly of the chip, and is used to form a pad pattern of the chip, that is, a pad combination designed for the chip. The pad unit 20 is used to realize data signal transmission between the chip and an external controller. The memory array unit 10 includes a large number of memory units arranged in an array, and each memory unit stores 1 bit of data. Since the memory array unit 10 is arranged in an array, it can be regarded as a typical mesh structure. The memory array unit 10 uses rows and columns to specify addresses. By specifying the intersection of the rows and the columns (that is, by setting the row address and the column address), the memory controller can access each memory unit in the chip and perform read or write operations on the data stored in the memory unit.

[0048] In combination Figure 3 In the present disclosure, by interleaving the command data pads 22 with the power pads 21, the interleaved pads can ensure that the signal transmission between each pad and the memory array unit 10 is not affected. In addition, by setting the distance between each command data pad 22 and the adjacent power pad 21 in the predetermined direction to be less than a preset threshold, the area occupied by the adjacent command data pad 22 and the power pad 21 is reduced. In this way, more pads can be accommodated in the limited size of the chip, and compared with the related art in which two rows of uniformly arranged pads are arranged in the middle of the chip, the number of pads that can be configured in the small-size chip is increased.

[0049] Please refer to Figure 3 , Figure 3 The chip structure provided by the embodiment of the present disclosure Figure 3 .

[0050] In combination Figure 3In the embodiments of the present disclosure, the at least one pad unit comprises: a middle pad unit 23. The storage array unit comprises: a first storage array unit 11 and a second storage array unit 12 arranged at intervals. The plurality of power pads comprises: a plurality of first power pads 211 and a plurality of second power pads 212. The plurality of command data pads comprises: a plurality of first command data pads 221 and a plurality of second command data pads 222.

[0051] In combination Figure 3 , the middle pad unit 23 is arranged between the first storage array unit 11 and the second storage array unit 12. The plurality of first power pads 211 is arranged at intervals along a predetermined direction and close to the first sub-region 31 of the first storage array unit 11. The plurality of second power pads 212 is arranged at intervals along a predetermined direction and close to the second sub-region 32 of the second storage array unit 12. The plurality of first command data pads 221 is arranged at intervals along a predetermined direction and between the plurality of first power pads 211 and the plurality of second power pads 212 and close to the first storage array unit 11. The plurality of second command data pads 222 is arranged at intervals along a predetermined direction and between the plurality of first power pads 211 and the plurality of second power pads 212 and close to the second storage array unit 12. In the embodiments of the present disclosure, the first command data pads 221 and the first power pads 211 are staggered in the predetermined direction, the distance between the center point of the first command data pad 221 and the center point of the adjacent first power pad 211 in the predetermined direction is less than a preset threshold, and the second command data pads 222 and the second power pads 212 are staggered in the predetermined direction, the distance between the center point of the second command data pad 222 and the center point of the adjacent second power pad 212 in the predetermined direction is less than a preset threshold.

[0052] In combination Figure 4 , the distance between the adjacent two first power pads 211, the distance between the adjacent two second power pads 212, the distance between the adjacent two first command data pads 221, and the distance between the adjacent two second command data pads 222 can be the same.

[0053] In combination Figure 4 , the plurality of first power pads 211 is arranged at intervals along a predetermined direction and close to the first sub-region 31 of the first storage array unit 11, and the purpose of this arrangement is to reduce the distance between the first power pad 211 and the first storage array unit 11, so that when the first power pad 211 provides power to the first storage array unit 11, the transmission distance of the electrical signal is reduced, and the loss of the electrical signal is also reduced accordingly. The plurality of second power pads 212 is arranged at intervals along a predetermined direction and close to the second sub-region 32 of the second storage array unit 12. Similarly, the plurality of second power pads 212 is arranged in this way, which can reduce the loss of the electrical signal transmitted by the second power pad 212 to the second storage array unit 12.

[0054] In combination Figure 4 , by interleaving the first command data pads 221 with the first power pads 211, the interleaving manner of the pads can make the first command data pads 221 transmit signals with the first memory array units 11 through the gap between two adjacent first power pads 211, so as to ensure that the signal transmission between each first command data pad 221 and the first memory array unit 11 is not affected. Since the distance between each first command data pad 221 and the adjacent first power pad 211 in the predetermined direction is set to be less than the preset threshold, the area occupied by the adjacent first command data pad 221 and the first power pad 211 is reduced, so that more pads can be accommodated in the chip with limited size. By interleaving the second command data pads 222 with the second power pads 212, the interleaving manner of the pads can make the second command data pads 222 transmit signals with the second memory array units 12 through the gap between two adjacent second power pads 212, so as to ensure that the signal transmission between each second command data pad 222 and the second memory array unit 12 is not affected. Since the distance between each second command data pad 222 and the adjacent second power pad 212 in the predetermined direction is set to be less than the preset threshold, the area occupied by the adjacent second command data pad 222 and the second power pad 212 is reduced, so that more pads can be accommodated in the chip with limited size, and the number of pads that can be configured in the small-size chip is increased.

[0055] Please refer to Figure 4 , Figure 4 The chip structure provided by the embodiments of the present disclosure Figure 4 .

[0056] In combination Figure 5 In the embodiments of the present disclosure, the plurality of first command data pads include a plurality of first command pads 2211 and a plurality of first data pads 2212. The plurality of second command data pads include a plurality of second command pads 2221 and a plurality of second data pads 2222. The plurality of first command pads 2211 are arranged equidistantly in a predetermined direction in the third sub-region 33, and the plurality of first data pads 2212 are arranged equidistantly in a predetermined direction in the fourth sub-region 34. The third sub-region 33 and the fourth sub-region 34 are arranged equidistantly in a predetermined direction. The plurality of second command pads 2221 are arranged equidistantly in a predetermined direction in the fifth sub-region 35, and the plurality of second data pads 2222 are arranged equidistantly in a predetermined direction in the sixth sub-region 36. The fifth sub-region 35 and the sixth sub-region 36 are arranged equidistantly in a predetermined direction.

[0057] In combination Figure 5The first command pad 2211 is a pad for receiving or sending an address command. The first data pad 2212 is a pad for receiving or sending a data signal. The second command pad 2221 is a pad for receiving or sending an address command. The second data pad 2222 is a pad for receiving or sending a data signal.

[0058] In the embodiments of the present disclosure, in combination with Figure 5 The reason for arranging the first command pad 2211 and the first data pad 2212 in two areas is that the plurality of first data pads 2212 are arranged in the fourth sub-area, the wiring of the plurality of first data pads 2212 does not need to be staggered, the wiring distance of the first data pad 2212 is shortened, and the signal transmission loss is also reduced in response. Similarly, arranging the second command pad 2221 and the second data pad 2222 in two areas can also reduce the signal transmission loss on the second data pad 2222.

[0059] In combination with Figure 5 In the embodiments of the present disclosure, the plurality of first power pads include a plurality of first power supply pads 2111 and a plurality of first ground pads 2112, and the plurality of second power pads include a plurality of second power supply pads 2121 and a plurality of second ground pads 2122. The first power supply pad 2111 and the first ground pad 2112 are arranged in two seventh sub-areas 37, and the two seventh sub-areas 37 are arranged in a predetermined direction. The second power supply pad 2121 and the second ground pad 2122 are arranged in two eighth sub-areas 38, and the two eighth sub-areas 38 are arranged in a predetermined direction.

[0060] The first power supply pad 2111 and the second power supply pad 2121 can be VDD pads. The first ground pad 2112 and the second ground pad 2122 can be VSS pads. The first command pad 2211 and the second command pad 2221 can be CA pads. The first data pad 2212 and the second data pad 2222 can be DQ pads.

[0061] In combination with Figure 5The first power supply pad 2111 is a pad for supplying power to the corresponding interface in the first storage array unit 11. The second power supply pad 2121 is a pad for supplying power to the corresponding interface in the second storage array unit 12. The first ground pad 2112 is a pad for supplying a ground voltage to the corresponding interface in the first storage array unit 11. The second ground pad 2122 is a pad for supplying a ground voltage to the corresponding interface in the second storage array unit 12. The first power supply pad 2111 and the first ground pad 2112 are arranged in two seventh sub-regions 37. The second power supply pad 2121 and the second ground pad 2122 are arranged in two eighth sub-regions 38. The purpose of this arrangement is to reduce the distance between the first power supply pad 2111 and the first ground pad 2112 in the two seventh sub-regions 37 and the first storage array unit 11, and to reduce the distance between the second power supply pad 2121 and the second ground pad 2122 in the two eighth sub-regions 38 and the second storage array unit 12. In this way, when the first power supply pad 2111 and the first ground pad 2112 supply power to the first storage array unit 11, the transmission distance of the electrical signal is reduced, and the loss of the electrical signal is also reduced accordingly. Similarly, when the second power supply pad 2121 and the second ground pad 2122 supply power to the second storage array unit 12, the transmission distance of the electrical signal is reduced, and the loss of the electrical signal is also reduced accordingly.

[0062] Please refer to Figure 6 The plurality of first command data pads include a plurality of first command pads 2211 and a plurality of first data pads 2212. The plurality of second command data pads include a plurality of second command pads 2221 and a plurality of second data pads 2222. The first command pads 2211 and the first data pads 2212 are arranged between the plurality of first power supply pads and the plurality of second power supply pads (i.e., between the first sub-region 31 and the second sub-region 32) and close to the first storage array unit 11. The second command pads 2221 and the second data pads 2222 are arranged between the plurality of first power supply pads and the plurality of second power supply pads (i.e., between the first sub-region 31 and the second sub-region 32) and close to the second storage array unit 12.

[0063] Please refer to Figure 6, the first command pads 2211 are staggered with the first power supply pads 2111 and the first ground pads 2112 in the first sub-region 31, the first data pads 2212 are staggered with the first power supply pads 2111 and the first ground pads 2112 in the first sub-region 31, the distance between each first command pad 2211 and the adjacent first power supply pad 2111 and the first ground pad 2112 in the first sub-region 31 in a predetermined direction is set to be less than a preset threshold, and the distance between each first data pad 2212 and the adjacent first power supply pad 2111 and the first ground pad 2112 in the first sub-region 31 in a predetermined direction is set to be less than a preset threshold. The staggered manner of the pads can make the first command pads 2211 transmit signals with the first memory array unit 11 through the gap between the adjacent first power supply pad 2111 and the first ground pad 2112, and can also make the first data pads 2212 transmit signals with the first memory array unit 11 through the gap between the adjacent first power supply pad 2111 and the first ground pad 2112, so as to ensure that the signal transmission between each pad and the first memory array unit 11 is not affected. In addition, since the distance between the first command pads 2211 and the first data pads 2212 and the adjacent pads in the first sub-region 31 in a predetermined direction is set to be less than a preset threshold, the area occupied by the first command pads 2211 and the adjacent first power supply pad 2111 or the first ground pad 2112 is reduced, and the area occupied by the first data pads 2212 and the adjacent first power supply pad 2111 or the first ground pad 2112 is also reduced. This arrangement can accommodate more pads in a chip with limited size.

[0064] In combination Figure 6The second command pads 2221 are staggered with the second power supply pads 2121 and the second ground pads 2122 in the second sub-region 32, and the second data pads 2222 are staggered with the second power supply pads 2121 and the second ground pads 2122 in the second sub-region 32. The distance between each second command pad 2221 and the adjacent second power supply pad 2121 and the adjacent second ground pad 2122 in the second sub-region 32 in a predetermined direction is less than a preset threshold, and the distance between each second data pad 2222 and the adjacent second power supply pad 2121 and the adjacent second ground pad 2122 in the second sub-region 32 in a predetermined direction is less than a preset threshold. The staggered arrangement of the pads can enable the second command pads 2221 to transmit signals to the second memory array unit 12 through the gap between the adjacent second power supply pad 2121 and the adjacent second ground pad 2122, and can also enable the second data pads 2222 to transmit signals to the second memory array unit 12 through the gap between the adjacent second power supply pad 2121 and the adjacent second ground pad 2122, thereby ensuring that the signal transmission between each pad and the second memory array unit 12 is not affected. In addition, the distance between the second command pads 2221 and the adjacent pads in the second sub-region 32 in a predetermined direction and the distance between the second data pads 2222 and the adjacent pads in the second sub-region 32 in a predetermined direction are both less than a preset threshold, thereby reducing the area occupied by the adjacent second command pads 2221 and the second power supply pad 2121 or the second ground pad 2122, and reducing the area occupied by the adjacent second data pads 2222 and the adjacent second power supply pad 2121 or the second ground pad 2122, so that more pads can be accommodated in a chip with limited size.

[0065] Please refer to Figure 6 The plurality of first power supply pads include a plurality of first power supply pads 2111 and a plurality of first ground pads 2112, and the plurality of second power supply pads include a plurality of second power supply pads 2121 and a plurality of second ground pads 2122. The first power supply pads 2111 and the first ground pads 2112 are arranged at intervals in the first sub-region 31. The second power supply pads 2121 and the second ground pads 2122 are arranged at intervals in the second sub-region 32.

[0066] Please refer to Figure 7The first power supply pad 2111 and the first ground pad 2112 are arranged in the first sub-region 31. The purpose of this arrangement is to reduce the distance between the first power supply pad 2111, the first ground pad 2112 and the first memory array unit 11. When the first power supply pad 2111 and the first ground pad 2112 provide power for the first memory array unit 11, the transmission distance of the electrical signal is reduced, and the loss of the electrical signal is also reduced accordingly. Similarly, the second power supply pad 2121 and the second ground pad 2122 are arranged in the second sub-region 32. This arrangement can reduce the loss of the electrical signal transmitted to the second memory array unit 12 in the second sub-region 32.

[0067] Please refer to Figure 7 , Figure 7 The chip structure provided by the embodiment of the present disclosure Figure 8 .

[0068] In combination Figure 8 In other embodiments, the plurality of power supply pads 21 and the plurality of command data pads 22 are arranged on the substrate. The orthographic projection of the command data pads 22 on the substrate is smaller than the orthographic projection of the power supply pads 21 on the substrate.

[0069] In combination Figure 9 In the embodiment of the present disclosure, the size of the power supply pad 21 can be 41 / 20-25. Specifically, the power supply pad 21 can be 41 um long, 20 um wide and 25 um high. The size of the command data pad 22 is smaller than the size of the power supply pad 21. Specifically, the length of the command data pad 22 can be smaller than the length of the power supply pad 21, the width of the command data pad 22 can be smaller than the width of the power supply pad 21, and the height of the command data pad 22 can be consistent with the height of the power supply pad 21.

[0070] In the embodiment of the present disclosure, the orthographic projection of the command data pad 22 on the substrate is arranged to be smaller than the orthographic projection of the power supply pad 21 on the substrate. The reason for this is that a larger power supply pad 21 can be arranged with more contact structures, reducing the contact resistance and increasing the electrical connection performance of the power supply pad 21 to the inside of the chip. The reason for arranging the orthographic projection of the command data pad 22 on the substrate to be smaller is that, in the case where the distance between the command data pad 22 and the adjacent power supply pad 21 in the predetermined direction is less than the preset threshold, the orthographic projection of the command data pad 22 on the substrate is further reduced, which can reduce the area occupied by the adjacent command data pad 21 and the power supply pad 22. Thus, more pads can be accommodated in the chip with limited size.

[0071] In combination Figure 9, the plurality of command data pads include a plurality of third command pads 24 and a plurality of third data pads 25. The plurality of power pads include a plurality of third power pads 26 and a plurality of third ground pads 27. The third power pads 26 and the third ground pads 27 are arranged in the first region 30 near the first side 101 of the memory array unit 10 in the predetermined direction with a spacing. The plurality of third command pads 24 are arranged in the ninth sub-region 39 in the predetermined direction with an equal spacing. The plurality of third data pads 25 are arranged in the tenth sub-region 40 in the predetermined direction with an equal spacing. The ninth sub-region 39 and the tenth sub-region 40 are arranged in the predetermined direction with a spacing.

[0072] In combination Figure 10 , the third command pads 24 and the third data pads 25 have a same size of orthographic projection on the base of the pad unit 20. The third power pads 26 and the third ground pads 27 have a same size of orthographic projection on the base of the pad unit 20. The third command pads 24 have a smaller size of orthographic projection on the base than the third power pads 26 and the third ground pads 27. The third data pads 25 have a smaller size of orthographic projection on the base than the third power pads 26 and the third ground pads 27.

[0073] In combination Figure 10 , the third command pads 24 and the third power pads 26 and the third ground pads 27 in the pad unit 20 are arranged in the predetermined direction with a staggered manner. The distance between the center point of the third command pad 24 and the center point of the adjacent third power pad 26 or the third ground pad 27 in the predetermined direction is less than a preset threshold. The third data pads 25 and the third power pads 26 and the third ground pads 27 are arranged in the predetermined direction with a staggered manner. The distance between the center point of the third data pad 25 and the center point of the adjacent third power pad 26 or the third ground pad 27 in the predetermined direction is less than a preset threshold. The staggered manner of the pads can make the third command pads 24 transmit signals to the memory array unit 10 through the gap between the adjacent third power pads 26 and the third ground pads 27. The third data pads 25 can also transmit signals to the memory array unit 10 through the gap between the adjacent third power pads 26 and the third ground pads 27. This ensures that the signal transmission between each pad and the memory array unit 10 is not affected. Since the distance between the third command pad 24 and the adjacent third power pad 26 or the third ground pad 27 in the predetermined direction is less than the preset threshold, and the distance between the third data pad 25 and the adjacent third power pad 26 or the third ground pad 27 in the predetermined direction is less than the preset threshold, the area occupied by the third command pad 24 and the adjacent third power pad 26 or the third ground pad 27 is reduced. The area occupied by the third data pad 25 and the adjacent third power pad 26 or the third ground pad 27 is also reduced. This allows more pads to be accommodated in the chip with limited size.

[0074] In combination Figure 11 The region where the memory array unit 10 is located includes four side edges. When the at least one pad unit includes two pad units, the two pad units are arranged at the periphery of two opposite side edges among the four side edges. In this case, Figure 12 In the case shown in FIG. 1, the first pad unit 201 is arranged at the first side edge 101 and the third pad unit 203 is arranged at the third side edge 103. In other embodiments, the two pad units can also be arranged on the second side edge 102 and the fourth side edge 104. In combination Figures 8 to 12 The two pad units are arranged at the periphery of two adjacent side edges among the four side edges. In this case, Figure 6 In the case shown in FIG. 1, the first pad unit 201 is arranged at the first side edge 101 and the second pad unit 202 is arranged at the second side edge 102. In other embodiments, the two pad units can also be arranged on the second side edge 102 and the third side edge 103, the two pad units can also be arranged on the third side edge 103 and the fourth side edge 104, and the two pad units can also be arranged on the fourth side edge 104 and the first side edge 101.

[0075] In combination Figure 13 When the at least one pad unit includes one pad unit, the one pad unit can be the first pad unit 201. The first pad unit 201 can be arranged at the periphery of any one side edge among the four side edges. In this case, Figure 10 In the case shown in FIG. 1, the first pad unit 201 is arranged at the first side edge 101. In other embodiments, the one pad unit can also be arranged on any one side edge among the second side edge 102, the third side edge 103, and the fourth side edge 104.

[0076] In the embodiments of the present disclosure, when the at least one pad unit includes three or four pad units, the three or four pad units are respectively arranged at the periphery of the corresponding side edge among the four side edges.

[0077] In combination Figure 13When the at least one pad unit includes three pad units, the three pad units are respectively arranged at the periphery of the corresponding side among the four sides. The three pad units include a first pad unit 201, a second pad unit 202, and a third pad unit 203. The first pad unit 201 is arranged on the first side 101, the second pad unit 202 is arranged on the second side 102, and the third pad unit 203 is arranged on the third side 103. In some other embodiments, the three pad units can also be arranged on the second side 102, the third side 103, and the fourth side 104, the three pad units can also be arranged on the third side 103, the fourth side 104, and the first side 101, and the three pad units can also be arranged on the fourth side 104, the first side 101, and the second side 102.

[0078] In combination Figure 14 When the at least one pad unit includes four pad units, the four pad units are respectively arranged at the periphery of the corresponding side among the four sides. The chip structure 70 includes one memory array unit 10 and four pad units. The four pad units include a first pad unit 201, a second pad unit 202, a third pad unit 203, and a fourth pad unit 204. The first pad unit 201 is arranged on the first side 101, the second pad unit 202 is arranged on the second side 102, the third pad unit 203 is arranged on the third side 103, and the fourth pad unit 204 is arranged on the fourth side 104.

[0079] In the embodiments of the present disclosure, Figure 14 The arrangement of the pads in any one of the pad units can refer to the arrangement of the pad unit 20 in Figure 14 The command data pads 22 and the power pads 21 are staggered in a predetermined direction, and the distance between the center point of the command data pad 22 and the center point of the adjacent power pad 21 in the predetermined direction is less than a preset threshold. Similarly, the staggered arrangement of the pads can enable the command data pad 22 to transmit signals to the memory array unit 10 through the gap of the adjacent power pad 21, which ensures that the signal transmission between each pad and the memory array unit 10 is not affected. Moreover, the distance between the command data pad 22 and the adjacent power pad 21 in the predetermined direction is set to be less than the preset threshold, so that the area occupied by the adjacent command data pad 22 and the power pad 21 is reduced, and more pads can be accommodated in the chip with limited size.

[0080] Please refer to Figure 15 , Figure 15 The structural diagram of the chip structure provided in the embodiments of the present disclosure is shown in Figure 15 three.

[0081] In combination ​The command data pad 22 is connected with the corresponding interface 45 in the memory array unit 10 through the first wire 42 arranged on the pad unit 20. The power pad 21 is connected with the corresponding interface 45 in the memory array unit 10 through the second wire 41 arranged on the pad unit 20. The resistance of the first wire 42 is smaller than that of the second wire 41.

[0082] In the embodiment of the present disclosure, the cross-sectional area of the first wire 42 is smaller than that of the second wire 41. The smaller cross-sectional area of the wire can reduce the resistance of the wire, which is conducive to the signal transmission of the first wire 42. Moreover, since the first wire 42 is arranged in the gap between the two power pads 21, the smaller cross-sectional area of the first wire 42 is conducive to reducing the gap between the two power pads 21, so that more pads can be accommodated in the chip with limited size. In some other embodiments, the cross-sectional areas of the first wire 42 and the second wire 41 can be the same, but the first wire 42 can be made of a conductive material with lower resistance.

[0083] In the embodiment of the present disclosure, the resistance of the first wire 42 is smaller than that of the second wire 41. The reason for such arrangement is that the smaller the resistance of the first wire 42, the less the loss of the signal transmitted by the first wire 42, and the electrical signal loss of the second wire 41 of the power pad 21 is less than that of the first wire 42, thereby ensuring that the electrical signal of the power pad 21 is not distorted.

[0084] Please refer to ​ , ​ The structure diagram of the pad structure provided in the embodiment of the present disclosure is shown.

[0085] In combination ​ The command data pad 22 includes a first aluminum base 54, a first copper column 53, a first solder cap 52 and a first bump 51 formed in sequence on the base 66 of the pad unit. The power pad 21 includes a second aluminum base 64, a second copper column 63, a second solder cap 62 and a second bump 61 formed in sequence on the base 66 of the pad unit. Among them, the height of the second copper column 63 is greater than the height of the first copper column 53, and the height of the second bump 61 is smaller than the height of the first bump 51.

[0086] Among them, a passivation layer 65 is arranged between the first aluminum base 54 and the second aluminum base 64. The final height of the command data pad 22 and the power pad 21 is consistent.

[0087] In this embodiment, the height of the second copper pillar 63 is greater than the height of the first copper pillar 53, while the height of the second bump 61 is less than the height of the first bump 51. This arrangement allows the copper pillars and bumps corresponding to the command data pad 21 and the power pad 22 to be staggered in three-dimensional space, eliminating the risk of short circuits in the solder bridges. Simultaneously, since the final heights of the command data pad 22 and the power pad 21 are the same, the problem of short circuits between the pins connected to the command data pad 22 and the power pad 21 is avoided.

[0088] ​ This is a schematic diagram of the structure of the memory provided in the embodiments of this disclosure, such as... ​ As shown, the memory 80 includes the chip structure 70 provided in the above embodiments.

[0089] In some embodiments of this disclosure, reference is made to ​ The memory 80 is Dynamic Random Access Memory (DRAM).

[0090] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0091] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0092] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip structure, characterized by Comprising: at least one pad unit, the pad unit comprising: a plurality of power pads and a plurality of command data pads; a plurality of the power pads are equidistantly arranged along a predetermined direction in a first region close to a storage array unit; a plurality of the command data pads are equidistantly arranged along the predetermined direction, and a plurality of the power pads are closer to the storage array unit than a plurality of the command data pads; wherein the command data pads and the power pads are staggered along the predetermined direction; a center point of each of the command data pads is less than a preset threshold distance from a center point of an adjacent power pad along the predetermined direction; wherein at least one of the pad unit comprises: an intermediate pad unit; the storage array unit comprises: a first storage array unit and a second storage array unit arranged at intervals; a plurality of the power pads comprises: a plurality of first power pads and a plurality of second power pads; a plurality of the command data pads comprises: a plurality of first command data pads and a plurality of second command data pads; the intermediate pad unit is arranged between the first storage array unit and the second storage array unit; a plurality of the first power pads are equidistantly arranged along the predetermined direction in a first sub-region close to the first storage array unit; a plurality of the second power pads are equidistantly arranged along the predetermined direction in a second sub-region close to the second storage array unit; a plurality of the first command data pads are equidistantly arranged along the predetermined direction between a plurality of the first power pads and a plurality of the second power pads and close to the first storage array unit; a plurality of the second command data pads are equidistantly arranged along the predetermined direction between a plurality of the first power pads and a plurality of the second power pads and close to the second storage array unit; 2. The chip structure of claim 1, wherein wherein the first command data pads and the first power pads are staggered along the predetermined direction, a center point of the first command data pads is less than the preset threshold distance from a center point of an adjacent first power pad along the predetermined direction, and the second command data pads and the second power pads are staggered along the predetermined direction, a center point of the second command data pads is less than the preset threshold distance from a center point of an adjacent second power pad along the predetermined direction. a plurality of the first command data pads comprises: a plurality of first command pads and a plurality of first data pads; a plurality of the second command data pads comprises: a plurality of second command pads and a plurality of second data pads; a plurality of the first command pads are equidistantly arranged along the predetermined direction in a third sub-region, and a plurality of the first data pads are equidistantly arranged along the predetermined direction in a fourth sub-region, the third sub-region and the fourth sub-region are arranged at intervals along the predetermined direction; a plurality of the second command pads are equidistantly arranged along the predetermined direction in a fifth sub-region, and a plurality of the second data pads are equidistantly arranged along the predetermined direction in a sixth sub-region, the fifth sub-region and the sixth sub-region are arranged at intervals along the predetermined direction.

3. The chip structure according to claim 1 or 2, characterized in that The first power supply pads include a plurality of first power supply pads and a plurality of first ground pads, and the second power supply pads include a plurality of second power supply pads and a plurality of second ground pads. The first power supply pads and the first ground pads are arranged in two seventh sub-regions, and the two seventh sub-regions are arranged at intervals along the predetermined direction. The second power supply pads and the second ground pads are arranged in two eighth sub-regions, and the two eighth sub-regions are arranged at intervals along the predetermined direction.

4. The chip structure of claim 1, wherein, The power supply pads and the command data pads are arranged on a substrate, and a projection of the command data pads on the substrate is smaller than a projection of the power supply pads on the substrate.

5. The chip structure of claim 1, wherein, The region where the memory array unit is located includes four sides. When the at least one pad unit includes two pad units, the two pad units are arranged at the periphery of two opposite sides of the four sides, or the two pad units are arranged at the periphery of two adjacent sides of the four sides.

6. The chip structure of claim 1, wherein, The command data pads are connected to corresponding interfaces in the memory array unit through first wires arranged on the pad unit. The power supply pads are connected to corresponding interfaces in the memory array unit through second wires arranged on the pad unit, and the resistance value of the first wires is smaller than that of the second wires.

7. The chip structure of claim 1, wherein, The command data pads include a first aluminum base, a first copper column, a first solder cap, and a first bump, which are sequentially formed on a substrate of the pad unit. The power supply pads include a second aluminum base, a second copper column, a second solder cap, and a second bump, which are sequentially formed on a substrate of the pad unit.

8. The chip structure of claim 7, wherein, The height of the second copper column is greater than that of the first copper column, and the height of the second bump is less than that of the first bump.

9. A chip structure, characterized by The memory includes the chip structure of any one of claims 1 to 9, and the memory is a dynamic random access memory (DRAM). The memory includes the chip structure of any one of claims 1 to 9, and the memory is a dynamic random access memory (DRAM). ​ ​ ​ 10. A memory, comprising: ​

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