Encodes byte information on the data bus

Abstract

Data may be communicated from a transmitter device to a receiver device via enabled or selected byte positions or other data bit groups of a data bus. The transmitter device may determine the data values ​​to be transmitted via the data bus, and may determine which byte positions are enabled or selected and which byte positions are not selected. The transmitter device may also determine a code. The code may be a value not included in the data values ​​to be transmitted via the data bus. The transmitter device may then transmit the selected data value in the selected byte positions of the data bus, and transmit the code in the unselected byte positions of the data bus. The transmitter device may also transmit the code to the receiver device independently of the data bit lanes of the data bus.

Description

[0001] Related technical description

[0002] A computing device may include multiple subsystems, cores, or other components. Such a computing device may be, for example, a portable computing device ("PCD") such as a laptop or palmtop computer, a cellular or smart phone, a portable digital assistant, a portable game console, or the like.

[0003] Multiple subsystems, cores, or other components of a computing device may be included within the same integrated circuit chip or in different chips. A "system on a chip" or "SoC" is an example of a chip that integrates numerous components to provide system-level functionality. For example, a SoC may include one or more types of processors, such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a digital signal processor ("DSP"), and a neural processing unit ("NPU"). A SoC may include other processing subsystems, such as a transceiver or "modem" subsystem that provides wireless connectivity, a memory subsystem, and the like.

[0004] The various subsystems can communicate with each other via a data bus. The data bus can be serial or parallel. A parallel data bus includes multiple signal lines, also referred to as bits, channels, etc. The number of data bus channels may be referred to as data bus width. A memory bus is a common example of a parallel data bus. Although a wider data bus may help increase bandwidth, some disadvantages of a wider data bus may include more chip area occupied by the data bus channels, increased power consumption, narrower timing margins, etc.

[0005] Depending on the application or data requirements, some types of memory devices can be configured to different data widths. Some systems with memories that can be configured to different data widths are characterized by the ability to selectively write only to a portion or subset of the widest data width. A technique known as "byte enable" allows selected bytes to be written into a wider data width block. For example, in the case of a 32-bit width (i.e., four bytes), only the lowest byte can be selected to be written instead of all four bytes. The byte enable ("BE") bit can be communicated from the transmitting subsystem to the receiving subsystem together with the corresponding data byte. A transmitting device (e.g., a processor) can selectively transmit data on all bytes of a data bus or only on a subset. A transmitting device can use the BE bit to indicate a selected or enabled byte position on a data bus. Based on the BE bit, a receiving device can only process data received in an enabled byte position on the data bus, and ignore (i.e., not process) data received in an unenabled byte position on the data bus. For example, a memory can only write data bytes indicated as enabled by the BE bit.

[0006] In a data bus scheme where a BE bit is included for each byte of data, the wider the data bus is, the greater the number of lanes reserved for BE bits rather than for data. It is desirable to provide a BE feature that increases the efficient use of lanes for data. Summary of the invention

[0007] Systems, methods, computer-readable media, and other examples are disclosed for communicating data from a transmitter device to a receiver device over a data bus using selected byte positions or other groups of data bits.

[0008] An exemplary method for communicating data via a data bus may be provided. The data bus may have a plurality of data bit groups. Each data bit group may have a plurality of data bit lanes. The method may include determining, by a transmitter device, a set of selected data values ​​to be transmitted via the data bus. The method may also include determining, by the transmitter device, a selected data bit group and an unselected data bit group. The method may also include determining, by the transmitter device, a code representing an unselected data value that is not included in the set of selected data values. The method may still further include transmitting, via the data bit lanes, the selected data values ​​in the selected data bit group and the code in the unselected data bit group to a receiver device. The method may still further include transmitting the code to the receiver device independently of the data bit lanes.

[0009] An exemplary system for communicating data via a data bus may be provided. The data bus may have a plurality of data bit groups. Each data bit group may have a plurality of data bit channels. The exemplary system may include an encoder and a data word formatter. The encoder may be configured to determine a set of selected data values ​​to be transmitted via the data bus. The data word formatter may be configured to determine a selected data bit group and an unselected data bit group. The data word formatter may also be configured to determine a code representing an unselected data value that is not included in the set of selected data values. The data word formatter may also be configured to provide a data word to a receiver device via the data bit channel, the data word having a selected data value in the selected data bit group and a code in the unselected data bit group. The data word formatter may still further be configured to provide the code to the receiver device via a plurality of code bit channels independent of the data bit channels.

[0010] Another exemplary system for communicating data via a data bus may be provided. The data bus may have a plurality of data bit groups. Each data bit group may have a plurality of data bit lanes. The system may include means for determining a set of selected data values ​​to be transmitted via the data bus. The system may also include means for determining a selected data bit group and an unselected data bit group. The system may also include means for determining a code representing an unselected data value that is not included in the set of selected data values. The system may still further include means for transmitting the selected data values ​​in the selected data bit group and the code in the unselected data bit group to a receiver device via the data bit lanes. The system may still further include means for transmitting the code to the receiver device independently of the data bit lanes.

[0011] An exemplary computer-readable medium for communicating data via a data bus may be provided. The data bus may have a plurality of data bit groups. Each data bit group may have a plurality of data bit lanes. The computer-readable medium may include a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form. The instructions, when executed by a processing system of a computing device, may configure the processing system to control the following operations. The instructions may configure the processing system to control: determining a set of selected data values ​​to be transmitted via the data bus. The instructions may also configure the processing system to control: determining a selected data bit group and an unselected data bit group. The instructions may also configure the processing system to control: determining a code representing an unselected data value that is not included in the set of selected data values. The instructions may still further configure the processing system to control: transmitting the selected data value in the selected data bit group and the code in the unselected data bit group to a receiver device via the data bit lane. The instructions may still further configure the processing system to control: transmitting the code to the receiver device independently of the data bit lane. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations, such as "102A" or "102B," the letter character designations may distinguish between two similar parts or elements in the same figure. The letter character designations of reference numerals may be omitted when it is intended that a reference numeral encompass all parts having the same reference numeral in all figures.

[0013] Figure 1 is a block diagram illustrating a system for communicating data between a transmitter device and a receiver device over a data bus according to an exemplary embodiment.

[0014] Figure 2 is an example of an exemplary embodiment Figure 1 A data diagram of exemplary data word configurations with which a system may operate.

[0015] Figure 3 is a flow chart illustrating an exemplary method for communicating data between a transmitter device and a receiver device over a data bus according to an exemplary embodiment.

[0016] Figure 4 is a block diagram illustrating a portion of a device configured to transmit or transfer data through a data bus according to an exemplary embodiment.

[0017] Figure 5 is an example Figure 4 A data diagram of an example of the operation of a transmitter device.

[0018] Figure 6 is a block diagram illustrating a portion of a device configured to receive data through a data bus according to an exemplary embodiment.

[0019] Figure 7 is a flow chart illustrating an exemplary method for receiving data through a data bus according to an exemplary embodiment.

[0020] Figure 8 is a block diagram illustrating another system for communicating data between a transmitter device and a receiver device over a data bus according to an exemplary embodiment.

[0021] Fig. 9 is a block diagram of a computing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0022] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." The word "exemplary" may be used herein synonymously with "exemplary." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] like Figure 1 As shown, the system 100 may include a transmitter device 102 and a receiver device 104. The transmitter device 102 and the receiver device 104 may be included on a system on a chip or "SoC" 106. That is, the transmitter device 102 and the receiver device 104 may each include electronic circuits on the SoC 106. In one example, the transmitter device 102 may include a processor or processing circuit, and the receiver device 104 may include a memory device with a configurable data width. Although in this exemplary embodiment, the transmitter device 102 and the receiver device 104 are on the same SoC 106 as each other, in other embodiments, such transmitter devices and receiver devices may be on separate chips. For example, the transmitter device and the receiver device may be on separate "chiplets" in a package.

[0024] A data bus 108 including a plurality ("N") of data bit lanes may interconnect the transmitter device 102 and the receiver device 104. Each data bit lane may be an electrical signal conductor or path, such as a metallized strip on the SoC 106. The data bus 108 may convey N bits of information or data in parallel, with each data bit lane conveying one bit of data. The width of the data bus 108 may be expressed in bits, bytes, or any other units. For purposes of this disclosure, the width of the data bus 108 may be expressed in units referred to as "data bit groups," each data bit group including two or more data bit lanes. In an example, each data bit group may consist of eight data bit lanes (i.e., one byte), and the data bus 108 may have a width of 256 bytes, conveyed by a total of N=2048 lanes (i.e., 256 bytes×8 lanes per byte).

[0025] Although in this example, each data bit group includes eight bits (i.e., one byte), in other examples, each data bit group may include any number of two or more bits. Although the terms "transmitter" and "receiver" are used for purposes of illustrating examples, and the exemplary direction of data communication is represented by Figure 1 , it should be understood that data bus 108 may be bidirectional in other examples. Additionally, the term "data bus" is used for convenience and should not be construed as limiting. For example, data bus 108 may be a complex data interconnect, such as a certain type of data interconnect sometimes referred to as a network on chip or "NoC", an interconnect "fabric", etc. Although Figure 1 , but according to the present disclosure, a data bus may interconnect any number of different devices. Any such device that transmits data to another such device via a data bus may be a "transmitter" device as the term is used herein. Similarly, any such device that receives data from another such device via a data bus may be a "receiver" device as the term is used herein. Since some devices may be bidirectional (i.e., transceivers) in some examples, a transmitter device may be a bidirectional device configured to be in a mode of transmitting data, and a receiver device may be a bidirectional device configured to be in a mode of receiving data.

[0026] In addition, multiple (“M”) code bit channels 110 may interconnect the transmitter device 102 and the receiver device 104. Similar to the above-mentioned data bit channels of the data bus 108, each code bit channel may be an electrical signal conductor or path, such as a metallized strip on the SoC 106. The code bit channel 110 may convey a code including M parallel code bits from the transmitter device 102 to the receiver device 104. The code may have the same data size as each data bit group. In an example in which each data bit group consists of eight data bit channels, the code may include eight bits (i.e., M=8 code bit channels 110). However, in other examples, the code may include any other number of bits that is not inconsistent with the operating principles described below. The code bit channel 110 may be part of the same interconnect structure as the data bus 108, but for clarity, it is not referred to in the example. Figure 1 The code bit channel 110 and the data bus 108 are depicted separately. Figure 1 In the example shown, at least N+M lanes interconnect or couple the transmitter device 102 and the receiver device 104 .

[0027] like Figure 2 As shown, the exemplary data word configuration 200 may be composed of 256 bytes, which in turn may be connected to a data bus 108 having N=2048 channels (ie, 256 bytes×8 channels per byte). Figure 1 ) is communicated. In the illustrated data word configuration 200, the byte position is the data bus 108 ( Figure 1 ) is an example of the above data bit group. Therefore, in Figure 2 In the example illustrated in , the data word configuration 200 consists of the following: a first byte position 202A (e.g., in the least significant byte position); a second byte position 202B adjacent to the first byte position 202A; a third byte position 202C adjacent to the second byte position 202B, and so on, to the 256th byte position 202N (e.g., in the most significant byte position). In the illustrated example: the first byte position 202A may include the first bit b0 of the data word, the second bit b1 of the data word, the third bit b2 of the data word, and so on, to the 8th bit b7 of the data word; the second byte position 202B may include the 9th bit b8 of the data word to the 16th bit b15 of the data word; the third byte position 202C may include the 17th bit b16 of the data word to the 24th bit b23 of the data word; and so on, to the 256th byte position 202N, which may include the 2041st bit b2040 of the data word to the 2048th bit b2047 of the data word.

[0028] exist Figure 3 In FIG. 3 , a method 300 for communicating data via a data bus is illustrated. The data bus may refer to Figure 1 to Figure 2The method 300 is configured as described above. That is, the data bus may include two or more data bit groups, such as two or more bytes, wherein each data bit group includes two or more data bit channels. The transmitter device may be configured to control some or all of the method 300. For example, in an embodiment in which the transmitter device includes a processor, the processor may be configured by software or firmware to control some or all of the method 300. In addition, the transmitter device or a portion thereof (e.g., a processor) may be an example of a component for performing the functions set forth in the method 300. The method 300 may include the following features, functions, actions, etc. indicated in blocks 302 to 310, which may be performed or otherwise occur in any order that is not inconsistent with the description herein. Blocks 302 to 310 are described in an order that is helpful for understanding the exemplary method 300, but the method for communicating data from a transmitter device to a receiver device via a data bus is not limited to this order.

[0029] As indicated at block 302, method 300 may include determining a set of data values ​​(i.e., selected data values) to be transmitted over a data bus. For example, a transmitter device may obtain data from another source and arrange or organize the data values ​​for transmission to a receiver device. In some examples, the data values ​​to be transmitted to the receiver device may be the result of a calculation performed by the transmitter device. See again Figure 2 In the example shown, each data value can be a byte, i.e., eight bits. In such examples, the data values ​​can range from 0 to 255. In some examples, the size of the set of selected data values ​​can be related to the size of the data word. For example, up to 256 one-byte data values ​​can be selected to be transmitted over the data bus. In such examples, the transmitter device can determine or provide a set of selected data values ​​to be transmitted in the form of a 256-byte data word. In such examples, method 300 can be repeated any number of times to transmit any number of data words.

[0030] As indicated at block 304, method 300 may further include determining selected data bit groups and unselected data bit groups. For example, the transmitter device may select in which data bit groups to transmit selected data values, and conversely, in which data bit groups not to transmit any selected data values. The transmitter device may select any or all of the data bit groups to collectively transmit a set of selected data values. See again Figure 2In the example shown, the transmitter device may select any of the byte positions 202A to 202N to include data in a transmission or transfer operation from the transmitter device to the receiver device. The selected data bit group (e.g., byte position) may also be referred to as an enabled data bit group. In examples where the data bit group is a byte position, the selected byte position may also be referred to as an enabled byte position or an enabled byte. As described below, in some examples of method 300, the transmitter device may generate a data structure, such as a bit array or vector, which may indicate which data bit groups are selected (or enabled) and which data bit groups are not selected.

[0031] The method 300 may still further include determining a code representing an unselected data value, as indicated at block 306. The code or unselected data value may be any data value that is not included in the set of selected data values.

[0032] As indicated at block 308, method 300 may still further include transmitting the selected data value in the selected data bit group and the code in the unselected data bit group to the receiver device via the data bit lane. In other words, in the transmitted data word, the selected data value is located or contained in the selected data bit group, and the code is located or contained in the unselected data bit group. As indicated at block 310, method 300 may further include transmitting the code to the receiver device independently of the data bit lane. For example, see again Figure 1 , the transmitter device 102 can transmit the code to the receiver device through the code bit channel 110.

[0033] like Figure 4 As shown, system 400 can be configured to output data words in which selected data values ​​are located or contained in selected data bit groups and codes are located or contained in unselected data bit groups. System 400 can be configured to output data words via a data bus ( Figure 4 The system 400 may be the transmitter device 102 ( Figure 1 ). System 400 may include processor logic components (eg, programmed by software or firmware), discrete circuits (eg, finite state machines, combinational logic, etc.), or any combination thereof.

[0034] The input data word 402 may include the above-described set of selected data values ​​at locations (e.g., byte positions) corresponding to selected data bit groups (e.g., selected byte positions). Locations in the input data word 402 that do not correspond to selected data bit groups, or conversely, to unselected data bit groups, may contain any data value (i.e., a logical "don't care" value). The input data word 402 may have a configuration similar to the data word configuration 200 described above ( Figure 2) configuration. The input BE vector 404 may consist of a bit array or vector that indicates which data bit groups in the input data word 402 are selected and which data bit groups are not selected. For example, the system 400 may maintain the input BE vector 404 in the form of a data structure. In which the receiver device 104 ( Figure 1 ) is an example of a memory bus having a configurable data width, the input BE vector 404 may indicate (e.g., by a '1' bit) a selected (i.e., enabled) memory bus byte, and may indicate (e.g., by a '0' bit) an unselected (i.e., not enabled) memory bus byte.

[0035] The binary to unary encoder 406 may be configured to receive, obtain, or otherwise determine a set of selected data values ​​to be transmitted over the data bus. For example, the binary to unary encoder 406 may be configured to determine an input data word 402. Determining the input data word 402 may include receiving the input data word 402 from a data source, such as, for example, another portion of a transmitter device (not shown). The binary to unary encoder 406 may similarly receive or otherwise determine an input BE vector 404. The binary to unary encoder 406 (which may also be referred to as a two's complement encoder or converter) may also be configured to convert the input data word 402 into a bit vector of selected data values ​​408 using the input BE vector 404. As described below with reference to an example, the bit vector of the selected data value 408 may include a '1' bit in each bit position where the bit position (i.e., the numerical index) is equal to the selected data value, and may include a '0' bit in each bit position where the bit position (i.e., the numerical index) is not equal to the selected data value. As will be appreciated by one of ordinary skill in the art, binary to unary encoder 406 may be implemented using a straightforward configuration of logic gates and conveniently provides a vectorized method for indicating the selected data values ​​described herein. However, binary to unary encoder 406 is only one example of a circuit for determining a set of selected data values ​​to be transmitted over a data bus, and other methods and examples may occur to one of ordinary skill in the art in view of the description herein.

[0036] The data word formatter 410 may be configured to receive the input data word 402, the input BE vector 404, and the bit vector of the selected data value 408. The data word formatter 410 may also be configured to use the bit vector of the selected data value 408 to determine a code representing an unselected data value. For example, the data formatter 410 may be configured to select a bit position in the bit vector of the selected data value 408 that contains a '0' bit. If there are two or more bit positions that contain a '0' bit, the data formatter 410 may select any one of them.

[0037] The data formatter 410 may also be configured to determine selected bytes or other groups of data bits and unselected bytes or other groups of data bits.In the illustrated example, the data formatter 410 may use the input BE vector 404 to determine selected bytes and unselected bytes.

[0038] The data word formatter 410 may also be configured to provide output data words to a receiver device (e.g., as described above with reference to Figure 1 The output data word may include selected data values ​​in the selected data bit groups and may include codes in the unselected data bit groups. For example, the data word formatter 410 may place the selected byte values ​​indicated in the input data word 402 into corresponding byte positions of the output data word and may place the codes into the remaining unselected byte positions of the output data word. The data word formatter 410 may also be configured to provide the codes to a receiver device independently of the output data word (e.g., by providing the codes to the receiver device as described above with reference to FIG. Figure 1 The code described is bit channel 110).

[0039] exist Figure 5 , an example of the operation of the above-described system 400 is shown. In the illustrated example, the 256-bit input BE vector includes: a '1' in bit position b255 (i.e., the most significant bit position) thereby indicating that the corresponding data bus byte position B255 is selected; a '1' in bit position b254 thereby indicating that the corresponding data bus byte position B254 is selected; a '0' in bit position b253 thereby indicating that the corresponding data bus byte position B253 is not selected; a '1' in bit position b0 (i.e., the least significant bit position) thereby indicating that the corresponding data bus byte position B0 is selected; and other bit values ​​(for clarity, not all bit values ​​are shown) The exemplary BE vector may also include some other exemplary (or nth) bit position "bn" having a '0' and thereby indicating that the corresponding data bus byte position Bn is not selected. For clarity, the bit values ​​in bit positions b252 to b(n+1) and bit positions b(n-1) to b1 are not shown, but similarly may have a value of '1' to indicate a selected data bus byte position or a value of '0' to indicate an unselected data bus byte position.

[0040] exist Figure 5In the example illustrated in , the 256-byte input data word includes: data byte value 252 in byte position B255 (i.e., the most significant byte position); data byte value 0 in byte position B254; and data byte value 2 in byte position B0 (i.e., the least significant byte position); and other data byte values ​​(not all of which are shown for clarity). The byte in byte position B253 may have any value, as indicated by the “don't care” symbol “X” because, as described above, the input BE vector in this example indicates that data bus byte position B253 is not selected. Similarly, the byte in byte position Bn may have any value, as indicated by the “don't care” symbol “X” because, as described above, the input BE vector in this example indicates that data bus byte position Bn is not selected. For clarity, the data values ​​in byte positions B252 to B(n+1) and byte positions B(n-1) to B1 are not shown, but may have any value. Note that since the data bit group in the illustrated example is one byte (ie, eight bits), each byte value can range from 0 to 255.

[0041] In this example ( Figure 5 ), in forming the bit vector of the selected data value, the binary to unary encoder 406 ( Figure 4 ) may place: a bit value of '1' in bit position b252, as indicated by arrow 502, because the data byte in the selected data bus byte position B255 in the input data word has a value of 252; a bit value of '1' in bit position b0, as indicated by another arrow 504, because the data byte in the selected data bus byte position B254 in the input data word has a value of 0; and a bit value of '1' in bit position b2, as indicated by another arrow 506, because the data byte in the selected data bus byte position B0 in the input data word has a value of 2; and other bit values ​​(not all of which are shown for clarity). Although data bytes in the input data word having data values ​​of 255 and 1 are not explicitly shown, in this example, bit values ​​are similarly set to '1' in bit positions b255 and b1 of the bit vector of the selected data value, as indicated by dashed arrows 508 and 510, respectively.

[0042] Note that the bit vector of the selected data values ​​indicates that the data value equal to the bit position (numerical index) is in the set of selected data values, i.e., in the input data word, by the presence of a '1' in the bit position. For example, a '1' in bit position b255 indicates that data value 255 is present in the input data word, a '1' in bit position b252 indicates that data value 252 is present in the input data word, and so on. Similarly, the bit vector of the selected data values ​​indicates that the data value equal to the bit position (numerical index) is not in the set of selected data values ​​by the presence of a '0' in the bit position. For example, a '0' in bit position b254 indicates that data value 254 is not in the set of selected data values, a '0' in bit position b253 indicates that data value 253 is not in the set of selected data values, a '0' in bit position b3 indicates that data value 3 is not in the set of selected data values, and so on.

[0043] In this example ( Figure 5 ), in forming the output data word, the data formatter 410 ( Figure 4 ) can first determine a code representing an unused or unselected data value. To determine the code, the data formatter 410 can determine which bit positions in the bit vector of the selected data value have a bit value of '0'. Figure 5 , the data formatter 410 may determine that bit positions b254, b253, b3 (and other bits that may not be shown) in the bit vector of the selected data value have a bit value of '0', and therefore data values ​​254, 253, and 3 (and other data values ​​that may not be shown) are not in the set of selected data values. In this example, the data formatter 410 may select any one of these unused data values ​​(i.e., data values ​​that are not in the set of selected data values) to serve as or represent the code. In the illustrated example, the data formatter 410 selects the unused data value 3. However, the data formatter 410 may alternatively select the unused data values ​​253 or 254. A rule for selecting an unused data value in an example where there are multiple unused data values ​​may be implemented, such as selecting a data value corresponding to a bit position that is closest to the least significant bit position.

[0044] In this example ( Figure 5), the data formatter 410 may then place a code (3 in this example) into each unselected data bus byte position when forming the output data word. Thus, in this example, the data formatter 410 may place the byte value 3 into data bus byte positions B253 and Bn, as indicated by arrows 512 and 514, respectively. The data formatter 410 may similarly place the byte value 3 into any other unselected data bus byte position (not shown for clarity). Although arrow indicators are not shown for clarity, the data formatter 410 may also place each selected data value (i.e., each data value present in the input word) into the same data bus byte position in the output data word as that data value present in the input data word. Thus, the data formatter 410 may place the data value 252 into data bus byte position B255 of the output data word, the data value 0 into data bus byte position B254 of the output data word, the data value 2 into data bus byte position B0 of the output data word, and so on. Data formatter 410 may similarly place other data values ​​(not shown for clarity) that may be present in the input data word into corresponding data bus byte positions in the output data word. Data formatter 410 may use the input BE vector to determine which data bus byte positions are selected and which data bus byte positions are not selected.

[0045] like Figure 6 As shown, system 600 may be configured to receive data words via a data bus (not shown). The data words may have the same Figure 5 The system 600 may be a receiver device 104 ( Figure 1 ). System 600 may include processor logic components (eg, programmed by software or firmware), discrete circuits (eg, finite state machines, combinational logic, etc.), or any combination thereof.

[0046] The system 600 may include a comparison logic unit 601. The comparison logic unit 601 may include a plurality of bit group (e.g., byte) comparators 602, the number of which is equal to the number of data bus bit group (e.g., byte) positions. For example, a system 600 having 256 data bus byte positions may include 256 comparators 602 (for clarity, Figure 6 Not all comparators are shown in FIG. 6 ). Each comparator 602 can be configured to compare a data value received in one of the data bus byte positions with a code. The system 600 can be configured to reconstruct a BE vector. That is, the system 600 can form a similar system as described above with reference to FIG. Figure 5 Once the system 600 forms the reconstructed BE vector, the system 600 or the receiver device 104 ( Figure 1 ) can then use the reconstructed BE vector to reconstruct or determine the data word in a conventional manner.

[0047] If the output of one of the comparators 602 indicates that the received data value matches the code, the system 600 places a bit value of '0' into the corresponding bit position in the reconstructed BE vector. If the output of one of the comparators 602 indicates that the received data value does not match the code, the system 600 places a bit value of '1' into the corresponding bit position in the reconstructed BE vector. Therefore, the comparator 602 (or other comparison logic components in other embodiments) enables the system 600 to determine each unselected data bus byte position indicated by the received data value that matches the code. Similarly, the comparator 602 enables the system 600 to determine each selected data bus byte position indicated by the received data value that does not match the code.

[0048] The system 600 or another portion of the receiver device 104, such as a processor or other processing logic component (not shown), may then reconstruct or determine the data word. For example, the receiver device 104 may ignore or treat as a logical "don't care" any data value received in one of the data bus byte positions that corresponds to a bit value of '0' in the corresponding bit position in the reconstructed BE vector. In other words, the reconstructed BE vector allows the receiver device 104 to determine which data bus byte positions are enabled, and therefore which received data values ​​are valid.

[0049] In which the received data value is the above reference Figure 5In the example of the data value of the output data word described, the reconstruction of the data word by the receiver device 104 may include the following. Since the reconstruction byte enable vector indicates that the received data value 252 in the data bus byte position B255 does not match the code (3 in this example), the received data value 252 is placed in the corresponding byte position in the reconstructed data word, as indicated by arrow 604. Similarly, since the reconstruction byte enable vector indicates that the received data value 0 in the data bus byte position B254 does not match the code, the received data value 0 is placed in the corresponding byte position in the reconstructed data word, as indicated by arrow 606. However, since the reconstruction byte enable vector indicates that the received data value 3 in the data bus byte position B253 matches the code, the byte position B253 in the reconstructed data word is invalid. Similarly, since the reconstruction byte enable vector indicates that the received data value 3 in the data bus byte position Bn matches the code, the corresponding byte position Bn in the reconstructed data word is invalid. Since the received data value 2 in data bus byte position B0 does not match the code, the received data value 2 is placed into the corresponding byte position in the reconstructed data word, as indicated by arrow 608 .

[0050] Once the receiver device 104 has reconstructed or determined the data word, the receiver device 104 may process all valid received data values ​​(and not process any invalid received data values) in a conventional manner. In examples where the receiver device 104 is a memory device, the memory device may store valid received data values ​​(and not store any invalid received data values). Alternatively or additionally, in some examples, the receiver device 104 may place zeros into invalid or unselected byte positions prior to such processing.

[0051] exist Figure 7 , a method 700 for receiving data via a data bus is illustrated. A receiver device may be configured to control some or all of the method 700. For example, in an embodiment in which the receiver device includes a processor, the processor may be configured by software or firmware to control some or all of the method 700. In addition, a receiver device or a portion thereof (e.g., a processor) may be an example of a component for performing the functions set forth in the method 700. The method 700 may include the following features, functions, actions, etc. indicated by blocks 702 to 712, which may be performed or otherwise occur in any order not inconsistent with the description herein. Blocks 702 to 712 are described in an order that is helpful for understanding the exemplary method 700, but the method for receiving data via a data bus is not limited to this order.

[0052] As indicated at block 702, method 700 may include the receiver device receiving the selected data value via a data bus (data bit lane) and receiving the code via a code bit lane. As indicated at block 704, method 700 may include the receiver device comparing the code to each data value received in each data bus byte position (or other data bit group). As indicated at block 706, method 700 may also include the receiver device determining or identifying each data bus byte position having a data value that matches the code (i.e., identifying the selected data bus byte position). Similarly, as indicated at block 708, method 700 may include the receiver device determining or identifying each data bus byte position having a data value that does not match the code (i.e., identifying the unselected data bus byte positions).

[0053] As indicated at block 710, method 700 may further include the receiver device reconstructing the byte enable vector. As indicated at block 712, method 700 may still further include the receiver device reconstructing the data word using the reconstructed byte enable vector and the received data value. In some examples, reconstructing the data word may include placing zeros into invalid or unselected byte positions.

[0054] like Figure 8 As shown, system 800 may include a transmitter device 802 and a receiver device 804 on a SoC 806. System 800 may be similar to system 100 ( Figure 1 ), and may include N data bit lanes 808 and M code bit lanes 810 interconnecting the transmitter device 802 and the receiver device 804. In addition, the system 800 may include a Full_Payload signal path 812 interconnecting the transmitter device 802 and the receiver device 804. The transmitter device may assert the Full_Payload signal on the signal path 812 to indicate that all data bit groups are selected. For example, in an embodiment in which there are 2048 data bit lanes 808 (i.e., N=2048) and each of the data bit groups may be selected to be a byte, the transmitter device may assert the Full_Payload signal to indicate that all 256 data bus byte positions are selected. In response to detecting the assertion of the Full_Payload signal, the receiver device 804 may abandon a portion of the above-described method for reconstructing the data word and may instead treat the data value received in each data bus byte position as valid. In other words, when the receiver device 804 determines that the Full_Payload signal is asserted, the receiver device 804 may process all data values ​​received in all data bus byte positions.

[0055] Additionally, the system 800 can include a Has_Payload signal path 814 interconnecting the transmitter device 802 and the receiver device 804. The transmitter device 802 can de-assert the Has_Payload signal on the signal path 814 when all data bus byte positions (or other data bit groups) are not selected, and can assert the Has_Payload signal when at least one data bus byte position (or other data bit group) is selected. De-assertion of the Has_Payload signal can indicate to the receiver device 804 that reception of data is not desired.

[0056] Fig. 9 An example of a PCD 900 such as a mobile phone or smart phone is illustrated in which exemplary embodiments of systems, methods, computer-readable media, and other examples of communicating data via a data bus may be provided. For clarity, some data buses, interconnects, signals, etc. are not shown in FIG. Fig. 9 Although PCD 900 is shown as an example, other embodiments of systems, methods, computer-readable media, and other examples of communicating data over a data bus may be provided in other types of computing devices or systems.

[0057] PCD 900 may include SoC 902. SoC 902 may include a central processing unit ("CPU") 904, a neural processing unit ("NPU") 905, a graphics processing unit ("GPU") 906, a digital signal processor ("DSP") 907, an analog signal processor 908, a modem or transceiver subsystem 954, or other processors. CPU 904 may include one or more CPU cores, such as a first CPU core 904A, a second CPU core 904B, and so on to an Nth CPU core 904N.

[0058] The display controller 910 and the touch screen controller 912 may be coupled to the CPU 904. A touch screen display 914 external to the SoC 902 may be coupled to the display controller 910 and the touch screen controller 912. The PCD 900 may also include a video decoder 916 coupled to the CPU 904. A video amplifier 918 may be coupled to the video decoder 916 and the touch screen display 914. A video port 920 may be coupled to the video amplifier 918. A universal serial bus (“USB”) controller 922 may also be coupled to the CPU 904, and a USB port 924 may be coupled to the USB controller 922. A subscriber identity module (“SIM”) card 926 may also be coupled to the CPU 904.

[0059] One or more memories may be coupled to the CPU 904. The one or more memories may include both volatile memory and non-volatile memory. Examples of volatile memory include static random access memory ("SRAM") 928 and dynamic random access memory ("DRAM") 930 and 931. Such memory may be located external to the SoC 902 (such as DRAM 930), or internal to the SoC 902 (such as DRAM 931). A DRAM controller 932 coupled to the CPU 904 may control writing data to and reading data from the DRAMs 930 and 931.

[0060] Although not shown for clarity, the data bus coupling one or more of the memories 928, 930, 931, etc. and the CPU 904 or other processors (e.g., NPU 905, GPU 906, DSP 907, etc.) may be the above-mentioned data bus 108 ( Figure 1 ) or data bus 808 ( Figure 8 ). Any such processor or subsystem may be an example of a transmitter device 102 ( Figure 1 ) or transmitter device 802 ( Figure 8 ), the receiver device 104 ( Figure 1 ) or receiver device 804 ( Figure 8 ), or a combination of such a transmitter device and a receiver device (ie, a transceiver device). Any of the memories 928, 930, 931, etc. may be a receiver device 104 ( Figure 1 ) or receiver device 804 ( Figure 8 ) example, wherein the memory has a configurable width. Thus, such a processor or subsystem may have a configuration as described above with reference to Figures 3 to 7 For clarity, Fig. 9 A data bus or other interconnect (e.g., a NoC) coupling or interconnecting such transmitter devices and receiver devices is not shown in the SoC 902. However, as will be appreciated by one of ordinary skill in the art, the SoC 902 may include any number of such data buses or other interconnects coupling or interconnecting various types of transmitter devices and receiver devices on the SoC 902. Other data buses may couple the SoC 902 with external devices, such as an external DRAM 930.

[0061] A stereo audio codec 934 may be coupled to the analog signal processor 908. Further, an audio amplifier 936 may be coupled to the stereo audio codec 934. A first stereo speaker 938 and a second stereo speaker 940 may be coupled to the audio amplifier 936, respectively. In addition, a microphone amplifier 942 may be coupled to the stereo audio codec 934, and a microphone 944 may be coupled to the microphone amplifier 942. A frequency modulation ("FM") radio tuner 946 may be coupled to the stereo audio codec 934. An FM antenna 948 may be coupled to the FM radio tuner 946. Further, a stereo headset 950 may be coupled to the stereo audio codec 934. Other devices that may be coupled to the CPU 904 include one or more digital (e.g., CCD or CMOS) cameras 952.

[0062] A modem or RF transceiver 954 may be coupled to the analog signal processor 908 and the CPU 904. An RF switch 956 may be coupled to the RF transceiver 954 and the RF antenna 958. In addition, a keypad 960, a mono headset 962 with a microphone, and a vibrator device 964 may be coupled to the analog signal processor 908.

[0063] SoC 902 may have one or more internal or on-chip thermal sensors 970A and may be coupled to one or more external or off-chip thermal sensors 970B. Analog-to-digital converter controller 972 may convert the voltage drop generated by thermal sensors 970A and 970B into a digital signal. Power supply 974 and PMIC 976 may provide power to SoC 902.

[0064] The firmware or software may be stored in any of the above memories, such as DRAM 930 or 931, SRAM 928, etc., or may be stored in local memory directly accessible by the processor hardware on which the software or firmware is executed. The execution of such firmware or software may control aspects of any of the above methods or configure aspects of any of the above systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium" as that term is understood in the patent dictionary.

[0065] The above solution can reduce the number of data bit lanes on the data bus. Reducing the number of data bit lanes can have an impact on reducing the required area or occupied area of ​​the data bus on the SoC or other system, improving the timing of the data bus, reducing power consumption, etc.

[0066] Specific implementation examples are described in the following numbered clauses:

[0067] 1. A method for communicating data via a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the method comprising:

[0068] determining, by a transmitter device, a set of selected data values ​​to be transmitted over the data bus;

[0069] determining, by the transmitter device, selected data bit groups and unselected data bit groups;

[0070] determining, by the transmitter device, a code representing an unselected data value not included in the set of selected data values;

[0071] transmitting the selected data values ​​in the selected data bit groups and the codes in the unselected data bit groups to a receiver device via the data bit channel; and

[0072] The code is transmitted to the receiver device independently of the data bit lanes.

[0073] 2. A method according to clause 1, wherein each data bit group consists of eight bits.

[0074] 3. The method of clause 1 or 2, wherein transmitting the code comprises transmitting the code via a plurality of code bit channels independent of the data bit channels.

[0075] 4. The method according to any one of clauses 1 to 3, further comprising:

[0076] determining, by the transmitter device, whether all data bit groups are selected; and

[0077] An indication that all groups of data bits are selected is transmitted to the receiver device independently of the data bit lanes.

[0078] 5. The method according to any one of clauses 1 to 4, further comprising:

[0079] determining, by the transmitter device, whether no data bit group is selected; and

[0080] An indication that no data bit groups were selected is transmitted to the receiver device independently of the data bit lanes.

[0081] 6. The method according to any one of clauses 1 to 5, further comprising:

[0082] receiving a data value via the data bit channel;

[0083] receiving the code independently of the data bit channel;

[0084] comparing, by the receiver device, the code with each data value in each data bit group received via the data bit channel;

[0085] determining, by the receiver device, each group of data bits having a data value that matches the code in one of the selected groups of data bits;

[0086] determining, by the receiver device, each data bit group having a data value that does not match the code in one of the unselected data bit groups; and processing the data values ​​in the selected data bit groups without processing the data values ​​in the unselected data bit groups.

[0087] 7. A method according to any one of clauses 1 to 6, wherein transmitting the selected data value to the receiver device through the data bit channel, transmitting the code to the receiver device, receiving the selected data value through the data bit channel, and receiving the code are all performed in a system on a chip ("SoC").

[0088] 8. A system for communicating data via a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising:

[0089] an encoder configured to determine a selected set of data values ​​to be transmitted over the data bus in a selected group of data bits; and

[0090] A data word formatter configured to: determine selected data bit groups and unselected data bit groups; determine codes representing unselected data values ​​that are not included in the set of selected data values; provide a data word to a receiver device through the data bit lane, the data word having the selected data values ​​in the selected data bit groups and the codes in the unselected data bit groups; and provide the codes to the receiver device through a plurality of code bit lanes independent of the data bit lanes.

[0091] 9. The system of clause 8, wherein the encoder comprises a binary to unary encoder configured to determine a bit vector having a plurality of bit positions corresponding to the selected data value.

[0092] 10. A system according to clause 8 or 9, wherein each data bit group consists of eight bits.

[0093] 11. A system according to any of clauses 8 to 10, wherein the data word formatter is further configured to determine whether all data bit groups are selected and to provide a signal to the receiver device via a signal channel indicating that all data bit groups are selected.

[0094] 12. A system according to any of clauses 8 to 11, wherein the data word formatter is further configured to determine whether no data bit group is selected and to provide a signal to the receiver device via a signal channel indicating that no data bit group is selected.

[0095] 13. The system of any of clauses 8 to 12, further comprising a receiver device coupled to the plurality of data bit lanes and the plurality of code bit lanes.

[0096] 14. A system according to any of clauses 8 to 13, wherein the receiver device comprises a memory device having a configurable data width.

[0097] 15. A system according to any of clauses 8 to 14, wherein the receiver device is configured to:

[0098] receiving a data value via the data bit channel;

[0099] receiving the code through the code bit channel;

[0100] comparing the code to each data value in each group of data bits received via the data bus;

[0101] determining each group of data bits having a data value matching the code in one of the selected groups of data bits; and

[0102] Each data bit group having a data value that does not match the code in one of the unselected data bit groups is determined.

[0103] 16. The system of any of clauses 8 to 15, wherein the data bus and the system for data communications are included in a system on a chip ("SoC").

[0104] 17. A system for communicating data via a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising:

[0105] means for determining, by a transmitter device, a set of selected data values ​​to be transmitted over said data bus;

[0106] means for determining, by the transmitter device, selected groups of data bits and unselected groups of data bits;

[0107] means for determining, by the transmitter device, a code representing an unselected data value not included in the set of selected data values;

[0108] means for transmitting selected data values ​​in selected groups of data bits and said codes in unselected groups of data bits to a receiver device via said data bit channel; and

[0109] Means for transmitting the code to the receiver device independently of the data bit lanes.

[0110] 18. The system of clause 17, wherein each data bit group consists of eight bits.

[0111] 19. The system of clause 17 or 18, wherein the means for transmitting the code comprises means for transmitting the code via a plurality of code bit lanes independent of the data bit lanes.

[0112] 20. The system of any of clauses 17 to 19, wherein the receiver device comprises a memory device having a configurable width.

[0113] 21. A system according to any one of clauses 17 to 20, further comprising:

[0114] means for determining, by the transmitter device, whether all data bit groups are selected; and

[0115] Means for transmitting, independently of the data bit lanes, to the receiver device an indication that all groups of data bits are selected.

[0116] 22. A system according to any one of clauses 17 to 21, further comprising:

[0117] means for determining, by the transmitter device, whether no data bit group is selected; and

[0118] Means for transmitting, independently of the data bit lanes, to the receiver device an indication that no groups of data bits were selected.

[0119] 23. A system according to any one of clauses 17 to 22, further comprising:

[0120] means for receiving a data value via said data bit channel;

[0121] means for receiving said code independently of said data bit channel;

[0122] means for comparing, by the receiver device, the code with each data value in each data bit group received via the data bit channel;

[0123] means for determining, by the receiver device, each group of data bits having a data value matching the code in one of the selected groups of data bits;

[0124] means for determining, by the receiver device, each group of data bits having a data value that does not match the code in one of the unselected groups of data bits; and

[0125] Means for processing data values ​​in the selected group of data bits and not processing data values ​​in the unselected group of data bits.

[0126] 24. A computer-readable medium for communicating data over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the computer-readable medium comprising a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form, the instructions, when executed by a processing system of a computing device, configuring the processing system to control:

[0127] determining a set of selected data values ​​to be transmitted via the data bus;

[0128] determining selected data bit groups and unselected data bit groups;

[0129] determining codes representing unselected data values ​​that are not included in the set of selected data values;

[0130] transmitting the selected data values ​​in the selected data bit groups and the codes in the unselected data bit groups to a receiver device via the data bit channel; and

[0131] The code is transmitted to the receiver device independently of the data bit lanes.

[0132] 25. The computer-readable medium of clause 24, wherein each data bit group consists of eight bits.

[0133] 26. The computer-readable medium of clause 24 or 25, wherein transmitting the code comprises transmitting the code over a plurality of code bit lanes independent of the data bit lanes.

[0134] 27. The computer-readable medium of any one of clauses 24 to 26, further comprising instructions that configure the processing system to control:

[0135] determining whether all data bit groups are selected; and

[0136] An indication that all groups of data bits are selected is transmitted to the receiver device independently of the data bit lanes.

[0137] 28. The computer-readable medium of any one of clauses 24 to 27, further comprising instructions that configure the processing system to control:

[0138] determining, by the transmitter device, whether no data bit group is selected; and

[0139] An indication that no data bit groups were selected is transmitted to the receiver device independently of the data bit lanes.

[0140] 29. A method for communicating data via a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the method comprising:

[0141] receiving, by a receiver device, a code independently of said data bit channel;

[0142] receiving, by the receiver device, a data value via the data bit lane of the data bus;

[0143] comparing, by the receiver device, the code to each data value in each group of data bits received via the data bus;

[0144] determining, by the receiver device, each group of data bits having a data value matching the code;

[0145] determining, by the receiver device, each group of data bits having a data value that does not match the code; and

[0146] An indication of a selected group of data bits is provided based on a determination of a group of data bits having data values ​​that match the code, and an indication of an unselected group of data bits is provided based on a determination of a group of data bits having data values ​​that do not match the code.

[0147] 30. The method of clause 29, further comprising processing data values ​​in the selected group of data bits and not processing data values ​​in the unselected group of data bits.

[0148] 31. A system for communicating data via a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising:

[0149] a comparison logic component configured to: receive a selected data value through the data bit lane; receive a code independently of the data bit lane; compare the code with each data value in each data bit group; determine each data bit group having a data value that matches the code in one of the selected data bit groups; and determine each data bit group having a data value that does not match the code in one of the unselected data bit groups; and

[0150] Processing logic configured to provide an indication of selected groups of data bits based on a determination of groups of data bits having data values ​​that match the code, and to provide an indication of unselected groups of data bits based on a determination of groups of data bits having data values ​​that do not match the code.

[0151] 32. The system of clause 31, wherein the processing logic component is configured to process data values ​​in the selected group of data bits and not process data values ​​in the unselected group of data bits.

[0152] Alternative embodiments will become apparent to those skilled in the art to which the invention pertains.Thus, while selected aspects have been illustrated and described in detail, it should be appreciated that various substitutions and changes may be made therein.

Claims

1. A method for communicating data via a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the method comprising: determining, by an encoder of a transmitter device, a set of selected data values ​​to be transmitted over the data bus, the encoder receiving a byte enable vector and an input data word, and the encoder using the byte enable vector to convert the input data word into a bit vector having a plurality of bit positions corresponding to the set of selected data values ​​to be transmitted over the data bus; determining, by a data word formatter of the transmitter device, the selected data bit groups and the unselected data bit groups, the data word formatter receiving the bit vector from the encoder; determining, by the data word formatter of the transmitter device from the bit vector, codes representing unselected data values ​​not included in the set of selected data values, the data word formatter generating an output data word; transmitting the output data word from the data word formatter to a receiver device through the data bit channel, the output data word having the selected data value in the selected data bit group and the code in the unselected data bit group; as well as The codes are communicated from the data word formatter to the receiver device using a code bit lane independently of the data bit lane.

2. The method of claim 1, wherein each data bit group consists of eight bits.

3. The method according to claim 1, further comprising: determining, by the transmitter device, whether all data bit groups are selected; as well as An indication that all groups of data bits are selected is transmitted to the receiver device independently of the data bit lanes.

4. The method according to claim 1, further comprising: determining, by the transmitter device, whether no data bit group is selected; as well as An indication that no data bit groups were selected is transmitted to the receiver device independently of the data bit lanes.

5. The method according to claim 1, further comprising: receiving the output data word having a data value via the data bit channel; receiving the code on the code bit channel independently from the data bit channel; comparing, by the receiver device, the code with each data value in each data bit group received via the data bit channel; determining, by the receiver device, each group of data bits having a data value that does not match the code in one of the selected groups of data bits; determining, by the receiver device, each group of data bits having a data value matching the code in one of the unselected groups of data bits; as well as Data values ​​in the selected data bit groups are processed, while data values ​​in the unselected data bit groups are not processed.

6. The method of claim 5, wherein transmitting the selected data value to the receiver device via the data bit channel, transmitting the code to the receiver device, receiving the selected data value via the data bit channel, and receiving the code are all performed in a system on a chip ("SoC").

7. A system for communicating data via a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising: an encoder receiving a byte enable vector and an input data word, and configured to determine a set of selected data values ​​to be transmitted over the data bus in a selected group of data bits by converting the input data word using the byte enable vector into a bit vector having a plurality of bit positions corresponding to the set of selected data values; and a data word formatter receiving the bit vector from the encoder and configured to: determine selected groups of data bits and unselected groups of data bits; determine a code from the bit vector, the code representing an unselected data value that is not included in the set of selected data values; providing an output data word to a receiver device via the data bit channel, the output data word having the selected data values ​​in the selected group of data bits and the codes in the unselected group of data bits; and providing the codes to the receiver device via a plurality of code bit channels independent of the data bit channels.

8. The system of claim 7, wherein each data bit group consists of eight bits.

9. The system of claim 7, wherein the data word formatter is further configured to determine whether all data bit groups are selected and provide a signal indicating that all data bit groups are selected to the receiver device via a signal channel.

10. The system of claim 7, wherein the data word formatter is further configured to determine if no data bit group is selected and provide a signal indicating no data bit group is selected to the receiver device via a signal path.

11. The system of claim 7, further comprising a receiver device coupled to the plurality of data bit channels and the plurality of code bit channels.

12. The system of claim 11, wherein the receiver device comprises a memory device having a configurable data width.

13. The system of claim 11, wherein the receiver device is configured to: receiving the output data word having a data value via the data bit channel; receiving the code through the code bit channel; comparing the code to each data value in each group of data bits received via the data bus; determining each data bit group having a data value that does not match the code in one of the selected data bit groups; as well as Each data bit group having a data value matching the code is determined to be in one of the unselected data bit groups.

14. The system of claim 7, wherein the data bus and the system for data communications are included in a system on a chip ("SoC").

15. A computer-readable medium for communicating data over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the computer-readable medium comprising a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form, the instructions, when executed by a processing system of a computing device, configuring the processing system to control: determining, with an encoder, a set of selected data values ​​to be transmitted over the data bus, the encoder receiving a byte enable vector and an input data word, and the encoder using the byte enable vector to convert the input data word into a bit vector having a plurality of bit positions corresponding to the set of selected data values; determining selected groups of data bits and unselected groups of data bits using a data word formatter that receives the bit vector from the encoder; determining, with the data word formatter, a code from the bit vector, the code representing an unselected data value not included in the set of selected data values, the data word formatter generating an output data word; transmitting the output data word from the data word formatter to a receiver device through the data bit channel, the output data word having the selected data value in the selected data bit group and the code in the unselected data bit group; as well as The codes are communicated from the data word formatter to the receiver device using a code bit lane independently of the data bit lane.

16. The computer-readable medium of claim 15, wherein each data bit group consists of eight bits.

17. The computer-readable medium of claim 15, further comprising instructions that configure the processing system to control: determining whether all data bit groups are selected; and An indication that all groups of data bits are selected is transmitted to the receiver device independently of the data bit lanes.

18. The computer-readable medium of claim 15, further comprising instructions that configure the processing system to control: determining, by the transmitter device, whether no data bit group is selected; and An indication that no data bit groups were selected is transmitted to the receiver device independently of the data bit lanes.

19. A method for communicating data via a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the method comprising: receiving, by a receiver device, a code via a code bit channel independently of said data bit channel; receiving, by the receiver device, a first data word having a data value via the data bit lane of the data bus; comparing, by a comparator in the receiver device, the code with the first data word having each data value in each data bit group received via the data bus; determining, by the receiver device, each group of data bits having a data value matching the code; determining, by the receiver device, each group of data bits having a data value that does not match the code; generating, with the receiver device, a byte enable vector from the first data word and the code, the byte enable vector comprising indications of selected groups of data bits based on determinations of groups of data bits having data values ​​that do not match the code and indications of unselected groups of data bits based on determinations of groups of data bits having data values ​​that match the code; as well as A second data word is reconstructed based on the byte enable vector.

20. The method of claim 19, further comprising processing data values ​​in the selected group of data bits and not processing data values ​​in the unselected group of data bits.

21. A system for communicating data via a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising: a comparison logic component configured to: receive a first data word having a selected data value through the data bit channel; receiving a code via a code bit channel independently of the data bit channel; comparing the code to each data value in each data bit group; and determining each data bit group having a data value that matches the code; and determining each group of data bits having a data value that does not match the code; a processing logic component configured to: generate a byte enable vector from the code and the first data word, the byte enable vector including an indication of selected groups of data bits based on a determination of groups of data bits having data values ​​that do not match the code, and an indication of unselected groups of data bits based on a determination of groups of data bits having data values ​​that match the code; and A processing logic component is configured to reconstruct a second data word based on the byte enable vector.

22. The system of claim 21, wherein the processing logic component is configured to process data values ​​in the selected group of data bits and not process data values ​​in the unselected group of data bits.

Images