Test structures, methods, and wafers for semiconductor structures

Abstract

The application discloses a test structure, a method and a wafer of a semiconductor structure, and belongs to the technical field of semiconductors. The gates of each transistor to be tested are coupled to a gating circuit in the test structure, and a selection circuit in the test structure controls the gating circuit to apply a third electric signal or a second electric signal on a second test pin to each transistor to be tested according to a first electric signal on a plurality of first test pins, so that a certain transistor is tested by the second electric signal, the gates of each transistor to be tested share the same second test pin, the number of test pins occupied by the gates of the transistors to be tested is reduced, the utilization rate of test pins in the test structure is increased, and the test structure can support more transistor tests.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a test structure of a semiconductor structure, a method and a wafer. BACKGROUND

[0002] At present, before a wafer is shipped, a mismatch test is performed on transistors in the wafer by using a test structure, wherein the test structure includes a plurality of test pins. In the mismatch test, first, a plurality of transistors to be tested in the wafer are copied to the test structure, the source of each transistor is coupled to the same test pin in the test structure, the drain of each transistor is coupled to the same test pin in the test structure, the substrate (also referred to as a substrate) of each transistor is coupled to the same test pin in the test structure, and the gate of each transistor is coupled to different test pins respectively. The mismatch test is performed on each transistor by applying a voltage to the test pin coupled to the source, the drain, the substrate and the gate of each transistor.

[0003] Since the gate of each transistor to be tested occupies one test pin, the utilization rate of the test pins in the test structure is low, and the number of test pins in the test structure is limited, so that the test structure cannot support more transistor tests. SUMMARY

[0004] Embodiments of the present application provide a test structure of a semiconductor structure, a method and a wafer, and the test structure can support a large number of transistor tests. The technical solutions are as follows:

[0005] In a first aspect, a test structure of a semiconductor structure is provided, and the test structure includes a plurality of first test pins 1, a second test pin 2, an addressing circuit 3 and a gating circuit 4.

[0006] The plurality of first test pins 1 are coupled to the addressing circuit 3, and the plurality of first test pins 1 are used to access a first electrical signal.

[0007] The second test pin 2 and the addressing circuit 3 are coupled to the gating circuit 4, the gating circuit 4 is coupled to the gate of a plurality of transistors 5 to be tested, the second test pin 2 is used to access a second electrical signal, and the second electrical signal is used to turn on a first transistor in the plurality of transistors 5.

[0008] The addressing circuit 3 is configured to:

[0009] According to the first electrical signal on the plurality of first test pins 1, the second electrical signal is applied to the gate of the first transistor by the gating circuit 4, and the third electrical signal is applied to the gate of a second transistor in the plurality of transistors by the gating circuit 4, the third electrical signal is used to turn off the second transistor, and the second transistor is a transistor in the plurality of transistors 5 except the first transistor.

[0010] In a possible implementation, the addressing circuit 3 comprises an inverting sub-circuit 31 and a plurality of addressing sub-circuits 32, the plurality of first test pins 1 are coupled to the inverting sub-circuit 31, the inverting sub-circuit 31 is coupled to the plurality of addressing sub-circuits 32, the plurality of addressing sub-circuits 32 are coupled to the gating circuit 4, and each addressing sub-circuit 32 corresponds to one transistor 5.

[0011] The inverting sub-circuit 31 is configured to perform an inverting logic operation on the first electrical signals on the plurality of first test pins 1 to obtain a plurality of fourth electrical signals, and to apply a plurality of signal groups composed of the plurality of fourth electrical signals and the plurality of first electrical signals to the plurality of addressing sub-circuits 32.

[0012] Each addressing sub-circuit 32 is configured to perform signal processing on one applied signal group to obtain a fifth electrical signal, and to apply the fifth electrical signal to the gating circuit 4, where the fifth electrical signal is used to control the gating circuit 4 to apply the second electrical signal or the third electrical signal to the corresponding transistor 5.

[0013] In a possible implementation, the gating circuit 4 comprises a plurality of switching sub-circuits 41, the second test pins 2 are coupled to the plurality of switching sub-circuits 41, and the plurality of addressing sub-circuits 32 are respectively coupled to the plurality of switching sub-circuits 41.

[0014] Each switching sub-circuit 41 is configured to apply the second electrical signal or the third electrical signal to the gate of the coupled transistor 5 according to the fifth signal applied by the coupled addressing sub-circuit 32.

[0015] In a possible implementation, the first test pins 1 are n in number, the transistors 5 are 2n in number, and n is an integer greater than 1.

[0016] In a possible implementation, the plurality of transistors 5 are arranged symmetrically left and right along a first symmetry axis.

[0017] The devices in the addressing circuit 3 are arranged symmetrically left and right along the first symmetry axis.

[0018] The devices in the gating circuit 4 are arranged symmetrically left and right along the first symmetry axis.

[0019] In a possible implementation, the plurality of transistors 5 are arranged in rows or columns.

[0020] In a possible implementation, the plurality of transistors 5 form a plurality of test pairs, and the distances between the transistors 5 of different test pairs are the same.

[0021] In a possible implementation, the transistors 5 of the same test pair in the plurality of test pairs are of the same type.

[0022] In a possible implementation, the addressing circuit 3 is a decoder.

[0023] In a possible implementation, the test structure is located on a scribe lane of a wafer, and the transistor 5 is a transistor in the wafer.

[0024] In a possible implementation, the test structure is a mismatch test structure, and the first electrical signals inputted on the plurality of first test pins 1 are used to select the first transistor for mismatch test.

[0025] In a possible implementation, the test structure further comprises at least one of a third test pin 6, a fourth test pin 7, a fifth test pin 8 and a sixth test pin 9, the third test pin 6 is coupled to the addressing circuit 3 and the gating circuit 4, and the third test pin 6 is used to input a power supply electrical signal;

[0026] The fourth test pin 7 is coupled to the addressing circuit 3 and the gating circuit 4, and the fourth test pin 7 is used to input a ground electrical signal;

[0027] The fourth test pin 7, the fifth test pin 8 and the sixth test pin 9 are respectively coupled to the source, the drain and the substrate of the plurality of transistors 5.

[0028] In a second aspect, a test method of a semiconductor structure is provided, the test method is applied to a test structure of the semiconductor structure, the test structure comprises a second test pin, a gating circuit and a plurality of first test pins, the second test pin is coupled to the gating circuit, and the gating circuit is coupled to the gate of a plurality of transistors to be tested; the test method comprises:

[0029] Applying first electrical signals to the plurality of first test pins and applying second electrical signals to the second test pin, the second electrical signals being used to turn on a first transistor to be tested in the plurality of transistors:

[0030] Controlling the gating circuit to apply the second electrical signals to the gate of the first transistor and controlling the gating circuit to apply third electrical signals to the gate of a second transistor according to the first electrical signals on the plurality of first test pins, the second transistor being a transistor other than the first transistor in the plurality of transistors, and the third electrical signals being used to turn off the second transistor.

[0031] In a possible implementation, controlling the gating circuit to apply the second electrical signals to the gate of the first transistor and controlling the gating circuit to apply the third electrical signals to the gate of the second transistor according to the first electrical signals on the plurality of first test pins comprises:

[0032] Performing an inverse logic operation on the first electrical signals on the plurality of first test pins to obtain a plurality of fourth electrical signals, the plurality of fourth electrical signals and the plurality of first electrical signals forming a plurality of signal groups;

[0033] The signal processing is performed on the plurality of signal groups respectively to obtain a plurality of fifth electric signals, and the fifth signals are applied to the gating circuit. The gating circuit applies the second electric signal or the third electric signal to the gate of the transistor according to the fifth signals.

[0034] In a third aspect, a wafer is provided, which includes a test region and a scribe lane. The scribe lane is provided with a test structure of the semiconductor structure according to the first aspect or any possible implementation of the first aspect, which is used to test a plurality of transistors in the test region.

[0035] The technical solution provided by the embodiments of the present application is that the gates of the transistors to be tested are all coupled to the gating circuit in the test structure, and the address circuit in the test structure controls the gating circuit to apply the third electric signal or the second electric signal on the second test pin to each transistor to be tested according to the first electric signals on the plurality of first test pins, so as to test a certain transistor by the second electric signal. Therefore, the gates of each transistor to be tested share the same second test pin, the number of test pins occupied by the gates of the transistors to be tested is reduced, the utilization rate of the test pins in the test structure is increased, and the test structure can support more transistor tests. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a schematic diagram of a test structure of a semiconductor structure according to an example embodiment;

[0037] Figure 2 is a schematic diagram of a structure of a chip according to an example embodiment;

[0038] Figure 3 is a schematic diagram of a structure of an address circuit according to an example embodiment;

[0039] Figure 4 is a schematic diagram of a structure of a gating circuit according to an example embodiment;

[0040] Figure 5 is a schematic diagram of a structure of a switch sub-circuit according to an example embodiment;

[0041] Figure 6 is a layout schematic diagram of a test structure according to an example embodiment;

[0042] Figure 7 is another layout schematic diagram of a test structure according to an example embodiment;

[0043] Figure 8 is a flowchart of a test method of a semiconductor structure according to an example embodiment. DETAILED DESCRIPTION

[0044] For the purpose of making the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0045] The terms "first", "second", and the like are used herein to distinguish between elements having substantially similar or related functions for the purposes of the present application. It is to be understood that there is no logic or chronological dependency between the terms "first", "second", "n-th", and that the terms do not limit the number or order of execution. It is also to be understood that, although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms.

[0046] These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first element can be called a second element, and similarly, a second element can also be called a first element. The first element and the second element can both be elements, and in some cases, can be separate and distinct elements.

[0047] At least one refers to one or more than one, for example, at least one element can be one element, two elements, three elements, or any integer greater than or equal to one. At least two refers to two or more than two, for example, at least two elements can be two elements, three elements, or any integer greater than or equal to two.

[0048] Figure 1 is a test structure schematic diagram of a semiconductor structure according to an example embodiment, as shown in Figure 1 The test structure 100 includes a plurality of first test pins 1, a plurality of second test pins 2, an addressing circuit 3, and a gating circuit 4. The plurality of first test pins 1 are coupled to the addressing circuit 3, the second test pins 2 and the addressing circuit 3 are coupled to the gating circuit 4, and the gating circuit 4 is coupled to the gates of a plurality of transistors 5 to be tested.

[0049] Next, the functions and working principles of the various components of the test structure will be described as follows in connection with 1.1 to 1.5 below.

[0050] 1.1, Transistor 5

[0051] The plurality of transistors 5 are transistors in a wafer to be tested, as shown in Figure 2 According to an example embodiment, a structure schematic diagram of a wafer is shown, the wafer 200 includes at least one cutting path 201 and a plurality of test regions 202, each test region 202 includes a plurality of transistors 5, the transistors in the same test region have similar manufacturing processes, the transistors in the same test region have the same function, and the plurality of transistors 5 to be tested are transistors in any test region 202 of the wafer 200.

[0052] In the testing process, the test structure is not located on or in communication with the wafer 200. The plurality of transistors 5 in a certain test region 202 is placed on the test structure 100 to test the plurality of transistors 5 through the test structure 100, and the test structure 100 includes the plurality of transistors 5 at this time. Alternatively, the test structure 100 is arranged on the scribe lane 201 to test the transistors 5 in the test region 202 close to the scribe lane 201, and the test structure 100 does not include the plurality of transistors 5 at this time, and the plurality of transistors 5 is located in the wafer 200. Alternatively, the test structure 100 is not arranged on the scribe lane 201, and the test structure 100 is arranged outside the wafer 200, and the test structure 100 is coupled to the plurality of transistors 5 in the wafer 200 to test the plurality of transistors 9, and the test structure 100 does not include the plurality of transistors 5 at this time, and the plurality of transistors 5 is located in the wafer.

[0053] The transistor 5 includes a source, a drain, a gate, and a body, wherein the body is also referred to as a substrate. For ease of description, an electrical signal connected to the source is referred to as a source electrical signal, and the source electrical signal is a ground electrical signal VSS when the source electrical signal is 0V. An electrical signal connected to the drain is referred to as a drain electrical signal VD, an electrical signal connected to the gate is referred to as a gate electrical signal VG, and an electrical signal connected to the body is referred to as a body electrical signal VB.

[0054] The gate electrical signal VG has two potential states of high potential and low potential, the high potential state is identified by "1", and the low potential state is identified by "0". The gate electrical signal VG in the potential state "1" and the gate electrical signal VG in the potential state "0" are mutually inverse electrical signals. When the gate electrical signal VG is in the potential state "1", the gate electrical signal VG is used to turn on the transistor 5, and the gate electrical signal VG in the potential state "1" is also referred to as a second electrical signal VG1. When the gate electrical signal VG is in the potential state "0", the gate electrical signal VG is used to turn off the transistor 5, and the gate electrical signal VG in the potential state "0" is also referred to as a third electrical signal VG0. The second electrical signal VG1 is greater than 0V, and the third electrical signal VG0 is less than or equal to 0V.

[0055] In combination with the above-described transistor 5, the connection mode of the transistor 5 is introduced as follows.

[0056] In some embodiments, as Figure 1As shown, the test structure 100 also includes at least one of the third test pin 6, the fourth test pin 7, the fifth test pin 8, and the sixth test pin 9. The third test pin 6 is coupled to the addressing circuit 3 and the gating circuit 4. The fourth test pin 7 is coupled to the addressing circuit 3 and the gating circuit 4. The fourth test pin 7, the fifth test pin 8, and the sixth test pin 9 are respectively coupled to the source, drain, and substrate of the plurality of transistors 5.

[0057] The third test pin 6 is used to connect the power supply signal VDD, which is a voltage signal with a potential of "1" and is greater than 0V. The fourth test pin 7 is used to connect the ground signal VSS.

[0058] like Figure 1 As shown, the third test pin 6 and the fourth test pin 7 are both coupled to the addressing circuit 3. During testing, a power supply signal VDD is applied to the third test pin 6 and a ground signal VSS is applied to the fourth test pin 7. This allows the power supply signal VDD and the ground signal VSS to act on the addressing circuit 3, providing the operating voltage required for the addressing circuit 3 to operate normally.

[0059] The third test pin 6 and the fourth test pin 7 are also coupled to the gating circuit 4. During testing, a power supply signal VDD is applied to the third test pin 6 and a ground signal VSS is applied to the fourth test pin 7. This allows the power supply signal VDD and the ground signal VSS to act on the gating circuit 4, providing the working voltage required for the gating circuit 4 to operate normally.

[0060] like Figure 1 As shown, the fourth test pin 7 is also coupled to the source of multiple transistors 5, so that the sources of multiple transistors 5 share the fourth test pin 7. During the test, the ground signal VSS on the fourth test pin 7 is applied as the source signal to the source of each transistor 5.

[0061] The fifth test pin 8 is used to connect the drain signal VD. The fifth test pin 8 is coupled to the drain of multiple transistors 5, so that the drains of multiple transistors 5 share the fifth test pin 8. During the test, the drain signal VD on the fifth test pin 8 is applied to the drain of each transistor 5.

[0062] The sixth test pin 9 is used to connect the substrate electrical signal VB. The sixth test pin 9 is coupled to the substrate of multiple transistors 5, so that the substrates of multiple transistors 5 share the sixth test pin 9. During the test, the substrate electrical signal VB on the sixth test pin 9 is applied to the substrate of each transistor 5.

[0063] During testing, when a base electrical signal VB, a ground electrical signal VSS, a drain electrical signal VD, and a second electrical signal VG1 are applied to the base, source, drain, and gate of any one of the multiple transistors 5, that transistor 5 is turned on, allowing testing of the turned-on transistor 5. When a base electrical signal VB, a ground electrical signal VSS, a drain electrical signal VD, and a third electrical signal VG0 are applied to the base, source, drain, and gate of any one of the multiple transistors 5, that transistor 5 is turned off, and the turned-off transistor 5 does not participate in the testing.

[0064] 1.2, Second test pin 2

[0065] like Figure 1 As shown, the second test pin 2 is used to connect to the second electrical signal VG1. The second test pin 2 is coupled to the gating circuit 4, which is coupled to the gates of multiple transistors 5. Based on this structure, when testing one of the transistors 5, the second electrical signal VG1 is applied to the second test pin 2 to provide the gating circuit 4 with the second electrical signal VG1. Under the control of the addressing circuit 3, the gating circuit 4 applies the second electrical signal VG1 from the second test pin 2 to the gate of one transistor 5 and applies the third electrical signal VG0 to the remaining transistors 5 to turn on the transistor 5 for testing, and turns off the remaining transistors 5 to prevent testing. The process of the addressing circuit 3 controlling the gating circuit 4 will be described in detail later, in conjunction with the content in 1.5 and 1.6.

[0066] As can be seen, in the test structure 100, the gates of multiple transistors 5 can share the second test pin 2 in the test structure 100 to connect to the gate electrical signal VG. This eliminates the need to provide a separate test pin for each gate of multiple transistors 5, reducing the number of test pins occupied by multiple transistors 5 and allowing the test structure 100 to have more test pins to support the testing of more transistors 5. Furthermore, since the volume of the test pin is much larger than the volume of the transistor, the size of the test structure 100 can be reduced when multiple transistors 5 share the same test pin.

[0067] 1.3, First test pin 1

[0068] In the test structure 100, the first test pin 1 is used to connect the test signal. The test signal is used to select one transistor 5 from multiple transistors 5 for testing. For ease of description, the transistor 5 selected for testing is called the first transistor. The transistors other than the first transistor among the multiple transistors 5 are called the second transistors, i.e., the transistors that are not selected for testing.

[0069] The test signal includes a plurality of first electrical signals, each of the first signals being applied to one of the first test pins 1 in the test structure 100. The first electrical signals have two potential states of high potential and low potential, wherein the first electrical signal of high potential is greater than 0V, the first electrical signal of high potential is represented by the potential state "1", the first electrical signal of low potential is less than or equal to 0V, and the first electrical signal of low potential is represented by the potential state "0", the first electrical signal of high potential and the first electrical signal of low potential are mutually inverse electrical signals.

[0070] According to the potential states of the first electrical signals, the potential states of the plurality of first electrical signals are combined to obtain the test signal, as shown in Figure 1 For example, as shown in Table 1 below, assuming that the transistors 5 to be tested are 16, and there are 4 test pins 1, the first electrical signals applied to the 4 test pins 1 are represented as din<1>, din<2>, din<3> and din<4> respectively, and according to the potential states of the first electrical signals, the 4 first electrical signals can be combined into 16 test signals, each of which is used to select one transistor (i.e. the first transistor) from the 16 transistors to enter the test.

[0071] Table 1

[0072]

[0073]

[0074] In the test of the plurality of transistors 5 to be tested, according to the order of the plurality of transistors 5, the first electrical signals of corresponding potential states are sequentially applied to the plurality of first test pins 1, so that the plurality of transistors 5 are sequentially tested. For example, in the above Table 1, the first signals in the potential state "0" are first applied to the 4 first test pins 1 to test the No. 1 transistor, and then the first electrical signals in the potential states "0", "0", "0" and "1" are respectively applied to the 4 first test pins 1 to test the No. 2 transistor. Alternatively, when there is a test requirement for a certain transistor 5 in the plurality of transistors 5, the first electrical signals of the potential states corresponding to the transistor 5 are applied to the plurality of first test pins 1 to test the transistor 5.

[0075] In the case that the first electrical signals have two potential states of "0" and "1", and each of the first test pins 1 is used to access one first electrical signal, the number of the first test pins 1 can determine the number of the transistors 5 to be tested, for example, the first test pins 1 are n, the transistors 5 are 2 n n is an integer greater than 1.

[0076] It should be understood that, Figure 1It is shown that the test structure 100 has 4 first test pins 1, in other embodiments, the number of first test pins 1 in the test structure 100 can be less than 4 or greater than 4, the more the number of first test pins 1 in the test structure 100, the more the test structure 100 can test the transistor 5, the number of first test pins 1 in the test structure 100 can be set according to the actual application scene, and in this embodiment, the number of first test pins 1 in the test structure 100 is not limited.

[0077] 1.4, address circuit 3

[0078] The address circuit 3 is configured to control the gating circuit 4 to apply the second electrical signal VG1 to the gate of the first transistor and control the gating circuit 4 to apply the third electrical signal to the gate of the second transistor in the plurality of transistors 5 according to the first electrical signals on the plurality of first test pins 1.

[0079] As shown in the figure, Figure 1 When testing the first transistor, the ground electrical signal VSS, the drain electrical signal VD and the substrate electrical signal VB are applied to the fourth test pin 7, the fifth test pin 8 and the sixth test pin 9 respectively, so that the ground electrical signal VSS, the drain electrical signal VD and the substrate electrical signal VB are applied to the source, the drain and the substrate of the plurality of transistors 5 through the corresponding test pins. The second electrical signal VG1 is applied to the second test pin 2 to provide the second electrical signal VG1 to the gating circuit 4, and the first electrical signal corresponding to the potential state of the first transistor is applied to the plurality of first test pins 1 to provide the plurality of first electrical signals to the address circuit 3. The address circuit 3 controls the gating circuit 4 to apply the second electrical signal VG1 to the gate of the first transistor to turn on the first transistor and apply the third electrical signal VG0 to the gate of each second transistor to turn off each second transistor, so that each second transistor does not participate in the test.

[0080] In a possible implementation, the address circuit 3 is a decoder, and the internal structure of the address circuit 3 will be described in detail below. Figure 3 The internal structure of the address circuit 3 will be described in detail below.

[0081] Figure 3 The structure of the address circuit according to an exemplary embodiment is shown in the figure, Figure 3 As shown in the figure, the address circuit 3 includes an inverting sub-circuit 31 and a plurality of address sub-circuits 32, the plurality of first test pins 1 are coupled to the inverting sub-circuit 31, the inverting sub-circuit 31 is coupled to the plurality of address sub-circuits 32, and the plurality of address sub-circuits 32 are coupled to the gating circuit 4.

[0082] The inverting sub-circuit 31 is configured to perform an inverting logic operation on the first electrical signals on multiple first test pins 1 to obtain multiple fourth electrical signals. Specifically, if a first electrical signal is applied to each of the multiple first test pins 1, then multiple first electrical signals are transmitted to the inverting sub-circuit 31. Each fourth electrical signal is the inverted signal of a first electrical signal; for example, if a first electrical signal is at a potential state of "0", then the fourth electrical signal is at a potential state of "1".

[0083] In one possible implementation, such as Figure 3 As shown, the inverter sub-circuit 31 includes multiple first inverters 311, each of which performs an inversion logic operation on a first electrical signal to obtain a fourth electrical signal.

[0084] The number of first inverters 311 is the same as the number of first electrical signals. Each first inverter 311 is coupled to a first test pin 1 so that each first inverter 311 can receive the first electrical signal on the coupled first test pin 1.

[0085] by Figure 3 For example, the inverter sub-circuit 31 includes four first inverters 311, such as first inverters 311a to 311d. Each first inverter 311 includes a first signal input terminal and a first signal output terminal. The first signal input terminal is coupled to a first test pin 1, so that the first electrical signal (such as din) on the first test pin 1... <1> to din <4> The first electrical signal (either of the four signals) is transmitted to the first signal input terminal, and then to the first inverter 311. The first inverter 311 performs an inversion logic operation on the input first electrical signal to obtain the fourth electrical signal (e.g., drb). <1> to drb <4> (one of them), and outputs the fourth electrical signal through the first signal output terminal.

[0086] Each addressing sub-circuit 32 includes multiple second signal input terminals and one second signal output terminal, wherein the number of second signal input terminals is the same as the number of first inverters 311.

[0087] The first signal input terminals and first signal output terminals of multiple first inverters 311 are coupled to the second signal input terminals of each addressing sub-circuit 32 in a combined manner, such that each addressing circuit 32 is connected to the first signal input terminal or the first signal input terminal of each first inverter 311.

[0088] For example, the first signal input terminal and the first signal output terminal of each first inverter 311 are respectively coupled to different addressing sub-circuits 32, and each second signal input terminal of the same addressing sub-circuit 32 is respectively coupled to one end (first signal input terminal or second signal input terminal) of different first inverters 311.

[0089] by Figure 3 Taking the addressing sub-circuits 32a and 32b as examples, the first signal output terminal and the first signal input terminal of the first inverter 311a are respectively coupled to a second signal input terminal of the addressing sub-circuit 32a and a second signal input terminal of the addressing sub-circuit 32b, so that the fourth electrical signal drb at the first signal output terminal of the first inverter 311a... <1> The first electrical signal din is input to the second signal input terminal of the addressing sub-circuit 32a and the first signal input terminal of the first inverter 311a. <1> The signal is input to the second signal input terminal of the addressing sub-circuit 32b. The first signal output terminals of the first inverters 311b-311d are both coupled to a second signal input terminal of the addressing sub-circuits 32a and 32b, so that the fourth electrical signal din... <2> to din <4> Inputs are sent to addressing sub-circuits 32a and 32b.

[0090] Figure 3 The diagram illustrates that, with four first electrical signals input, the first electrical signals input to the four first inverters 311 and the fourth electrical signals output are transmitted in combination to the 16 addressing sub-circuits 32. In other embodiments, there may be four or fewer first electrical signals, and correspondingly, the combination of the first and fourth electrical signals may differ. This application does not limit this, as long as each addressing sub-circuit 32 can receive the electrical signals from all the first inverters 311, and the electrical signal received from each first inverter 311 is either a first electrical signal or a fourth electrical signal.

[0091] Multiple fourth electrical signals and multiple first electrical signals can form multiple signal groups. Each signal group includes multiple electrical signals, which originate from different first inverters 311. Each electrical signal is either a first electrical signal input to a first inverter 311 or a fourth electrical signal output from a first inverter 311. Based on this, the inverter sub-circuit 31 is further configured to apply these multiple signal groups to multiple addressing sub-circuits 32, such as applying different signal groups to different addressing sub-circuits 32. Figure 3 Taking the address selection sub-circuit 32a as an example, the fourth electrical signal drb <1> to drb <4> It is a group of signals output from the inverting sub-circuit 31 to the addressing sub-circuit 32a.

[0092] The number of addressing sub-circuits 32 in the addressing circuit 3 is the same as the number of transistors 5, with each addressing sub-circuit 32 corresponding to one transistor 5. Each addressing sub-circuit 32 is configured to: process an applied signal group to obtain a fifth electrical signal, and apply the fifth electrical signal to the gating circuit 4. The fifth electrical signal is used to control the gating circuit 4 to apply the second electrical signal or the third electrical signal to the corresponding transistor 5.

[0093] The fifth electrical signal is in a potential state "1" or a potential state "0". If the fifth electrical signal is in the potential state "1", the fifth electrical signal controls the gating circuit 4 to apply the second electrical signal to the corresponding transistor 5 (i.e. the first transistor). If the fifth electrical signal is in the potential state "0", the fifth electrical signal controls the gating circuit 4 to apply the third electrical signal to the corresponding transistor 5 (i.e. the second transistor), so that each address sub-circuit 32 can select the corresponding transistor 5 through the fifth electrical signal.

[0094] In a possible implementation, as shown in Figure 3 each address sub-circuit 32 includes an NAND sub-circuit 321 and a second inverter 322 connected in series, the NAND sub-circuit 321 includes a plurality of second signal input terminals to receive a signal group output by the inverting sub-circuit 31, a signal output terminal of the NAND sub-circuit 321 is coupled to a signal input terminal of the second inverter 322, and the second inverter 322 further includes a second signal output terminal.

[0095] The NAND sub-circuit 321 is configured to perform an NAND logic operation on the signal group to obtain a sixth electrical signal, and apply the sixth electrical signal to the second inverter 322.

[0096] The second inverter 322 is configured to perform an inversion logic operation on the applied sixth electrical signal to obtain a fifth electrical signal, and apply the fifth electrical signal to the gating circuit 4.

[0097] Still taking the address sub-circuit 32a in Figure 3 as an example, the NAND sub-circuit in the address sub-circuit 32a receives the signal group: the fourth electrical signals dib<1> to dib<4> through the second signal input terminals, performs an NAND logic operation on the fourth electrical signals dib<1> to dib<4> to obtain a sixth electrical signal, and outputs the sixth electrical signal to the connected second inverter, the second inverter performs an inversion logic operation on the input sixth electrical signal to obtain a fifth electrical signal d<1>, and outputs the fifth electrical signal d<1> through the second signal output terminal. In a similar manner, Figure 3 the fifth electrical signals output by the 16 address sub-circuits 32 in

[0098] It should be understood that each addressing sub-circuit 32 outputs a fifth electrical signal, and there are multiple addressing sub-circuits 32 in the addressing circuit 3, accordingly, the addressing circuit 3 is capable of outputting multiple fifth electrical signals, since the multiple fifth electrical signals are the processing results of different signal groups, only one of the multiple fifth electrical signals is in the potential state "1" and the other fifth electrical signals are in the potential state "0", so that the multiple fifth electrical signals select one transistor (i.e. the first transistor) for testing through the gating circuit 4, so as to achieve the purpose of addressing the first transistor for testing from the multiple transistors 5.

[0099] In addition, as shown in Figure 3 each device (such as the first inverter 311, the NAND sub-circuit 321 or the second inverter 322) in the addressing circuit 3 has a power supply input end and a ground input end, the power supply input end is coupled to the third test pin 6 to input the power supply electrical signal VDD on the third test pin 6 to the device, and the ground input end is coupled to the fourth test pin 7 to input the ground electrical signal VSS on the fourth test pin 7 to the device, the power supply electrical signal VDD and the ground electrical signal VSS are used to provide working voltage for the corresponding device, so that the corresponding device can work.

[0100] 1.5, the gating circuit 4

[0101] Figure 4 is a structural schematic diagram of a gating circuit according to an exemplary embodiment, and the gating circuit 4 includes multiple switch sub-circuits 41. The multiple switch sub-circuits 41 are all coupled to the second test pin 2, so that the second electrical signal VG1 on the second test pin 2 can be input to each switch sub-circuit 41. For example, each switch sub-circuit 41 includes a third signal input end, the third signal input end is coupled to the second test pin 2, and the second electrical signal VG1 on the second test pin 2 is input to the switch sub-circuit 41 through the third signal input end.

[0102] The multiple switch sub-circuits 41 correspond to the multiple addressing sub-circuits 32 one by one, and each addressing sub-circuit 32 is coupled to the corresponding switch sub-circuit 41, so that the fifth electrical signal output by each addressing sub-circuit 32 can be input to the corresponding switch sub-circuit 41. For example, each switch sub-circuit 41 further includes a fourth signal input end, the fourth signal input end is coupled to the second signal output end of the corresponding switch sub-circuit 41, so that the fifth electrical signal output by the second signal output end is input to the switch sub-circuit 41 through the fourth signal input end. As shown in Figure 3 For example, as shown in Figure 4 the fifth electrical signals d<1> to d<16> output by the 16 switch sub-circuits 41 are input to the 16 switch sub-circuits respectively.

[0103] Based on this, each switch sub-circuit 41 can receive a second electrical signal and a fifth electrical signal. Each switch sub-circuit 41 is configured to apply the second electrical signal or the third electrical signal to the gate of the transistor 5 coupled thereto according to the fifth signal output by the selection sub-circuit 32 coupled thereto.

[0104] The third electrical signal is the inverse of the second electrical signal. For ease of description, the electrical signal output by each switch sub-circuit 41 is referred to as a target electrical signal, which can be the second electrical signal or the third electrical signal. When the fifth electrical signal input to a switch sub-circuit 41 is in the potential state "0", the target electrical signal is the third electrical signal. When the fifth electrical signal input to a switch sub-circuit 41 is in the potential state "1", the target electrical signal is the second electrical signal.

[0105] It should be understood that the third signal output end of each switch sub-circuit 41 respectively outputs a target electrical signal, which can be the second electrical signal or the third electrical signal. However, only one of the target electrical signals output by all switch sub-circuits 41 is the second electrical signal, and the other target electrical signals are the third electrical signal. Figure 4 For example, 16 fifth electrical signals d<1> to d<16> are input to the selection circuit 4, and switch sub-circuits 1-16 process one fifth electrical signal to output a target electrical signal, and there are 16 target electrical signals V<1> to V<16>, of which only one is the second electrical signal, and the other 15 target electrical signals are the third electrical signal.

[0106] In a possible implementation, each switch sub-circuit 41 is an AND gate sub-circuit. At this time, each switch sub-circuit 41 is configured to perform AND logic operation on the input fifth electrical signal and the second electrical signal to obtain the target electrical signal, and apply the target electrical signal to the gate of the transistor 5 coupled to the switch sub-circuit 41. In the case where the fifth electrical signal and the second electrical signal are both in the potential state "1", the target electrical signal is in the potential state "1", and the target electrical signal at this time is the second electrical signal. In the case where there is an electrical signal in the potential state "0" in the fifth electrical signal and the second electrical signal, the target electrical signal is in the potential state "0", and the target electrical signal at this time is the third electrical signal.

[0107] In addition, the present application also provides another switch sub-circuit 41, which is described below with reference to Figure 5 According to an exemplary embodiment, a structure diagram of a switch sub-circuit is shown as follows: Figure 5As shown, the switching sub-circuit 41 includes a third inverter 411, a fourth inverter 412, a third transistor 413, a fourth transistor 414, a fifth transistor 415, and a third signal output terminal 416. The third transistor 413 and the fifth transistor 415 are both N-type metal-oxide-semiconductor (NMOS), and the fourth transistor 414 is a P-type metal-oxide-semiconductor (PMOS).

[0108] like Figure 5 As shown, a third inverter 411, a fourth inverter 412, and a third transistor 413 are present, wherein the fourth inverter 412 is coupled to the gate of the third transistor 413. The third inverter 411 is coupled to the gate of the fourth transistor 414. The drains of the third transistor 413 and the fourth transistor 414 are coupled to the second test pin 2 so that the second electrical signal VG1 on the second test pin 2 is transmitted to the drain. The sources of the third transistor 413, the fourth transistor 414, and the fifth transistor 415 are all coupled to the fourth signal output terminal 416. The base of the third transistor 413, the base of the fifth transistor 415, and the drain are all coupled to the fourth pin 4 so that the ground electrical signal VSS on the fourth pin 4 is transmitted to the coupled position. The base of the fourth transistor 414 is coupled to the third test pin 6 so that the power supply signal VDD on the third test pin 6 is applied to the base.

[0109] The i-th (i>1) fifth electrical signal d among multiple fifth electrical signals Input to Figure 5 The switch sub-circuit 41 shown in the example is a fifth electric signal d The input is given to the third inverter 411, which in turn inputs the fifth electrical signal d. performing an inverse logic operation to obtain a fifth electrical signal d the inverted electrical signal d' The signal output end of the fourth inverter 412, the gate of the fourth transistor 414, and the gate of the fourth transistor 415 are respectively outputted with the inverse phase electric signal d' . The fourth inverter 412 inverts the inverted electrical signal d' performing an inverse logic operation to obtain a fifth electrical signal d , and outputs a fifth electric signal d to the gate of the third transistor 413 If the fifth electrical signal d in the state "1", the inverting signal d' is a fifth electrical signal d in the potential state "0", in the potential state "1" The gate of the third transistor 413 is applied to, so that the third transistor 413 is turned on, the inverted electrical signal d' in the state "0" The gate of the fourth transistor 414 is applied to, so that the fourth transistor 414 is closed, so that the second electrical signal VG1 can be transmitted to the fourth signal output port 416 through the third transistor 413. The inverted electrical signal d' is in the potential state "0". The fifth transistor 415 is applied to the gate of the fifth transistor 415, and the fifth transistor 415 is closed, so that the ground signal VSS at the drain of the fifth transistor 415 cannot be transmitted to the fourth signal output port 416.

[0110] If the fifth electric signal d in the potential state "0", the inverting electrical signal d' a fifth electrical signal d in the potential state "1", in the potential state "0" The gate of the third transistor 413 is applied to, so that the third transistor 413 is closed, so that the second electrical signal VG1 cannot be transmitted to the fourth signal output port 416 through the third transistor 413, at this time, the inverted electrical signal d' The gates of the fourth transistor 414 and the fifth transistor 415 are applied, causing both the fourth transistor 414 and the fifth transistor 415 to be turned on. As a result, the ground signal VSS on the drain of the fifth transistor 415 can be transmitted to the fourth signal output port 416 through the fifth transistor 415. The ground signal VSS is an electrical signal in the potential state "0". At this time, the ground signal VSS is also the third electrical signal VG0.

[0111] For the two types of switch sub-circuits 41 described above, for ease of description, when the switch sub-circuit 41 is an AND gate circuit, the signal output terminal of the AND gate circuit is also called the fourth signal output terminal, that is, the signal output terminal of the switch sub-circuit 41.

[0112] The fourth signal output terminal of each switching sub-circuit 41 is coupled to the gate of one of the multiple transistors 5. The target electrical signal output from the fourth signal output terminal of each switching sub-circuit 41 is applied to the gate of the coupled transistor 5. For a given transistor 5, if the target electrical signal on the gate of the transistor 5 is the second electrical signal, then the transistor 5 can be turned on to test it, and this transistor 5 is the first transistor addressed. If the target electrical signal on the gate of the transistor 5 is the third electrical signal, then the transistor 5 cannot be turned on to avoid testing it, and this transistor 5 is the second transistor addressed.

[0113] Since only one of the target electrical signals is the second electrical signal and the rest are the third electrical signals, only one of the multiple transistors 5 can be turned on for testing, while the rest cannot be turned on to avoid testing the rest of the transistors.

[0114] In addition, such as Figure 4 As shown, each device in the gating circuit 4 (such as the switch sub-circuit 41) includes a power input terminal and a ground input terminal. The power input terminal is coupled to the third test pin 6 to input the power signal VDD on the third test pin 6 to the device. The ground input terminal is coupled to the fourth test pin 7 to input the ground signal VSS on the fourth test pin 7 to the device. The power signal VDD and the ground signal VSS can provide the device with the operating voltage, enabling the device to work.

[0115] by Figure 5 The third inverter 411 and the fourth inverter 412 in the switch sub-circuit 41 are coupled to the third test pin 6 and the fourth test pin 7 respectively, so that the power supply electrical signal VDD on the third test pin 6 and the ground electrical signal VSS on the fourth test pin 7 can be input to the third inverter 411 and the fourth inverter 412 to ensure that the third inverter 411 and the fourth inverter 412 can work.

[0116] Based on the above-described test structure, the gate of each transistor to be tested is coupled to the gating circuit, and the gating circuit is controlled by the addressing circuit to apply the third electrical signal or the second electrical signal on the second test pin to each transistor to be tested according to the first electrical signal on the plurality of first test pins, so that each transistor to be tested is tested by the second electrical signal, thereby making the gates of the transistors to be tested share the same second test pin, reducing the number of test pins occupied by the gates of the transistors to be tested, increasing the utilization rate of the test pins in the test structure, and enabling the test structure to support more transistor testing.

[0117] Next, the layout of components in the test structure is described in detail.

[0118] When testing the transistors on the test structure, especially when performing mismatch testing on the transistors, in order to ensure the accuracy of the test results, it is necessary to strictly control the influence of the arrangement of components on the test structure on the transistors.

[0119] For example, on the test structure, the addressing circuit, the gating circuit and the plurality of transistors are arranged in an axial symmetry manner or an approximate axial symmetry manner. For example, Figure 6 According to an example embodiment, a layout diagram of a test structure is shown, the devices in the addressing circuit, the devices in the gating circuit and the plurality of transistors are arranged symmetrically left and right about the first symmetry axis 600, wherein the devices in the addressing circuit are approximately symmetrically arranged left and right about the first symmetry axis 600, the plurality of addressing sub-circuits in the addressing circuit are symmetrically arranged left and right about the first symmetry axis 600, and the plurality of inverting sub-circuits are located on the left side of the addressing sub-circuits. In other embodiments, the plurality of inverting sub-circuits can also be distributed above or below the plurality of addressing sub-circuits and symmetrically arranged left and right about the first symmetry axis 600, so that the devices in the addressing circuit are symmetrically arranged left and right about the first symmetry axis 600.

[0120] The switch sub-circuits in the gating circuit are symmetrically arranged left and right about the first symmetry axis 600, and the plurality of transistors are arranged in rows, forming at least one row of transistors, each row of transistors being symmetrically arranged left and right about the first symmetry axis 600.

[0121] For another example, Figure 7 According to a schematic diagram of another test structure shown in an exemplary embodiment, the devices in the addressing circuit, the devices in the gating circuit, and the multiple transistors are all arranged symmetrically about a first axis of symmetry 700. Specifically, the devices in the addressing circuit are arranged approximately symmetrically about the first axis of symmetry 700. Multiple addressing sub-circuits in the addressing circuit are arranged symmetrically about the first axis of symmetry 700, and multiple inverting sub-circuits are located to the left of the addressing sub-circuits. In other embodiments, the multiple inverting sub-circuits may also be distributed above or below the multiple addressing sub-circuits and arranged symmetrically about the first axis of symmetry 700, thereby ensuring that the devices in the addressing circuit are arranged symmetrically about the first axis of symmetry 700.

[0122] When testing multiple transistors on a test structure, the transistors are organized into multiple test pairs, each test pair consisting of two transistors arranged in an axially symmetrical manner.

[0123] Test pairs are formed by two transistors in each row that are symmetrical about the first axis of symmetry, 600°. Figure 6 Taking the row-arranged transistors as an example, each row of transistors includes four test pairs. Each test pair is arranged symmetrically about the first axis of symmetry 600, such as transistors 601 and 602 forming one test pair. Figure 7 Taking the transistor shown as an example, the switching sub-circuits in the gating circuit are arranged symmetrically about the first axis of symmetry 700, and multiple transistors are arranged in columns to form at least one test pair. The transistors in each test pair are arranged symmetrically about the first axis of symmetry 700.

[0124] The transistors in the same test pair are of the same model, so as to test the performance differences between different transistors of the same model. For example Figure 6 Transistor 601 and transistor 602 are of the same model and belong to the same test pair.

[0125] The transistors in different test pairs are of the same model. Figure 6 For example, Figure 6 The multiple transistors shown are of the same model, therefore, Figure 6 The multiple transistors shown have the same shape.

[0126] The transistors used in different test pairs may also be of different models. Figure 7 For example, Figure 7 Four test pairs are shown. Within each test pair, the transistors in the same pair are of the same model, while the transistors in different test pairs are of different models. Figure 7 The different sizes of the transistors represent different models of the transistors. Of course, in other embodiments, the different models of the transistors can also have the same shape or size.

[0127] The distances between the transistors of different test pairs are the same to avoid the influence of different test environments on different test pairs during the test. For example, the transistors arranged in columns have the same model in the same column, and the distances between the transistors of different test pairs and the first axis of symmetry are the same in the same column.

[0128] Of course, the distances between the transistors of different test pairs can also be different to Figure 6 For example, the transistors 601 and 602 belong to one test pair, the transistors 603 and 604 belong to one test pair, and the distance between the transistors 601 and 602 is greater than the distance between the transistors 603 and 604.

[0129] To minimize the influence of the test environment on the test results, the wires between the components in the test structure are arranged in axial symmetry, and the wires between the devices in the same component are arranged in axial symmetry. For example, Figure 6 For example, the wires between the addressing sub-circuits and the inverting sub-circuits in the addressing circuit are arranged in axial symmetry, the wires between the different addressing sub-circuits and the switch sub-circuits are arranged in axial symmetry, for example, the wires between the addressing sub-circuit 610 and the switch sub-circuit 630 and the wires between the addressing sub-circuit 620 and the switch sub-circuit 640 are symmetrically arranged on the left and right of the first axis of symmetry 600. The wires between the different switch sub-circuits and the transistors are arranged in axial symmetry, for example, the wires between the switch sub-circuit 640 and the transistor 601 and the wires between the switch sub-circuit 630 and the transistor 602 are symmetrically arranged on the left and right of the first axis of symmetry 600.

[0130] The test structure described above can be a mismatch test structure, and accordingly, the first electrical signals applied to the plurality of first test pins are used to select the first transistors for mismatch test. When the first transistors are turned on, the mismatch test of the first transistors can be performed. Of course, the test structure described above can also be used for other types of tests of the transistors other than mismatch test, and here, the application does not limit the types of tests to which the test structure is applicable.

[0131] Based on the test structure described above, the application also provides a test method of a semiconductor structure, which is described with reference to Figure 8 A flowchart of a test method of a semiconductor structure according to an example embodiment is shown. The method is applied to any of the test structures described above, and the method includes the following steps:

[0132] 801. Apply a first electrical signal to a plurality of first test pins on the test structure, and apply a second electrical signal to a second test pin.

[0133] If the third test pin in the test structure has not been connected to the power supply signal, and / or the fourth test pin in the test structure has not been connected to the ground signal, the power supply signal is further applied to the third test pin, and the ground signal is further applied to the fourth test pin, so as to provide the power supply signal and the ground signal to each component in the test structure through the third test pin and the fourth test pin, to ensure that each component can work.

[0134] 802. According to the first electrical signals on the plurality of first test pins, the gating circuit is controlled to apply the second electrical signal to the gate of the first transistor, and the gating circuit is controlled to apply the third electrical signal to the gate of the second transistor.

[0135] In this step 802, the addressing circuit in the test structure is used.

[0136] For example, the first electrical signals on the plurality of first test pins are subjected to an inverse logic operation to obtain a plurality of fourth electrical signals, the plurality of fourth electrical signals and the plurality of first electrical signals are combined into a plurality of signal groups, and the plurality of signal groups are respectively subjected to signal processing to obtain a plurality of fifth electrical signals. For any fifth signal, the fifth signal is applied to the gating circuit, and the gating circuit applies the second electrical signal or the third electrical signal to the gate of a transistor according to the fifth signal, so as to turn on or turn off the transistor. If the second electrical signal is applied to the gate of the transistor, the transistor can be turned on, so as to test the transistor. At this time, the transistor is the first transistor. If the third electrical signal is applied to the gate of the transistor, the transistor cannot be turned on, so as to avoid testing the transistor. At this time, the transistor is the second transistor.

[0137] The process of subjecting the first electrical signals on the plurality of first test pins to an inverse logic operation to obtain a plurality of fourth electrical signals can be performed by an inverse sub-circuit in the addressing circuit. For details, please refer to the related introduction of the inverse sub-circuit above.

[0138] The process of subjecting each signal group to signal processing can be performed by an addressing sub-circuit in the inverse sub-circuit in the addressing circuit. For details, please refer to the related introduction of the addressing sub-circuit above.

[0139] The process of applying the second electrical signal or the third electrical signal to the gate of a transistor according to the fifth signal can be performed by a switch sub-circuit in the gating circuit. For details, please refer to the related introduction of the switch sub-circuit above.

[0140] The above only describes optional embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A test structure for a semiconductor structure, characterized in that, The test structure includes multiple first test pins (1), second test pins (2), addressing circuit (3), and gating circuit (4); The plurality of first test pins (1) are coupled to the addressing circuit (3). The plurality of first test pins (1) are used to connect to a first electrical signal. The first electrical signal is in one of two potential states. The potential states of the first electrical signal connected to the plurality of first test pins (1) are combined to form a test signal. The test signal is used to select a first transistor from the plurality of transistors (5) to be tested for testing. There are n first test pins (1) and 2 transistors (5). n There are n, where n is an integer greater than 1; The second test pin (2) and the addressing circuit (3) are coupled to the gating circuit (4), the gating circuit (4) is coupled to the gate of the plurality of transistors (5), the second test pin (2) is used to connect to the second electrical signal, and the second electrical signal is used to turn on the first transistor; The addressing circuit (3) is configured as follows: Based on the first electrical signal on the plurality of first test pins (1), the gating circuit (4) is controlled to apply the second electrical signal to the gate of the first transistor, and the gating circuit (4) is controlled to apply the third electrical signal to the gate of the second transistor among the plurality of transistors. The third electrical signal is used to turn off the second transistor, which is a transistor among the plurality of transistors (5) other than the first transistor.

2. The test structure according to claim 1, characterized in that, The addressing circuit (3) includes an inverting sub-circuit (31) and multiple addressing sub-circuits (32). The multiple first test pins (1) are coupled to the inverting sub-circuit (31), the inverting sub-circuit (31) is coupled to the multiple addressing sub-circuits (32), and the multiple addressing sub-circuits (32) are coupled to the gating circuit (4). Each addressing sub-circuit (32) corresponds to a transistor (5). The inverting sub-circuit (31) is configured to: perform inverting logic operation on the first electrical signals on the plurality of first test pins (1) to obtain a plurality of fourth electrical signals, and apply pressure to a plurality of signal groups composed of the plurality of fourth electrical signals and the plurality of first electrical signals to a plurality of addressing sub-circuits (32). Each addressing sub-circuit (32) is configured to: process an applied signal group to obtain a fifth electrical signal, and apply the fifth electrical signal to the gating circuit (4), wherein the fifth electrical signal is used to control the gating circuit (4) to apply the second electrical signal or the third electrical signal to the corresponding transistor (5).

3. The test structure according to claim 2, characterized in that, The gating circuit (4) includes multiple switching sub-circuits (41), the second test pin (2) is coupled to the multiple switching sub-circuits (41), and the multiple addressing sub-circuits (32) are respectively coupled to the multiple switching sub-circuits (41). Each switching sub-circuit (41) is configured to apply the second electrical signal or the third electrical signal to the gate of the coupled transistor (5) according to the fifth electrical signal applied by the coupled addressing sub-circuit (32).

4. The test structure according to any one of claims 1-3, characterized in that, The plurality of transistors (5) are arranged symmetrically about the first axis of symmetry. The devices in the addressing circuit (3) are arranged symmetrically on the left and right sides according to the first axis of symmetry; The devices in the gating circuit (4) are arranged symmetrically on the left and right sides according to the first axis of symmetry.

5. The test structure according to any one of claims 1-3, characterized in that, The plurality of transistors (5) are arranged in rows or columns.

6. The test structure according to claim 5, characterized in that, The plurality of transistors (5) form a plurality of test pairs, and the distance between the transistors (5) in different test pairs is the same.

7. The test structure according to claim 6, characterized in that, The transistors (5) in the same test pair among the multiple test pairs are of the same type.

8. The test structure according to any one of claims 1-3 or 6-7, characterized in that, The addressing circuit (3) is a decoder.

9. The test structure according to any one of claims 1-3 or 6-7, characterized in that, The test structure is located on the dicing track of the wafer, and the transistor (5) is a transistor in the wafer.

10. The test structure according to any one of claims 1-3 or 6-7, characterized in that, The test structure is a mismatch test structure, and the first electrical signal connected to the plurality of first test pins (1) is used to select the first transistor for mismatch testing.

11. The test structure according to any one of claims 1-3 or 6-7, characterized in that, The test structure also includes at least one of a third test pin (6), a fourth test pin (7), a fifth test pin (8), and a sixth test pin (9). The third test pin (6) is coupled to the addressing circuit (3) and the gating circuit (4). The third test pin (6) is used to connect to the power supply signal. The fourth test pin (7) is coupled to the addressing circuit (3) and the gating circuit (4), and the fourth test pin (7) is used to connect to the ground signal; The fourth test pin (7), the fifth test pin (8), and the sixth test pin (9) are respectively coupled to the source, drain, and substrate of the plurality of transistors (5).

12. A method for testing semiconductor structures, characterized in that, The method is applied to the test structure of claim 1, and the method includes: A first electrical signal is applied to the plurality of first test pins, and a second electrical signal is applied to the second test pins. The second electrical signal is used to turn on the first transistor to be tested among the plurality of transistors. The first electrical signal is in one of two potential states. The potential states of the first electrical signals applied to the plurality of first test pins are combined to form a test signal. The test signal is used to select the first transistor from the plurality of transistors for testing. Based on the first electrical signal on the plurality of first test pins, the gating circuit is controlled to apply the second electrical signal to the gate of the first transistor, and the gating circuit is controlled to apply the third electrical signal to the gate of the second transistor, wherein the second transistor is a transistor other than the first transistor among the plurality of transistors, and the third electrical signal is used to turn off the second transistor.

13. The test method according to claim 12, characterized in that, The step of controlling the gating circuit to apply a second electrical signal to the gate of the first transistor based on the first electrical signal on the plurality of first test pins, and controlling the gating circuit to apply a third electrical signal to the gate of the second transistor, includes: The first electrical signals on the plurality of first test pins are inverted to obtain a plurality of fourth electrical signals, and the plurality of fourth electrical signals and the plurality of first electrical signals form a plurality of signal groups; Multiple signal groups are processed to obtain multiple fifth electrical signals. The fifth electrical signals are then applied to the gating circuit, which, based on the fifth electrical signals, applies either the second electrical signal or the third electrical signal to the gate of a transistor.

14. A wafer, characterized in that, The wafer includes a test area and a dicing channel, wherein a test structure as described in any one of claims 1 to 11 is provided in the dicing channel, and the test structure is used to test a plurality of transistors in the test area.

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