Lower electrode assembly, semiconductor process chamber, and semiconductor process apparatus

Abstract

This application discloses a lower electrode assembly, a semiconductor process chamber, and semiconductor process equipment, relating to the semiconductor field. A lower electrode structure includes an interface component, a carrier component, an RF feed component, and a shield. The carrier component supports a wafer. The interface component includes an interface disk disposed below the carrier component. One end of the shield is connected to the interface disk, and the other end is bent radially outward toward the carrier component. The RF feed component passes through the shield and connects to the carrier component after passing through the interface disk, for feeding RF power to the carrier component. Multiple first grooves are provided on the side of the interface disk near the bending direction of the shield. This application solves the problem of geometric asymmetry affecting etching uniformity.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a lower electrode assembly, a semiconductor process chamber, and semiconductor process equipment. Background Technology

[0002] With the development of semiconductor manufacturing processes, the requirements for uniformity in semiconductor etching processes are becoming increasingly stringent. In inductively coupled plasma (ICP) etching equipment, the coil of the upper electrode generates plasma inside the chamber through inductive coupling. Simultaneously, a certain frequency of video power is applied to the lower electrode, and the radio frequency power acts on the plasma on the wafer surface through capacitive coupling. This controls the energy of the ions reaching the wafer surface. High-energy ions bombard the wafer surface, destroying the CF film and other substances that hinder the etching reactor during the etching process, thereby accelerating the etching rate.

[0003] Therefore, the main factors affecting the uniformity of the etching process include: the plasma uniformity of the wafer surface, the uniformity of ion energy distribution controlled by the lower electrode circuit, and the uniformity of the density distribution of etching reactants reaching the wafer surface. The symmetry of the lower electrode circuit is a crucial factor in determining the uniformity of the etching process.

[0004] However, in etching apparatus, the asymmetry in the geometry of components (such as wafer transfer ports, cantilever arms, etc.) can have a significant impact on etching uniformity. Summary of the Invention

[0005] The purpose of this application is to provide a lower electrode assembly, a semiconductor process chamber, and a semiconductor process equipment, which can at least solve the problem of etching uniformity being affected by the asymmetry of the component geometry.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows:

[0007] This application provides a lower electrode assembly, including: a carrier, an interface, an RF feeder, and a shield;

[0008] The carrier is used to support the wafer;

[0009] The interface component includes an interface disk, which is disposed below the carrier component;

[0010] One end of the shield is connected to the interface panel, and the other end is bent radially outward toward the carrier.

[0011] The radio frequency feeder is installed inside the shield and is connected to the carrier after passing through the interface panel, for feeding radio frequency power into the carrier;

[0012] The interface disk has multiple first grooves on the side near the bending direction of the shield.

[0013] This application embodiment also provides a semiconductor process chamber, including: a cavity, an inner liner, the aforementioned lower electrode assembly, and a cantilever;

[0014] Both the inner liner and the lower electrode assembly are disposed within the cavity. The lower electrode assembly is connected to the side wall of the cavity via the cantilever. The inner liner is ring-shaped on the outside of the lower electrode assembly. One end of the inner liner is electrically connected to the cavity, and the other end of the inner liner is electrically connected to the interface of the lower electrode assembly.

[0015] This application also provides a semiconductor process apparatus, including the aforementioned semiconductor process chamber.

[0016] In this embodiment, because the other end of the shielding member is bent radially outward toward the carrier member, the structure of the lower electrode assembly is not completely symmetrical. As one of the components that transmit current in the lower electrode assembly, the interface disk has multiple first grooves in the area near the bending direction of the shielding member. This increases the inductance of the interface disk in the area near the bending direction of the shielding member when the current flows through it. This can compensate for the current asymmetry caused by the inconsistent circuit impedance of the lower electrode assembly due to the structural asymmetry of the lower electrode assembly itself, thereby improving the symmetry of the current in the lower electrode assembly on the side near the bending direction of the shielding member and the side away from the bending direction of the shielding member. This can improve the process uniformity and improve product performance. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the semiconductor process chamber disclosed in the embodiments of this application;

[0018] Figure 2 A first schematic diagram showing multiple grooves of equal width and depth in the interface component disclosed in the embodiments of this application;

[0019] Figure 3 A second schematic diagram showing multiple grooves of equal width and depth in the interface component disclosed in the embodiments of this application;

[0020] Figure 4 A first schematic diagram showing multiple grooves of different widths and depths in the interface component disclosed in the embodiments of this application;

[0021] Figure 5 A second schematic diagram showing that the interface component disclosed in the embodiments of this application has multiple grooves with non-uniform width and depth dimensions;

[0022] Figure 6A schematic diagram showing multiple grooves of different widths and depths in the interface component disclosed in the embodiments of this application;

[0023] Figure 7 This is a top view of the semiconductor process chamber where the wafer transfer port is located in the vertical direction of the cantilever, as disclosed in the embodiments of this application.

[0024] Figure 8 This is a top view of a semiconductor process chamber with a groove asymmetrically arranged about the centerline of the cantilever, as disclosed in an embodiment of this application.

[0025] Explanation of reference numerals in the attached figures:

[0026] 100 - Cavity; 110 - Transmission port;

[0027] 200-lining;

[0028] 300-Lower electrode assembly; 310-Base; 320-Interface component; 321-Interface plate; 3211-First groove; 32111-First slot segment; 32112-Second slot segment; 322-Inner grounding ring; 3221-One side area; 330-Carrier component; 340-RF feed component; 350-Shielding component;

[0029] 400-Cantilever;

[0030] 500-matcher. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0033] The embodiments of this application will be described in detail below with reference to the accompanying drawings and specific examples and application scenarios.

[0034] refer to Figures 1 to 8 This application discloses a lower electrode assembly 300, which includes a carrier 330, an interface 320, an RF feed 340, and a shield 350.

[0035] The carrier 330 is used to carry the wafer. Exemplarily, the carrier 330 can be a carrier disk, i.e., an electrostatic chuck. Optionally, the carrier disk can be a disc having a carrier surface to carry the wafer to be processed. Additionally, the carrier 330 can direct the fed radio frequency power onto the plasma on the wafer surface to control the ion energy of the plasma reaching the wafer surface.

[0036] like Figure 1 As shown, the interface component 320 includes an interface disk 321, which is located below the carrier component 330 and is used to support the carrier component 330; one end of the shield 350 is connected to the interface disk 321, and the other end is bent radially outward toward the carrier component 330; and the RF feeder 340 passes through the shield 350 and is connected to the carrier component 330 after passing through the interface disk 321, for feeding RF power to the carrier component 330.

[0037] For example, the interface disk 321 can be a disc-shaped component that can provide a mounting base for the shield 350, ensuring the installation stability of the shield 350. Additionally, the interface disk 321 may have an opening to allow the RF feed 340 to pass through.

[0038] To accommodate the shape of the RF feed 340, the shield 350 can be a shielding cylinder. Specifically, the shield 350 may include a straight cylindrical section and a curved cylindrical section that are connected or integrally formed. Based on this, the shield 350 can block at least a portion of the RF feed 340 to achieve a shielding effect.

[0039] Based on the above configuration, by placing the shielding component 350 on the outside of the RF feed component 340, a section of the RF feed component 340 can be blocked to achieve a shielding effect, effectively reduce energy loss, and reduce the impact on the etching process to a certain extent.

[0040] In addition, the RF feeder 340 can be connected to the matching unit 500, which is located on one side of the lower electrode assembly 300, so that the matching unit 500 can feed RF power to the carrier 330 through the RF feeder 340, thereby controlling the ion energy reaching the wafer surface carried on the carrier 330.

[0041] However, in the actual process, the inventors discovered that because the other end of the shield 350 extends radially outward toward the carrier 330, the geometry of the lower electrode assembly 300 is asymmetrical on the side near the matching device 500 and the side away from the matching device 500. This results in a difference in current density in the circuits of the lower electrode assembly 300 on the side near the matching device 500 and the side away from the matching device 500, which in turn affects the uniformity of etching.

[0042] Based on the above, in this embodiment, the interface disk 321 is provided with a plurality of first grooves 3211 on the side near the bending direction of the shield 350. Therefore, by providing a plurality of first grooves 3211, the inductance near the matching unit 500 can be increased, thereby adjusting the impedance of the lower electrode circuit on the side near and away from the matching unit 500. This can compensate for the asymmetry of the lower electrode circuit caused by the inherent asymmetry in the geometric distribution of components in the lower electrode assembly 300, and further make the current density in the lower electrode circuit more uniform, thereby improving the uniformity of the etching process and improving product performance.

[0043] It should be noted that the area of ​​the interface disk 321 near the bending direction of the shield 350 (or near the matching device 500) can be understood as follows: there is a plane passing through the axis of the interface disk 321, which can divide the interface disk 321 into two parts, thus forming the first part being the area near the bending direction of the shield 350, and the second part being the area away from the bending direction of the shield 350. That is, the area of ​​the interface disk 321 between the plane and the matching device 500 is the area of ​​the interface disk 321 near the matching device 500.

[0044] To compensate for the asymmetry of the circuit path as much as possible, the more first grooves 3211 provided on the interface plate 321, the better. However, in actual working conditions, the interface plate 321 has multiple holes, such as PIN pin openings, temperature measuring holes, and water inlet / outlet holes, resulting in a limited area on the interface plate 321 available for forming the first grooves 3211. To balance the size of the lower electrode assembly 300 and the compensation effect, in some embodiments, the interface plate 321 can have 10 to 50 first grooves 3211, for example, 10, 20, 30, 40, 50, etc. In this way, on the one hand, the impedance can be increased by increasing the number of first grooves 3211, and on the other hand, it can also prevent the interface plate 321 from being too large, resulting in a large size of the entire lower electrode assembly 300.

[0045] In some embodiments, the interface disk 321 can be a ring-shaped structure, such as a circular ring structure, etc., with multiple first grooves 3211 arranged from the inner diameter edge to the outer diameter edge of the interface disk 321. This arrangement can, to a certain extent, extend the current path of the interface disk 321 on the side near the bending direction of the shield 350, thereby further increasing the inductance in that side region to compensate for the asymmetry of the lower electrode assembly circuit caused by geometric asymmetry.

[0046] In this embodiment of the application, the interface component 320 may further include an inner grounding ring 322, such as Figure 1 As shown, the inner liner grounding ring 322 may also have multiple second grooves on the side region 3221 near the bending direction of the shield 350. Exemplarily, the multiple second grooves may be arranged along the axial direction of the lower electrode assembly 300 on the inner or outer wall of the inner liner grounding ring 322, and the specific location and number are not limited. Furthermore, the inner liner grounding ring 322 is connected to the interface disk 321 and is disposed around the carrier 330, and the inner liner grounding ring 322 is connected to the liner 200 of the semiconductor process chamber to transmit current.

[0047] It should be noted that the arrangement of multiple second grooves can also refer to the arrangement of multiple first grooves 3211, for example, equidistant, non-equidistant, equal width, non-equal width, etc. In addition, the inner grounding ring 322 and the interface plate 321 can be two connected independent structures or an integrated structure; the specific form is not limited.

[0048] Based on the above settings, the flow path of current in the region 3221 on the side of the inner grounding ring 322 near the bending direction of the shield 350 can be extended, thereby increasing the inductance in that region to compensate for the asymmetry of the lower electrode assembly circuit caused by the asymmetry of geometric distribution.

[0049] Continue to refer to Figure 1 In some embodiments, the lower electrode assembly 300 may further include a base 310, with an interface component 320 disposed on the base 310. The base 310 provides a mounting and support foundation for the interface component 320, the carrier component 330, the RF feed component 340, and the shielding component 350. For example, when the lower electrode assembly 300 is installed into a semiconductor process cavity, the cantilever 400 connects the base 310 to the cavity 100, thereby enabling the installation and support of the first lower electrode assembly 300 to ensure its stability.

[0050] In actual working conditions, the interface disk 321 is located on top of the base 310, and the carrier 330 is located on the side of the interface disk 321 away from the base 310. In this way, the base 310 can support the interface disk 321, and the interface disk 321 can support the carrier 330.

[0051] refer to Figure 3 and Figure 4 In some embodiments, each first groove 3211 can be a sector-shaped groove, and the center of each sector-shaped groove coincides with the center of the interface disk 321. For example, the interface disk 321 can be a circular interface disk, and the shape of the sector-shaped groove can be adapted to the circular interface disk, and can cover a larger area on the interface disk 321. To a certain extent, this can help increase the inductance of the area near the bending direction of the shield 350, so as to improve the compensation effect.

[0052] For example, the central angle of the sector slot ranges from 30° to 90°, including, for example, 30°, 40°, 45°, 50°, 60°, 70°, 80°, 90°, etc., and of course, other degrees are also possible. This arrangement ensures that the sector slot has sufficient extension length to cover a larger area, thereby reducing the area on the interface panel 321 where the sector slot is not located, thus increasing the probability of current flowing through the sector slot.

[0053] In this embodiment, the projection of each first groove 3211 in the first plane at least partially coincides with the projection of the center line of the shield 350 in the first plane. In this way, each first groove 3211 can cover the current flow path, so that the current can flow through each first groove 3211 in sequence, increasing the current path in the area near the bending direction of the shield 350, which helps to compensate for the small inductance in that area. The first plane is perpendicular to the axis of the lower electrode assembly 300.

[0054] In some embodiments, the projection of each first groove 3211 in the first plane can be symmetrically arranged about the projection of the center line of the shield 350 in the first plane. This arrangement can make the area covered by each first groove 3211 on both sides of the center line of the shield 350 the same, thereby ensuring the uniformity of the inductance of the interface plate 321 in the area on both sides of the center line of the shield 350, so as to ensure the uniformity of the current.

[0055] In other embodiments, the projection of each first groove 3211 in the first plane may also be asymmetrically arranged about the projection of the shield 350 in the first plane about the center line of the shield 350.

[0056] refer to Figure 8Each first groove 3211 may include a first groove segment 32111 and a second groove segment 32112, wherein the projection of each first groove segment 32111 in the first plane is located on one side of the projection of the center line of the shield 350 in the first plane, and the projection of each second groove segment 32112 in the first plane is located on the other side of the projection of the center line of the shield 350 in the first plane; the extension dimension of the first groove segment 32111 is different from the extension dimension of the second groove segment 32112, so as to compensate for the adverse effects caused by the asymmetry of the lower electrode assembly 300 with respect to the center line of the shield 350, thereby improving the uniformity of the process.

[0057] Optionally, based on the process results, the asymmetry about the center line of the shield 350 is about 1%. Accordingly, when the first groove 3211 is opened on the interface plate 321, the extension dimension of the first groove segment 32111 of each first groove 3211 can be about 1% longer than the extension dimension of the second groove segment 32112 to balance the non-uniformity caused by the asymmetry about the center line of the shield 350.

[0058] For example, when the first groove 3211 is a rectangular groove, the first groove segment 32111 in the rectangular groove is about 1% longer than the second groove segment 32112; when the first groove 3211 is an arc-shaped groove, assuming the arc angle of the arc-shaped groove is 120°, the arc angle of the first groove segment 32111 is 60.3°, while the arc angle of the second groove segment 32112 is 59.7°.

[0059] In some embodiments, the width of a plurality of first grooves 3211 can be equal in the direction from the axis of the lower electrode assembly 300 to its edge, and the slotting interval between any two adjacent first grooves 3211 is equal. This arrangement ensures that the plurality of first grooves 3211 are evenly distributed in the direction from the axis to the edge of the lower electrode assembly 300. On the one hand, this guarantees that each first groove 3211 has the same impedance to current. Therefore, based on the current asymmetry between the region near the bending direction of the shielding member 350 and the region away from the bending direction of the shielding member 350, it is easier to set up a plurality of first grooves 3211, reducing the difficulty of slotting. On the other hand, it also avoids the situation where the interval between two adjacent first grooves 3211 is too small, reducing the strength of the interface plate 321, or the interval is too large, resulting in a small number of first grooves 3211.

[0060] In other embodiments, the width dimensions of the plurality of first grooves 3211 may not be completely equal in the direction from the axis of the lower electrode assembly 300 to the edge of the lower electrode assembly 300. For example, some first grooves 3211 may have a larger width dimension, while others may have a smaller width dimension. The specific dimensions can be set according to the actual working conditions, as long as the symmetry of the loop path can be compensated.

[0061] Furthermore, a larger width of each first groove 3211 results in a greater increase in impedance, which is more beneficial for improving the asymmetry of the balanced circuit path. Of course, the size of the interface plate 321 also needs to be considered to prevent it from becoming too large. Based on this, in some embodiments, the width of each first groove 3211 can range from 5mm to 8mm, for example, including 5mm, 6mm, 7mm, 8mm, etc., and of course, other sizes are also possible. This design prevents the first groove 3211 from being too small, which would make processing inconvenient and reduce the processing difficulty, while also preventing the first groove 3211 from being too large, which would affect the overall strength of the interface plate 321. Therefore, the above-mentioned design can both reduce the processing difficulty of the first groove 3211 and improve the overall strength of the interface plate 321.

[0062] The slotting interval between two adjacent first grooves 3211 can range from 1mm to 3mm, for example, including 1mm, 1.5mm, 2mm, 2.5mm, 3mm, etc., and of course, other values ​​are also possible. This setting ensures that the distance between two adjacent first grooves 3211 is neither too large nor too small. On the one hand, it meets the compensation requirements, and on the other hand, it effectively prevents the overall mechanical strength of the interface plate 321 from being affected by an excessively small interval.

[0063] In some embodiments, the interval between any two adjacent first grooves 3211 may be equal or unequal, and can be set according to the actual working conditions, as long as it can compensate for the symmetry of the loop path and ensure the overall mechanical strength of the interface plate 321.

[0064] In the axial direction of the lower electrode assembly 300, the depth dimension of each first groove 3211 can be in the range of 10mm to 15mm, for example, including 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, etc., and of course, other values ​​are also possible. In short, the depth dimension of the first groove 3211 can be comprehensively considered based on the symmetry of the compensation circuit path and the overall strength of the interface disk 321, so as to both compensate for the symmetry of the circuit path and ensure the overall mechanical strength of the interface disk 321.

[0065] In some embodiments, the depth dimensions of the multiple first grooves 3211 can be equal or unequal, and can be set according to the actual working conditions, as long as it can compensate for the symmetry of the loop path and ensure the overall mechanical strength of the interface disk 321. It should be noted that, since the interface disk 321 has a locally thicker reserved area, the depth of the first groove 3211 in the area corresponding to the reserved area is shallower, so as to reduce the adverse effect of the interface disk 321's mechanical strength being reduced due to the deeper first groove 3211.

[0066] refer to Figures 1 to 8 Based on the aforementioned lower electrode assembly 300, this application discloses a semiconductor process chamber, which includes a cavity 100, an inner liner 200, the aforementioned lower electrode assembly 300, and a cantilever 400.

[0067] The cavity 100 is a basic component that provides an installation base for components such as the liner 200, the lower electrode assembly 300, and the cantilever 400. In some embodiments, both the liner 200 and the lower electrode assembly 300 are disposed within the cavity 100. The lower electrode assembly 300 is connected to the side wall of the cavity 100 via the cantilever 400. The liner 200 is arranged around the outside of the lower electrode assembly 300. One end of the liner 200 is electrically connected to the cavity 100, and the other end of the liner 200 is electrically connected to the interface 320 of the lower electrode assembly 300.

[0068] In this embodiment, the lower electrode assembly 300 is fixed to the cavity 100 by the cantilever 400, ensuring the firmness and stability of the installation of the lower electrode assembly 300. Exemplarily, the cantilever 400 may have a cantilever 400 channel, into which the shielding member 350 can pass and ultimately connect to the side wall of the cavity 100. This partially shields the RF feed member 340, achieving a shielding effect, effectively mitigating energy loss, and to some extent reducing the impact on the etching process. Furthermore, the cantilever 400 channel is mainly used to connect external cables and pipes, and also to ground the cavity 100 to form an electrical circuit.

[0069] By setting the liner 200, on the one hand, process gases, plasmas, etc. can be isolated from the inner wall of the cavity 100 during the process, thereby protecting the inner wall of the cavity 100; on the other hand, the liner 200 can also enable electrical conduction between the interface 320 and the cavity 100.

[0070] Considering the presence of components such as the cantilever 400, and the extension of the RF feed 340 from the side containing the cantilever 400 (or matching device 500) towards the carrier 330, the geometry of the lower electrode assembly 300 exhibits asymmetry on the side near and away from the cantilever 400. This results in a difference in current density in the two circuits, affecting etching uniformity. Specifically, the current paths on both the side near and away from the cantilever 400 are: liner - liner grounding ring - interface plate - shield - matching device. However, the current on the liner 200 near the cantilever 400 is in the opposite direction to the current in the shield 350, resulting in a magnetic field cancellation effect. This causes the inductance on the side near the cantilever 400 to be smaller than the inductance on the side away from the cantilever 400, ultimately leading to current asymmetry.

[0071] Based on the above, in this embodiment of the application, the interface component 320 in the lower electrode assembly 300 has at least a plurality of first grooves 3211 in the area of ​​the interface disk 321 near the cantilever 400, thereby increasing the inductance of the area on that side to achieve inductance balance on both sides, thereby making the current on both sides tend to be symmetrical, and thus ensuring the uniformity of the etching process.

[0072] like Figure 7 As shown, the sidewall of the cavity 100 may be provided with a wafer transfer port 110 for wafers to enter and exit the cavity 100. In the circumferential direction of the semiconductor process chamber, the wafer transfer port 110 is offset from the cantilever 400. For example, the axis of the wafer transfer port 110 may be perpendicular to the center line of the cantilever 400.

[0073] Based on the above, the misalignment between the transfer port 110 and the cantilever 400 will affect the uneven distribution of the flow field inside the cavity 100. That is, the flow field distribution on the side of the cavity 100 near the transfer port 110 is uneven with the flow field distribution on the side away from the transfer port 110. This situation will also affect the uniformity of the process.

[0074] In this embodiment, the uniformity of the process is ensured by changing the size of the first groove 3211 in the region on both sides of the center line of the cantilever 400 to balance the adverse effects caused by the misalignment between the transfer port 110 and the cantilever 400.

[0075] refer to Figure 8Each first groove 3211 may include a first groove segment 32111 and a second groove segment 32112. The projection of the first groove segment 32111 onto the first plane and the projection of the wafer transfer port 110 onto the first plane are located on the same side of the projection of the centerline of the cantilever 400 onto the first plane. The projection of the second groove segment 32112 onto the first plane is located on the other side of the projection of the centerline of the cantilever 400 onto the first plane, and the extension dimension of the first groove segment 32111 is greater than the extension dimension of the second groove segment 32112. This arrangement can compensate for the adverse effects of asymmetry of the semiconductor process chamber with respect to the centerline of the cantilever 400, thereby improving process uniformity.

[0076] It should be noted that the centerline of the aforementioned cantilever 400 is collinear with the centerline of a portion of the shield 350.

[0077] Based on the aforementioned semiconductor process chamber, this application also discloses a semiconductor process apparatus, including the aforementioned semiconductor process chamber.

[0078] In summary, the embodiments of this application compensate for the inconsistency of the lower electrode circuit impedance caused by the inherent structural asymmetry in the semiconductor process chamber by opening multiple first grooves 3211 in the area of ​​the interface disk 321 near the side of the shield 350 in the bending direction. This can effectively alleviate the problem of current asymmetry in the lower electrode assembly 300 caused by the inconsistency of the lower electrode circuit impedance, thereby improving the process uniformity and thus improving product performance.

[0079] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A lower electrode assembly, characterized in that, include: The carrier (330), the interface (320), the radio frequency feed (340), and the shield (350); The carrier (330) is used to carry the wafer; The interface component (320) includes an interface disk (321), which is disposed below the carrier component (330); One end of the shield (350) is connected to the interface disk (321), and the other end is bent radially outward toward the carrier (330); The radio frequency feed (340) passes through the shield (350), and the radio frequency feed (340) passes through the interface disk (321) and is connected to the carrier (330) for feeding radio frequency power into the carrier (330); The interface disk (321) has a plurality of first grooves (3211) on one side near the bending direction of the shield (350).

2. The lower electrode assembly according to claim 1, characterized in that, The interface disk (321) has a ring-shaped structure, and a plurality of the first grooves (3211) are arranged from the inner diameter edge to the outer diameter edge of the interface disk (321).

3. The lower electrode assembly according to claim 1, characterized in that, The interface component (320) further includes an inner grounding ring (322), which is connected to the interface disk (321) and is arranged around the carrier component (330); The inner grounding ring (322) has a plurality of second grooves on one side (3221) near the bending direction of the shield (350).

4. The lower electrode assembly according to claim 1, characterized in that, The lower electrode assembly (300) also includes a base (310), and the interface (320) is disposed on the base (310).

5. The lower electrode assembly according to claim 1 or 2, characterized in that, The first groove (3211) is a fan-shaped groove, and the center of each fan-shaped groove coincides with the center of the interface disk (321).

6. The lower electrode assembly according to claim 5, characterized in that, The central angle of each of the said sector slots ranges from 30° to 90°.

7. The lower electrode assembly according to claim 1, characterized in that, The projection of each of the first grooves (3211) in a first plane at least partially coincides with the projection of the center line of the shield (350) in the first plane, wherein the first plane is perpendicular to the axis of the lower electrode assembly (300).

8. The lower electrode assembly according to claim 7, characterized in that, The projection of each of the first grooves (3211) in the first plane is symmetrical about the projection of the center line of the shield (350) in the first plane.

9. The lower electrode assembly according to claim 7, characterized in that, Each of the first grooves (3211) includes a first groove segment (32111) and a second groove segment (32112); the projection of each of the first groove segments (32111) in the first plane is located on one side of the projection of the center line of the shield (350) in the first plane, and the projection of each of the second groove segments (32112) in the first plane is located on the other side of the projection of the center line of the shield (350) in the first plane; The extension dimension of the first groove segment (32111) is different from the extension dimension of the second groove segment (32112).

10. The lower electrode assembly according to claim 1, characterized in that, In the direction from the axis of the lower electrode assembly (300) to the edge of the lower electrode assembly (300), the width of the plurality of first grooves (3211) is equal, and the slot spacing between each adjacent pair of first grooves (3211) is equal.

11. The lower electrode assembly according to claim 1, characterized in that, In the direction from the axis of the lower electrode assembly (300) to the edge of the lower electrode assembly (300), the width dimensions of the plurality of first grooves (3211) are not exactly equal.

12. The lower electrode assembly according to claim 1, 10, or 11, characterized in that, The width of each of the first grooves (3211) ranges from 5 mm to 8 mm; And / or, the slot spacing between two adjacent first grooves (3211) ranges from 1 mm to 3 mm.

13. The lower electrode assembly according to claim 1, characterized in that, In the axial direction of the lower electrode assembly (300), the depth dimension of each of the first grooves (3211) ranges from 10 mm to 15 mm.

14. A semiconductor process chamber, characterized in that, include: The cavity (100), the liner (200), the lower electrode assembly (300) and the cantilever (400), wherein the lower electrode assembly (300) is the lower electrode assembly (300) according to any one of claims 1 to 13; The liner (200) and the lower electrode assembly (300) are both disposed inside the cavity (100). The lower electrode assembly (300) is connected to the side wall of the cavity (100) through the cantilever (400). The liner (200) is arranged around the outside of the lower electrode assembly (300). One end of the liner (200) is electrically connected to the cavity (100), and the other end of the liner (200) is electrically connected to the interface piece (320) of the lower electrode assembly (300).

15. The semiconductor process chamber according to claim 14, characterized in that, The side wall of the cavity (100) is provided with a wafer transfer port (110), and the wafer transfer port (110) is offset from the cantilever (400) in the circumferential direction of the semiconductor process chamber. The first groove (3211) includes a first groove segment (32111) and a second groove segment (32112). The projection of the first groove segment (32111) in the first plane and the projection of the transfer port (110) in the first plane are located on the same side of the projection of the center line of the cantilever (400) in the first plane. The projection of the second groove segment (32112) in the first plane is located on the other side of the projection of the center line of the cantilever (400) in the first plane. The extension dimension of the first groove segment (32111) is greater than the extension dimension of the second groove segment (32112).

16. A semiconductor process apparatus, characterized in that, Includes the semiconductor process chamber as described in claim 14 or 15.

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