Device manufacturing method and semiconductor device

Abstract

The present disclosure provides a device preparation method and a semiconductor device. In the device preparation method, a substrate is provided, wherein a first dielectric layer and a first conductive part of a conductive member are formed on the substrate, and the first conductive part is filled in a first via hole formed in the first dielectric layer; a patterned second dielectric layer is formed, wherein a second via hole is formed in the second dielectric layer, and the second via hole is in communication with the first via hole; and a second conductive part of the conductive member is formed, which is filled in the second via hole, wherein the second conductive part is electrically connected with the first conductive part, and a thickness of the second conductive part is less than or equal to a preset thickness, so that there is no pore in the second conductive part or a characteristic size of the pore in the second conductive part is less than or equal to a preset size.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a device fabrication method and a semiconductor device. Background Technology

[0002] In semiconductor manufacturing, electrical connections between devices or between devices and external circuits are often achieved through conductive elements filled within vias in dielectric material. However, because conductive material is difficult to completely fill vias with large aspect ratios, the performance of such electrical connections is poor and may affect the structure and quality of other film layers, leading to a deterioration in device performance and reliability. Therefore, there is a need to improve semiconductor manufacturing processes. Summary of the Invention

[0003] One of the purposes of this disclosure is to provide a method for fabricating a device and a semiconductor device.

[0004] According to a first aspect of this disclosure, a method for fabricating a device is provided, comprising:

[0005] A substrate is provided, wherein a first dielectric layer and a first conductive portion of a conductive element are formed on the substrate, and the first conductive portion fills a first through-hole formed in the first dielectric layer.

[0006] A patterned second dielectric layer is formed, wherein a second through-hole is formed in the second dielectric layer, and the second through-hole is connected to the first through-hole; and

[0007] A second conductive portion is formed in the second through hole of the conductive element, wherein the second conductive portion is electrically connected to the first conductive portion, and the thickness of the second conductive portion is less than or equal to a preset thickness, so that there are no pores in the second conductive portion or the characteristic size of the pores present in the second conductive portion is less than or equal to a preset size.

[0008] In some embodiments, forming a first conductive portion of a first dielectric layer and a conductive element on the substrate includes:

[0009] A patterned first dielectric layer is formed on the substrate, wherein a first through-hole is formed in the first dielectric layer;

[0010] Depositing a first conductive material, wherein the deposited first conductive material includes a first conductive material portion filling the first via and a second conductive material portion covering the top surface of the first dielectric layer and the first conductive material portion; and

[0011] Chemical mechanical polishing is performed to remove at least a portion of the second conductive material.

[0012] In some embodiments, the first conductive portion of forming the first dielectric layer and the conductive element on the substrate further includes:

[0013] Before depositing the first conductive material, a first conductive adhesive material is deposited, wherein the first conductive adhesive material at least covers the top surface of the substrate exposed to the first via and the inner wall of the first via.

[0014] In some embodiments, forming a patterned second dielectric layer includes:

[0015] A second dielectric material is deposited in the form of a continuous thin film on the top surface of the first dielectric layer and the first conductive portion;

[0016] A patterned anti-etching layer is formed on the second dielectric material;

[0017] The portion of the second dielectric material not covered by the etch-resistant layer is etched to form the second via; and

[0018] Remove the remaining anti-etching layer.

[0019] In some embodiments, forming a patterned second dielectric layer includes:

[0020] A stop material and a second dielectric material are sequentially deposited in a continuous thin film on the top surface of the first dielectric layer and the first conductive portion.

[0021] A patterned anti-etching layer is formed on the second dielectric material;

[0022] The portion of the second dielectric material not covered by the etch-resistant layer is etched using a first etching condition, and then the uncovered portion of the stop material is etched using a second etching condition different from the first etching condition to form the second via; and

[0023] Remove the remaining anti-etching layer.

[0024] In some embodiments, the stop material comprises silicon nitride, and the deposition thickness of the stop material is greater than or equal to a preset safety thickness and less than the preset thickness.

[0025] In some embodiments, the second conductive portion forming the conductive element and filling the second through-hole includes:

[0026] Depositing a second conductive material, wherein the deposited second conductive material includes a third conductive material portion filling the second via and a fourth conductive material portion covering the top surface of the second dielectric layer and the third conductive material portion; and

[0027] Chemical mechanical polishing is performed to remove at least the fourth conductive material portion.

[0028] In some embodiments, the second conductive portion forming the conductive element and filling the second through-hole further includes:

[0029] Before depositing the second conductive material, a second conductive adhesive material is deposited, wherein the second conductive adhesive material at least covers the top surface of the first conductive portion and the inner wall of the second through hole.

[0030] In some embodiments, at least one of the first conductive adhesive material and the second conductive adhesive material comprises titanium or titanium nitride.

[0031] In some embodiments, at least one of the first dielectric layer and the second dielectric layer comprises phosphosilicate glass; and / or

[0032] At least one of the first conductive portion and the second conductive portion comprises tungsten.

[0033] In some embodiments, the first dielectric layer and the second dielectric layer are formed of the same dielectric material; and / or

[0034] The first conductive portion and the second conductive portion are formed of the same conductive material.

[0035] In some embodiments, the thickness of the second conductive portion is less than the thickness of the first conductive portion.

[0036] In some embodiments, the first conductive portion includes:

[0037] A dense portion, wherein the dense portion contains no pores or the characteristic size of the pores present in the dense portion is less than or equal to the preset size; and

[0038] A non-dense portion, wherein the non-dense portion is located above the dense portion, and the characteristic size of the pores present in the non-dense portion is larger than the preset size;

[0039] Wherein, the thickness of the second conductive portion is less than or equal to the thickness of the dense portion of the first conductive portion.

[0040] In some embodiments, the preset size is 5-10nm, or 10-15nm, or 15-20nm, or 20-25nm, or 25-30nm, or 30-35nm, or 35-40nm, or 40-45nm, or 45-50nm, or 50-55nm, or 55-60nm.

[0041] In some embodiments, the thickness of the second conductive portion is 30–50 nm or 50–100 nm; and / or

[0042] The characteristic dimension of the cross section of the second conductive portion perpendicular to the thickness direction is 100-200 nm or 200-300 nm.

[0043] According to a second aspect of this disclosure, a semiconductor device is provided, including a conductive element comprising a first conductive portion and a second conductive portion, and the semiconductor device is fabricated by the device fabrication method described above.

[0044] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0045] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0046] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0047] Figure 1 A schematic flowchart of a device fabrication method according to an exemplary embodiment of the present disclosure is shown;

[0048] Figure 2 A schematic flowchart illustrating the process of forming a first conductive portion of a first dielectric layer and a conductive element in a device fabrication method according to an exemplary embodiment of the present disclosure is shown.

[0049] Figure 3 A schematic flowchart illustrating the process of forming a second conductive portion of a conductive element and a second dielectric layer in a device fabrication method according to an exemplary embodiment of the present disclosure is shown.

[0050] Figure 4 A schematic flowchart illustrating the formation of a second conductive portion of a second dielectric layer and a conductive element in a device fabrication method according to another exemplary embodiment of the present disclosure is shown.

[0051] Figures 5(a) to 5(f) A schematic diagram illustrating the fabrication process of a conductive element in a semiconductor device according to an exemplary embodiment of the present disclosure is shown.

[0052] Figures 6(a) to 6(c) A schematic diagram illustrating a portion of the fabrication process of a conductive element in a semiconductor device according to another exemplary embodiment of the present disclosure is shown;

[0053] Figures 7(a) and 7(b) show scanning electron microscope (SEM) images of cross sections perpendicular to the thickness direction of conductive parts formed using conventional and the processes of this disclosure, respectively, in a specific example.

[0054] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0055] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0056] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0057] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and are not exhaustive.

[0058] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0059] In semiconductor manufacturing, conductive elements housed within vias in a dielectric layer are often used to achieve electrical connections between devices or between devices and external circuits. The dielectric material surrounding the conductive element provides good electrical isolation. However, in some cases, the via itself may have a large aspect ratio, making it difficult for the conductive material to completely fill it, resulting in gaps within the conductive element and degrading electrical connection performance. Furthermore, one or more layers above the dielectric layer and the conductive element may experience downward depressions or collapses at these gaps; that is, the structure and quality of such layers may undergo undesirable changes, affecting device performance and reliability.

[0060] To address the aforementioned issues, this disclosure provides a device fabrication method that employs at least two deposition processes to form a conductive component, thereby reducing or even eliminating porosity in at least the upper portion of the conductive component, thus improving conductivity and ensuring the structural and quality stability of the subsequently deposited film, thereby enhancing device performance and reliability.

[0061] In one exemplary embodiment of this disclosure, such as Figure 1 and Figures 5(a) to 5(c) As shown, the device fabrication method may include:

[0062] Step S110: Provide substrate 210.

[0063] The substrate 210 has a first conductive portion 231 formed on the first dielectric layer 220 and the conductive element 230, and the first conductive portion 231 is filled in the first through hole 221 formed in the first dielectric layer 220.

[0064] In some embodiments, the first dielectric layer 220 and the first conductive portion 231 may have been pre-formed on the substrate 210 in various ways. In this way, a dense second conductive portion can be formed on the existing first conductive portion in the manner described below to solve the problems that may be caused by the presence of pores in the first conductive portion.

[0065] In other embodiments, the first dielectric layer 220 and the first conductive portion 231 may also be formed on the substrate 210 in the manner described below. Specifically, as Figure 2 As shown in FIG. 5(a), the first conductive portion 231 of forming the first dielectric layer 220 and the conductive element 230 on the substrate 210 may include:

[0066] Step S111: A patterned first dielectric layer 220 is formed on the substrate 210.

[0067] A first via 221 is formed in the first dielectric layer 220. In some embodiments, a first dielectric material in the form of a continuous thin film may first be deposited on the top surface of the substrate 210. For example, the first dielectric material may include silicon phosphosilicate glass (PSG) or other dielectric materials. Then, one or more first vias 221 may be formed at desired locations based on an etching process, thereby forming a patterned first dielectric layer 220. Specifically, a patterned resist layer may be formed on the first dielectric material. This resist layer may be formed only by photoresist, or it may also be formed by materials such as deposited silicon nitride to further improve the etching ratio. Then, the portion of the first dielectric material not covered by the resist layer may be etched to form the first via 221. Finally, the remaining resist layer may be removed as needed to avoid the resist layer affecting subsequent processes. Alternatively, in other embodiments, a patterned photoresist layer may be first formed on the top surface of the substrate 210 based on a photolithography process, followed by deposition of a first dielectric material in the form of a continuous thin film, and finally the photoresist and the first dielectric material thereon may be removed based on a lift-off process, thereby forming a patterned first dielectric layer 220 having one or more first vias 221 in the remaining first dielectric material.

[0068] In some embodiments, the formed first via 221 may be in the shape of an inverted trapezoid, wider at the top and narrower at the bottom, so that conductive material can be deposited inside the via. However, it is understood that, depending on the specific process, the formed first via 221 may also have a consistent cross-sectional dimension at the top and bottom, or be narrower at the top and wider at the bottom, and this is not limited here.

[0069] Furthermore, such as Figure 2 As shown in Figure 5(b), the first conductive portion 231 on which the first dielectric layer 220 and the conductive element 230 are formed on the substrate 210 may further include:

[0070] Step S112: Deposit the first conductive material.

[0071] The deposited first conductive material may include a first conductive material portion 2311 filling the first via 221 and a second conductive material portion 2312 covering the top surface of the first dielectric layer 220 and the first conductive material portion 2311. In some embodiments, the first conductive material may include tungsten (W) or other conductive materials, and may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0072] In some embodiments, when the through-hole has a large aspect ratio or a shape that is narrower at the top and wider at the bottom, the first conductive material may have difficulty completely filling the first through-hole 221. Thus, as shown in FIG5(b), pores 250 of a certain size may form inside the first conductive material portion 2311. Since the top of the first conductive material portion 2311 has been sealed, these pores 250 are difficult to fill with the first conductive material, which may adversely affect the conductivity of the conductive component and the film structure formed in subsequent processes. In this disclosure, this problem will be solved by continuing to form a dense second conductive portion, as will be described in detail later.

[0073] Furthermore, considering that conductive materials such as tungsten may have poor adhesion to other materials, in some embodiments, to prevent the conductive components from detaching and to improve the deposition quality of the conductive material, a first conductive adhesive material may be deposited before depositing the first conductive material. The first conductive adhesive material can at least cover the top surface of the substrate 210 exposed to the first through-hole 221 and the inner wall of the first through-hole 221, so that the first conductive material forms a reliable electrical connection with any electrodes (not shown) that may be present on the top surface of the substrate 210 exposed to the first through-hole 221, and can improve the film quality of the first conductive material deposited in the first through-hole 221. In some embodiments, the first conductive adhesive material may include titanium or titanium nitride, and the deposition of the first conductive adhesive material with good conformal properties can be achieved by methods such as atomic layer deposition (ALD), physical vapor deposition (PVD) such as sputtering, or metal-organic chemical vapor deposition (MOCVD).

[0074] Furthermore, such as Figure 2 and Figures 5(b) to 5(c) As shown, the first conductive portion 231 on which the first dielectric layer 220 and the conductive element 230 are formed on the substrate 210 may further include:

[0075] Step S113, perform chemical mechanical polishing (CMP) to at least remove the second conductive material portion 2312.

[0076] Ideally, chemical mechanical polishing (CMP) could remove only the second conductive material portion 2312 of the first conductive material, leaving the first conductive portion 231 of the conductive element 230. However, in practice, CMP is often performed after removing the second conductive material portion 2312, which removes a small portion of the top of the first dielectric layer 220 and the first conductive material portion 2311, exposing the pores 250 that were originally located inside the first conductive portion 231 (or, in other words, the top openings of the pores 250 are open as shown in Figure 5(c)). This open top of the pores 250 may adversely affect subsequent processes such as film deposition.

[0077] Furthermore, as shown in Figures 5(b) and 5(c), since the bottom of the first conductive portion 231 is formed earlier, this portion is usually dense, containing no pores, or even if pores exist, their feature size is very small and has virtually no impact on conductivity or the structure and quality of subsequent film layers. Therefore, to solve the above problem, the operation of forming a dielectric layer and a conductive portion can be performed again on the structure shown in Figure 5(c) to produce a dense second conductive portion. Specifically, as... Figure 1 As shown in Figures 5(d) and 6(a), the device fabrication method of this disclosure may further include:

[0078] Step S120: A patterned second dielectric layer 240 is formed.

[0079] In the second dielectric layer 240, a second through hole 241 is provided, and the second through hole 241 is connected to the first through hole 221 so that the second conductive part 232 subsequently deposited in the second through hole 241 and the first conductive part 231 deposited in the first through hole 221 form a complete conductive element 230.

[0080] In one exemplary embodiment, similar to the formation of the patterned first dielectric layer 220, such as... Figure 3As shown in Figure 5(d), forming a patterned second dielectric layer may include: step S121, depositing a second dielectric material in the form of a continuous thin film on the top surface of the first dielectric layer 220 and the first conductive portion 231. The second dielectric material may be the same as the first dielectric material, for example, it may include phosphosilicate glass (PSG) or other dielectric materials. Alternatively, a different dielectric material from the first dielectric material may be used as the second dielectric material as needed, without limitation. Then, one or more second vias 241 may be generated at desired locations based on an etching process, thereby forming a patterned second dielectric layer 240. Specifically, forming a patterned second dielectric layer may further include: step S122, forming a patterned etch-resistant layer on the second dielectric material. This etch-resistant layer may be formed solely of photoresist, or it may also be formed of materials such as deposited silicon nitride to further improve the etching ratio. Next, forming the patterned second dielectric layer may further include: step S123, etching the portion of the second dielectric material not covered by the resist layer to form the second via 241. Finally, forming the patterned second dielectric layer may include: step S124, removing the remaining resist layer as needed to avoid the resist layer affecting subsequent processes. It is understood that in other embodiments, a patterned photoresist layer may be first formed on the top surface of the first dielectric layer 220 and the first conductive portion 231 based on a photolithography process, then a second dielectric material in the form of a continuous thin film may be deposited, and finally the photoresist and the second dielectric material thereon may be removed based on a lift-off process, thereby forming a patterned second dielectric layer 240 having one or more second vias 241 in the remaining second dielectric material. It is understood that the aperture of the formed second via 241 may be less than, equal to or greater than the aperture of the first via 221 below it, and is not limited herein.

[0081] In another exemplary embodiment, such as Figure 4As shown in Figure 6(a), a stop layer can also be added between the first dielectric material and the second dielectric material. That is, the second dielectric layer 240 can be formed by the stop material located below and the second dielectric material located above. This helps to improve the shape of the formed via and conductive part, and can also effectively ensure the thickness of the second conductive part, as will be explained in detail later. Accordingly, forming a patterned second dielectric layer may include: step S125, depositing a stop material 260 and a second dielectric material in a continuous thin film on the top surface of the first dielectric layer 220 and the first conductive part 231. The stop material 260 may include silicon nitride, etc., which will not be etched or will be etched very little under the first etching conditions used to etch the subsequently deposited second dielectric material, and thus can serve as an etching stop layer for the second dielectric material. The second dielectric material may be the same as the first dielectric material, for example, it may include phosphosilicate glass (PSG) or other dielectric materials. Alternatively, a dielectric material different from the first dielectric material may be used as the second dielectric material as needed, without limitation. Then, one or more second vias 241 can be generated at desired locations based on an etching process, thereby forming a patterned second dielectric layer 240. Specifically, forming the patterned second dielectric layer may further include: step S126, forming a patterned resist layer on the second dielectric material, which may be formed solely by photoresist, or may also be formed by additionally deposited materials such as silicon nitride to further improve the etching ratio. Next, forming the patterned second dielectric layer may further include: step S127, etching the portion of the second dielectric material not covered by the resist layer using a first etching condition, and then etching the uncovered portion of the stop material 260 using a second etching condition different from the first etching condition to form the second vias 241. Finally, forming the patterned second dielectric layer may include: step S124, removing the remaining resist layer as needed to avoid the resist layer affecting subsequent processes. It is understood that, in other embodiments, a patterned photoresist layer may first be formed on the top surface of the first dielectric layer 220 and the first conductive portion 231 based on a photolithography process. Then, a stop material 260 and a second dielectric material in the form of a continuous thin film may be deposited. Finally, the photoresist and the stop material 260 and the second dielectric material thereon may be removed using a lift-off process, thereby forming a patterned second dielectric layer 240 with one or more second vias 241 in the remaining stop material 260 and the second dielectric material. Similarly, the aperture of the formed second via 241 may be less than, equal to, or greater than the aperture of the first via 221 below it, and is not limited thereto.

[0082] In some embodiments, the formed second via 241 may be in the shape of an inverted trapezoid, wider at the top and narrower at the bottom, so that conductive material can be deposited inside the via. However, it is understood that, depending on the specific process, the formed second via 241 may also have a consistent cross-sectional dimension at the top and bottom, or be narrower at the top and wider at the bottom, and this is not limited thereto.

[0083] Furthermore, such as Figure 1 , Figures 5(e) to 5(f) and Figures 6(b) to 6(c) As shown, the device fabrication method may further include:

[0084] Step S130: A second conductive portion 232 is formed in which the conductive element 230 is filled in the second through hole 241.

[0085] The second conductive portion 232 is electrically connected to the first conductive portion 231 to form a complete conductive element 230. Furthermore, the thickness h1 of the second conductive portion 232 can be less than or equal to a preset thickness, or in other words, the thickness h1 of the second conductive portion 232 can be less than the thickness h2 of the first conductive portion 231. Specifically, the thickness h1 of the second conductive portion 232 can be less than or equal to the thickness ha of the dense portion 231a at the bottom of the first conductive portion 231, so that there are no pores in the second conductive portion 232 or the characteristic size of the pores present in the second conductive portion 232 is less than or equal to a preset size. Here, there are no pores in the dense portion 231a of the first conductive portion 231, or the characteristic size of the pores present in the dense portion 231a is less than or equal to the preset size. In addition, the first conductive portion 231 may also include a non-dense portion 231b located above the dense portion 231a, and the non-dense portion 231b contains pores with a characteristic size greater than the preset size. In other words, during the formation of the conductive element, the first conductive portion 231 located below and the second conductive portion 232 located above can be formed in two steps. This is to make the structure of the second conductive portion 232 above similar to the structure of the dense portion 231a located at the bottom of the first conductive portion 231, so as to reduce or even avoid the adverse effects of the pores (e.g., pores with top openings) located at the top of the conductive element 230 on the conductivity and the subsequent film structure and quality.

[0086] Here, the characteristic size of the pore can refer to the largest dimension (direction) of the pore in a cross-section perpendicular to the thickness direction. For example, when the cross-section of the pore perpendicular to the thickness direction is circular, its characteristic size can refer to the diameter of the circle (e.g., d2 shown in Figure 5(f)). When the cross-section of the pore perpendicular to the thickness direction is rectangular, its characteristic size can be the size of the long side of the rectangle. Furthermore, the preset size can be set according to actual needs, corresponding to a critical size that will not adversely affect conductivity or subsequent film structure and quality. For example, depending on the specific requirements for device performance, the preset size can be 5–10 nm, or 10–15 nm, or 15–20 nm, or 20–25 nm, or 25–30 nm, or 30–35 nm, or 35–40 nm, or 40–45 nm, or 45–50 nm, or 50–55 nm, or 55–60 nm.

[0087] In some embodiments, similar to the formation of the first conductive portion 231, such as... Figure 3 , Figure 4 As shown in Figures 5(e) and 6(b), the second conductive portion 232 filling the second through-hole 241 to form the conductive element 230 may include:

[0088] Step S131: Deposit the second conductive material.

[0089] The deposited second conductive material may include a third conductive material portion 2321 filling the second via 241 and a fourth conductive material portion 2322 covering the top surface of the second dielectric layer 240 and the third conductive material portion 2321. In some embodiments, the second conductive material may be the same as the first conductive material. For example, the second conductive material may include tungsten (W) or other conductive materials, and may be deposited using methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). Alternatively, in other embodiments, a different conductive material than the first conductive material may be used as the second conductive material, which is not limited here.

[0090] Furthermore, considering that conductive materials such as tungsten may have poor adhesion to other materials, in some embodiments, to avoid detachment of conductive components and improve the deposition quality of conductive materials, a second conductive adhesive material may be deposited before depositing the second conductive material. The second conductive adhesive material may at least cover the top surface of the first conductive portion 231 (or the top surface of the first conductive portion 231 exposed to the second via 241) and the inner wall of the second via 241, so that the second conductive material forms a reliable electrical connection with the top surface of the first conductive portion 231, and can improve the film quality of the second conductive material deposited in the second via 241. In some embodiments, the second conductive adhesive material may be the same as or different from the first conductive adhesive material. For example, the second conductive adhesive material may include titanium or titanium nitride, and the deposition of the second conductive adhesive material with good conformability can be achieved by methods such as atomic layer deposition (ALD), physical vapor deposition (PVD) such as sputtering, or metal-organic chemical vapor deposition (MOCVD).

[0091] Furthermore, such as Figure 3 , Figure 4 As shown in Figures 5(f) and 6(c), the second conductive portion 232 filling the second through-hole 241 to form the conductive element 230 may further include:

[0092] Step S132, perform chemical mechanical polishing to remove at least the fourth conductive material portion 2322.

[0093] Similarly, in an ideal scenario, chemical mechanical polishing (CMP) can remove only the fourth conductive material portion 2322 of the second conductive material, leaving the second conductive portion 232 of the conductive element 230. However, in normal cases, CMP is performed after removing the fourth conductive material portion 2322, which removes a small portion of the top of the second dielectric layer 240 and the third conductive material portion 2321. To avoid over-polishing and the formation of exposed pores, as described above, the thickness of the final formed second conductive portion 232 should be less than or equal to a preset thickness. Accordingly, in some embodiments, the thickness of the deposited second dielectric layer 240 can be controlled within the range of 30–50 nm or 50–100 nm. Thus, the thickness of the third conductive material portion 2321 filling the second via 241 in the second dielectric layer 240 is also within the range of 30–50 nm or 50–100 nm. After CMP, the thickness of the final formed second conductive portion 232 can be less than or equal to the preset thickness.

[0094] Furthermore, in Figures 6(a) to 6(c)In the specific embodiment shown that includes a stop material, it becomes difficult to continue chemical mechanical polishing (CMP) when it reaches the stop material 260. Therefore, the stop material 260 can effectively stop CMP and prevent over-polishing. For this purpose, the thickness of the deposited stop material 260 can be greater than or equal to a preset safety thickness to prevent excessive CMP from exposing the openings of the pores 250 in the first conductive portion 231. On the other hand, the deposition thickness of the stop material 260 can be less than the preset thickness to create a second conductive portion 232 with a desired sufficiently small thickness.

[0095] According to the scanning electron microscope images of the conductive element 230 perpendicular to the thickness direction shown in Figures 7(a) and 7(b), there are pores 250 in the conductive element 230 formed by conventional process (as shown in Figure 7(a)); while in the conductive element 230 formed by the process of this disclosure, the pores have been effectively eliminated (as shown in Figure 7(b)), thus it can have better conductivity and will not affect the structure and quality of subsequent film layers.

[0096] Furthermore, in some embodiments, the characteristic dimension of the cross-section of the second conductive portion 232 perpendicular to the thickness direction can be 100–200 nm or 200–300 nm. For example, when the cross-section of the second conductive portion 232 perpendicular to the thickness direction is circular, its characteristic dimension can refer to the diameter of the circle (e.g., d1 as shown in FIG5(f)).

[0097] As mentioned above, depositing conductive material in a via with a large aspect ratio is likely to generate porosity. However, in this disclosure, by filling a second via 241 with a smaller aspect ratio relative to the first via 221 with conductive material to form a second conductive portion 232, the generation of porosity can be effectively reduced or even avoided, thereby improving the conductivity of the conductive component and avoiding adverse effects on the structure and quality of subsequent film layers.

[0098] In addition, in some embodiments, the device fabrication method may also include high-temperature treatment to remove moisture from the surface of the structure, thereby further improving the performance of the device.

[0099] According to another aspect of this disclosure, a semiconductor device is also provided, as shown in Figures 5(f) and 6(c). This semiconductor device may include a conductive element 230, wherein the conductive element 230 may include a first conductive portion 231 and a second conductive portion 232. It is understood that the semiconductor device may also include other components (not shown in the figures), such as an active region, a contact region, and electrodes, to achieve the desired electrical function. Furthermore, the semiconductor device of this disclosure can be fabricated by the device fabrication method described above.

[0100] In the technical solution disclosed herein, considering that a dense portion with a certain thickness can be formed at the bottom during the deposition of conductive material into the via, the first conductive portion located below and the second conductive portion located above the conductive element can be formed in at least two steps. By controlling the thickness of the second conductive portion to be less than or equal to the maximum possible thickness of the dense portion, the top of the formed conductive element is made dense, thereby improving the conductivity of the conductive element and avoiding the adverse effects of open pores at the top on the structure and quality of subsequent film layers, thereby improving the performance and reliability of the device.

[0101] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, enabling embodiments of this disclosure described herein to operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0102] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0103] As used herein, the term “exemplary” means “serving as an example, instance, or illustration” and not as a “model” to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, this disclosure is not limited to any theory expressed or implied as given in the field of art, background art, summary of invention, or detailed description.

[0104] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0105] Furthermore, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0106] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0107] In this disclosure, the term “provide” is used broadly to cover all ways of obtaining an object, and therefore “provide an object” includes, but is not limited to, “purchasing,” “preparing / manufacturing,” “arranging / setting up,” “installing / assembling,” and / or “ordering” an object.

[0108] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0109] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0110] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A device manufacturing method, characterized by, The device fabrication method includes: providing a substrate, wherein a first dielectric layer and a first conductive portion of a conductive member are formed on the substrate, the first conductive portion is filled in a first via hole formed in the first dielectric layer, the first conductive portion includes a dense portion and a non-dense portion above the dense portion, wherein there is no pore in the dense portion or the characteristic size of the pores in the dense portion is less than or equal to a preset size, and the characteristic size of the pores in the non-dense portion is greater than the preset size; forming a patterned second dielectric layer, wherein a second via hole is formed in the second dielectric layer, and the second via hole is in communication with the first via hole; and forming a second conductive portion of the conductive member filled in the second via hole, wherein the second conductive portion is electrically connected with the first conductive portion, wherein forming the second conductive portion of the conductive member filled in the second via hole includes: depositing a second conductive material, wherein the deposited second conductive material includes a third conductive material portion filled in the second via hole and a fourth conductive material portion covering a top surface of the second dielectric layer and the third conductive material portion, performing chemical mechanical polishing to at least remove the fourth conductive material portion, so that the thickness of the second conductive portion is less than or equal to the thickness of the dense portion, so that there is no pore in the second conductive portion or the characteristic size of the pores in the second conductive portion is less than or equal to the preset size.

2. A device production method according to claim 1, wherein forming the first dielectric layer and the first conductive portion of the conductive member on the substrate includes: forming a patterned first dielectric layer on the substrate, wherein a first via hole is formed in the first dielectric layer; depositing a first conductive material, wherein the deposited first conductive material includes a first conductive material portion filled in the first via hole and a second conductive material portion covering a top surface of the first dielectric layer and a top surface of the first conductive material portion; and performing chemical mechanical polishing to at least remove the second conductive material portion.

3. A device production method according to claim 2, wherein forming the first dielectric layer and the first conductive portion of the conductive member on the substrate further includes: before depositing the first conductive material, depositing a first conductive adhesive material, wherein the first conductive adhesive material covers at least a top surface of the substrate exposed to the first via hole and an inner wall of the first via hole.

4. The device production method according to claim 1, wherein forming the patterned second dielectric layer includes: depositing a second dielectric material in a continuous thin film on a top surface of the first dielectric layer and the first conductive portion; forming a patterned etch-resistant layer on the second dielectric material; etching a portion of the second dielectric material not covered by the etch-resistant layer to form the second via hole; and removing the remaining etch-resistant layer.

5. The device production method according to claim 1, wherein forming the patterned second dielectric layer includes: sequentially depositing a stop material and a second dielectric material in a continuous thin film on a top surface of the first dielectric layer and the first conductive portion; forming a patterned etch-resistant layer on the second dielectric material; etching the uncovered portion of the second dielectric material using a first etching condition, and etching the uncovered portion of the stop material using a second etching condition different from the first etching condition to form the second via; and removing the remaining etch-resistant layer.

6. A device production method according to claim 5, wherein The stop material comprises silicon nitride, and a deposition thickness of the stop material is greater than or equal to a preset safe thickness and less than a thickness of the dense portion.

7. The device production method according to claim 3, wherein forming a second conductive portion of the conductive member filling in the second via further comprises: depositing a second conductive adhesive material before depositing the second conductive material, wherein the second conductive adhesive material covers at least a top surface of the first conductive portion and an inner wall of the second via.

8. A device production method according to claim 7, wherein At least one of the first conductive adhesive material and the second conductive adhesive material comprises titanium or titanium nitride.

9. The device production method according to claim 1, wherein At least one of the first dielectric layer and the second dielectric layer comprises phosphosilicate glass; and / or At least one of the first conductive portion and the second conductive portion comprises tungsten.

10. The device production method according to claim 1, wherein The first dielectric layer and the second dielectric layer are formed of the same dielectric material; and / or The first conductive portion and the second conductive portion are formed of the same conductive material.

11. The device production method according to claim 1, wherein The preset size is 5-10 nm, or 10-15 nm, or 15-20 nm, or 20-25 nm, or 25-30 nm, or 30-35 nm, or 35-40 nm, or 40-45 nm, or 45-50 nm, or 50-55 nm, or 55-60 nm.

12. The device production method according to claim 1, wherein A thickness of the second conductive portion is 30-50 nm or 50-100 nm; and / or A characteristic size of a cross section of the second conductive portion perpendicular to a thickness direction is 100-200 nm or 200-300 nm.

13. A semiconductor device, characterized by comprising: The semiconductor device comprises a conductive member comprising a first conductive portion and a second conductive portion, and the semiconductor device is prepared by the device preparation method according to any one of claims 1-12.

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