Extended resistance test structure and manufacturing method thereof, and extended resistance test method

Abstract

The present invention provides an extended resistance test structure and a method for manufacturing the same, as well as an extended resistance test method, comprising the following steps: providing a sample to be tested having at least one chip unit and a scribe area surrounding the chip unit, wherein the chip unit includes a cell area and a terminal area surrounding the cell area and including multiple terminal ring structures, wherein multiple marking structures corresponding one-to-one to the terminal ring structures are formed in the scribe area, and the area where the marking structures are located corresponds to the cell area in the X direction; forming multiple test areas on the chip unit, which are spaced apart in the X direction and have preset dimensions in the Y direction, wherein different test areas correspond one-to-one to different terminal ring structures, wherein one end of the test area in the Y direction is located in the cell area, and the other end exposes the corresponding terminal ring structure, and in the process of forming the test area, the marking structures corresponding to the terminal ring structures exposed in the test area are used as stop marks. The present invention achieves precise positioning of the extended resistance test position and improves test accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of extended resistance testing, and in particular to an extended resistance testing structure and a manufacturing method thereof, and an extended resistance testing method. Background Art

[0002] The spreading resistance test (SRP) technology is a method for testing electrical parameters such as diffusion resistance, resistivity, and carrier concentration distribution of semiconductor materials with relatively high resolution. The steps of this method are to first measure the spreading resistance of a series of point contacts (Rs is the ratio of the potential drop between a conductive metal probe and a reference point on the silicon wafer to the current flowing through the probe), and then use a calibration curve to determine the resistivity of the sample under test near the probe contact point, and then convert it into the carrier concentration corresponding to the series of test points. In order to improve the spatial resolution, and according to the target measurement depth, the sample cross-section direction can be ground into a series of angles. After the silicon wafer is ground, the changes in the resistivity of the structure with a depth of 1-100nm or even deeper can be measured. The spreading resistance method can test the spatial distribution of carrier concentration in the epitaxial, diffusion, and injection processes of Si, InP, GaAs, SiC, etc., and is one of the more important testing methods in semiconductor material preparation and process production.

[0003] An IGBT (insulated-gate bipolar transistor) is a power semiconductor device that combines the characteristics of a bipolar junction transistor (BJT) and a metal-oxide semiconductor field-effect transistor (MOSFET). Its operating principle is based on turning the IGBT on and off by controlling the gate voltage. When the gate voltage is positive, the IGBT conducts, allowing current to flow from the collector (C) to the emitter (E). Conversely, when the gate voltage is zero or negative, the IGBT is off, blocking current.

[0004] The front structure of the IGBT mainly consists of the cell area, the gate pad area and the terminal area with multiple terminal ring structures on the periphery. The terminal ring structure is generally a P-type ion implanted structure, and the upper surface of the terminal ring structure is covered with metal electrodes. The terminal ring structure sometimes has hot spots and requires SRP testing to determine the injection junction depth and resistivity. Figure 1 The following is an SEM image of the terminal ring structure. If you want to use SRP to test the carrier concentration injected by the terminal ring structure, you usually use the method of grinding parallel to the terminal ring structure. Figure 2 and Figure 3 As shown in the figure, they are respectively a schematic diagram of the structure of the chip unit and a schematic diagram of the test results of the extended resistance test of the chip unit ( Figure 2The dotted line portion in the figure represents the path of the test probe during the extended resistance test, including the chip unit 01, the cell area 011, the terminal area 012, the terminal ring structure 0121, and the test area 02. However, the width of the terminal ring structure of the chip structure to be tested does not meet the dual-probe spacing, and the test results cannot be obtained. In addition, if the conventional vertical terminal ring structure grinding method is used, the specific test position cannot be determined.

[0005] In view of this, there is an urgent need for an extended resistance test structure and a manufacturing method thereof that can accurately locate the extended resistance test position and accurately obtain the test results. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an extended resistance test structure and its manufacturing method, and an extended resistance test method, which are used to solve the problem that the extended resistance test structure in the prior art cannot accurately determine the specific test position and cannot obtain accurate test results.

[0007] To achieve the above and other related objectives, the present invention provides a method for manufacturing an extended resistance test structure, comprising the following steps:

[0008] A sample to be tested is provided, the sample to be tested comprising at least one chip unit and a scribe area surrounding the chip unit, the chip unit comprising at least a cellular region and a terminal region surrounding the cellular region, the terminal region comprising a plurality of terminal ring structures spaced apart and surrounding the cellular region, a plurality of marking structures corresponding one-to-one to different terminal ring structures formed in the scribe area, the region where the marking structures are located corresponding to the region where the cellular region is located in the X direction;

[0009] A plurality of test areas are formed on the chip unit, which are spaced apart in the X direction and have a preset size in the Y direction. Different test areas correspond one-to-one to different terminal ring structures. One end of the test area in the Y direction is located in the cell area, and the other end of the test area in the Y direction exposes the corresponding terminal ring structure. In the process of forming the test area, the mark structure corresponding to the terminal ring structure exposed in the test area is used as a stop mark.

[0010] Optionally, the marking structure includes a marking body and marking lines arranged at both ends of the marking body along the X direction, and the endpoint of one end of the test area located in the cell area in the X direction is located on a straight line where the marking line is located along the X direction.

[0011] Optionally, the shapes of the marking bodies in different marking structures are different.

[0012] Optionally, the spacing distance between one end of two adjacent marking structures located in the cell region in the Y direction is consistent with the spacing distance between the corresponding terminal ring structures in the Y direction.

[0013] Optionally, the method of forming the marking structure includes laser marking, wet etching, and dry etching.

[0014] Optionally, the test area is set at a preset angle to the plane where the upper surface of the chip unit is located, and there is a preset height between the end of the test area where the terminal ring structure is exposed and the plane where the upper surface of the chip unit is located. The preset size of the test area in the Y direction is l=h / sinθ, where h represents the preset height and θ represents the preset angle.

[0015] Optionally, the value of the implantation depth of the doped region in the terminal ring structure is the same as the value of the preset height.

[0016] Optionally, the method of forming the test area includes mechanical grinding.

[0017] The present invention also provides an extended resistance test structure, comprising:

[0018] A sample to be tested includes at least one chip unit and a scribe area surrounding the chip unit, wherein the chip unit includes at least a cell area and a terminal area surrounding the cell area, and the terminal area includes a plurality of terminal ring structures arranged at intervals and surrounding the cell area;

[0019] Multiple test areas are arranged on the chip unit, the test areas are arranged at intervals in the X direction and have a preset size in the Y direction, different test areas correspond to different terminal ring structures, one end of the test area in the Y direction is located in the cell area, and the other end of the test area in the Y direction reveals the corresponding terminal ring structure.

[0020] The present invention also provides a method for testing extended resistance, comprising the following steps:

[0021] Provide an extended resistance test device and an extended resistance test structure manufactured by the method for manufacturing an extended test structure according to any one of claims 1 to 8, and place a test probe of the extended resistance test device at either end of the test area in the Y direction;

[0022] The test probe is controlled to move from one end of the test area in the Y direction to the other end of the test area in the Y direction, and a corresponding test result is output.

[0023] As described above, the extended resistance test structure, the manufacturing method thereof, and the extended resistance test method of the present invention have the following beneficial effects: by forming a plurality of the marking structures corresponding one-to-one to the terminal ring structures in the dicing area, the endpoint of one end of the test area located in the cell area in the X direction is located on the straight line of the marking line along the X direction. In the process of forming the test area, the marking structure corresponding to the terminal ring structure exposed in the test area is used as a stop mark, thereby achieving precise positioning of the positions for extended resistance testing of different terminal ring structures, thereby improving test accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Shown is an SEM image of the terminal ring structure in the prior art.

[0025] Figure 2 Shown is a schematic structural diagram of a sample to be tested in the prior art.

[0026] Figure 3 Shown is a schematic diagram of the test results of the extended resistance test of the sample to be tested in the prior art.

[0027] Figure 4 The SEM image of a chip unit showing the method for fabricating the extended resistance test structure of the present invention.

[0028] Figure 5 It is a schematic structural diagram showing the method for manufacturing the extended resistance test structure of the present invention after forming the marking structure.

[0029] Figure 6 It is a structural schematic diagram showing the method for manufacturing the extended resistance test structure of the present invention after the sample to be tested is fixed on the conical surface of the angle gauge.

[0030] Figure 7 It shows a structural schematic diagram after forming the test area in the manufacturing method of the extended resistance test structure of the present invention.

[0031] Figure 8 It is another structural schematic diagram of the extended resistance test structure of the present invention after the test area is formed.

[0032] Figure 9 It is a schematic diagram showing a part of the structure after forming the test area in the method for manufacturing the extended resistance test structure of the present invention.

[0033] Figure 10 Shown is a test structure schematic diagram of an extended resistance test structure of an extended resistance test method of the present invention.

[0034] Figure 11The figure shows the test results of the extended resistance of the extended resistance test structure according to the extended resistance test method of the present invention.

[0035] Component number description

[0036] 01 Chip Unit

[0037] 011 Cellular Area

[0038] 012 Terminal Area

[0039] 0121 Terminal Ring Structure

[0040] 02 Test Area

[0041] 1 Sample to be tested

[0042] 11 chip units

[0043] 111 Cell Area

[0044] 112 Terminal Area

[0045] 112a Terminal ring structure

[0046] 12. Zoning

[0047] 2 Markup Structure

[0048] 21 Marking the subject

[0049] 22 Marking Line

[0050] 3 Test Area

[0051] 4 Angle gauge

[0052] 41 Cone DETAILED DESCRIPTION

[0053] The following describes the implementation of the present invention through specific embodiments. People skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0054] See also Figures 4 to 11. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0055] Example 1

[0056] This embodiment provides a method for manufacturing an extended resistance test structure, comprising the following steps:

[0057] S1: Providing a sample to be tested, wherein the sample to be tested has at least one chip unit and a scribe area surrounding the chip unit, wherein the chip unit includes at least a cell area and a terminal area surrounding the cell area, wherein the terminal area includes a plurality of terminal ring structures spaced apart and surrounding the cell area, and wherein a plurality of marking structures corresponding to different terminal ring structures are formed in the scribe area, wherein the region where the marking structure is located corresponds to the region where the cell area is located in the X direction;

[0058] S2: forming a plurality of test areas on the chip unit, which are spaced apart in the X direction and have a preset size in the Y direction, wherein different test areas correspond one-to-one to different terminal ring structures, one end of the test area in the Y direction is located within the cell area, and the other end of the test area in the Y direction exposes the corresponding terminal ring structure, and in the process of forming the test area, a marking structure corresponding to the terminal ring structure exposed in the test area is used as a stop mark.

[0059] For details, please refer to Figure 4-Figure 5 , perform step S1, provide a sample 1 to be tested, the sample 1 to be tested includes at least one chip unit 11 and a scribe area 12 surrounding the chip unit 11, the chip unit 11 includes at least a cell area 111 and a terminal area 112 surrounding the cell area 111, the terminal area 112 includes a plurality of terminal ring structures 112a arranged at intervals and surrounding the cell area 111, and a plurality of mark structures 2 corresponding to different terminal ring structures 112a are formed in the scribe area 12, and the area where the mark structure 2 is located corresponds to the area where the cell area 111 is located in the X direction.

[0060] Specifically, while meeting the performance requirements of the extended resistance test structure, the number of terminal ring structures 112a can be selected based on actual conditions and is not limited herein. The implantation depth of the doped regions of the terminal ring structures 112a and the width of the terminal ring structures 112a can also be selected based on actual conditions and are not limited herein. In this embodiment, the terminal region 112 includes three terminal ring structures 112a, each having an implantation depth of 3 μm and a width of 1.2 μm. The implantation depth refers to the ion implantation depth of the doped regions of the terminal ring structures 112a, and the width refers to the width of the terminal ring structures 112a.

[0061] Specifically, under the condition that the performance of the extended test structure is met, the spacing distance between adjacent terminal ring structures 112a can be selected according to actual conditions and is not limited here. In this embodiment, the spacing distance between adjacent terminal ring structures 112a is 10 μm.

[0062] Specifically, the sample to be tested 1 is provided with a plurality of chip units 11 arranged in an array and spaced apart.

[0063] Specifically, when a plurality of chip units 11 arranged in an array and spaced apart are provided in the sample 1 to be tested, before forming the test area 3, a step of dicing the sample 1 to be tested is also included. The structure after dicing consists of a chip unit 11 and a dicing area 12 surrounding the chip unit 11. A plurality of marking structures 2 corresponding one-to-one to different terminal ring structures 112a are provided in the dicing area 12 after dicing.

[0064] Specifically, the method of scribing the sample 1 to be tested includes etching, mechanical cutting or other suitable methods.

[0065] Specifically, the mark structure 2 is formed before the sample 1 is diced, or the mark structure 2 is formed after the sample 1 is diced, or the mark structure 2 is formed and diced simultaneously.

[0066] As an example, the method of forming the mark structure 2 includes laser marking, wet etching, dry etching or other suitable methods.

[0067] Specifically, when the marking structure 2 is formed before the sample 1 is diced, or after the sample 1 is diced, or a chip unit 11 is provided in the sample 1, the marking structure 2 is formed by laser marking.

[0068] Specifically, when the marking structure 2 is formed and the sample 1 to be tested is diced simultaneously, the marking structure 2 is formed by wet etching or dry etching.

[0069] As an example, Figure 4 and Figure 5 The figures show an SEM image of the chip unit 11 and a schematic diagram of the structure after the marking structure 2 is formed. The test area 3 is arranged at a preset angle to the plane of the top surface of the chip unit 11. A preset height exists between the end of the test area 3 where the terminal ring structure 112a is exposed and the plane of the top surface of the chip unit 11. The preset dimension l of the test area 3 in the Y direction is l = h / sinθ, where h represents the preset height and θ represents the preset angle. The value of the preset dimension l can be derived based on the known values ​​of the preset height h and the preset angle θ.

[0070] Specifically, the preset size of the test area in the Y direction is l=l1+l2, where l2 is the distance between the terminal ring structure 112a to be tested and the edge of the cell area 111 located between the two ends of the test area 3 in the Y direction, and l1 is the distance between one end of the test area 3 in the cell area 111 and the edge of the cell area 111 located between the two ends of the test area 3 in the Y direction. Among them, l2 is known, l1 is unknown, and the distance l2 between different terminal ring structures 112a and the edge of the cell area 111 is different. The position of the marking structure 2 corresponding to the different terminal ring structures 112a can be obtained based on the difference between the two, and a corresponding marking structure 2 with a preset shape is formed here. In this embodiment, taking the terminal ring structure 112a farthest from the cell area 111 as an example, the target height is 3 μm, the preset angle is 1°9′, and the preset size of the test area 3 in the Y direction is 3 / sin1°9′, which is approximately 150 μm. Since l2 is 92 μm, l1=l-l2, which should be 58 μm, that is, the marking structure 2 should be set in the slicing area 12 corresponding to the area where the cell area 111 is located in the X direction, and the distance between the plane where the edge of the cell area 111 is located is 58 μm. Then, a marking structure 2 with a preset shape is made at this position.

[0071] As an example, the value of the implantation depth of the doped region in the terminal ring structure 112 a is the same as the value of the predetermined height.

[0072] Specifically, the value of the preset angle between the test area 3 and the plane where the upper surface of the chip unit 11 is located is the same as the value of the inclination angle of the inclined conical surface 41 of the angle gauge 4 used to subsequently form the test area 3 .

[0073] Specifically, angle gauge 4 is a commonly used tool for performing extended resistance testing. The shape and size of angle gauge 4 can be selected based on actual conditions, provided that the performance of the extended test structure is met, and are not limited here. The inclination angle of conical surface 41 can also be selected based on actual conditions, and are not limited here. In this embodiment, the inclination angle of conical surface 41 is 1°9′.

[0074] Specifically, the marking structure 2 is formed in the scribe area 12, which can avoid affecting the chip unit 11 and can clearly mark the chip unit 11 while not damaging it.

[0075] Specifically, the number of the marking structures 2 is consistent with the number of the terminal ring structures 112 a , that is, a corresponding marking structure 2 is required to test each terminal ring structure 112 a . In this embodiment, the number of the marking structures 2 is three.

[0076] As an example, the spacing distance between one end of two adjacent marking structures 2 located in the cell region in the Y direction is consistent with the spacing distance between the corresponding terminal ring structures 112 a in the Y direction.

[0077] As an example, the marking structure 2 includes a marking body 21 and marking lines 22 arranged at both ends of the marking body 21 along the X direction. The endpoint of one end of the test area 3 located in the cell area 111 in the X direction is located on the straight line where the marking line 22 is located along the X direction.

[0078] As an example, the shapes of the marking bodies 21 in different marking structures 2 are different.

[0079] Specifically, the shape of the marking body 21 includes a rectangle, a diamond, a cross or other suitable shapes.

[0080] Specifically, while meeting the performance requirements of the extended test structure, the size of the marking body 21 can be selected according to actual conditions and is not limited here; the size of the marking line 22 can be selected according to actual conditions and is not limited here.

[0081] Specifically, a plurality of marking structures 2 corresponding to different terminal ring structures 112 a are formed in the dicing area 12, so that the endpoint of one end of the test area 3 located in the cell area 111 in the X direction is located on the straight line of the marking line 22 along the X direction. The marking structure 2 can be used as a stop mark for forming the test area 3, and can accurately locate the position of the test area 3 when testing the corresponding terminal ring structure 112 a, thereby realizing the precise positioning of different terminal ring structures 112 a for extended resistance testing.

[0082] For details, please refer to Figure 6-Figure 9 , executing step S2, forming a plurality of test areas 3 spaced apart in the X direction and having a preset size in the Y direction on the chip unit 11, wherein different test areas 3 correspond to different terminal ring structures 112a, one end of the test area 3 in the Y direction is located within the cell area 111, and the other end of the test area 3 in the Y direction exposes the corresponding terminal ring structure 112a, and in the process of forming the test area 3, the mark structure 2 corresponding to the terminal ring structure 112a exposed in the test area 3 is used as a stop mark.

[0083] As an example, the method of forming the test area 3 includes mechanical grinding or other suitable methods.

[0084] Specifically, Figure 6-Figure 9 As shown, they are respectively a schematic diagram of the structure after the chip structure to be tested 1 is fixed on the conical surface 41 of the angle gauge 4, a schematic diagram of a structure after the test area 3 is formed, another schematic diagram of the structure after the test area 3 is formed, and a schematic diagram of part of the structure after the test area 3 is formed ( Figure 8-Figure 9 The dotted line portion in the figure represents the travel path of the test probe when performing the extended resistance test), and forming the test area 3 includes the following steps: fixing the sample 1 to be tested on the conical surface 41 of the angle gauge 4, using the position of the cell area 111 corresponding to the extension line of the corresponding marking line 22 in the X direction as the grinding stop end for forming the test area 3, and grinding the chip unit 11 to form a test area 3 with a preset size in the Y direction.

[0085] Specifically, the sample 1 to be tested is fixed on the angle gauge 4 by hot melt adhesive.

[0086] Specifically, the hot melt adhesive should be applied as thinly as possible on the angle gauge 4, and can ensure that the chip structure 1 to be tested does not affect its tilt angle when it is attached to the angle gauge 4, and does not move in the subsequent process of forming the test area 3.

[0087] Specifically, the test results obtained by the extended resistance test device at the terminal ring structure 112 a within the width range of the terminal ring structure 112 a are all conditions of the carrier concentration of the terminal ring structure 112 a.

[0088] Specifically, Figure 10 、 Figure 11 The diagram shows the test structure of the extended resistance test structure and the test result of the extended resistance of the extended resistance test structure. Figure 3 Compared with the test results of the prior art shown in the figure, the extended resistance test is performed on the extended resistance test structure obtained by the method for manufacturing the extended resistance test structure, and the test results of the corresponding terminal ring structure 112a can be accurately obtained. The test results obtained by the extended resistance test device at the terminal ring structure 112a within the width range of the terminal ring structure 112a are all the carrier concentration conditions of the terminal ring structure 112a. In this embodiment, since the distance between the terminal ring structure 112a to be tested and the edge of the cell area 111 located between the two ends of the test area 3 in the Y direction is 92μm, 92*sin(1°9′) is approximately 1.8μm, that is, the results from 1.8μm to 3μm in the test results, that is, within the width range of the terminal ring structure 112a, are all the ion implantation conditions of the doping region of the terminal ring structure 112a.

[0089] The method for manufacturing the extended test structure of this embodiment forms a plurality of marking structures 2 corresponding one-to-one to the terminal ring structures 1112a in the dicing area 12, so that the endpoint of one end of the test area 3 located in the cell area 111 in the X direction is located on the straight line of the marking line 22 along the X direction. The marking structure 2 can serve as a stop mark for forming the test area 3, and can accurately locate the position of the test area 3 when testing the corresponding terminal ring structure 112a, thereby achieving precise positioning of the test position for performing extended resistance testing on different terminal ring structures 112a, thereby improving test accuracy.

[0090] Example 2

[0091] This embodiment provides an extended resistance test structure, which is manufactured by the manufacturing method of the extended resistance test structure described in Example 1. The extended resistance test structure includes: a chip structure 1 to be tested and a test area 3, wherein the chip structure 1 to be tested includes at least one chip unit 11 and a scribe area 12 surrounding the chip unit 11, the chip unit 11 includes at least a cell area 111 and a terminal area 112 surrounding the cell area 111, and the terminal area 112 includes a plurality of terminal ring structures 112a arranged at intervals and surrounding the cell area 111; multiple test areas 3 are arranged on the chip unit 11, the test areas 3 are spaced apart in the X direction and have a preset size in the Y direction, different test areas 3 correspond to different terminal ring structures 112a, one end of the test area 3 in the Y direction is located within the cell area 111, and the other end of the test area 3 in the Y direction exposes the corresponding terminal ring structure 112a.

[0092] Specifically, the test area 3 is arranged at a preset angle to the plane where the upper surface of the chip unit 11 is located.

[0093] Specifically, multiple test areas 3 corresponding to the terminal ring structures 112a are obtained on the chip unit 11 through different marking structures 2. By measuring the change in resistivity in the target depth direction, the carrier concentration at the corresponding terminal ring structure 112a can be obtained.

[0094] The extended resistance test structure of this embodiment provides a plurality of test areas 3 on the chip unit 11 corresponding to the terminal ring structures 112 a , thereby performing corresponding extended resistance tests with high test accuracy.

[0095] Example 3

[0096] This embodiment provides a method for testing extended resistance, including the following steps:

[0097] S100: Providing an extended resistance test device and an extended resistance test structure manufactured by the method for manufacturing an extended test structure according to any one of claims 1 to 8, and placing a test probe of the extended resistance test device at either end of a test area in the Y direction;

[0098] S200: Control the test probe to move from one end of the test area in the Y direction to the other end of the test area in the Y direction, and output corresponding test results.

[0099] Specifically, execute step S100, provide an extended resistance test device (not shown) and an extended resistance test structure manufactured by the manufacturing method of the extended test structure as described in Example 1, and place the test probe of the extended resistance test device at any one end of the test area in the Y direction.

[0100] Specifically, the test probe has a double-probe structure, and the two probes in the test probe are arranged parallel to each other.

[0101] Specifically, step S200 is executed to control the test probe to move from one end of the test area 3 in the Y direction to the other end of the test area 3 in the Y direction, and output corresponding test results.

[0102] Specifically, when the test probe moves from one end of the test area 3 in the Y direction to the other end of the test area 3 in the Y direction, the test probe and the plane where the test area 4 is located are perpendicular to each other.

[0103] Specifically, the test probe can move from one end of the test area 3 located in the cell area 111 to the other end of the test area located at the terminal ring structure 112a, or it can move from one end of the test area 3 located at the terminal ring structure 112a to the other end of the test area located in the cell area 111, and the selection can be made according to actual conditions.

[0104] Specifically, by controlling the test probe to move from one end of the test region 3 in the Y direction to the other end of the test region 3 in the Y direction, the carrier concentration at the corresponding terminal ring structure 112 a can be obtained.

[0105] Specifically, the test results obtained by the extended resistance test device at the terminal ring structure 112 a within the width range of the terminal ring structure 112 a are all conditions of the carrier concentration of the terminal ring structure 112 a.

[0106] Specifically, by using the extended resistance test structure manufactured by the manufacturing method of the extended resistance test structure described in the first embodiment to test the extended resistance of different terminal ring structures 112a, the corresponding extended resistance test results of the terminal ring structure 112a can be accurately obtained.

[0107] The extended resistance testing method of this embodiment uses the extended resistance testing structure manufactured by the manufacturing method of the extended resistance testing structure described in the first embodiment to test the extended resistance of different terminal ring structures 112a, and the test accuracy is high.

[0108] In summary, the extended resistance test structure and its fabrication method, as well as the extended resistance test method of the present invention, form multiple marking structures corresponding one-to-one with terminal ring structures within the scribe area, ensuring that the endpoint of one end of the test area located within the cell area in the X direction is located on a straight line along the marking line along the X direction. During the formation of the test area, the marking structure corresponding to the terminal ring structure exposed in the test area serves as a stop mark, thereby achieving precise positioning of the extended resistance test for different terminal ring structures and improving test accuracy. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial application value.

[0109] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing an extended resistance test structure, characterized in that: The following steps are involved: A sample to be tested is provided, the sample to be tested comprising at least one chip unit and a scribe area surrounding the chip unit, the chip unit comprising at least a cellular region and a terminal region surrounding the cellular region, the terminal region comprising a plurality of terminal ring structures spaced apart and surrounding the cellular region, a plurality of marking structures corresponding one-to-one to different terminal ring structures formed in the scribe area, the region where the marking structures are located corresponding to the region where the cellular region is located in the X direction; A plurality of test areas are formed on the chip unit, which are spaced apart in the X direction and have a preset size in the Y direction. Different test areas correspond one-to-one to different terminal ring structures. One end of the test area in the Y direction is located in the cell area, and the other end of the test area in the Y direction exposes the corresponding terminal ring structure. In the process of forming the test area, the mark structure corresponding to the terminal ring structure exposed in the test area is used as a stop mark.

2. The method for manufacturing the extended resistance test structure according to claim 1, wherein: The marking structure includes a marking body and marking lines arranged at both ends of the marking body along the X direction. The endpoint of one end of the test area located in the cell area in the X direction is located on a straight line where the marking line is located along the X direction.

3. The method for manufacturing the extended resistance test structure according to claim 2, wherein: The shapes of the marking bodies in different marking structures are different.

4. The method for manufacturing the extended resistance test structure according to claim 1, wherein: The spacing distance between one end of two adjacent marking structures located in the cell region in the Y direction is consistent with the spacing distance between the corresponding terminal ring structures in the Y direction.

5. The method for manufacturing the extended resistance test structure according to claim 1, wherein: Methods for forming the marking structure include laser marking, wet etching, and dry etching.

6. The method for manufacturing the extended resistance test structure according to claim 1, wherein: The test area is set at a preset angle to the plane where the upper surface of the chip unit is located. There is a preset height between the end of the test area that exposes the terminal ring structure and the plane where the upper surface of the chip unit is located. The preset size of the test area in the Y direction is ,in, h represents the preset height, θ represents the preset angle.

7. The method for manufacturing the extended resistance test structure according to claim 6, wherein: The value of the implantation depth of the doped region in the terminal ring structure is the same as the value of the preset height.

8. The method for manufacturing the extended resistance test structure according to claim 1, wherein: The method of forming the test area includes mechanical grinding.

9. An extended resistance test structure, characterized in that: The extended resistance test structure is manufactured by the manufacturing method of the extended test structure according to any one of claims 1 to 8, comprising: A sample to be tested includes at least one chip unit and a scribe area surrounding the chip unit, wherein the chip unit includes at least a cell area and a terminal area surrounding the cell area, and the terminal area includes a plurality of terminal ring structures arranged at intervals and surrounding the cell area; Multiple test areas are arranged on the chip unit, the test areas are arranged at intervals in the X direction and have a preset size in the Y direction, different test areas correspond to different terminal ring structures, one end of the test area in the Y direction is located in the cell area, and the other end of the test area in the Y direction reveals the corresponding terminal ring structure.

10. A method for testing extended resistance, characterized in that: The following steps are involved: Providing an extended resistance test device and an extended resistance test structure manufactured by the method for manufacturing an extended test structure according to any one of claims 1 to 8, placing a test probe of the extended resistance test device at either end of the test area in the Y direction; The test probe is controlled to move from one end of the test area in the Y direction to the other end of the test area in the Y direction, and a corresponding test result is output.

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