Memory management method and storage device

Abstract

The present application provides a memory management method and a storage device. The method comprises: configuring a plurality of cache entity units; performing a host write operation to store data from a host system; obtaining a first evaluation value reflecting a total number of at least one first entity unit, wherein the first entity unit does not belong to an idle entity unit; determining a target management strategy according to the first evaluation value; and if the target management strategy is a first management strategy, determining a recycling quantity condition according to the first evaluation value, and performing a data consolidation operation on at least one first cache entity unit which does not belong to an idle entity unit according to the recycling quantity condition. Thus, a good balance can be achieved between maintaining the data write performance of the host write operation and prolonging the service life of the storage device.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory management method and a storage device. BACKGROUND

[0002] Some types of flash memory devices have both cache blocks and normal blocks. Compared with normal blocks, cache blocks have the characteristics of faster access speed but smaller capacity. Therefore, in general, when a host write operation is performed, data is quickly written to the cache blocks. Further, the data in the cache blocks can be moved to the normal blocks with larger capacity for storage, and the original cache blocks are released to store data from the host system again.

[0003] However, as more and more data is stored in the storage device, the cache blocks or normal blocks can be heavily used. A common solution in practice is to trigger a garbage collection (GC) operation to release storage areas when it is detected that there is a serious shortage of idle blocks. However, after triggering the garbage collection operation, the data write performance of the host write operation can be greatly reduced, thereby seriously affecting the user experience. In addition, if the garbage collection operation is triggered too frequently, the write amplification (WA) can be excessively increased due to frequent data movement, thereby shortening the service life of the storage device.

[0004] Therefore, there is an urgent need for a memory management method to solve the above problems. SUMMARY

[0005] The present application provides a memory management method and a storage device, which can improve the above problems, and further achieve a good balance between maintaining the data write performance of the host write operation and prolonging the service life of the storage device without affecting the normal operation of the storage device.

[0006] Embodiments of the present application provide a memory management method for a storage device, wherein the storage device comprises a memory module including a plurality of physical units, and the memory management method comprises: configuring a plurality of cache physical units in the plurality of physical units; performing a host write operation to store data from a host system to at least one of the plurality of physical units; obtaining a first evaluation value, wherein the first evaluation value reflects a total number of at least one first physical unit in the plurality of physical units, and the at least one first physical unit does not belong to an idle physical unit; determining a target management strategy according to the first evaluation value; and if the target management strategy is a first management strategy, determining a recycling quantity condition according to the first evaluation value, and performing a data consolidation operation on at least one first cache physical unit in the plurality of cache physical units which does not belong to the idle physical unit according to the recycling quantity condition, to release the at least one first cache physical unit as the idle physical unit.

[0007] Embodiments of the present application also provide a storage device, which comprises a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: configure a plurality of cache physical units in the plurality of physical units; perform a host write operation to store data from the host system to at least one of the plurality of physical units; obtain a first evaluation value, wherein the first evaluation value reflects a total number of at least one first physical unit in the plurality of physical units, and the at least one first physical unit does not belong to an idle physical unit; determine a target management strategy according to the first evaluation value; and if the target management strategy is a first management strategy, determine a recycling quantity condition according to the first evaluation value, and perform a data consolidation operation on at least one first cache physical unit in the plurality of cache physical units which does not belong to the idle physical unit according to the recycling quantity condition, to release the at least one first cache physical unit as the idle physical unit.

[0008] Based on the above, after obtaining the first evaluation value, the target management strategy can be determined according to the first evaluation value. The first evaluation value can reflect a total number of at least one first physical unit in the memory module, and the first physical unit does not belong to an idle physical unit. In particular, if the target management strategy is a first management strategy, a recycling quantity condition can be determined according to the first evaluation value and used to perform a data consolidation operation on at least one first cache physical unit which does not belong to the idle physical unit, to release the first cache physical unit as the idle physical unit. In this way, the operation flexibility of the data consolidation operation can be increased, thereby achieving a good balance between maintaining the data write performance of the host write operation and prolonging the service life of the storage device without affecting the regular operation of the storage device. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present application;

[0010] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present application;

[0011] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present application;

[0012] Figure 4 is a schematic diagram of different first entity units corresponding to different management strategies according to an embodiment of the present application;

[0013] Figure 5 is a flowchart of a memory management method according to an embodiment of the present application. DETAILED DESCRIPTION

[0014] Reference will now be made in detail to exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0015] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present application. Please refer to Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer arranged in a specific carrier (such as a vehicle), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state disk, a U disk, a memory card, or other types of non-volatile storage devices.

[0016] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Thus, the storage device 12 can communicate (e.g., exchange signals, instructions, and / or data) with the host system 11 via the connection interface 121.

[0017] The memory module 122 is used to store data. For example, the memory module 122 can include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module can include one or more arrays of storage units. A storage unit in an array of storage units stores data in the form of a voltage (also referred to as a threshold voltage). For example, the memory module 122 can include a Single Level Cell (SLC) NAND-type flash memory module, a Multi Level Cell (MLC) NAND-type flash memory module, a Triple Level Cell (TLC) NAND-type flash memory module, a Quad Level Cell (QLC) NAND-type flash memory module, and / or other memory modules having the same or similar characteristics.

[0018] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered the control core of the memory device 12 and is used to control the memory device 12. For example, the memory controller 123 can be used to control or manage all or part of the operation of the memory device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0019] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0020] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0021] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 can include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0022] In an embodiment, the memory controller 123 can further include a buffer memory 24. The buffer memory 24 is used to buffer data. For example, the buffer memory 24 can be used to buffer instructions from the host system 11, data from the host system 11 and / or data from the memory module 122. In an embodiment, the memory controller 123 can further include other types of circuit modules (e.g. power management circuit, etc.), which are not limited by the present application.

[0023] Figure 3 is a schematic diagram showing a management of a memory module according to an embodiment of the present application. Please refer to Figures 1 to 3 The memory module 122 includes a plurality of physical units 301(1)~301(D). Each physical unit includes a plurality of memory cells and is used to store data non-volatilely.

[0024] In an embodiment, one physical unit can include one or more physical erase units. One physical erase unit can include a plurality of physical program units. One physical program unit can include a plurality of physical sectors. For example, the data capacity of one physical sector can be 512 Bytes (B), and one physical program unit can include 8 physical sectors. However, the data capacity of one physical sector and / or the total number of physical sectors included in one physical program unit can be adjusted according to practical needs, which are not limited by the present application. In an embodiment, one physical program unit can be regarded as one physical page. For example, the data capacity of one physical program unit can be 4 kilobytes (4 KB), which is not limited by the present application.

[0025] In one embodiment, a physical program unit is a minimum unit of data that is written synchronously in the memory module 122. For example, when a program operation (also referred to as a write operation or a data write operation) is performed on a physical program unit to write data to the physical program unit, multiple memory cells in the physical program unit can be programmed synchronously to store corresponding data. For example, when a physical program unit is programmed, a program voltage can be applied to the physical program unit to change threshold voltages of at least some memory cells in the physical program unit. The threshold voltage of each memory cell can reflect a bit of data stored in the memory cell.

[0026] In one embodiment, multiple physical program units in a physical erase unit can be erased synchronously. For example, when an erase operation is performed on a physical erase unit, an erase voltage can be applied to multiple physical program units in the physical erase unit to change threshold voltages of at least some memory cells in the physical program units. By performing an erase operation on a physical erase unit, data stored in the physical erase unit can be cleared.

[0027] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1) to 301(A) to a data area (also referred to as a first type of data area or a cache area) 31 and associate the physical units 301(A+1) to 301(B) to a data area (also referred to as a second type of data area) 32. The physical units 301(1) to 301(A) in the data area 31 and the physical units 301(A+1) to 301(B) in the data area 32 can all store data (also referred to as user data) from the host system 11. For example, any of the physical units in the data areas 31 and 32 can store valid data and / or invalid data.

[0028] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(B+1) to 301(C) and 301(C+1) to 301(D) to a spare area 33. For example, the physical units 301(B+1) to 301(C) and 301(C+1) to 301(D) in the spare area 33 can not store data (e.g., valid data).

[0029] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated to the spare area 33. In addition, a physical unit in the spare area 33 can be erased to clear data in the physical unit. In one embodiment, a physical unit in the spare area 33 is also referred to as a spare physical unit. In one embodiment, the spare area 33 is also referred to as a free pool.

[0030] In an embodiment, the physical units in the free area 33 can be considered as free physical units. In an embodiment, the physical units in the data areas 31 and 32 can be considered as non-free physical units.

[0031] In an embodiment, the memory control circuit 23 can configure the physical units 301(B+1)~301(C) as first-type physical units (also referred to as cache physical units). In an embodiment, the memory control circuit 23 can configure the physical units 301(C+1)~301(D) as second-type physical units (also referred to as normal physical units).

[0032] In an embodiment, the access performance of the first-type physical units can be higher than the access performance of the second-type physical units. For example, the speed of the memory control circuit 23 to access the first-type physical units (e.g., the speed of reading data from the first-type physical units and / or the speed of writing data to the first-type physical units) can be higher than the speed of the memory control circuit 23 to access the second-type physical units (e.g., the speed of reading data from the second-type physical units and / or the speed of writing data to the second-type physical units).

[0033] In an embodiment, the memory control circuit 23 can program the first-type physical units based on a certain programming mode (also referred to as a first programming mode) to store data in the first-type physical units. In an embodiment, the memory control circuit 23 can program the second-type physical units based on another programming mode (also referred to as a second programming mode) to store data in the second-type physical units. The first programming mode is different from the second programming mode.

[0034] In an embodiment, the first programming mode can include an SLC mode or a pseudo SLC (pSLC) mode. In an embodiment, the second programming mode can include an MLC, a TLC mode or a QLC mode. It should be noted that the first programming mode and the second programming mode can be set or adjusted according to practical needs, and the present application is not limited thereto.

[0035] In an embodiment, one storage unit in the first-type physical units can store k bits. In an embodiment, one storage unit in the second-type physical units can store p bits, and k is less than p. For example, assuming that k is "1", p can be "2", "3", "4" or other integers greater than "1". Alternatively, assuming that k is "2", p can be "3", "4" or other integers greater than "2". The present application does not limit the values of k and p.

[0036] In one embodiment, when data is to be stored, the memory control circuit 23 can select one or more physical units from the spare area 33 and instruct the memory module 122 to store the data into the selected physical units. In particular, if the selected physical units belong to the first type of physical units (e.g., one of the physical units 301(B+1)~301(C)), after storing the data into the physical units, the physical units can be associated with the data area 31. However, if the selected physical units belong to the second type of physical units (e.g., one of the physical units 301(C+1)~301(D)), after storing the data into the physical units, the physical units can be associated with the data area 32. In other words, the first type of physical units (i.e., the physical units 301(1)~301(A) and 301(B+1)~301(C)) can be alternately used between the data area 31 and the spare area 33, while the second type of physical units (i.e., the physical units 301(A+1)~301(B) and 301(C+1)~301(D)) can be alternately used between the data area 32 and the spare area 33.

[0037] In one embodiment, the memory control circuit 23 can configure the plurality of logical units 302(1)~302(E) to map the physical units (i.e., the physical units 301(1)~301(A) and 301(A+1)~301(B)) in the data areas 31 and 32. For example, one logical unit can correspond to one logical block address (LBA) or other logical management unit. One logical unit can be mapped to one or more physical units in the data areas 31 and / or 32.

[0038] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit currently stores valid data. Otherwise, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit currently does not store any valid data.

[0039] In one embodiment, the memory control circuit 23 can record the mapping relationship between the logical units and the physical units in a logical-to-physical mapping table. In one embodiment, the memory control circuit 23 can instruct the memory module 122 to perform data read, write or erase operations according to the information in the logical-to-physical mapping table.

[0040] In one embodiment, the memory control circuit 23 can fetch an instruction from the host system 11. For example, the instruction includes a write instruction. The write instruction can instruct to store certain data. In one embodiment, the memory control circuit 23 can perform a write operation (also referred to as a host write operation) according to the instruction to store data from the host system 11. For example, in the host write operation, the memory control circuit 23 can send a sequence of write instructions to the memory module 122 to instruct the memory module 122 to store certain data to at least one physical unit in the memory module 122.

[0041] In one embodiment, in the host write operation, the memory control circuit 23 can instruct the memory module 122 to store data from the host system 11 to the first type of physical units (e.g., the physical units 301(B+1)~301(C)) first. In this way, the data write efficiency of the host write operation can be improved. However, if the first type of physical units are exhausted (e.g., the physical units 301(B+1)~301(C) are all associated with the data area 31), the memory control circuit 23 can instead instruct the memory module 122 to store data from the host system 11 to the second type of physical units (e.g., the physical units 301(C+1)~301(D)). In this way, although the data write efficiency of the host write operation can be reduced, the normal execution of the host write operation can still be maintained.

[0042] In one embodiment, the memory control circuit 23 can obtain an evaluation value (also referred to as a first evaluation value) related to the plurality of physical units in the memory module 122. The first evaluation value can reflect the total number of the physical units in the memory module 122 that are not idle physical units (also referred to as first physical units). In one embodiment, the physical units that are not idle physical units can be considered as used physical units. Therefore, in one embodiment, the first evaluation value can also reflect the total number of the used physical units (i.e., the first physical units) in the memory module 122. In one embodiment, the first evaluation value can also reflect the total number of the physical units (i.e., the first physical units) in the memory module 122 that are not in the idle state.

[0043] In one embodiment, the first evaluation value can be equal to the total number of the first physical units. Alternatively, in one embodiment, the first evaluation value can be positively related to the total number of the first physical units. That is, the more the total number of the first physical units, the larger the first evaluation value can be.

[0044] In one embodiment, each physical unit in the idle area 33 (i.e., physical units 301 (B+1) - 301 (D)) is a non-used physical unit, and each physical unit in the data areas 31 and 32 (i.e., physical units 301 (1) - 301 (B)) is a used physical unit (i.e., a first physical unit). Thus, the first evaluation value can reflect the total number of the physical units 301 (1) - 301 (B) currently associated with the data areas 31 and 32. For example, the first evaluation value can be equal to or positively correlated with the total number of the physical units 301 (1) - 301 (B) currently associated with the data areas 31 and 32.

[0045] In one embodiment, the first physical unit refers to any used physical unit in the memory module 122. For example, the first physical unit can include any physical unit in the data areas 31 and 32, but not include any physical unit in the idle area 33. In one embodiment, the memory control circuit 23 can monitor the total number of the used physical units (i.e., the first physical units) in the memory module 122 in real time to obtain the first evaluation value.

[0046] In one embodiment, the memory control circuit 23 can determine a management policy (also referred to as a target management policy) according to the first evaluation value. In other words, the target management policy is determined according to the first evaluation value. In one embodiment, the target management policy can correspondingly change when the first evaluation value changes. The memory control circuit 23 can manage the memory module 122 according to the target management policy determined at the moment.

[0047] In one embodiment, the memory control circuit 23 can pre-configure a plurality of management policies (also referred to as candidate management policies). For example, according to the first evaluation value, the memory control circuit 23 can determine a certain management policy (also referred to as a first management policy) from the plurality of candidate management policies as the target management policy. The candidate management policies can include, but are not limited to, the first management policy, the second management policy, the third management policy, and the like mentioned in the embodiments of the present application.

[0048] It should be noted that the present application does not limit the total number of the plurality of candidate management policies. For example, in one embodiment, the plurality of candidate management policies can further include a fourth management policy or more or less management policies, which are not limited by the present application.

[0049] In one embodiment, the memory control circuit 23 can compare the first evaluation value with at least one threshold value. The memory control circuit 23 can determine the target management policy from the plurality of candidate management policies according to the comparison result of the first evaluation value and the at least one threshold value. In other words, the memory control circuit 23 can determine one of the plurality of candidate management policies as the target management policy according to the comparison result of the first evaluation value and the at least one threshold value.

[0050] Figure 4 This is a schematic diagram showing that the total number of different first entity units corresponds to different management strategies according to an embodiment of the present invention. Figure 4 In one embodiment, it is assumed that the candidate management strategies include management strategies A to C. Management strategy A belongs to the second management strategy. Management strategy B belongs to the first management strategy. Management strategy C belongs to the third management strategy. In addition, it is assumed that the at least one critical value includes a critical value THR(1) (also referred to as the first critical value) and a critical value THR(2) (also referred to as the second critical value). Critical value THR(2) is greater than critical value THR(1).

[0051] In one embodiment, the memory control circuit 23 may compare the first evaluation value with the threshold value THR(1) and / or THR(2) and obtain a comparison result. The comparison result may reflect the relationship between the total number of used physical units (i.e., the first physical units) in the memory module 122 and the threshold value, for example, the total number is greater than the threshold value THR(2), the total number is between the threshold values ​​THR(1) and THR(2), or the total number is less than the threshold value THR(1).

[0052] In one embodiment, if the comparison result indicates that the total number of used physical units (i.e., the first physical units) in the memory module 122 is less than the threshold THR(1), the memory control circuit 23 may determine management policy A (i.e., the second management policy) as the target management policy. The memory control circuit 23 may then manage the memory module 122 based on management policy A.

[0053] In one embodiment, if the comparison result indicates that the total number of used physical units (i.e., the first physical units) in the memory module 122 is between the thresholds THR(1) and THR(2), the memory control circuit 23 may determine management strategy B (i.e., the first management strategy) as the target management strategy. The memory control circuit 23 may then manage the memory module 122 based on management strategy B.

[0054] In one embodiment, if the comparison result indicates that the total number of used physical units (i.e., the first physical units) in the memory module 122 is greater than the threshold THR(2), the memory control circuit 23 may determine the management policy C (i.e., the third management policy) as the target management policy. The memory control circuit 23 may then manage the memory module 122 based on the management policy C.

[0055] It should be noted that, in one embodiment, the total number of the critical values ​​used to determine the target management policy and the total number of the candidate management policies may be more or less, and the present invention is not limited thereto.

[0056] As can be seen, based on the method proposed in the above embodiment, by comparing the relationship between the first evaluation value and the critical value, a corresponding target management policy is determined, and the data consolidation operation is executed according to the target management policy. This allows for flexible configuration of the execution scheme of the data consolidation operation, and further enables the dynamic release of non-idle physical units to idle physical units for the next data storage, thereby improving data writing efficiency and effective utilization of storage space.

[0057] In one embodiment, if the target management policy is the first management policy (eg Figure 4 In the case of the management strategy B in FIG1 , the memory control circuit 23 may determine a quantity condition (also referred to as a reclaim quantity condition or a data consolidation execution condition) based on the first evaluation value. When the first management strategy is used to manage the memory module 122, the memory control circuit 23 may perform a data consolidation operation on at least one cache physical unit (also referred to as a first cache physical unit) in the memory module 122 that is not an idle physical unit based on the reclaim quantity condition. This data consolidation operation may release the first cache physical unit as an idle physical unit.

[0058] In one embodiment, Figure 3 Each cache physical unit in the idle area 33 (i.e., physical units 301(B+1)-301(C)) is an unused cache physical unit, while the cache physical units in the data area 31 (i.e., physical units 301(1)-301(A)) are used cache physical units. In one embodiment, the first cache physical unit may include physical units that refer to at least a portion of the data area 31, but does not include any physical units in the data area 32 or the idle area 33.

[0059] In one embodiment, the recycling quantity condition reflects a number (also referred to as a target number). The target number can be used to determine the total number of first cache physical units participating in the aforementioned data consolidation operation. For example, assuming that the target number reflected by the recycling quantity condition is "N", the memory control circuit 23 can limit the total number of first cache physical units participating in the aforementioned data consolidation operation to "N" based on the recycling quantity condition. N can be any positive integer. For example, N can be "1", "2", "8" or other positive integers, and the present invention is not limited thereto.

[0060] In one embodiment, the memory control circuit 23 can determine the target number (e.g., "N") according to the first evaluation value. In one embodiment, the target number can be positively correlated to the total number of used physical units (i.e., first physical units) in the memory module 122. That is, the greater the total number of used physical units (i.e., first physical units) in the memory module 122, the greater the target number can be. Alternatively, from another perspective, in the case where the memory module 122 is managed using the first management policy, the greater the total number of used physical units (i.e., first physical units) in the memory module 122, the more used cache physical units the memory control circuit 23 can perform data compaction operations on to release first cache physical units that meet the recycling number condition as idle physical units as soon as possible through data compaction operations.

[0061] In one embodiment, the memory control circuit 23 can obtain another evaluation value (also referred to as a second evaluation value) related to a plurality of physical units in the memory module 122. The second evaluation value can reflect the total number of cache physical units (i.e., the total number of cache physical units among the first physical units) in the memory module 122 that do not belong to idle physical units. Illustratively, the cache physical units that do not belong to idle physical units can be considered as used cache physical units. Illustratively, the cache physical units that do not belong to idle physical units can also be considered as cache physical units in a non-idle state. Therefore, in one embodiment, the second evaluation value can also reflect the total number of used (or in a non-idle state) cache physical units in the memory module 122. Figure 3 For example, in the case where the memory module 122 is managed using the first management policy, the memory control circuit 23 can select at least one physical unit (e.g., N first cache physical units) that meets the recycling number condition from the data area 31 (i.e., physical units 301(1) to 301(A)) as a source physical unit, and select at least one physical unit from the idle area 33 (e.g., physical units 301(C+1) to 301(D)) as a target physical unit. The memory control circuit 23 can collect valid data from the source physical unit and store the collected valid data into the target physical unit (i.e., move the valid data from the source physical unit to the target physical unit). If all the valid data in a source physical unit has been moved to the target physical unit, the memory control circuit 23 can associate this source physical unit to the idle area 33 (e.g., become one of physical units 301(B+1) to 301(C)). In one embodiment, the operation of associating the source physical unit to the idle area 33 is equivalent to releasing a new idle physical unit.

[0062] In one embodiment, the memory control circuit 23 can obtain another evaluation value (also referred to as a second evaluation value) related to a plurality of physical units in the memory module 122. The second evaluation value can reflect the total number of cache physical units (i.e., the total number of cache physical units among the first physical units) in the memory module 122 that do not belong to idle physical units. Illustratively, the cache physical units that do not belong to idle physical units can be considered as used cache physical units. Illustratively, the cache physical units that do not belong to idle physical units can also be considered as cache physical units in a non-idle state. Therefore, in one embodiment, the second evaluation value can also reflect the total number of used (or in a non-idle state) cache physical units in the memory module 122.

[0063] In one embodiment, the second evaluation value can be equal to the total number of cache physical units in the memory module 122 that do not belong to the idle physical units, i.e., the used cache physical units. Alternatively, in one embodiment, the first evaluation value can be positively correlated to the total number of cache physical units in the memory module 122 that do not belong to the idle physical units. That is, the more the total number of cache physical units in the memory module 122 that do not belong to the idle physical units, the greater the second evaluation value can be.

[0064] In one embodiment, Figure 3 Each cache physical unit in the idle area 33, i.e., the physical units 301(B+1)~301(C), belongs to a cache physical unit that has not been used, while each cache physical unit in the data area 31 belongs to a cache physical unit that has been used. In one embodiment, the memory control circuit 23 can monitor the total number of cache physical units in the memory module 122 that have been used in real time to obtain the second evaluation value.

[0065] In one embodiment, the memory control circuit 23 can determine the recycling quantity condition (e.g., "N") according to the first evaluation value and the second evaluation value. In one embodiment, N can be positively correlated to the total number of cache physical units in the memory module 122 that have been used. That is, the more the total number of cache physical units in the memory module 122 that have been used, the greater N can be.

[0066] In one embodiment, the memory control circuit 23 can perform an interpolation operation according to the first evaluation value, the second evaluation value, the first threshold value, and the second threshold value. The memory control circuit 23 can determine the recycling quantity condition according to the result of the interpolation operation.

[0067] In one embodiment, the memory control circuit 23 can determine the recycling quantity condition (e.g., "N") according to the following equation (1.1).

[0068] N = ((M - THR(1)) / (THR(2) - (THR(1))) x M(1) (1.1)

[0069] In equation (1.1), M is the total number of physical units in the memory module 122 that have been used, i.e., the first physical units, M(1) is the total number of cache physical units in the memory module 122 that have been used, THR(1) is the first threshold value, THR(2) is the second threshold value, and N can represent the recycling quantity condition. It should be noted that equation (1.1) can also be adjusted according to practical needs, and the present application is not limited thereto.

[0070] In one embodiment, when the usage level of the memory module 122 is moderate (e.g., the total number of used physical units is between the first threshold value and the second threshold value), the dynamic control of the memory module 122 by employing the first management policy to perform the data compaction operation only on the cache physical units that meet the reclaim quantity condition can release the cache physical units needed to maintain the smooth operation of the system in a moderate manner according to the current usage state of the memory module 122.

[0071] In this way, a good balance between maintaining the data write performance of the host write operation and reducing the write amplification of data can be achieved as much as possible.

[0072] In one embodiment, when the target management policy is the second management policy (e.g., the management policy A in Figure 4 , the memory control circuit 23 can not perform the data compaction operation on any cache physical unit in the memory module 122. For example, after determining the second management policy (e.g., the management policy A in Figure 4 as the target management policy, the memory control circuit 23 can stop or prohibit the performance of the data compaction operation on any used cache physical unit in the memory module 122.

[0073] In this way, when the usage level of the memory module 122 is relatively low (e.g., the total number of used physical units is less than the first threshold value), by employing the second management policy to reduce unnecessary data compaction operations, the write amplification of data can be effectively reduced without affecting the data write performance of the host write operation.

[0074] In one embodiment, when the target management policy is the third management policy (e.g., the management policy C in Figure 4 , the memory control circuit 23 can perform the data compaction operation on all cache physical units in the memory module 122 that do not belong to the idle physical units. For example, after determining the third management policy (e.g., the management policy C in Figure 4 as the target management policy, the memory control circuit 23 can allow or force the performance of the data compaction operation on all used cache physical units in the memory module 122.

[0075] In this way, when the usage level of the memory module 122 is relatively high (e.g., the total number of used physical units is greater than the second threshold value), by performing the data compaction operation on any used cache physical unit to release as many available cache physical units as possible, the data write performance of the host write operation can be ensured to be maintained as stable as possible.

[0076] In one embodiment, the memory control circuit 23 may monitor the data write efficiency of a current host write operation. For example, the data write efficiency of a host write operation may be positively correlated with the amount of data stored by the host system 11 to the storage device 12 per unit time. In one embodiment, the memory control circuit 23 may evaluate the execution efficiency of executed or pending data consolidation operations. For example, the execution efficiency of a data consolidation operation may be positively correlated with the total number of idle physical units released by the data consolidation operation per unit time.

[0077] In one embodiment, the memory control circuit 23 may determine (including adjusting or updating) at least one of the first threshold value and the second threshold value based on at least one of the data write performance of the host write operation and the execution performance of the data consolidation operation. For example, the memory control circuit 23 may input a parameter value that can be used to represent the data write performance of the host write operation (also referred to as the first parameter value) and / or a parameter value that can be used to represent the execution performance of the data consolidation operation (also referred to as the second parameter value) into a specific algorithm or lookup table. The memory control circuit 23 may then obtain the first threshold value and / or the second threshold value based on the output of the specific algorithm or lookup table. In one embodiment, the specific algorithm or lookup table may be designed according to practical needs and is not limited by the present invention.

[0078] In one embodiment, the data write performance of the host write operation may be positively correlated with the first threshold value and / or the second threshold value. In one embodiment, the data write performance of the host write operation may be negatively correlated with the first threshold value and / or the second threshold value. In one embodiment, the execution performance of the data consolidation operation may be positively correlated with the first threshold value and / or the second threshold value. In one embodiment, the execution performance of the data consolidation operation may be negatively correlated with the first threshold value and / or the second threshold value.

[0079] In one embodiment, the first threshold and / or the second threshold are determined based on at least one of the data write performance of the host write operation and the execution performance of the data merge operation. The first threshold and / or the second threshold can be dynamically set to a value that best reflects the current usage of the storage device 12. This also helps determine a target management policy.

[0080] Figure 5 FIG is a flow chart of a memory management method according to an embodiment of the present invention. Figure 5 The memory management method described in the present application solution specifically includes the following steps:

[0081] In step S501 , a plurality of cache physical units are arranged in a plurality of physical units of a memory module.

[0082] In step S502, a host write operation is performed to store data from a host system to at least one of the plurality of physical units.

[0083] In step S503, a first evaluation value is obtained, wherein the first evaluation value reflects a total number of at least one first physical unit of the plurality of physical units, and the at least one first physical unit does not belong to the idle physical units.

[0084] In step S504, a target management policy is determined according to the first evaluation value.

[0085] In an embodiment, if the target management policy is the first management policy, in step S505, a reclaim quantity condition is determined according to the first evaluation value, and a data consolidation operation is performed on at least one first cache physical unit of the memory module which does not belong to the idle physical units according to the reclaim quantity condition, to release the at least one first cache physical unit as an idle physical unit.

[0086] In an embodiment, if the target management policy is the second management policy, in step S506, the data consolidation operation is not performed on any cache physical unit of the memory module.

[0087] In an embodiment, if the target management policy is the third management policy, in step S507, the data consolidation operation is performed on all cache physical units of the memory module which do not belong to the idle physical units.

[0088] In an embodiment, the step of determining the target management policy according to the first evaluation value comprises: comparing the first evaluation value with at least one threshold value; and determining the target management policy from a plurality of candidate management policies according to a comparison result, wherein the plurality of candidate management policies comprises the first management policy.

[0089] In an embodiment, the at least one threshold value comprises a first threshold value and a second threshold value, the second threshold value is greater than the first threshold value, the plurality of candidate management policies further comprises a second management policy and a third management policy, and the step of determining the target management policy from the plurality of candidate management policies according to the comparison result comprises: if the comparison result reflects that the total number of the at least one first physical unit is between the first threshold value and the second threshold value, determining the first management policy as the target management policy; if the comparison result reflects that the total number of the at least one first physical unit is less than the first threshold value, determining the second management policy as the target management policy; and if the comparison result reflects that the total number of the at least one first physical unit is greater than the second threshold value, determining the third management policy as the target management policy.

[0090] In one embodiment, the step of determining the reclaim quantity condition according to the first evaluation value comprises: obtaining a second evaluation value, wherein the second evaluation value reflects a total number of cache entity units in the plurality of cache entity units that do not belong to the idle entity units; and determining the reclaim quantity condition according to the first evaluation value and the second evaluation value.

[0091] In one embodiment, the step of determining the reclaim quantity condition according to the first evaluation value and the second evaluation value comprises: performing an interpolation operation according to the first evaluation value, the second evaluation value, a first threshold value and a second threshold value; and determining the reclaim quantity condition according to a result of the interpolation operation.

[0092] In one embodiment, the memory management method further comprises: determining at least one of the first threshold value and the second threshold value according to at least one of a data write performance of the host write operation and an execution performance of the data consolidation operation.

[0093] However, Figure 5 The steps in the above embodiments have been described in detail, and thus will not be repeated here. It is worth noting that, Figure 5 The steps in the above embodiments can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. In addition, Figure 5 The method of the above embodiment can be used in combination with the above exemplary embodiments, or can be used alone, and the present application is not limited thereto.

[0094] In summary, the memory management method and the storage device provided by the present application can determine a suitable target management strategy to manage the memory module according to the total number of used entity units in the memory module at the moment. For example, different target management strategies can be used to accurately control whether to allow the data consolidation operation to be performed on the used cache entity units in the memory module and / or how many used cache entity units the data consolidation operation is allowed to be performed on. In this way, a good balance between maintaining the data write performance of the host write operation and prolonging the service life of the storage device can be achieved without affecting the regular operation of the storage device.

[0095] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory management method, characterized in that: For use in a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of physical units, and the memory management method includes: disposing a plurality of cache entity units in the plurality of entity units; performing a host write operation to store data from a host system into at least one of the plurality of physical units; Obtaining a first evaluation value, wherein the first evaluation value reflects the total number of at least one first entity unit among the plurality of entity units, and the at least one first entity unit is not an idle entity unit; comparing the first evaluation value with at least one critical value; If the comparison result indicates that the total number of the at least one first entity unit is between the first critical value and the second critical value, determining the first management strategy as the target management strategy; If the comparison result reflects that the total number of the at least one first entity unit is less than the first critical value, determining the second management strategy as the target management strategy; If the comparison result reflects that the total number of the at least one first entity unit is greater than the second critical value, determining the third management strategy as the target management strategy; If the target management policy is the first management policy, determining a recycling quantity condition based on the first evaluation value, and performing a data consolidation operation on at least one first cache physical unit that is not one of the idle physical units among the plurality of cache physical units based on the recycling quantity condition, so as to release the at least one first cache physical unit as the idle physical unit, wherein the at least one first cache physical unit includes at least a portion of physical units in the cache area but does not include any physical units in the data area and the idle area; If the target management policy is the second management policy, not performing the data consolidation operation on any cache physical unit among the plurality of cache physical units; and If the target management policy is the third management policy, the data consolidation operation is performed on all cache physical units that are not the idle physical units among the plurality of cache physical units. 2 . The memory management method according to claim 1 , wherein the recycling quantity condition reflects a target quantity, and the target quantity is used to determine the total number of the at least one first cache physical unit participating in the data consolidation operation. 3 . The memory management method according to claim 2 , wherein the target quantity is positively correlated with the total number of the at least one first physical unit.

4. The memory management method according to claim 1 , wherein the step of determining the recycling quantity condition according to the first evaluation value comprises: Obtaining a second evaluation value, wherein the second evaluation value reflects the total number of cache physical units in the plurality of cache physical units that are not the idle physical units; as well as The recycling quantity condition is determined according to the first evaluation value and the second evaluation value.

5. The memory management method according to claim 4, wherein the step of determining the recycling quantity condition according to the first evaluation value and the second evaluation value comprises: performing an interpolation operation according to the first evaluation value, the second evaluation value, the first critical value, and the second critical value; as well as The recycling quantity condition is determined according to the result of the interpolation operation.

6. The memory management method according to claim 5, further comprising: At least one of the first threshold and the second threshold is determined according to at least one of the data writing performance of the host write operation and the execution performance of the data merge operation.

7. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: disposing a plurality of cache entity units in the plurality of entity units; performing a host write operation to store data from the host system to at least one of the plurality of physical units; Obtaining a first evaluation value, wherein the first evaluation value reflects the total number of at least one first entity unit among the plurality of entity units, and the at least one first entity unit is not an idle entity unit; comparing the first evaluation value with at least one critical value; If the comparison result indicates that the total number of the at least one first entity unit is between the first critical value and the second critical value, determining the first management strategy as the target management strategy; If the comparison result reflects that the total number of the at least one first entity unit is less than the first critical value, determining the second management strategy as the target management strategy; If the comparison result reflects that the total number of the at least one first entity unit is greater than the second critical value, determining the third management strategy as the target management strategy; If the target management policy is the first management policy, determining a recycling quantity condition based on the first evaluation value, and performing a data consolidation operation on at least one first cache physical unit that is not one of the idle physical units among the plurality of cache physical units based on the recycling quantity condition, so as to release the at least one first cache physical unit as the idle physical unit, wherein the at least one first cache physical unit includes at least a portion of physical units in the cache area but does not include any physical units in the data area and the idle area; If the target management policy is the second management policy, not performing the data consolidation operation on any cache entity unit among the plurality of cache entity units; as well as If the target management policy is the third management policy, the data consolidation operation is performed on all cache physical units that are not the idle physical units among the plurality of cache physical units. 8 . The storage device of claim 7 , wherein the recycling quantity condition reflects a target quantity, and the target quantity is used to determine a total number of the at least one first cache physical unit participating in the data consolidation operation. 9 . The storage device according to claim 8 , wherein the target quantity is positively correlated with the total number of the at least one first physical unit.

10. The storage device according to claim 7, wherein the memory controller determines the recycling quantity condition according to the first evaluation value, comprising: Obtaining a second evaluation value, wherein the second evaluation value reflects the total number of cache physical units in the plurality of cache physical units that are not the idle physical units; as well as The recycling quantity condition is determined according to the first evaluation value and the second evaluation value.

11. The storage device according to claim 10 , wherein the memory controller determines the recycling quantity condition according to the first evaluation value and the second evaluation value, comprising: performing an interpolation operation according to the first evaluation value, the second evaluation value, the first critical value, and the second critical value; as well as The recycling quantity condition is determined according to the result of the interpolation operation.

12. The storage device according to claim 11, wherein the memory controller is further configured to: At least one of the first threshold and the second threshold is determined according to at least one of the data writing performance of the host write operation and the execution performance of the data merge operation.

Images