A method to improve FLASH programming efficiency

Abstract

The present invention provides a method for improving the Program efficiency of FLASH, and relates to the field of computer technology. The method includes supporting two modes of pipeline programming and command programming. By connecting a bus with a write cache FIFO inside a Flash controller, the Flash controller simultaneously connects and controls FLASH0 and FLASH1, and a write cache FIFO is provided in the Flash controller, so that the write data Length can be configured and flexibly support 64-bit to 4096-bit programming. One Flash controller corresponds to two Flashes. The method for improving the Program efficiency of FLASH adopts the programming schemes of ping-pong programming and pipeline programming, provides flexible programming Length configuration, and higher programming efficiency, so that the time occupied by bus writing data can be effectively shortened, and the user experience is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method for improving FLASH program efficiency. Background Art

[0002] NOR Flash is a non-volatile flash memory technology. The advantage of NOR is on-chip execution (XIP, eXecute In Place), so that the application can run directly in the flash memory without having to read the code into the system RAM. NOR has a high transmission efficiency and is very cost-effective at a small capacity of 1 to 4MB, but its performance is greatly affected by its low write and erase speeds. However, since the Program efficiency of Nor eFlash is relatively low, improving Program efficiency can help shorten the time to burn Flash during SOTA and bring a better user experience. The time to complete the Program is divided into two parts: one is the time taken by the bus to write data; the other is the time taken to program the data into Flash.

[0003] In the prior art, the bus writes data to the cache RAM using the command load page, and each bus clock cycle can write 32 bits of data. Therefore, the time for programming 64 bits of data in this conventional solution is 2 to 4 clk periods + program periods, and the time for programming 256 bits of data is 8 to 16 clk periods + program periods. However, the prior art has the problem of no pipelining and low efficiency of bus writing data. Summary of the invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a method for improving the Program efficiency of FLASH to solve the problems raised in the above background technology. The present invention can shorten the time occupied by bus writing data and improve the user experience.

[0005] In order to achieve the above-mentioned purpose, the present invention is implemented through the following technical solutions: a method for improving the Program efficiency of FLASH, including supporting two modes of pipeline programming and command programming; the bus is connected to the write cache FIFO inside the Flash controller, the Flash controller simultaneously connects and controls FLASH0 and FLASH1, and the Flash controller is provided with a write cache FIFO, which can configure the write data Length and flexibly support 64bit~4096bit programming; one Flash controller corresponds to two Flashes.

[0006] Furthermore, the operation flow of the pipeline programming includes: before the last Program Flash is finished, the bus can start writing FIFO.

[0007] Furthermore, as long as the data in the FIFO reaches the set length, Program Flash can be started automatically.

[0008] Furthermore, the operation sequence of the command programming is: after the last Program Flash is finished, the bus starts writing FIFO.

[0009] Furthermore, the Program command can be initiated to start Program Flash only after the data in the FIFO reaches the set length.

[0010] Furthermore, two Flash memories can be programmed simultaneously to halve the total programming time.

[0011] Furthermore, the Flash controller implements ping-pong programming through address control.

[0012] Beneficial effects of the present invention:

[0013] 1. The method for improving the programming efficiency of FLASH adopts the programming scheme of ping-pong programming and pipeline programming, provides flexible programming length configuration and higher programming efficiency, thereby effectively shortening the time occupied by bus writing data and improving user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a connection diagram between the Flash controller and the Flash;

[0015] Figure 2 A comparison chart of programming time between command programming and pipeline programming;

[0016] Figure 3 A comparison chart of programming time between Flash and Ping-Pong Flash. DETAILED DESCRIPTION

[0017] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further explained below in conjunction with specific implementation methods.

[0018] See also Figures 1 to 3The present invention provides the following technical solutions: a method for improving the Program efficiency of FLASH, in which a bus is connected to a write cache FIFO inside a Flash controller, and the write cache FIFO simultaneously controls the connection of FLASH0 and FLASH1. The method for improving the Program efficiency of FLASH adopts a programming scheme of ping-pong programming and pipeline programming, provides a flexible programming length configuration, and has a higher programming efficiency, thereby effectively shortening the time occupied by the bus to write data and improving the user experience.

[0019] This embodiment supports two modes: pipeline programming and command programming:

[0020] Operation of pipeline programming: The bus can start writing FIFO before the last Program Flash is finished; Program Flash can start automatically as long as the data in FIFO reaches the set length.

[0021] The operation sequence of command programming is as follows: after the last Program Flash is completed, the bus starts writing FIFO; after the data in FIFO reaches the set length, the Program command can be issued to start Program Flash.

[0022] Take the bus clock cycle of 10ns and the programming data of 256bit as an example. Figure 2 As shown:

[0023] In command programming, the total programming time is 55040ns, including 40ns for bus writing and 55000ns for Program.

[0024] In pipeline programming, the total time consumed for one pipeline programming is 55000ns.

[0025] In this embodiment, a write cache FIFO is set in the Flash controller, and the write data length can be configured, so as to flexibly support 64-bit to 4096-bit programming.

[0026] In this embodiment, one Flash controller corresponds to two Flashes, and ping-pong programming is implemented through address control. The two Flashes can be programmed at the same time, which reduces the total programming time by half.

[0027] Take the bus clock cycle of 10ns and the programming data of 256bit as an example. Figure 3 As shown:

[0028] The total time for programming a 256-bit Flash is 110,000 ns, including the superposition of two Program times of 55,000 ns;

[0029] The total time required to program a 256-bit ping-pong Flash is 55,000 ns. When two Flashes are programmed simultaneously, the time required to program each Flash is the same as the total time, which is 55,000 ns.

[0030] The basic principles and main features of the present invention and the advantages of the present invention are shown and described above. For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention.

[0031] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for improving FLASH Program efficiency, characterized by: It supports both pipeline programming and command programming modes. The bus is connected to the write cache FIFO inside the Flash controller. The Flash controller controls the connection of FLASH0 and FLASH1 at the same time. The Flash controller is equipped with a write cache FIFO, which can configure the write data length and flexibly support 64-bit to 4096-bit programming. One Flash controller corresponds to two Flashes.

2. A method for improving FLASH Program efficiency according to claim 1, characterized in that: The operation flow of pipeline programming includes: the bus starts writing FIFO before the last Program Flash is finished.

3. A method for improving FLASH Program efficiency according to claim 2, characterized in that: As long as the data in FIFO reaches the set length, Program Flash will automatically start.

4. The method for improving FLASH Program efficiency according to claim 1, characterized in that: The operation sequence of the command programming is: after the last Program Flash is finished, the bus starts writing FIFO.

5. A method for improving FLASH Program efficiency according to claim 4, characterized in that: After the data in the FIFO reaches the set length, a Program command is issued to start Program Flash.

6. The method for improving FLASH Program efficiency according to claim 1, characterized in that: Programming two Flash memories simultaneously reduces the total programming time by half.

7. The method for improving FLASH Program efficiency according to claim 1, characterized in that: The Flash controller implements ping-pong programming through address control.

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